MAX4521CPE [ROCHESTER]
SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16;
| 型号： | MAX4521CPE |
| 厂家： | 
Rochester Electronics |
| 描述： | SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, DIP-16 光电二极管 输出元件 |
| 文件： | 总19页 (文件大小：1247K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-1136; Rev 6; 7/07
Quad, Low-Voltage, SPST Analog Switches
General Description
Features
The MAX4521/MAX4522/MAX4523 are quad, low-volt-
age, single-pole/single-throw (SPST) analog switches.
On-resistance (100Ω max) is matched between switch-
es to 4Ω max, and is flat (12Ω max) over the specified
signal range. Each switch can handle rail-to-rail analog
signals. The off-leakage current is only 1nA at +25°C
and 10nA at +85°C.
♦ +2V to +12V Single Supply
±2V to ±ꢀV ꢁuDl Supplieꢂ
♦ 100Ω SignDl PDthꢂ with ±±V Supplieꢂ
♦ Low Power Conꢂumption, <1µW
♦ 4 SepDrDtely Controlled SPST Switcheꢂ
♦ RDil-to-RDil SignDl HDndling
The MAX4521 has four normally closed (NC) switches,
and the MAX4522 has four normally open (NO) switch-
es. The MAX4523 has two NC switches and two NO
switches.
♦ Pin CompDtible with Induꢂtry-StDndDrd
ꢁG211/ꢁG212/ꢁG213
These CMOS switches can operate with dual power
supplies ranging from 2ꢀ to ꢁꢀ or a single supply
between +2ꢀ and +12ꢀ. They are fully specified for sin-
gle +2.7ꢀ operation.
♦ >2kV ESꢁ Protection per Method 301±.7
♦ TTL/CMOS-CompDtible Inputꢂ with ±±V or
Single +±V Supply
Ordering Information
All digital inputs have +0.8ꢀ and +2.4ꢀ logic thresh-
olds, ensuring TTL/CMOS-logic compatibility when
using 5ꢀ or a single +5ꢀ supply.
PIN-
PACKAGE
PKG
COꢁE
PART
TEMP RANGE
Applications
MAX4±21CPE
MAX4521CSE
MAX4521CEE
MAX4521CUE
MAX4521CGE
MAX4521C/D
0°C to +70°C 1ꢁ Plastic DIP
0°C to +70°C 1ꢁ Narrow SO
0°C to +70°C 1ꢁ QSOP
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
—
Battery-Operated Equipment
Data Acquisition
Test Equipment
Avionics
0°C to +70°C 1ꢁ TSSOP
0°C to +70°C 1ꢁ QFN-EP**
0°C to +70°C
Dice*
Audio Signal Routing
Networking
Ordering Information continued at end of data sheet.
*Contact factory for dice specifications.
**EP = Exposed pad.
Pin Configurations/Functional Diagrams/Truth Tables
TOP VIEW
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
IN1
16
15
14
IN1
16 IN2
15 COM2
14 NO2
13 V+
IN1
16 IN2
15 COM2
14 NC2
13 V+
IN2
COM1
NC1
V-
COM2
NC2
COM1
NO1
V-
COM1
NO1
V-
13 V+
MAX4522
MAX4523
MAX4521
N.C.
GND
NC4
12
11
10
9
12
12
11
10
9
GND
NO4
GND
NO4
N.C.
N.C.
NC3
COM3
IN3
NC3
COM3
IN3
11
10
9
NO3
COM3
IN3
COM4
IN4
COM4
IN4
COM4
IN4
ꢁIP/SO/QSOP/TSSOP
ꢁIP/SO/QSOP/TSSOP
ꢁIP/SO/QSOP/TSSOP
MAX4521
MAX4522
MAX4523
SWITCHES
1, 4
SWITCHES
LOGIC
SWITCH
LOGIC
SWITCH
LOGIC
2, 3
0
1
ON
0
1
OFF
ON
0
1
OFF
ON
ON
OFF
OFF
SWITCHES SHOWN FOR LOGIC "0" INPUT
N.C. = NOT CONNECTED
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
Quad, Low-Voltage, SPST Analog Switches
ABSOLUTE MAXIMUM RATINGS
ꢀoltages Referenced to GND
Continuous Power Dissipation (T = +70°C) (Note 2)
A
ꢀ+.....................................................................-0.3ꢀ to +13.0ꢀ
ꢀ- .....................................................................-13.0ꢀ to +0.3ꢀ
ꢀ+ to ꢀ- ............................................................-0.3ꢀ to +13.0ꢀ
All Other Pins (Note 1)..........................(ꢀ- - 0.3ꢀ) to (ꢀ+ + 0.3ꢀ)
Continuous Current into Any Terminal.............................. 10mA
Peak Current into Any Terminal
Plastic DIP (derate 10.53mW/°C above +70°C) ..........842mW
Narrow SO (derate 8.70mW/°C above +70°C) ............ꢁ9ꢁmW
QSOP (derate 9.52mW/°C above +70°C)....................7ꢁ2mW
CERDIP (derate 10.00mW/°C above +70°C)...............800mW
TSSOP (derate ꢁ.7mW/°C above +70°C) ....................457mW
QFN (derate 1ꢁ.9mW/°C above +70°C) ....................1349mW
Operating Temperature Ranges
MAX452_C_E......................................................0°C to +70°C
MAX452_E_E ...................................................-40°C to +85°C
MAX452_MJE ................................................-55°C to +125°C
Storage Temperature Range.............................-ꢁ5°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
(pulsed at 1ms,10% duty cycle)................................... 20mA
ESD per Method 3015.7 ..................................................>2000ꢀ
Note 1: Signals on NC_, NO_, COM_, or IN_ exceeding ꢀ+ or ꢀ- are clamped by internal diodes. Limit forward-diode current to maxi-
mum current rating.
Note 2: All leads are soldered or welded to PC boards.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS—ꢁuDl Supplieꢂ
(ꢀ+ = +4.5ꢀ to +5.5ꢀ, ꢀ- = -4.5ꢀ to -5.5ꢀ, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 3)
MAX
PARAMETER
ANALOG SWITCH
SYMBOL
CONꢁITIONS
T
UNITS
A
ꢀ
, ꢀ
NC_
,
COM_ NO_
Analog Signal Range
(Note 4)
C, E, M
ꢀ-
ꢀ+
ꢀ
ꢀ
+25°C
C, E, M
+25°C
ꢁ5
1
100
125
4
COM_ to NO_, COM_ to NC_
On-Resistance
ꢀ+ = 5ꢀ, ꢀ- = -5ꢀ,
3ꢀ, I
R
Ω
ON
ꢀ
=
= 1mA
= 1mA
COM_
COM_
COM_ to NO_, COM_ to NC_
On-Resistance Match Between
Channels (Note 5)
ꢀ+ = 5ꢀ, ꢀ- = -5ꢀ,
3ꢀ, I
ΔR
Ω
Ω
ON
ꢀ
=
COM_
COM_
C, E, M
+25°C
C, E, M
ꢁ
7
12
15
COM_ to NO_, COM_ to NC_
On-Resistance Flatness
(Note ꢁ)
ꢀ+ = 5ꢀ, ꢀ- = -5ꢀ,
3ꢀ, I
R
FLAT(ON)
ꢀ
=
= 1mA
COM_
COM_
+25°C
C, E
M
-1
-10
-100
-1
0.01
0.01
0.01
1
10
100
1
NO_, NC_ Off-Leakage Current
(Note 7)
I
I
,
ꢀ+ = 5.5ꢀ, ꢀ- = -5.5ꢀ,
4.5ꢀ, ꢀ
NO_(OFF)
nA
nA
nA
ꢀ
=
=
N_
4.5ꢀ
4.5ꢀ
NC_(OFF)
COM_
+25°C
C, E
M
COM_ Off-Leakage Current
(Note 7)
ꢀ+ = 5.5ꢀ, ꢀ- = -5.5ꢀ,
4.5ꢀ, ꢀ =
N_
I
-10
-100
-2
10
100
2
COM_(OFF)
ꢀ
=
COM_
+25°C
C, E
M
COM_ On-Leakage Current
(Note 7)
ꢀ+ = 5.5ꢀ, ꢀ- = -5.5ꢀ,
4.5ꢀ
I
-20
-200
20
200
COM_(ON)
ꢀ
=
COM_
2
_______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
ELECTRICAL CHARACTERISTICS—ꢁuDl Supplieꢂ (continued)
(ꢀ+ = +4.5ꢀ to +5.5ꢀ, ꢀ- = -4.5ꢀ to -5.5ꢀ, T = T
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
A
MIN
MIN
TYP
(Note 3)
MAX
PARAMETER
LOGIC INPUT
SYMBOL
CONꢁITIONS
T
UNITS
A
IN_ Input Logic Threshold High
IN_ Input Logic Threshold Low
ꢀ
C, E, M
C, E, M
1.ꢁ
1.ꢁ
2.4
1
ꢀ
ꢀ
IN_H
ꢀ
0.8
-1
IN_L
IN_ Input Current Logic High
or Low
I
, I
ꢀ
ꢀ
= 0.8ꢀ or 2.4ꢀ
C, E, M
0.03
µA
INH_ INL_
IN_
SWITCH ꢁYNAMIC CHARACTERISTICS
+25°C
C, E, M
+25°C
C, E, M
45
15
80
100
30
=
3ꢀ, ꢀ+ = 4.5ꢀ,
COM_
Turn-On Time
Turn-Off Time
t
ns
ns
ns
pC
ON
ꢀ- = -4.5ꢀ, Figure 1
ꢀ
COM_
=
3ꢀ, ꢀ+ = 4.5ꢀ,
t
OFF
ꢀ- = -4.5ꢀ, Figure 1
40
Break-Before-Make Time Delay
(MAX4523 only)
ꢀ
COM_
=
3ꢀ, ꢀ+ = 5.5ꢀ,
t
+25°C
+25°C
5
20
1
BBM
Q
ꢀ- = -5.5ꢀ, Figure 2
C = 1nF, ꢀ
L
Figure 3
= 0, R = 0Ω,
S
NO_
Charge Injection (Note 4)
5
ꢀ
= GND, f = 1MHz,
NO_
NO_, NC_ Off-Capacitance
COM_ Off-Capacitance
COM_ On-Capacitance
C
+25°C
+25°C
+25°C
2
2
5
pF
pF
pF
N_(OFF)
Figure ꢁ
ꢀ
COM_
= GND, f = 1MHz,
C
COM_(OFF)
Figure ꢁ
ꢀ
COM_
= ꢀ
= GND,
NO_
C
COM_(ON)
f = 1MHz, Figure 7
R = 50Ω, C = 15pF,
L
L
Off-Isolation (Note 8)
ꢀ
ꢀ
= 1ꢀ
, f = 100kHz,
+25°C
+25°C
C, E, M
+25°C
C, E, M
+25°C
C, E, M
< -90
< -90
dB
dB
ISO
N_
RMS
Figure 4
R = 50Ω, C = 15pF,
L
L
Channel-to-Channel Crosstalk
(Note 9)
ꢀ
ꢀ
N_
= 1ꢀ
, f = 100kHz,
CT
RMS
Figure 5
POWER SUPPLY
Power-Supply Range
ꢀ+, ꢀ-
I+
-ꢁ
ꢁ
ꢀ
-1
-1
-1
-1
0.05
0.05
1
1
1
1
ꢀ+ Supply Current
ꢀ- Supply Current
ꢀ+ = 5.5ꢀ, all ꢀ
ꢀ- = -5.5ꢀ
= 0 or ꢀ+
µA
IN_
I-
µA
_______________________________________________________________________________________
3
Quad, Low-Voltage, SPST Analog Switches
ELECTRICAL CHARACTERISTICS—Single +±V Supply
(ꢀ+ = +4.5ꢀ to +5.5ꢀ, ꢀ- = 0ꢀ, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 3)
MAX
PARAMETER
SYMBOL
CONꢁITIONS
T
UNITS
A
ANALOG SWITCH
ꢀ
, ꢀ
NC_
,
COM_ NO_
Analog Signal Range
(Note 4)
ꢀ+ = 4.5ꢀ, ꢀ
C, E, M
0
ꢀ+
ꢀ
ꢀ
+25°C
C, E, M
+25°C
125
2
200
250
8
COM_ to NO_, COM_ to NC_
On-Resistance
= 3.5ꢀ,
COM_
R
Ω
ON
I
= 1mA
COM_
COM_ to NO_, COM_ to NC_
On-Resistance Match Between
Channels (Note 5)
ꢀ+ = 5ꢀ, ꢀ
= 3.5ꢀ,
COM_
ΔR
Ω
ON
I
= 1mA
COM_
C, E, M
10
+25°C
C, E
M
-1
-10
-100
-1
0.01
0.01
0.01
1
10
100
1
NO_, NC_ Off-Leakage Current
(Notes 7, 10)
I
I
,
ꢀ+ = 5.5ꢀ; ꢀ
= 1ꢀ, 4.5ꢀ;
= 1ꢀ, 4.5ꢀ;
NO_(OFF)
COM_
nA
nA
nA
ꢀ
N_
= 4.5ꢀ, 1ꢀ
NC_(OFF)
+25°C
C, E
M
COM_ Off-Leakage Current
(Notes 7, 10)
ꢀ+ = 5.5ꢀ; ꢀ
COM_
I
-10
-100
-2
10
100
2
COM_(OFF)
ꢀ
N_
= 4.5ꢀ, 1ꢀ
+25°C
C, E,
M
COM_ On-Leakage Current
(Notes 7, 10)
I
ꢀ+ = 5.5ꢀ; ꢀ
= 4.5ꢀ, 1ꢀ
-20
-200
20
200
COM_(ON)
COM_
LOGIC INPUT
IN_ Input Logic Threshold High
IN_ Input Logic Threshold Low
ꢀ
C, E
C, E
1.ꢁ
1.ꢁ
2.4
1
ꢀ
ꢀ
IN_H
ꢀ
0.8
-1
IN_L
IN_ Input Current Logic High
or Low
I
, I
ꢀ
ꢀ
= 0.8ꢀ or 2.4ꢀ
C, E
0.03
µA
INH_ INL_
IN_
SWITCH ꢁYNAMIC CHARACTERISTICS
+25°C
C, E, M
+25°C
C, E, M
ꢁ0
20
100
150
50
= 3ꢀ, ꢀ+ = 4.5ꢀ,
COM_
Turn-On Time
Turn-Off Time
t
ns
ns
ns
pC
ON
Figure 1
ꢀ
COM_
= 3ꢀ, ꢀ+ = 4.5ꢀ,
t
OFF
Figure 1
ꢀ = 3ꢀ, ꢀ+ = 5.5ꢀ,
COM_
75
Break-Before-Make Time Delay
(MAX4523 only)
t
+25°C
+25°C
10
30
1
BBM
Figure 2
C = 1nF, ꢀ
L
Figure 3
= 0, R = 0Ω,
S
NO_
Charge Injection (Note 4)
POWER SUPPLY
Q
5
+25°C
C, E, M
+25°C
C, E, M
-1
-1
-1
-1
0.05
0.05
1
1
1
1
ꢀ+ Supply Current
I+
I-
ꢀ+ = 5.5ꢀ, all ꢀ
ꢀ- = 0
= 0 or ꢀ+
µA
µA
IN_
ꢀ- Supply Current
4
_______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
ELECTRICAL CHARACTERISTICS—Single +3V Supply
(ꢀ+ = +2.7ꢀ to +3.ꢁꢀ, ꢀ- = 0ꢀ, T = T
A
to T
, unless otherwise noted. Typical values are at T = +25°C.)
MAX A
MIN
MIN
TYP
(Note 3)
MAX
PARAMETER
SYMBOL
CONꢁITIONS
T
UNITS
A
ANALOG SWITCH
ꢀ
, ꢀ
NC_
,
COM_ NO_
Analog Signal Range
(Note 4)
ꢀ+ = 2.7ꢀ, ꢀ
C, E, M
0
ꢀ+
ꢀ
ꢀ
+25°C
2ꢁ0
500
ꢁ00
COM_ to NO_, COM_ to NC_
On-Resistance
= 1.0ꢀ,
COM_
R
Ω
ON
I
= 0.1mA
COM_
C, E, M
LOGIC INPUT
IN_ Input Logic Threshold High
IN_ Input Logic Threshold Low
ꢀ
C, E
C, E
1.ꢁ
1.ꢁ
2.4
1
ꢀ
ꢀ
IN_H
ꢀ
0.8
-1
IN_L
IN_ Input Current Logic High
or Low
I
, I
ꢀ
ꢀ
= 0.8ꢀ or 2.4ꢀ
C, E
0.03
µA
INH_ INL_
IN_
SWITCH ꢁYNAMIC CHARACTERISTICS (Note 4)
+25°C
C, E, M
+25°C
C, E, M
120
40
250
300
80
= 1.5ꢀ, ꢀ+ = 2.7ꢀ,
COM_
Turn-On Time
Turn-Off Time
t
ns
ns
ns
pC
ON
Figure 1
ꢀ
COM_
= 1.5ꢀ, ꢀ+ = 2.7ꢀ,
t
OFF
Figure 1
ꢀ = 1.5ꢀ, ꢀ+ = 3.ꢁꢀ,
COM_
100
Break-Before-Make Time Delay
(MAX4523 only)
t
+25°C
+25°C
15
50
BBM
Figure 2
C = 1nF, ꢀ
L
Figure 3
= 0, R = 0Ω,
S
NO_
Charge Injection
POWER SUPPLY
ꢀ+ Supply Current
Q
0.5
5
+25°C
C, E, M
+25°C
C, E, M
-1
-1
-1
-1
0.05
0.05
1
1
1
1
I+
I-
ꢀ+ = 3.ꢁꢀ, all ꢀ
ꢀ- = 0
= 0 or ꢀ+
µA
µA
IN_
ꢀ- Supply Current
Note 3: The algebraic convention is used in this data sheet; the most negative value is shown in the minimum column.
Note 4: Guaranteed by design.
Note ±: ΔR
= ΔR
- ΔR
.
ON
ON(MAX)
ON(MIN)
Note ꢀ: Resistance flatness is defined as the difference between the maximum and minimum on-resistance values, as measured
over the specified analog signal range.
Note 7: Leakage parameters are 100% tested at maximum rated temperature, and guaranteed by correlation at T = +25°C.
A
Note 8: Off-Isolation = 20log [ ꢀ
/ (ꢀ
or ꢀ
) ], ꢀ
NO_
= output, ꢀ
or ꢀ
= input to off switch.
10
COM_
NC_
COM_
NC_
NO_
Note 9: Between any two switches.
Note 10: Leakage testing for single-supply operation is guaranteed by testing with dual supplies.
_______________________________________________________________________________________
±
Quad, Low-Voltage, SPST Analog Switches
Typical Operating Characteristics
(ꢀ+ = +5ꢀ, ꢀ- = -5ꢀ, GND = 0, T = +25°C, unless otherwise noted.)
A
ON-RESISTANCE vs. V
(DUAL SUPPLIES)
ON-RESISTANCE vs. V
(SINGLE SUPPLY)
ON-RESISTANCE vs. V
TEMPERATURE (DUAL SUPPLIES)
AND
COM
COM
COM
180
160
140
120
100
80
350
300
250
200
150
100
50
110
100
90
V+, V- = 2.0V
V+ = 2.7V
T
= +125°C
= +25°C
A
V+, V- = 3.0V
V+ = 3.3V
80
T
= +85°C
A
70
T
A
60
60
V+, V- = 4.0V
50
V+ = 5.0V
40
T
= 0°C
A
V+, V- = 5.0V
40
30
20
T
= -55°C
A
0
0
-5 -4 -3 -2 -1
V
0
1
2
3
4
5
0
1
2
3
4
5
-5 -4 -3 -2 -1
V
0
1
2
3
4
5
(V)
V
(V)
COM
(V)
COM
COM
ON-RESISTANCE vs. V
TEMPERATURE (SINGLE SUPPLY)
AND
CHARGE INJECTION
COM
ON- AND OFF-LEAKAGE CURRENT
vs. TEMPERATURE
vs. V
COM
2
1
200
180
160
10n
T
= +125°C
A
1n
100p
10p
1p
ON LEAKAGE
140
120
100
80
V+ = +5V
V- = -5V
T
= +85°C
A
T
= +25°C
V+ = +5V
V- = 0V
A
0
T
= 0°C
A
-1
-2
OFF LEAKAGE
T
= -55°C
4
A
60
0.1p
0
1
2
3
5
-5 -4 -3 -2 -1
V
0
1
2
3
4
5
-55
-25
0
25 50 75 100 125
V
(V)
(V)
COM
TEMPERATURE (°C)
COM
TURN-ON/OFF TIME
vs. SUPPLY VOLTAGE
TURN-ON/OFF TIME
vs. TEMPERATURE
POWER-SUPPLY CURRENT
vs. TEMPERATURE
200
180
100
90
1
160
140
120
100
80
80
70
60
50
40
30
20
10
0
0.1
0.01
I+
I-
t
ON
0.001
t
ON
60
t
OFF
40
0.0001
0.00001
t
OFF
20
0
2
3
4
5
6
7
8
9
10 11 12
-55
-25
0
25 50 75 100 125
-55
-25
0
25 50 75 100 125
TEMPERATURE (°C)
TEMPERATURE (°C)
V+ (V)
ꢀ
_______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
Typical Operating Characteristics (continued)
(ꢀ+ = +5ꢀ, ꢀ- = -5ꢀ, GND = 0, T = +25°C, unless otherwise noted.)
A
TOTAL HARMONIC DISTORTION
FREQUENCY RESPONSE
vs. FREQUENCY
100
0
-10
-20
5
V+ = +5V
V- = -5V
600Ω IN AND OUT
0
10
1
-5
INSERTION LOSS
-10
-15
-20
-25
-30
-35
-40
-30
-40
-50
-60
-70
-80
-90
OFF-ISOLATION
0.1
0.01
ON-PHASE
50Ω IN/OUT
0.001
10
100
1k
10k
100k
0.01
0.1
1
10
100 300
FREQUENCY (Hz)
FREQUENCY (MHz)
Pin Description
PIN
NAME
FUNCTION
MAX4±21
TSSOP/SO QFN
MAX4±22
MAX4±23
TSSOP/SO QFN
TSSOP/SO
QFN
1, 1ꢁ, 9, 8 15, 14, 7, ꢁ 1, 1ꢁ, 9, 8 15, 14, 7, ꢁ 1, 1ꢁ, 9, 8 15, 14, 7, ꢁ
IN1–1N4
Logic-Control Digital Input
2, 15, 10, 7 1ꢁ, 13, 8, 5 2, 15, 10, 7 1ꢁ, 13, 8, 5 2, 15, 10, 7 1ꢁ, 13, 8, 5 COM1–COM4 Analog Switch Common* Terminals
Analog Switch Normally Closed
Terminals
3, 14, 11, ꢁ 1, 12, 9, 4
—
—
—
—
—
—
NC1–NC4
NO1–NO4
NO1, NO4
NC2, NC3
Analog Switch Normally Open
Terminals
—
—
—
—
—
—
3, 14, 11, ꢁ 1, 12, 9, 4
Analog Switch Normally Open
Terminals
—
—
—
—
3, ꢁ
1, 4
12, 9
Analog Switch Normally Closed
Terminals
14, 11
Negative Analog Supply-ꢀoltage
Input. Connect to GND for single
supply operation.
4
2
4
2
4
2
ꢀ-
Ground. Connect to digital ground.
(Analog signals have no ground
reference; they are limited to ꢀ+
and ꢀ-.)
5
3
5
3
5
3
GND
N.C.
No Connection. Not internally
connected.
12
10
12
10
12
10
Positive Analog and Digital Supply-
ꢀoltage Input. Internally connected
to substrate.
13
—
11
EP
13
—
11
EP
13
—
11
EP
ꢀ+
EP
Exposed Pad. Connect EP to ꢀ+.
*NO_ (or NC_) and COM_ pins are identical and interchangeable. Either may be considered as an input or output; signals pass
equally well in either direction.
_______________________________________________________________________________________
7
Quad, Low-Voltage, SPST Analog Switches
The logic-level thresholds are CMOS/TTL compatible
Applications Information
Power-Supply Considerations
when ꢀ+ = +5ꢀ. The threshold increases slightly as ꢀ+
is raised, and when ꢀ+ reaches +12ꢀ, the level thresh-
old is about 3.1ꢀ. This is above the TTL output high-
level minimum of 2.8ꢀ, but still compatible with CMOS
outputs.
Overview
The MAX4521/MAX4522/MAX4523 construction is typi-
cal of most CMOS analog switches. They have three
supply pins: ꢀ+, ꢀ-, and GND. ꢀ+ and ꢀ- are used to
drive the internal CMOS switches, and they set the lim-
its of the analog voltage on any switch. Reverse ESD-
protection diodes are internally connected between
each analog-signal pin and both ꢀ+ and ꢀ-. If any ana-
log signal exceeds ꢀ+ or ꢀ-, one of these diodes con-
ducts. During normal operation these reverse-biased
ESD diodes leak, forming the only current drawn from
ꢀ+ or ꢀ-.
Bipolar Supplies
The MAX4521/MAX4522/MAX4523 operate with bipolar
supplies between 2ꢀ and ꢁꢀ. The ꢀ+ and ꢀ- sup-
plies need not be symmetrical, but their sum cannot
exceed the absolute maximum rating of 13.0ꢀ. ꢁo not
connect the MAX4±21/MAX4±22/MAX4±23 V+ to +3V,
Dnd then connect the logic-level-input pinꢂ to TTL
logic-level ꢂignDlꢂ. TTL logic-level outputꢂ in exceꢂꢂ
of the Dbꢂolute mDximum rDtingꢂ cDn dDmDge the
pDrt Dnd/or externDl circuitꢂ.
ꢀirtually all the analog leakage current is through the
ESD diodes. Although the ESD diodes on a given sig-
nal pin are identical and therefore fairly well balanced,
they are reverse biased differently. Each is biased by
either ꢀ+ or ꢀ- and the analog signal. This means their
leakages vary as the signal varies. The difference in the
two diode leakages from the signal path to the ꢀ+ and
ꢀ- pins constitutes the analog-signal-path leakage cur-
rent. All analog leakage current flows to the supply ter-
minals, not to the other switch terminal. This explains
how both sides of a given switch can show leakage
currents of the same or opposite polarity.
CDution: The absolute maximum ꢀ+ to ꢀ- differential
voltage is 13.0ꢀ. Typical ꢁꢀ or 12ꢀ supplies with
10% tolerances can be as high as 13.2ꢀ. This voltage
can damage the MAX4521/MAX4522/MAX4523. Even
5% tolerance supplies may have overshoot or noise
spikes that exceed 13.0ꢀ.
Single Supply
The MAX4521/MAX4522/MAX4523 operate from a
single supply between +2ꢀ and +12ꢀ when ꢀ- is con-
nected to GND. All of the bipolar precautions must be
observed.
There is no connection between the analog-signal
paths and GND. The analog-signal paths consist of an
N-channel and P-channel MOSFET with their sources
and drains paralleled, and their gates driven out of
phase to ꢀ+ and ꢀ- by the logic-level translators.
High-Frequency Performance
In 50Ω systems, signal response is reasonably flat up
to 50MHz (see Typical Operating Characteristics).
Above 20MHz, the on-response has several minor
peaks that are highly layout dependent. The problem
with high-frequency operation is not turning the switch
on, but turning it off. The off-state switch acts like a
capacitor and passes higher frequencies with less
attenuation. At 10MHz, off-isolation is about -52dB in
50Ω systems, becoming worse (approximately 20dB
per decade) as frequency increases. Higher circuit
impedances also make off-isolation worse. Adjacent
channel attenuation is about 3dB above that of a bare
IC socket, and is due entirely to capacitive coupling.
ꢀ+ and GND power the internal logic and logic-level
translators, and set the input logic thresholds. The
logic-level translators convert the logic levels to
switched ꢀ+ and ꢀ- signals to drive the gates of the
analog switches. This drive signal is the only connec-
tion between the logic supplies and the analog sup-
plies. ꢀ+ and ꢀ- have ESD-protection diodes to GND.
The logic-level inputs and output have ESD protection
to ꢀ+ and to GND.
Increasing ꢀ- has no effect on the logic-level thresh-
olds, but it does increase the drive to the P-channel
switches, reducing their on-resistance. ꢀ- also sets the
negative limit of the analog-signal voltage.
8
_______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
Test Circuits/Timing Diagrams
MAX4521
MAX4522
MAX4523
V+
V+
t < 20ns
t < 20ns
f
r
+3V
0
SWITCH
OUTPUT
LOGIC
INPUT
50%
COM
NO
or NC
SWITCH
INPUT
V
COM
V
OUT
R
C
L
35pF
L
t
300Ω
OFF
IN, EN
GND
V
OUT
V-
V-
0.9 x V
0.9 x V
OUT
LOGIC
INPUT
0UT
SWITCH
OUTPUT
0
0
t
ON
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
R
LOGIC INPUT WAVEFORMS INVERTED FOR EN AND SWITCHES
THAT HAVE THE OPPOSITE LOGIC SENSE.
L
V
OUT
= V
COM
(
)
R + R
L
ON
Figure 1. Switching Time
V+
MAX4523
+3V
LOGIC
INPUT
50%
V+
NO
NC
COM1
V
OUT1
0
V
V
COM1
COM2
IN1, 2
R
L1
V
C
L1
OUT2
SWITCH
OUTPUT 1
COM2
0.9 x V
0UT1
0
0
(V
OUT1
)
R
L2
C
L2
SWITCH
OUTPUT 2
LOGIC
INPUT
GND
V-
V-
0.9 x V
OUT2
(V
)
OUT2
R = 300Ω
L
t
D
t
D
C = 35pF
L
C INCLUDES FIXTURE AND STRAY CAPACITANCE.
L
Figure 2. Break-Before-Make Interval (MAX4523 only)
MAX4521
MAX4522
V+
ΔV
OUT
MAX4523
V+
V
OUT
R
GEN
COM
NC or
NO
V
OUT
IN
OFF
OFF
OFF
OFF
C
L
V
GEN
ON
ON
V-
V-
GND
IN
IN
Q = (ΔV )(C )
OUT
L
V
= +3V
IN
IN DEPENDS ON SWITCH CONFIGURATION;
INPUT POLARITY DETERMINED BY SENSE OF SWITCH.
Figure 3. Charge Injection
_______________________________________________________________________________________
9
Quad, Low-Voltage, SPST Analog Switches
Test Circuits/Timing Diagrams (continued)
MAX4521
MAX4522
MAX4523
V+
V+
MAX4521
MAX4522
MAX4523
V+
V+
10nF
COM
10nF
SIGNAL
GENERATOR 0dBm
COM
0 or
2.4V
IN
0 or
2.4V
IN
CAPACITANCE
METER
NC
or NO
NC
ANALYZER
or NO
f = 1MHz
GND
V-
GND
V-
V-
10nF
10nF
R
L
V-
Figure 4. Off-Isolation
Figure 6. Channel Off-Capacitance
MAX4521
MAX4522
MAX4523
MAX4521
MAX4522
MAX4523
V+
10nF
V+
V+
10nF
SIGNAL
GENERATOR 0dBm
V+
50Ω
COM
N01
IN2
COM1
CAPACITANCE
METER
IN1
IN
0 or
2.4V
0 or 2.4V
0 or 2.4V
f = 1MHz
NC
COM2
N02
or NO
ANALYZER
NC
GND
V-
10nF
GND
V-
10nF
R
L
V-
V-
Figure 5. Crosstalk
Figure 7. Channel On-Capacitance
10 ______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
Ordering Information (continued)
Chip Topography
PIN-
PACKAGE
PKG
COꢁE
PART
TEMP RANGE
"B"
GND
V-
"A"
MAX4521EPE -40°C to +85°C 1ꢁ Plastic DIP
MAX4521ESE -40°C to +85°C 1ꢁ Narrow SO
MAX4521EEE -40°C to +85°C 1ꢁ QSOP
MAX4521EUE -40°C to +85°C 1ꢁ TSSOP
MAX4521EGE -40°C to +85°C 1ꢁ QFN-EP**
MAX4521MJE -55°C to +125°C 1ꢁ CERDIP***
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
J1ꢁ-3
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
—
COM4
IN4
COM1
IN1
MAX4±22CPE
MAX4522CSE
MAX4522CEE
MAX4522CUE
MAX4522CGE
MAX4522C/D
0°C to +70°C 1ꢁ Plastic DIP
0°C to +70°C 1ꢁ Narrow SO
0°C to +70°C 1ꢁ QSOP
0°C to +70°C 1ꢁ TSSOP
0°C to +70°C 1ꢁ QFN-EP**
IN3
IN2
0°C to +70°C
Dice*
COM2
COM3
MAX4522EPE -40°C to +85°C 1ꢁ Plastic DIP
MAX4522ESE -40°C to +85°C 1ꢁ Narrow SO
MAX4522EEE -40°C to +85°C 1ꢁ QSOP
MAX4522EUE -40°C to +85°C 1ꢁ TSSOP
MAX4522EGE -40°C to +85°C 1ꢁ QFN-EP**
MAX4522MJE -55°C to +125°C 1ꢁ CERDIP***
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
J1ꢁ-3
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
—
0.057"
(1.45mm)
MAX4±23CPE
MAX4523CSE
MAX4523CEE
MAX4523CUE
MAX4523CGE
MAX4523C/D
0°C to +70°C 1ꢁ Plastic DIP
0°C to +70°C 1ꢁ Narrow SO
0°C to +70°C 1ꢁ QSOP
"C"
V+
"D"
0.046"
(1.19mm)
0°C to +70°C 1ꢁ TSSOP
0°C to +70°C 1ꢁ QFN-EP**
MAX4±21
MAX4±22
MAX4±23
0°C to +70°C
Dice*
MAX4523EPE -40°C to +85°C 1ꢁ Plastic DIP
MAX4523ESE -40°C to +85°C 1ꢁ Narrow SO
MAX4523EEE -40°C to +85°C 1ꢁ QSOP
MAX4523EUE -40°C to +85°C 1ꢁ TSSOP
MAX4523EGE -40°C to +85°C 1ꢁ QFN-EP**
MAX4523MJE -55°C to +125°C 1ꢁ CERDIP***
P1ꢁ-1
S1ꢁ-2
E1ꢁ-4
U1ꢁ-2
G1ꢁ44-1
J1ꢁ-3
PIN
NAME
PIN
NAME
PIN
NAME
A
B
C
D
NC1
A
B
C
D
NO1
NO4
NO3
NO2
A
NO1
NC4
NC3
NC2
B
C
D
NO4
NC3
NC2
*Contact factory for dice specifications.
**EP = Exposed pad.
***Contact factory for availability.
SUBSTRATE CONNECTED TO ꢀ+
______________________________________________________________________________________ 11
Quad, Low-Voltage, SPST Analog Switches
Pin Configurations
TOP VIEW
COM1
16
IN1
15
IN2
14
COM2
13
COM1
16
IN1
15
IN2
14
COM2
13
COM1
16
IN1
15
IN2
14
COM2
13
NC1
V-
1
2
3
4
12 NC2 NO1
1
2
3
4
12 NO2 NO1
1
2
3
4
12 NC2
11 V+
11 V+
V-
11 V+
V-
MAX4521
MAX4522
MAX4523
GND
NC4
10 N.C. GND
10 N.C. GND
10 N.C.
*EP
*EP
*EP
9
9
9
NC3 NO4
NO3 NO4
NC3
5
6
7
8
5
6
7
8
5
6
7
8
COM4
IN4
IN3
COM3
COM4
IN4
IN3
COM3
COM4
IN4
IN3
COM3
QFN
QFN
QFN
*EP = Exposed Pad, connect EP to V+
12 ______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.mDxim-ic.com/pDckDgeꢂ.)
PACKAGE OUTLINE, QSOP .150", .025" LEAD PITCH
1
21-0055
F
1
INCHES
MILLIMETERS
DIM
A
MIN
MAX
0.069
0.010
0.019
0.010
MIN
1.35
0.10
0.35
0.19
MAX
1.75
0.25
0.49
0.25
0.053
0.004
0.014
0.007
N
A1
B
C
e
0.050 BSC
1.27 BSC
E
0.150
0.228
0.016
0.157
0.244
0.050
3.80
5.80
0.40
4.00
6.20
1.27
E
H
H
L
VARIATIONS:
INCHES
1
MILLIMETERS
DIM
D
MIN
MAX
0.197
0.344
0.394
MIN
4.80
8.55
9.80
MAX
5.00
N
8
MS012
AA
TOP VIEW
0.189
0.337
0.386
D
8.75 14
10.00 16
AB
D
AC
D
C
A
B
0∞-8∞
e
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
REV.
1
21-0041
B
1
______________________________________________________________________________________ 13
Quad, Low-Voltage, SPST Analog Switches
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.mDxim-ic.com/pDckDgeꢂ.)
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
1
21-0106
E
2
PACKAGE OUTLINE
12,16,20,24L QFN, 4x4x0.90 MM
2
21-0106
E
2
14 ______________________________________________________________________________________
Quad, Low-Voltage, SPST Analog Switches
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.mDxim-ic.com/pDckDgeꢂ.)
PACKAGE OUTLINE, TSSOP 4.40mm BODY
1
21-0066
I
1
Revision History
Pages changed at Rev ꢁ: 1, 7, 11, 12, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
1± __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2007 Maxim Integrated Products
is a registered trademark of Maxim Integrated Products, Inc.
ENGL ISH • ? ? ? ? • ? ? ? • ? ? ?
WH AT 'S NEW
PR OD UC TS
SO LUTI ONS
D ES IG N
A PPNOTES
SU PPORT
B U Y
COM PA N Y
M EMB ERS
M A X 4 5 2 2
Pa rt Nu m ber T abl e
N o t e s :
1 . S e e t h e M A X 4 5 2 2 Q u i c k V i e w D a t a S h e e t f o r f u r t h e r i n f o r m a t i o n o n t h i s p r o d u c t f a m i l y o r d o w n l o a d t h e
M A X 4 5 2 2 f u l l d a t a s h e e t ( P D F , 8 9 2 k B ) .
2 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
3 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n
o n e b u s i n e s s d a y .
4 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e f u l l
d a t a s h e e t o r P a r t N a m i n g C o n v e n t i o n s .
5 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e
p r o d u c t u s e s .
P a r t N u m b e r
F r e e
S a m p l e
B u y
D i r e c t
T e m p
R o H S / L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : T Y P E P I N S S I Z E
D R A W I N G C O D E / V A R *
M A X 4 5 2 2 M J E
- 5 5 C t o + 1 2 5 C R o H S / L e a d - F r e e : N o
R o H S / L e a d - F r e e : N o
M A X 4 5 2 2 C / D
M A X 4 5 2 2 C P E +
M A X 4 5 2 2 E P E +
M A X 4 5 2 2 C P E
M A X 4 5 2 2 E P E
M A X 4 5 2 2 E G E
P D I P ; 1 6 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 1 6 + 1 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
P D I P ; 1 6 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 1 6 - 1 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
P D I P ; 1 6 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 1 6 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
Q F N ; 1 6 p i n ; 4 x 4 x 0 . 9 m m
D w g : 2 1 - 0 1 0 6 E ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : G 1 6 4 4 - 1 *
M A X 4 5 2 2 E G E - T
M A X 4 5 2 2 C E E +
M A X 4 5 2 2 C E E + T
M A X 4 5 2 2 C E E
Q F N ; 1 6 p i n ; 4 x 4 x 0 . 9 m m
D w g : 2 1 - 0 1 0 6 E ( P D F )
U s e p k g c o d e / v a r i a t i o n : G 1 6 4 4 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 + 4 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 + 4 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 - 4 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 4 5 2 2 C E E - T
M A X 4 5 2 2 E E E
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 - 4 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : E 1 6 - 4 *
M A X 4 5 2 2 E E E - T
M A X 4 5 2 2 E E E + T
M A X 4 5 2 2 E E E +
M A X 4 5 2 2 C S E +
M A X 4 5 2 2 C S E + T
M A X 4 5 2 2 C S E
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 - 4 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
Q S O P ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 5 5 F ( P D F )
U s e p k g c o d e / v a r i a t i o n : E 1 6 + 4 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 + 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
R o H S / L e a d - F r e e : Y e s
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 4 5 2 2 C S E - T
M A X 4 5 2 2 E S E + T
M A X 4 5 2 2 E S E
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 + 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 4 5 2 2 E S E - T
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 4 5 2 2 E S E +
M A X 4 5 2 2 C U E +
M A X 4 5 2 2 C U E + T
M A X 4 5 2 2 E U E + T
M A X 4 5 2 2 E U E +
M A X 4 5 2 2 C U E
S O I C ; 1 6 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 1 6 + 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
T S S O P ; 1 6 p i n ; 4 . 4 m m
D w g : 2 1 - 0 0 6 6 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 1 6 + 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
R o H S / L e a d - F r e e : Y e s
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
T S S O P ; 1 6 p i n ; 4 . 4 m m
D w g : 2 1 - 0 0 6 6 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 1 6 + 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
T S S O P ; 1 6 p i n ; 4 . 4 m m
D w g : 2 1 - 0 0 6 6 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 1 6 - 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 4 5 2 2 C U E - T
M A X 4 5 2 2 E U E - T
M A X 4 5 2 2 E U E
T S S O P ; 1 6 p i n ; 4 . 4 m m
D w g : 2 1 - 0 0 6 6 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 1 6 - 2 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
T S S O P ; 1 6 p i n ; 4 . 4 m m
D w g : 2 1 - 0 0 6 6 I ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : U 1 6 - 2 *
D i d n ' t F i n d W h a t Y o u N e e d ?
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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