MAX5048AAUT [ROCHESTER]
7.6 A BUF OR INV BASED MOSFET DRIVER, PDSO6, MO-178AB, SOT-23, 6 PIN;
| 型号： | MAX5048AAUT |
| 厂家： | 
Rochester Electronics |
| 描述： | 7.6 A BUF OR INV BASED MOSFET DRIVER, PDSO6, MO-178AB, SOT-23, 6 PIN 驱动 信息通信管理 光电二极管 接口集成电路 驱动器 |
| 文件： | 总14页 (文件大小：1408K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-2419; Rev 4; 7/05
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
General Description
Features
♦ Independent Source-and-Sink Outputs for
The MAX5048A/MAX5048B are high-speed MOSFET
drivers capable of sinking/sourcing 7.6A/1.3A peak cur-
rents. These devices take logic input signals and drive
a large external MOSFET. The MAX5048A/MAX5048B
have inverting and noninverting inputs that give the
user greater flexibility in controlling the MOSFET. They
feature two separate outputs working in complementary
mode, offering flexibility in controlling both turn-on and
turn-off switching speeds.
Controllable Rise and Fall Times
♦ +4V to +12.6V Single Power Supply
♦ 7.6A/1.3A Peak Sink/Source Drive Current
♦ 0.23Ω Open-Drain n-Channel Sink Output
♦ 2Ω Open-Drain p-Channel Source Output
♦ 12ns (typ) Propagation Delay
The MAX5048A/MAX5048B have internal logic circuitry,
which prevents shoot-through during output state
changes. The logic inputs are protected against volt-
age spikes up to +14V, regardless of V+ voltage.
Propagation delay time is minimized and matched
between the inverting and noninverting inputs. The
MAX5048A/MAX5048B have very fast switching times
combined with very short propagation delays (12ns
typ), making them ideal for high-frequency circuits.
♦ Matching Delay Time Between Inverting and
Noninverting Inputs
♦ V /2 CMOS (MAX5048A)/TTL (MAX5048B) Logic
CC
Inputs
♦ 1.6V Input Hysteresis
♦ Up to +14V Logic Inputs (Regardless of V+
Voltage)
The MAX5048A/MAX5048B operate from a +4V to +12.6V
single power supply and typically consume 0.95mA of
supply current. The MAX5048A has CMOS input logic
levels, while the MAX5048B has standard TTL input logic
levels. These devices are available in space-saving
6-pin SOT23 and TDFN packages.
♦ Low Input Capacitance: 2.5pF (typ)
♦ -40°C to +125°C Operating Temperature Range
♦ 6-Pin SOT23 and TDFN Packages
Ordering Information
Applications
PIN-
LOGIC TOP
PART
TEMP RANGE
PACKAGE INPUT MARK
Power MOSFET Switching
Switch-Mode Power Supplies
DC-DC Converters
V
/2
CC
MAX5048AAUT-T -40°C to +125°C 6 SOT23-6
ABEC
CMOS
MAX5048BAUT-T -40°C to +125°C 6 SOT23-6 TTL ABED
Motor Control
V
/2
CC
MAX5048AATT-T -40°C to +125°C 6 TDFN-6
MAX5048BATT-T -40°C to +125°C 6 TDFN-6
AKV
CMOS
Power-Supply Modules
TTL
AKW
Typical Operating Circuit
Pin Configurations
TOP VIEW
V+
V+
P_OUT
V+
P_OUT
N_OUT
1
2
3
6
5
4
IN+
IN-
MAX5048A
MAX5048B
MAX5048A
MAX5048B
IN+
IN-
N_OUT
N
GND
GND
SOT23
Pin Configurations continued at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
ABSOLUTE MAXIMUM RATINGS
Voltages Referenced to GND
Junction to Case Thermal Resistance, θ (SOT23)....75°C/W
JC
V+...........................................................................-0.3V to +13V
IN+, IN-...................................................................-0.3V to +14V
N_OUT, P_OUT ............................................-0.3V to (V+ + 0.3V)
N_OUT Continuous Output Current (Note 1) ....................390mA
P_OUT Continuous Output Current (Note 1).....................100mA
6-Pin TDFN (derate 18.2mW/°C above +70°C) .........1454mW
Junction to Case Thermal Resistance, θ (TDFN) ....8.5°C/W
JC
Operating Temperature Range .........................-40°C to +125°C
Storage Temperature Range.............................-65°C to +150°C
Junction Temperature......................................................+150°C
Lead Temperature (soldering, 10s) .................................+300°C
Continuous Power Dissipation* (T = +70°C)
A
6-Pin SOT23 (derate 9.1mW/°C above +70°C)............727mW
Note 1: Continuous output current is limited by the power dissipation of the package.
*As per JEDEC51 standard.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V+ = +12V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER SUPPLY
V+ Operating Range
V+
4.0
12.6
4.00
V
V
V+ Undervoltage Lockout
UVLO
V+ rising
3.25
3.6
V+ Undervoltage Lockout
Hysteresis
400
mV
V+ Undervoltage Lockout to
Output Delay Time
V+ rising
300
ns
V+ Supply Current
I+
IN+ = IN- = V+
0.95
1.5
mA
n-CHANNEL OUTPUT
T
T
T
T
= +25°C
0.23
0.38
0.24
0.40
0.31
0.46
0.32
0.48
3.3
0.26
0.43
0.28
0.47
0.34
0.51
0.36
0.55
10
A
A
A
A
A
V+ = +10V,
Driver Output Resistance—
Pulling Down (MAX5048AAUT/
MAX5048BAUT)
I
= -100mA
N-OUT
= +125°C
= +25°C
= +125°C
= +25°C
= +125°C
= +25°C
= +125°C
R
R
Ω
Ω
ON-N
V+ = +4.5V,
= -100mA
I
N-OUT
T
T
T
T
V+ = +10V,
= -100mA
Driver Output Resistance—
Pulling Down (MAX5048AATT/
MAX5048BATT)
I
N-OUT
A
A
A
ON-N
V+ = +4.5V,
= -100mA
I
N-OUT
Power-Off Pulldown Resistance
V+ = 0 or floating, I
V+ = 0 or floating, I
= -10mA, T = +25°C
A
Ω
N-OUT
N-OUT
Power-Off Pulldown Clamp
Voltage
= -10mA,
0.85
1.0
20
V
T
A
= +25°C
Output Leakage Current
Peak Output Current (Sinking)
p-CHANNEL OUTPUT
I
I
N_OUT = V+
6.85
7.6
µA
A
LK-N
PK-N
C = 10,000pF
L
T
A
T
A
T
A
T
A
= +25°C
= +125°C
= +25°C
= +125°C
2.00
2.85
2.20
3.10
3.00
4.30
3.30
4.70
V+ = +10V,
Driver Output Resistance—
Pulling Up (MAX5048AAUT/
MAX5048BAUT)
I
= 50mA
P-OUT
R
ON-P
Ω
V+ = +4.5V,
= 50mA
I
P-OUT
2
_______________________________________________________________________________________
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
ELECTRICAL CHARACTERISTICS (continued)
(V+ = +12V, T = -40°C to +125°C, unless otherwise noted. Typical values are at T = +25°C.) (Note 2)
A
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
2.08
2.93
2.28
3.18
0.001
1.3
MAX
3.08
4.38
3.38
4.78
10
UNITS
T
A
T
A
T
A
T
A
= +25°C
V+ = +10V,
= 50mA
Driver Output Resistance—
Pulling Up (MAX5048AATT/
MAX5048BATT)
I
P-OUT
= +125°C
= +25°C
= +125°C
R
ON-P
Ω
V+ = +4.5V,
= 50mA
I
P-OUT
Output Leakage Current
Peak Output Current (Sourcing)
LOGIC INPUT
I
P_OUT = 0
µA
A
LK-P
I
C = 10,000pF
L
PK-P
MAX5048A
MAX5048B
MAX5048A
MAX5048B
MAX5048A
MAX5048B
0.67 x V+
2.4
Logic 1 Input Voltage
Logic 0 Input Voltage
Logic-Input Hysteresis
V
V
V
V
IH
0.33 x V+
0.8
V
IL
1.6
0.68
0.001
2.5
V
HYS
Logic-Input Current
Input Capacitance
V
= V+ or 0
10
µA
pF
IN_
C
IN
SWITCHING CHARACTERISTICS FOR V+ = +10V
C = 1000pF
L
8
45
Rise Time
Fall Time
t
ns
ns
C = 5000pF
L
R
C = 10,000pF
82
L
C = 1000pF
L
3.2
7.5
12.5
12
t
C = 5000pF
L
F
C = 10,000pF
L
Turn-On Propagation Delay Time
Turn-Off Propagation Delay Time
Break-Before-Make Time
t
Figure 1, C = 1000pF (Note 3)
7
7
25
25
ns
ns
ns
D-ON
L
t
Figure 1, C = 1000pF (Note 3)
12
D-OFF
L
2.5
SWITCHING CHARACTERISTICS FOR V+ = +4.5V
C = 1000pF
12
41
L
Rise Time
t
C = 5000pF
L
ns
ns
R
C = 10,000pF
74
L
C = 1000pF
L
3.0
7.0
11.3
14
Fall Time
t
C = 5000pF
L
F
C = 10,000pF
L
Turn-On Propagation Delay Time
Turn-Off Propagation Delay Time
Break-Before-Make Time
t
Figure 1, C = 1000pF (Note 3)
8
8
27
27
ns
ns
ns
D-ON
L
t
Figure 1, C = 1000pF (Note 3)
14
D-OFF
L
4.2
Note 2: All DC specifications are 100% tested at T = +25°C. Specifications over -40°C to +125°C are guaranteed by design.
A
Note 3: Guaranteed by design, not production tested.
_______________________________________________________________________________________
3
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Typical Operating Characteristics
(C = 1000pF, T = +25°C, unless otherwise noted.)
L
A
PROPAGATION DELAY TIME, LOW-TO-HIGH
vs. SUPPLY VOLTAGE
RISE TIME vs. SUPPLY VOLTAGE
FALL TIME vs. SUPPLY VOLTAGE
20
17
14
11
8
6.0
20
18
16
14
12
10
T
= +85°C
T
= +125°C
A
A
T = +125°C
A
5.5
5.0
4.5
4.0
3.5
T
= +125°C
A
T = +85°C
A
T
= +85°C
T
= +25°C
A
T
= -40°C
A
A
T
= 0°C
A
T
= 0°C
A
T
= +25°C
A
T
= -40°C
A
T = -40°C
A
T
= 0°C
T
= +25°C
A
A
3.0
2.5
2.0
5
4
6
8
10
12
4
6
8
10
12
4
6
8
10
12
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
PROPAGATION DELAY TIME, HIGH-TO-LOW
vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. SUPPLY VOLTAGE
SUPPLY CURRENT vs. LOAD CAPACITANCE
20
18
16
14
12
10
12
10
8
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
V+ = +10V
f = 100kHz
DUTY CYCLE = 50%
DUTY CYCLE = 50%
V+ = +10V, C = 0
L
T
= +125°C
A
T
= +85°C
A
1MHz
T
= 0°C
T
= -40°C
T
= +25°C
A
A
A
6
500kHz
4
100kHz
75kHz
2
0
4
6
8
10
12
4
6
8
10
12
0
400
800
1200
1600
2000
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
LOAD CAPACITANCE (pF)
MAX5048A
INPUT THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX5048A
SUPPLY CURRENT vs. INPUT VOLTAGE
SUPPLY CURRENT vs. TEMPERATURE
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
1.8
1.7
1.6
1.5
1.4
1.3
1.2
8
7
6
5
4
3
2
1
0
V+ = +10V
f = 100kHz, C = 0
L
INPUT
HIGH-TO-LOW
INPUT
LOW-TO-HIGH
DUTY CYCLE = 50%
RISING
FALLING
0
2
4
6
8
10
12
-50 -25
0
25
50
75 100 125
4
6
8
10
12
INPUT VOLTAGE (V)
TEMPERATURE (°C)
SUPPLY VOLTAGE (V)
4
_______________________________________________________________________________________
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Typical Operating Characteristics (continued)
(C = 1000pF, T = +25°C, unless otherwise noted.)
L
A
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, C = 5000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, C = 10,000pF)
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, C = 5000pF)
MAX5048 toc12
L
L
L
MAX5048 toc10
MAX5048 toc11
IN+
IN+
2V/div
2V/div
IN+
2V/div
OUTPUT
2V/div
OUTPUT
2V/div
OUTPUT
2V/div
20ns/div
20ns/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
INPUT VOLTAGE vs. OUTPUT VOLTAGE
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +4V, C = 10,000pF)
(V+ = +12V, C = 5000pF)
(V+ = +12V, C = 10,000pF)
L
MAX5048 toc15
L
L
MAX5048 toc13
MAX5048 toc14
IN+
IN+
5V/div
5V/div
IN+
2V/div
OUTPUT
2V/div
OUTPUT
5V/div
OUTPUT
5V/div
20ns/div
20ns/div
20ns/div
INPUT VOLTAGE vs. OUTPUT VOLTAGE
INPUT VOLTAGE vs. OUTPUT VOLTAGE
(V+ = +12V, C = 5000pF)
(V+ = +12V, C = 10,000pF)
L
MAX5048 toc17
L
MAX5048 toc16
IN+
IN+
5V/div
5V/div
OUTPUT
5V/div
OUTPUT
5V/div
20ns/div
20ns/div
_______________________________________________________________________________________
5
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Undervoltage Lockout (UVLO)
Pin Description
When V+ is below the UVLO threshold, the N-channel
is ON and the P-channel is OFF, independent of the
state of the inputs. The UVLO is typically 3.6V with
400mV typical hysteresis to avoid chattering.
PIN
NAME
FUNCTION
Power Supply. Bypass to GND with a
0.1µF ceramic capacitor.
1
V+
p-Channel Open-Drain Output. Sources
current for MOSFET turn-on.
Driver Outputs
The MAX5048A/MAX5048B provide two separate out-
puts. One is an open-drain P-channel, the other an
open-drain N-channel. They have distinct current sourc-
ing/sinking capabilities to independently control the rise
and fall times of the MOSFET gate. Add a resistor in
series with P_OUT/N_OUT to slow the corresponding
rise/fall time of the MOSFET gate.
2
P_OUT
n-Channel Open-Drain Output. Sinks
current for MOSFET turn-off.
3
4
5
N_OUT
GND
IN-
Ground
Inverting Logic Input Terminal. Connect
to GND when not used.
Noninverting Logic Input Terminal.
Connect to V+ when not used.
Applications Information
Supply Bypassing, Device Grounding,
and Placement
6
IN+
EP
Exposed paddle. Connect to GND.
Solder EP to the GND plane for
improved thermal performance.
—
Ample supply bypassing and device grounding are
extremely important because when large external
capacitive loads are driven, the peak current at the V+
pin can approach 1.3A, while at the GND pin the peak
Detailed Description
current can approach 7.6A. V
drops and ground
CC
Logic Inputs
shifts are forms of negative feedback for inverters and, if
excessive, can cause multiple switching when the IN-
input is used and the input slew rate is low. The device
driving the input should be referenced to the
MAX5048A/MAX5048B GND pin especially when the IN-
input is used. Ground shifts due to insufficient device
grounding may disturb other circuits sharing the same
AC ground return path. Any series inductance in the V+,
P_OUT, N_OUT and/or GND paths can cause oscilla-
tions due to the very high di/dt that results when the
MAX5048A/MAX5048B are switched with any capacitive
load. A 0.1µF or larger value ceramic capacitor is rec-
ommended bypassing V+ to GND and placed as close
to the pins as possible. When driving very large loads
(e.g., 10nF) at minimum rise time, 10µF or more of paral-
lel storage capacitance is recommended. A ground
plane is highly recommended to minimize ground return
resistance and series inductance. Care should be taken
to place the MAX5048A/MAX5048B as close as possi-
ble to the external MOSFET being driven to further mini-
mize board inductance and AC path resistance.
The MAX5048A/MAX5048Bs’ logic inputs are protected
against voltage spikes up to +14V, regardless of the V+
voltage. The low 2.5pF input capacitance of the inputs
reduces loading and increases switching speed. These
devices have two inputs that give the user greater flexi-
bility in controlling the MOSFET. Table 1 shows all pos-
sible input combinations.
The difference between the MAX5048A and the
MAX5048B is the input threshold voltage. The
MAX5048A has V /2 CMOS logic-level thresholds,
CC
while the MAX5048B has TTL logic-level thresholds (see
the Electrical Characteristics). For V+ above 5.5V, V
IH
(typ) = 0.5x(V+) + 0.8V and V (typ) = 0.5x(V+) - 0.8V.
IL
As V+ is reduced from 5.5V to 4V, V and V gradually
IH
IL
approach V (typ) = 0.5x(V+) + 0.65V and V (typ) =
IH
IL
0.5x(V+) - 0.65V. Connect IN+ to V+ or IN- to GND
when not used. Alternatively, the unused input can be
used as an ON/OFF pin (see Table 1).
Table 1. Truth Table
IN+
L
IN-
L
p-CHANNEL
OFF
n-CHANNEL
Power Dissipation
Power dissipation of the MAX5048A/MAX5048B con-
sists of three components, caused by the quiescent
current, capacitive charge and discharge of internal
nodes, and the output current (either capacitive or
resistive load). The sum of these components must be
kept below the maximum power-dissipation limit.
ON
ON
OFF
ON
L
H
L
OFF
H
ON
H
H
OFF
L = Logic low
H = Logic high
6
_______________________________________________________________________________________
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
IN+
V
IH
V
IL
P_OUT AND
N_OUT
TIED
TOGETHER
90%
10%
t
t
t
t
R
D–OFF
F
D–ON
TIMING DIAGRAM
V+
V+
MAX5048A
MAX5048B
P_OUT
IN+
IN-
INPUT
OUTPUT
N_OUT
C
L
GND
TEST CIRCUIT
Figure 1. Timing Diagram and Test Circuit
The quiescent current is 0.95mA typical. The current
required to charge and discharge the internal nodes is
frequency dependent (see the Typical Operating
Characteristics). The MAX5048A/MAX5048B power dis-
sipation when driving a ground referenced resistive
load is:
following PC board layout guidelines are recommended
when designing with the MAX5048A/MAX5048B:
• Place one or more 0.1µF decoupling ceramic capaci-
tor(s) from V+ to GND as close to the device as possi-
ble. At least one storage capacitor of 10µF (min)
should be located on the PC board with a low resis-
tance path to the V+ pin of the MAX5048A/MAX5048B.
2
P = D x R
x I
LOAD
ON(MAX)
where D is the fraction of the period the MAX5048A/
MAX5048Bs’ output pulls high, R is the maxi-
• There are two AC current loops formed between the
device and the gate of the MOSFET being driven.
The MOSFET looks like a large capacitance from
gate to source when the gate is being pulled low.
The active current loop is from N_OUT of the
MAX5048A/MAX5048B to the MOSFET gate to the
MOSFET source and to GND of the MAX5048A/
MAX5048B. When the gate of the MOSFET is being
pulled high, the active current loop is from P_OUT of
the MAX5048A/MAX5048B to the MOSFET gate to
the MOSFET source to the GND terminal of the
decoupling capacitor to the V+ terminal of the
decoupling capacitor and to the V+ terminal of the
MAX5048A/MAX5048B. While the charging current
loop is important, the discharging current loop is crit-
ical. It is important to minimize the physical distance
and the impedance in these AC current paths.
ON (MAX)
mum on-resistance of the device with the output high
(P-channel), and I is the output load current of the
LOAD
MAX5048A/MAX5048B.
For capacitive loads, the power dissipation is:
2
P = C
x (V+) x FREQ
LOAD
where C
is the capacitive load, V+ is the supply
LOAD
voltage, and FREQ is the switching frequency.
Layout Information
The MOSFET drivers MAX5048A/MAX5048B source-
and-sink large currents to create very fast rise and fall
edges at the gate of the switching MOSFET. The high
di/dt can cause unacceptable ringing if the trace
lengths and impedances are not well controlled. The
_______________________________________________________________________________________
7
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
• In a multilayer PC board, the component surface
Chip Information
layer surrounding the MAX5048A/MAX5048B should
consist of a GND plane containing the discharging
and charging current loops.
TRANSISTOR COUNT: 676
PROCESS: BiCMOS
V
S
V+
MAX5048A
MAX5048B
V+
(4V TO 12.6V)
P
V+
P_OUT
BREAK-
BEFORE-
MAKE
P_OUT
N_OUT
IN-
IN+
MAX5048A
MAX5048B
CONTROL
IN+
IN-
N_OUT
N
GND
GND
Figure 2. MAX5048A/MAX5048B Functional Diagram
Figure 3. Noninverting Application
4V TO 12V
V
S
V+
IN+
P_OUT
P
MAX5048A/
MAX5048B
N_OUT
V+
(4V TO 12.6V)
IN-
IN+
V
OUT
V+
P_OUT
GND
V+
FROM PWM
CONTROLLER
(BUCK)
MAX5048A
MAX5048B
V
OUT
FROM PWM
CONTROLLER
(BOOST)
IN+
IN-
N_OUT
P_OUT
MAX5048A
MAX5048B
GND
N_OUT
N
IN-
GND
Figure 4. Boost Converter
Figure 5. MAX5048A/MAX5048B in High-Power Synchronous
Buck Converter
8
_______________________________________________________________________________________
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Pin Configurations (continued)
TOP VIEW
V+
P_OUT
N_OUT
1
2
3
6
5
4
IN+
IN-
MAX5048A
MAX5048B
GND
EXPOSED PAD
TDFN
3mm x 3mm
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, SOT 6L BODY
1
21-0058
G
1
_______________________________________________________________________________________
9
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
D2
D
A2
PIN 1 ID
N
0.35x0.35
b
[(N/2)-1] x e
REF.
PIN 1
INDEX
AREA
E
E2
DETAIL A
e
A1
k
C
C
L
L
A
L
L
e
e
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
1
-DRAWING NOT TO SCALE-
21-0137
G
2
10 ______________________________________________________________________________________
7.6A, 12ns, SOT23/TDFN, MOSFET Driver
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
SYMBOL
MIN.
0.70
2.90
2.90
0.00
0.20
MAX.
0.80
3.10
3.10
0.05
0.40
A
D
E
A1
L
k
0.25 MIN.
0.20 REF.
A2
PACKAGE VARIATIONS
DOWNBONDS
ALLOWED
PKG. CODE
T633-1
N
6
D2
E2
e
JEDEC SPEC
MO229 / WEEA
MO229 / WEEA
MO229 / WEEC
MO229 / WEEC
MO229 / WEEC
b
[(N/2)-1] x e
1.90 REF
1.90 REF
1.95 REF
1.95 REF
1.95 REF
2.00 REF
2.40 REF
2.40 REF
1.50±0.10 2.30±0.10 0.95 BSC
1.50±0.10 2.30±0.10 0.95 BSC
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
1.50±0.10 2.30±0.10 0.65 BSC
0.40±0.05
0.40±0.05
0.30±0.05
0.30±0.05
0.30±0.05
NO
NO
T633-2
6
T833-1
8
NO
T833-2
8
NO
T833-3
8
YES
NO
T1033-1
T1433-1
T1433-2
10
14
14
1.50±0.10 2.30±0.10 0.50 BSC MO229 / WEED-3 0.25±0.05
1.70±0.10 2.30±0.10 0.40 BSC
1.70±0.10 2.30±0.10 0.40 BSC
- - - -
- - - -
0.20±0.05
0.20±0.05
YES
NO
PACKAGE OUTLINE, 6,8,10 & 14L,
TDFN, EXPOSED PAD, 3x3x0.80 mm
2
-DRAWING NOT TO SCALE-
21-0137
G
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 11
© 2005 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
ENG LISH • ? ? ? ? • ? ? ? •
WH AT' S N EW
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M A X 5 0 4 8 A A U T # T G 1 6
M A X 5 0 4 8 B A U T # T G 1 6
M A X 5 0 4 8 B A U T
S O T - 2 3 ; 6 p i n ; 9 m m
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U s e p k g c o d e / v a r i a t i o n : U 6 F H - 6 *
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M a t e r i a l s A n a l y s i s
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U s e p k g c o d e / v a r i a t i o n : T 6 3 3 + 2 *
- 4 0 C t o + 1 2 5 C R o H S / L e a d - F r e e : L e a d F r e e
M a t e r i a l s A n a l y s i s
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D w g : 2 1 - 0 1 3 7 I ( P D F )
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M a t e r i a l s A n a l y s i s
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M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : T 6 3 3 + 2 *
M A X 5 0 4 8 B A T T - T
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M A X 5 0 4 8 A A T T + T
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U s e p k g c o d e / v a r i a t i o n : T 6 3 3 - 2 *
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M a t e r i a l s A n a l y s i s
T H I N Q F N ( D u a l ) ; 6 p i n ; 1 0 m m
D w g : 2 1 - 0 1 3 7 I ( P D F )
U s e p k g c o d e / v a r i a t i o n : T 6 3 3 - 2 *
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M a t e r i a l s A n a l y s i s
T H I N Q F N ( D u a l ) ; 6 p i n ; 1 0 m m
D w g : 2 1 - 0 1 3 7 I ( P D F )
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M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : T 6 3 3 + 2 *
D i d n ' t F i n d W h a t Y o u N e e d ?
N e x t D a y P r o d u c t S e l e c t i o n A s s i s t a n c e f r o m A p p l i c a t i o n s E n g i n e e r s
P a r a m e t r i c S e a r c h
A p p l i c a t i o n s H e l p
Q u i c k V i e w
T e c h n i c a l D o c u m e n t s
O r d e r i n g I n f o
M o r e I n f o r m a t i o n
D e s c r i p t i o n
D a t a S h e e t
A p p l i c a t i o n N o t e s
D e s i g n G u i d e s
E n g i n e e r i n g J o u r n a l s
R e l i a b i l i t y R e p o r t s
S o f t w a r e / M o d e l s
E v a l u a t i o n K i t s
P r i c e a n d A v a i l a b i l i t y
S a m p l e s
B u y O n l i n e
P a c k a g e I n f o r m a t i o n
L e a d - F r e e I n f o r m a t i o n
R e l a t e d P r o d u c t s
N o t e s a n d C o m m e n t s
E v a l u a t i o n K i t s
K e y F e a t u r e s
A p p l i c a t i o n s / U s e s
K e y S p e c i f i c a t i o n s
D i a g r a m
D o c u m e n t R e f . : 1 9 - 2 4 1 9 ; R e v 4 ; 2 0 0 5 - 0 9 - 2 7
T h i s p a g e l a s t m o d i f i e d : 2 0 0 7 - 0 7 - 2 7
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
相关型号：
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