MAX819LCPA+ [ROCHESTER]
1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8;
| 型号： | MAX819LCPA+ |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PDIP8, 0.300 INCH, ROHS COMPLIANT, PLASTIC, DIP-8 光电二极管 |
| 文件： | 总19页 (文件大小：1051K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
19-0486; Rev 3; 12/05
+5V Microprocessor Supervisory Circuits
General Description
____________________________Features
♦ Precision Supply-Voltage Monitor:
4.65V (MAX81_L)
The MAX817/MAX818/MAX819 microprocessor (µP)
supervisory circuits simplify power-supply monitoring,
battery control, and chip-enable gating in µP systems
by reducing the number of components required.
These devices are designed for use in +5V-powered
systems. Low supply current (11µA typical) and small
package size make these devices ideal for portable
applications. The MAX817/MAX818/MAX819 are specif-
4.40V (MAX81_M)
♦ 11µA Quiescent Supply Current
♦ 200ms Reset Time Delay
♦ Watchdog Timer with 1.6sec Timeout
(MAX817/MAX818)
ically designed to ignore fast transients on V . Other
CC
♦ Battery-Backup Power Switching; Battery Voltage
supervisory functions include active-low reset, backup-
battery switchover, watchdog input, battery freshness
seal, and chip-enable gating. The Selector Guide below
lists the specific functions available from each device.
Can Exceed V
CC
♦ Battery Freshness Seal
♦ On-Board, 3ns Gating of Chip-Enable Signals
These devices offer two pretrimmed reset threshold volt-
ages for ±5ꢀ or ±1±ꢀ power suppliesꢁ :.45V for the L
versions and :.:±V for the M versions. The MAX817/
MAX818/MAX819 are available in space-saving µMAX
packages, as well as 8-pin DIP/SO.
(MAX818)
♦ Uncommitted Voltage Monitor for Power-Fail or
Low-Battery Warning (MAX817/MAX819)
♦ Manual Reset Input (MAX819)
______________Ordering Information
_____________________Selector Guide
†
PART
TEMP. RANGE
±°C to +7±°C
±°C to +7±°C
±°C to +7±°C
PIN-PACKAGE
8 Plastic DIP
8 SO
MAX817 MAX818 MAX819
FEATURE
MAX817_CPA
MAX817_CSA
MAX817_CUA
L/M
✔
L/M
✔
L/M
✔
Active-Low Reset
8 µMAX
✔
✔
✔
Backup-Battery Switchover
Power-Fail Comparator
Watchdog Input
Ordering Information continued on last page.
✔
✔
—
✔
✔
†
These parts offer a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
✔
—
✔
✔
✔
Battery Freshness Seal
Manual Reset Input
Chip-Enable Gating
—
—
—
✔
—
8-DIP/SO/ 8-DIP/SO/ 8-DIP/SO/
Pin-Package
µMAX
µMAX
µMAX
SUFFIX
RESET THRESHOLD (V)
L
:.45
:.:±
Low-Power, Pin-
Compatible Upgrades forꢁ MAX492A
MAX49±A/
MAX7±3/
MAX7±:
—
M
_________________Pin Configurations
________________________Applications
Battery-Powered Computers and Controllers
Embedded Controllers
TOP VIEW
1
2
3
4
8
7
6
5
BATT
RESET
WDI
OUT
Intelligent Instruments
V
CC
Critical µP Monitoring
MAX817
GND
PFI
Portable Equipment
PFO
Typical Operating Circuit appears at end of data sheet.
DIP/SO/µMAX
Pin Configurations continued at end of data sheet.
*Patents Pending
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at
1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.
+5V Microprocessor Supervisory Circuits
ABSOLUTE MAXIMUM RATINGS
Input Voltage
Continuous Power Dissipation (T = +7±°C)
A
V
, BATT ..........................................................-±.3V to +4.±V
Plastic DIP (derate 9.±9mW/°C above +7±°C) .............727mW
SO (derate 5.88mW/°C above +7±°C)..........................:71mW
µMAX (derate :.1±mW/°C above +7±°C) .....................33±mW
Operating Temperature Ranges
MAX81_ _C_A......................................................±°C to +7±°C
MAX81_ _E_A ...................................................-:±°C to +85°C
Storage Temperature Range.............................-45°C to +14±°C
Lead Temperature (soldering, 1±sec) .............................+3±±°C
CC
All Other Pins (Note 1).............................-±.3V to (V
Input Current
V
V
BATT Peak .....................................................................25±mA
BATT Continuous .............................................................5±mA
GND .................................................................................25mA
Output Current
+ ±.3V)
CC
Peak ..............................................................................1A
CC
Continuous .............................................................25±mA
CC
OUT................................................................................25±mA
All Other Outputs .............................................................25mA
OUT Short-Circuit Duration.................................................1±sec
Note 1: The input voltage limits on PFI and WDI may be exceeded (up to 12V V ) if the current into these pins is limited to less
IN
than 1±mA.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V
= +:.75V to +5.5V for MAX81_L, V
= +:.5V to +5.5V for MAX81_M, V
= 2.8V, T = T
A
to T
, unless otherwise
MAX
CC
CC
BATT
MIN
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Operating Voltage Range, V
,
CC
±
5.5
V
V
(Note 2)
BATT
MAX81_ _C
MAX81_ _E
11
11
:5
4±
As applicable; CE IN = ±V,
WDI and MR unconnected
Supply Current (excluding I
)
I
µA
µA
OUT
SUPPLY
T
A
= +25°C
±.±5
1.±
Supply Current in Battery-
V
= ±V
CC
T
T
= T
MAX
to
MIN
A
Backup Mode (excluding I
)
OUT
5.±
T
= +25°C
-±.1±
-1.±±
±.±2
±.±2
A
BATT Standby Current (Note 3)
5.5V > V > (V
+ ±.2V)
µA
µA
CC
BATT
T
T
= T
to
MIN
A
MAX
BATT Leakage Current,
Freshness Seal Enabled
V
= ±V, V
= 5mA
= ±V
OUT
1
CC
OUT
OUT
V
±.±5
-
V
-
CC
CC
I
I
±.±25
V
V
Output
V
OUT
V
±.5
-
V
CC
-
CC
= 5±mA
±.25
to OUT On-Resistance
5
1±
Ω
Ω
CC
BATT to OUT On-Resistance
1±±
V
V
BATT -
±.1
BATT -
±.±2
V
in Battery-Backup Mode
I
= 25±µA, V
< (V - ±.2V)
BATT
V
OUT
OUT
CC
Power-up
Power-down
2±
-2±
:±
Battery Switch Threshold
(V - V
V
< V
mV
mV
CC
RST
)
BATT
CC
Battery Switchover Hysteresis
2
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V
= +:.75V to +5.5V for MAX81_L, V
= +:.5V to +5.5V for MAX81_M, V
= 2.8V, T = T
A
to T
, unless otherwise
MAX
CC
CC
BATT
MIN
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
RESET AND WATCHDOG TIMER
MAX81_L
MAX81_M
:.5±
:.25
:.45
:.:±
25
:.75
:.5±
Reset Threshold
V
V
RST
Reset Threshold Hysteresis
Reset Timeout Period
mV
ms
t
1:±
2±±
28±
RP
V
V
V
> V
< V
I
= 8±±µA
V
- 1.5
CC
OH
CC
CC
RST(MAX), SOURCE
I
= 3.2mA
±.:
±.3
RST(MIN), SINK
MAX81_ _C, V = 1V, V falling,
CC
CC
V
RESET Output Voltage
V
BATT
= ±V, I
= 5±µA
SINK
V
OL
MAX81_ _E, V = 1.2V, V falling,
CC
CC
±.3
V
BATT
= ±V, I
= 1±±µA
SINK
From V
, V
falling at 1±V/ms
1±±
µs
sec
ns
V
to RESET Delay
RST CC
CC
Watchdog Timeout Period
WDI Pulse Width
t
1.±±
5±
1.4±
2.25
±.8
WD
t
V
V
= ±.:V, V = ±.8V
IH CC
WDI
IL
V
IL
WDI Input Threshold (Note :)
WDI Input Current (Note 5)
= 5V
V
CC
V
3.5
-2±
IH
WDI = V , time average
CC
12±
-15
14±
µA
WDI = GND, time average
POWER-FAIL COMPARATOR (MAX817/MAX819 only)
PFI Input Threshold
PFI Input Hysteresis
PFI Input Current
V
1.2±
-25
1.25
:
1.3±
V
PFT
mV
nA
I
±.±1
25
PFI
V
V
V
V
< 1.2±V, I
> 1.3±V, I
= ±V
= 3.2mA, V > :.5±V
CC
±.:
OL
PFI
PFI
SINK
V
PFO Output Voltage
V
= :±µA, V
> :.5V
V
- 1.5
CC
OH
SOURCE
CC
25±
5±±
2.±
µA
PFO Short-Circuit Current
PFO
MANUAL RESET INPUT (MAX819 only)
V
±.8
IL
V
MR Input Threshold
MR Pulse Width
V
IH
1
µs
ns
MR Pulse that Would Not Cause
a Reset
1±±
12±
43
ns
MR to Reset Delay
:5
85
kΩ
MR Pull-Up Resistance
_______________________________________________________________________________________
3
+5V Microprocessor Supervisory Circuits
ELECTRICAL CHARACTERISTICS (continued)
(V
= +:.75V to +5.5V for MAX81_L, V
= +:.5V to +5.5V for MAX81_M, V
= 2.8V, T = T
A
to T
, unless otherwise
MAX
CC
CC
BATT
MIN
noted. Typical values are at T = +25°C.)
A
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHIP-ENABLE GATING (MAX818 only)
Disable mode
Enable mode
±±.±±5
:±
±1
µA
CE IN Leakage Current
CE IN to CE OUT Resistance
(Note 4)
15±
Ω
CE OUT Short-Circuit Current
(Reset Active)
±.1
±.75
3
2.±
8
mA
ns
V
Disable mode, CE OUT = ±V
CE IN to CE OUT Propagation
Delay (Note 7)
5±Ω source impedance driver, C
= 5±pF
LOAD
I
I
= -1±±µA, V
= ±V
V
- 1V
CC
OUT
CC
V
CE OUT Output
OH
= -1µA, V
= ±V, V
= 2.8V
BATT
2.7
OUT
CC
V
±.8
IH
V
= 5V
V
CE OUT Input Threshold
RESET to CE OUT Delay
CC
V
3.5
IL
Power-down
15
µs
Note 2: Either V
or V
BATT
can go to ±V if the other is greater than 2.±V.
CC
Note 3: “-” = battery-charging current, “+” = battery-discharging current.
Note 4: WDI is internally serviced within the watchdog timeout period if WDI is left unconnected.
Note 5: WDI input is designed to be driven by a three-stated output device. To float WDI, the “high-impedance mode” of the output
device must have a maximum leakage current of 1±µA and a maximum output capacitance of 2±±pF. The output device
must also be able to source and sink at least 2±±µA when active.
Note 6: The chip-enable resistance is tested with V
= +:.75V for the MAX818L and V
= +:.5V for the MAX818M.
CC
CC
V
= V
= V /2.
CE OUT CC
CE IN
Note 7: The chip-enable propagation delay is measured from the 5±ꢀ point at CE IN to the 5±ꢀ point at CE OUT.
4
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
__________________________________________Typical Operating Characteristics
(V
= +5V, V
= 3.±V, T = +25°C, unless otherwise noted.)
BATT A
CC
SUPPLY CURRENT
vs. TEMPERATURE (NO LOAD)
BATTERY SUPPLY CURRENT
(BACKUP MODE) vs. TEMPERATURE
CE IN TO CE OUT ON-RESISTANCE
vs. TEMPERATURE
16
100
90
80
70
60
50
40
30
20
10
0
160
140
V
= 0V
CC
V
= 4V
V
= 5.0V
CE IN
BATT
14
12
120
100
80
60
40
20
0
V
V
= 3V
= 2V
CE IN
CE IN
V
= 2.8V
= 2.0V
BATT
BATT
V
10
8
20
TEMPERATURE (°C)
-40 -20
0
40
60
80 100
-40 -20
0
20
40
60
80 100
-40 -20
0
20
40
60
80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
BATT TO OUT ON-RESISTANCE
vs. TEMPERATURE
RESET TIMEOUT PERIOD
vs. TEMPERATURE
V
CC
TO OUT ON-RESISTANCE
vs. TEMPERATURE
300
250
200
220
210
200
7
6
5
4
3
V
= 0V
CC
V
= 2.0V
BATT
150
100
50
V
V
= 2.8V
= 5.0V
BATT
BATT
190
180
0
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
V
CC
TO RESET PROPAGATION DELAY
vs. TEMPERATURE
BATTERY FRESHNESS SEAL
LEAKAGE CURRENT vs. TEMPERATURE
WATCHDOG TIMEOUT PERIOD
vs. TEMPERATURE
500
400
300
20
15
1.70
1.65
V
FALLING AT:
0.25V/ms
CC
1V/ms
10
5
1.60
1.55
200
100
0
10V/ms
0
1.50
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
_______________________________________________________________________________________
5
+5V Microprocessor Supervisory Circuits
____________________________Typical Operating Characteristics (continued)
(V
= +5V, V
= 3.±V, T = +25°C, unless otherwise noted.)
BATT A
CC
BATTERY SUPPLY CURRENT
vs. SUPPLY VOLTAGE
RESET THRESHOLD
vs. TEMPERATURE
MAXIMUM TRANSIENT DURATION
vs. RESET THRESHOLD OVERDRIVE
8
7
4.7
1600
1400
1200
1000
MAX81_L
4.6
6
5
4
800
4.5
4.4
4.3
RESET OCCURS
ABOVE CURVE
600
400
3
2
1
0
MAX81_M
200
0
1
10
100
1000
10,000
0
1
2
3
4
5
6
-40
-20
0
20
40
60
80
V
(V)
TEMPERATURE (°C)
RESET COMPARATOR OVERDRIVE, V -V (mV)
TH CC
CC
CE IN TO CE OUT PROPAGATION DELAY
vs. TEMPERATURE
MAX817/MAX819 PFI TO PFO PROPAGATION
DELAY vs. TEMPERATURE
MAX817/MAX819 PFI THRESHOLD
vs. TEMPERATURE
33
7
6
1.254
1.252
1.250
1.248
1.246
1.244
1.242
1.240
32
31
30
29
28
5
4
3
t
-
PD
t
+
PD
2
1
0
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
-40 -20
0
20
40
60 80 100
TEMPERATURE (°C)
TEMPERATURE (°C)
TEMPERATURE (°C)
6
_______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
______________________________________________________________Pin Description
PIN
NAME
FUNCTION
MAX817
MAX818
MAX819
Supply Output for CMOS RAM. When V
rises above the reset threshold
CC
1
1
1
OUT
or above V
MOSFET switch. When V
, OUT is connected to V
through an internal P-channel
, BATT connects to OUT.
BATT
CC
BATT
falls below V
CC
2
3
2
3
2
3
V
Input Supply Voltage, +5V input.
CC
GND
Ground. ±V reference for all signals.
Power-Fail Comparator Input. When V is below V
or when V is below
CC
PFI
PFT
:
—
:
:
PFI
V
, PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator
BATT
section). Connect to ground if unused.
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to
ground if unused.
—
—
CE IN
Power-Fail Comparator Output. When PFI is less than V
or when V
is
PFT
CC
below V
, PFO goes low; otherwise PFO remains high. PFO is also used to
BATT
5
—
5
5
PFO
enable the battery freshness seal (see Battery Freshness Seal and Power-Fail
Comparator sections).
Chip-Enable Output. CE OUT goes low only if CE IN is low while reset is not
asserted. If CE IN is low when reset is asserted, CE OUT will remain low for
15µs or until CE IN goes high, whichever occurs first. CE OUT is pulled up to
OUT in battery-backup mode. CE OUT is also used to enable the battery
freshness seal (see Battery Freshness Seal section).
—
—
CE OUT
Watchdog Input. If WDI remains either high or low for longer than the watch-
dog timeout period, the internal watchdog timer runs out and a reset is trig-
gered. If WDI is left unconnected or is connected to a high-impedance
three-state buffer, the watchdog feature is disabled. The internal watchdog
timer clears whenever reset is asserted, WDI is three-stated, or WDI sees a ris-
ing or falling edge. The WDI input is designed to be driven by a three-stated-
output device with a maximum high-impedance leakage current of 1±µA and a
maximum output capacitance of 2±±pF. The output device must also be capa-
ble of sinking and sourcing 2±±µA when active.
4
4
—
WDI
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted
for as long as MR is held low and for 2±±ms after MR returns high. The active-
low input has an internal 43kΩ pull-up resistor. It can be driven from a TTL- or
CMOS-logic line or shorted to ground with a switch. Leave open, or connect to
—
—
4
MR
V
if unused.
CC
Active-Low Reset Output. Pulses low for 2±±ms when triggered and remains
low whenever V is below the reset threshold or when MR is a logic low. It
CC
7
8
7
8
7
8
RESET
remains low for 2±±ms after V
rises above the reset threshold, the watchdog
CC
triggers a reset, or MR goes low to high.
Backup-Battery Input. When V falls below V
, OUT switches from V to
CC
CC
BATT
BATT
BATT. When V
rises above V
, OUT reconnects to V
.
CC
BATT
CC
_______________________________________________________________________________________
7
+5V Microprocessor Supervisory Circuits
BATT
OUT
BATTERY SWITCHOVER
CIRCUITRY
V
CC
MAX817
MAX818
MAX819
RESET
GENERATOR
RESET
1.25V
THIS PIN
FOR MAX819
ONLY.
MR
BATTERY
FRESHNESS
SEAL CIRCUITRY
WATCHDOG
TIMER
WDI
THIS SECTION
FOR MAX817/
MAX818 ONLY.
PFI
THIS SECTION
FOR MAX817/
MAX819 ONLY.
PFO
CHIP-ENABLE
OUTPUT
CONTROL
1.25V
THIS SECTION
FOR MAX818
ONLY.
CE IN
CE OUT
GND
Figure 1. Functional Diagram
_______________________________________________________________________________________
8
+5V Microprocessor Supervisory Circuits
During the reset timeout period (t ), MR’s state is
RP
_______________Detailed Description
ignored if the battery freshness seal is enabled. MR has
an internal 43kΩ pull-up resistor, so it can be left open
if not used. This input can be driven with TTL/CMOS-
logic levels or with open-drain/collector outputs.
Connect a normally open momentary switch from MR to
GND to create a manual reset function; external
debounce circuitry is not required. If MR is driven from
long cables or the device is used in a noisy environ-
ment, connect a ±.1µF capacitor from MR to GND to
provide additional noise immunity.
General Timing Characteristics
Designed for 5V systems, the MAX817/MAX818/
MAX819 provide a number of microprocessor (µP)
supervisory functions (see the Selector Guide on the
first page). Figure 2 shows the typical timing relation-
ships of the various outputs during power-up and
power-down with typical V
rise and fall times.
CC
RESET Output
A µP’s reset input starts the µP in a known state. The
MAX817/MAX818/MAX819 µP supervisory circuits
assert a reset to prevent code-execution errors during
power-up, power-down, and brownout conditions.
Note that MR must be high or open to enable the bat-
tery freshness seal. Once the battery freshness seal is
enabled its operation is unaffected by MR.
RESET is guaranteed to be a logic low for ±V < V
<
CC
Battery Freshness Seal
The MAX817/MAX818/MAX819 battery freshness seal
disconnects the backup battery from internal circuitry
and OUT until it is needed. This allows an OEM to
ensure that the backup battery connected to BATT will
be fresh when the final product is put to use. To enable
the freshness seal on the MAX817 and MAX819ꢁ
V
if V
is greater than 1V. Without a backup bat-
RST
tery (V
CC
BATT
= GND) RESET is guaranteed valid for
BATT
V
≥ 1V. Once V
exceeds the reset threshold an
CC
internal timer keeps RESET low for the reset timeout
period, t . After this interval RESET returns high
RP
(Figure 2).
If a brownout condition occurs (V
drops below the
CC
1) Connect a battery to BATT.
reset threshold), RESET goes low. Each time RESET is
2) Ground PFO.
asserted it stays low for at least the reset timeout peri-
od. Any time V
goes below the reset threshold the
CC
3) Bring V
above the reset threshold and hold it
CC
internal timer clears. The reset timer starts when V
CC
there until reset is deasserted following the reset
timeout period.
returns above the reset threshold. RESET both sources
and sinks current.
:) Bring V
down again (Figure 3).
CC
Manual Reset Input (MAX819)
Many µP-based products require manual reset capabil-
ity, allowing the operator, a test technician, or external
logic circuitry to initiate a reset. On the MAX819, a logic
low on MR asserts reset. Reset remains asserted while
Use the same procedure for the MAX818, but ground
CE OUT instead of PFO. Once the battery freshness
seal is enabled (disconnecting the backup battery from
internal circuitry and anything connected to OUT), it
remains enabled until V
is brought above V
.
CC
RST
MR is low, and for t
(2±±ms) after it returns high.
RP
V
BATT
V
RST
V
RST
V
RST
V
RST
V
CC
V
BATT
V
OUT
V
CC
V
BATT
t
RP
RESET TO
CE OUT
V
RESET
PFO FOLLOWS PFI
t
RP
RESET
DELAY**
CE OUT STATE LATCHED
AT 1/2 t AND 3/4 t
V
PFO*
,
RP
CE OUT (MAX818)
RP
V
CE OUT**
FRESHNESS SEAL ENABLED
(EXTERNALLY HELD AT 0V)
V
BATT
PFO STATE LATCHED
CE OUT FOLLOWS CE IN
AT 1/2 t AND 3/4 t
,
PFO (MAX817/MAX819)
RP
RP
FRESHNESS SEAL ENABLED
(EXTERNALLY HELD AT 0V)
*MAX817/MAX819 ONLY.
** MAX818 ONLY.
Figure 3. Battery Freshness Seal Timing
Figure 2. Power-Up and Power-Down Timing
_______________________________________________________________________________________
9
+5V Microprocessor Supervisory Circuits
On the MAX819, MR must be high or open to enable
the battery freshness seal. Once the battery freshness
seal is enabled its operation is unaffected by MR.
V
CC
Watchdog Input (MAX817/MAX818)
In the MAX817/MAX818, the watchdog circuit monitors
the µP’s activity. If the µP does not toggle the watchdog
t
RP
t
WD
RESET
WDI
input (WDI) within t
(1.4sec), reset asserts. The inter-
WD
nal 1.4sec timer is cleared by either a reset pulse or by
toggling WDI, which can detect pulses as short as
5±ns. The timer remains cleared and does not count for
as long as reset is asserted. As soon as reset is
released, the timer starts counting (Figure :).
Figure 4. Watchdog Timing
To disable the watchdog function, leave WDI uncon-
nected or three-state the driver connected to WDI. The
watchdog input is internally driven low during the first
7/8 of the watchdog timeout period, then momentarily
pulses high, resetting the watchdog counter. When
WDI is left open-circuited, this internal driver clears the
1.4sec timer every 1.:sec. When WDI is three-stated or
left unconnected, the maximum allowable leakage cur-
rent is 1±µA and the maximum allowable load capaci-
tance is 2±±pF.
BATTERY
SWITCHOVER
CIRCUITRY
MAX817
MAX818
BATTERY
RESET
GENERATOR
FRESHNESS
SEAL CIRCUITRY
OUT
Chip-Enable Gating (MAX818)
Internal gating of the chip-enable (CE) signal prevents
erroneous data from corrupting CMOS RAM in the
event of an undervoltage condition. The MAX818 uses
a series transmission gate from CE IN to CE OUT
(Figure 5). During normal operation (reset not assert-
ed), the CE transmission gate is enabled and passes
all CE transitions. When reset is asserted, this path
becomes disabled, preventing erroneous data from
corrupting the CMOS RAM. The short CE propagation
delay from CE IN to CE OUT enables the MAX818 to be
used with most µPs. If CE IN is low when reset asserts,
CE OUT remains low for typically 15µs to permit the
current write cycle to complete.
CHIP-ENABLE
OUTPUT
CONTROL
P
CE IN
CE OUT
N
Figure 5. Chip-Enable Transmission Gate
Chip-Enable Input (MAX818)
The CE transmission gate is disabled and CE IN is high
impedance (disabled mode) while reset is asserted.
V
RST
V
RST
V
RST
V
RST
V
CC
During a power-down sequence when V
passes the
CC
reset threshold, the CE transmission gate disables and
CE IN immediately becomes high impedance if the volt-
age at CE IN is high. If CE IN is low when reset asserts,
the CE transmission gate will disable 15µs after reset
asserts (Figure 4). This permits the current write cycle
to complete during power-down.
V
CE OUT
V
BATT
V
BATT
t
RP
t
RP
15µs
V
RESET
V
CE IN
Figure 6. Chip-Enable Timing
10 ______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
Any time a reset is generated, the CE transmission gate
Power-Fail Comparator
(MAX817/MAX819)
remains disabled and CE IN remains high impedance
(regardless of CE IN activity) for the reset timeout peri-
od. When the CE transmission gate is enabled, the
impedance of CE IN appears as a :±Ω resistor in series
with the load at CE OUT. The propagation delay
The MAX817/MAX819 PFI input is compared to an inter-
nal reference. If PFI is less than the power-fail threshold
PFT
(V
), PFO goes low. The power-fail comparator is
intended for use as an undervoltage detector to signal a
failing power supply (Figure 8). However, the comparator
does not need to be dedicated to this function because it
is completely separate from the rest of the circuitry.
through the CE transmission gate depends on V , the
CC
source impedance of the drive connected to CE IN,
and the loading on CE OUT (see Typical Operating
Characteristics). The CE propagation delay is produc-
tion tested from the 5±ꢀ point on CE IN to the 5±ꢀ
point on CE OUT using a 5±Ω driver and a 5±pF load
capacitance (Figure 7). For minimum propagation
delay, minimize the capacitive load at CE OUT and use
a low-output-impedance driver.
The power-fail comparator turns off and PFO goes low
when V
falls below V
. During the reset timeout
BATT
CC
period (t ), PFO is forced high, regardless of the state
RP
of V
(see Battery Freshness Seal section). If the com-
PFI
parator is unused, connect PFI to ground and leave PFO
unconnected. PFO can be connected to MR on the
MAX819 so that a low voltage on PFI will generate a
reset (Figure 9). In this configuration, when the monitored
Chip-Enable Output (MAX818)
When the CE transmission gate is enabled, the imped-
ance of CE OUT is equivalent to a :±Ω resistor in series
with the source driving CE IN. In the disabled mode,
the transmission gate is off and an active pull-up con-
nects CE OUT to OUT (Figure 5). This pull-up turns off
when the transmission gate is enabled.
voltage causes PFI to fall below V , PFO pulls MR low,
PFT
causing a reset to be asserted. Reset remains asserted
as long as PFO holds MR low, and for t (2±±ms) after
RP
PFO pulls MR high when the monitored supply is above
the programmed threshold. When PFO is connected to
MR, it is not possible to enable the battery freshness
seal. Enabling the battery freshness seal requires MR to
be high or open. Once the battery freshness seal is
enabled, it is no longer affected by PFO’s connection to
MR.
+5V
V
IN
+5V
POWER-FAIL-WARNING TRIP VOLTAGE
R1 + R2
REGULATOR
V
CC
V
WARN
= 1.25
( )
BATT
CE IN
R2
V
MAX818
CC
MAX817
MAX819
R1
R2
CE OUT
RESET
PFO
RESET
NMI
50Ω
PFI
GND
50Ω
50pF
C *
µP
L
1.25V
* C INCLUDES LOAD CAPACITANCE, STRAY CAPACITANCE,
L
AND SCOPE-PROBE CAPACITANCE.
Figure 7. CE Propagation Delay Test Circuit
Figure 8. Using the Power-Fail Comparator to Generate a
Power-Fail Warning
______________________________________________________________________________________ 11
+5V Microprocessor Supervisory Circuits
When V exceeds the reset threshold, it is connected to
Backup-Battery Switchover
In a brownout or power failure, it may be necessary to
preserve the contents of RAM. With a backup battery
installed at BATT, the MAX817/MAX818/MAX819 auto-
CC
the substrate, regardless of the voltage applied to BATT
(Figure 1±). During this time, the diode (D1) between
BATT and the substrate will conduct current from BATT
to V
if V is ±.4V greater than V . When BATT
BATT CC
matically switch RAM to backup power when V
falls.
CC
CC
connects to OUT, backup mode is activated and the
internal circuitry is powered from the battery (Table 1).
These devices require two conditions before switching
to battery-backup modeꢁ 1) V
must be below the
CC
When V
is just below V
, the current draw from
drops to more than 1V
reset threshold, and 2) V
CC
must be below V
.
BATT
CC
BATT
BATT is typically 4µA. When V
Table 1 lists the status of the inputs and outputs in bat-
tery-backup mode.
CC
below V
, the internal switchover comparator shuts
BATT
off and the supply current falls to less than 1µA.
As long as V
exceeds the reset threshold, OUT con-
CC
nects to V
through a 5Ω PMOS power switch. Once
CC
__________Applications Information
The MAX817/MAX818/MAX819 are protected for typical
short-circuit conditions of 1±sec or less. Shorting OUT
to ground for longer than 1±sec destroys the device.
Decouple V , OUT, and BATT to ground by placing
CC
±.1µF capacitors as close to the device as possible.
V
falls below the reset threshold, V
or V
CC BATT
CC
(whichever is higher) switches to OUT. When V
falls
CC
below V
and V
, BATT switches to OUT through
RST
BATT
an 8±Ω switch.
Table 1. Input and Output Status in
Battery-Backup Mode
SIGNAL
STATUS
Disconnected from V
BATT
V
CC
V
CC
.
OUT
Connected to V
PMOS switch.
through an internal 8±Ω
BATT
V
OUT
Connected to V
. Current drawn from
OUT
V
the battery is less than 1µA, as long as
< V - ±.2V.
BATT
SW1
SW2
SW3
SW4
D1 D2
V
CC
BATT
SUBSTRATE
V
Logic low
RESET
V
Watchdog timer is disabled.
WDI
D3
Logic high. The open-circuit voltage is equal
MAX817
MAX818
MAX819
V
CE OUT
to V
.
OUT
V
High impedance
CE IN
OUT
V1
ADDITIONAL SUPPLY RESET VOLTAGE
R1 + R2
V2
= 1.25
CONDITION
SW1/SW2 SW3/SW4
(RESET)
( )
R2
V
CC
V2
V
> Reset Threshold
Open
Open
Closed
Closed
Open
CC
R1
R2
MAX819
V
CC
V
CC
< Reset Threshold and
RESET
MR
RESET
> V
BATT
PFI
V
CC
V
CC
< Reset Threshold and
Closed
< V
BATT
µP
PFO
RESET THRESHOLD = 4.65V IN MAX81_L
RESET THRESHOLD = 4.4V IN MAX81_M
Figure 9. Monitoring an Additional Supply by Connecting
PFO to MR.
Figure 10. Backup-Battery-Switchover Block Diagram
12 ______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
V
, the SuperCap on BATT discharges through V
BATT
Watchdog Input Current
The MAX817/MAX818 WDI inputs are internally driven
through a buffer and series resistor from the watchdog
counter (Figure 1). When WDI is left unconnected, the
watchdog timer is serviced within the watchdog timeout
period by a low-high-low pulse from the counter chain.
For minimum watchdog input current (minimum overall
power consumption), leave WDI low for the majority of the
watchdog timeout period, pulsing it low-high-low once
CC
until V
CC
reaches the reset threshold. Battery-backup
mode is then initiated and the current through V
goes to zero.
CC
Operation Without a
Backup Power Source
The MAX817/MAX818/MAX819 were designed for bat-
tery-backed applications. If a backup battery is not
used, connect V
ground.
to OUT, and connect BATT to
7
CC
within /8 of the watchdog timeout period to reset the
watchdog timer. If instead WDI is externally driven high for
the majority of the timeout period, up to 15±µA can flow
into WDI.
Replacing the Backup Battery
The backup power source can be removed while V
CC
remains valid, without danger of triggering a reset
pulse, if BATT is decoupled with a ±.1µF capacitor to
Using a SuperCap™ as a
Backup Power Source
ground. As long as V
stays above the reset thresh-
CC
SuperCaps are capacitors with extremely high capaci-
tance values (on the order of ±.:7F) for their size. Since
old, battery-backup mode cannot be entered.
BATT has the same operating voltage range as V , and
CC
Adding Hysteresis to the Power-Fail
Comparator (MAX817/MAX819)
The power-fail comparator has a typical input hystere-
sis of :mV. This is sufficient for most applications where
a power-supply line is being monitored through an
external voltage divider (see Monitoring an Additional
Supply).
the battery switchover threshold voltages are typically
±3±mV centered at V
, a SuperCap and simple
BATT
charging circuit can be used as a backup power source.
Figure 11 shows a SuperCap used as a backup source.
If V
is above the reset threshold and V
is ±.5V
BATT
CC
above V , current flows to OUT and V
from BATT
CC
CC
until the voltage at BATT is less than ±.5V above V
.
CC
For additional noise margin, connect a resistor between
For example, if a SuperCap is connected to BATT
through a diode to V , and V quickly changes from
PFO and PFI, as shown in Figure 12. Select the ratio of
CC
CC
R1 and R2 such that PFI sees V
when V falls to the
IN
PFT
5.:V to :.9V, the capacitor discharges through OUT
and V until V reaches 5.1V typical. Leakage cur-
CC
BATT
+5V
V
IN
rent through the SuperCap charging diode and the
internal power diode eventually discharges the
V
CC
R1
R2
SuperCap to V . Also, if V
and V
start from
BATT
CC
CC
±.1V above the reset threshold and power is lost at
PFI
MAX817
MAX819
R3
+5V
C1*
PFO
OUT
GND
V
CC
TO STATIC RAM
TO µP
*OPTIONAL
MAX817
MAX818
MAX819
+5V
RESET
BATT
TO µP
PFO
0V
0V
V
V
H
L
V
TRIP
0.1F
100k
V
IN
R2
R1 + R2
GND
(
)
V
= 1.25V
TRIP
||
R2 R3
V
= 1.25V
H
(
)
+
||
R1 R2 R3
V - 1.25
L
5 - 1.25
R3
1.25
R2
+
=
Figure 11. Using a SuperCap™ as a Backup Power Source
with a +5V 10ꢀ Supply
R1
Figure 12. Adding Hysteresis to the Power-Fail Comparator
SuperCap is a trademark of Baknor Industries.
______________________________________________________________________________________ 13
+5V Microprocessor Supervisory Circuits
desired trip point (V
). Resistor R3 adds hysteresis.
TRIP
It will typically be an order of magnitude greater than R1
or R2. The current through R1 and R2 should be at least
1µA to ensure that the 25nA (max) PFI input leakage
current does not shift the trip point. R3 should be larger
than 2±±kΩ to prevent it from loading down the PFO pin.
Capacitor C1 adds additional noise rejection.
+5V
V
CC
R1
R2
MAX817
MAX819
PFI
PFO
Monitoring an Additional Supply
(MAX817/MAX819)
The MAX817/MAX819 µP supervisors can monitor either
positive or negative supplies using a resistor voltage
divider to PFI. PFO can be used to generate an interrupt
to the µP or to trigger a reset (Figures 9 and 13).
GND
V-
+5V
Interfacing to µPs with
Bidirectional Reset Pins
PFO
0V
µPs with bidirectional reset pins, such as the Motorola
48HC11 series, can contend with the MAX817/MAX818/
MAX819 RESET output. If, for example, the RESET out-
put is driven high and the µP wants to pull it low, inde-
terminate logic levels may result. To correct this,
connect a :.7kΩ resistor between the RESET output
and the µP reset I/O, as in Figure 1:. Buffer the RESET
output to other system components.
V
TRIP
V-
0V
5 - 1.25
R1
1.25 - V
R2
TRIP
=
NOTE: V
IS NEGATIVE
TRIP
Figure 13. Monitoring a Negative Voltage
Negative-Going V
Transients
CC
These supervisors are relatively immune to short-dura-
tion, negative-going V transients (glitches) while
CC
issuing a reset to the µP during power-up, power-down,
and brownout conditions. Therefore, resetting the µP
when V
experiences only small glitches is usually not
BUFFERED RESET TO OTHER SYSTEM COMPONENTS
CC
desirable.
The Typical Operating Characteristics show a graph of
Maximum Transient Duration vs. Reset Threshold
Overdrive for which reset pulses are not generated. The
V
CC
V
CC
graph was produced using negative-going V
pulses,
CC
MAX817
MAX818
MAX819
starting at 3.3V and ending below the reset threshold by
the magnitude indicated (reset threshold overdrive). The
graph shows the maximum pulse width that a negative-
4.7k
RESET
RESET
going V
transient can typically have without triggering
CC
a reset pulse. As the amplitude of the transient increases
(i.e., goes farther below the reset threshold), the maxi-
GND
GND
mum allowable pulse width decreases. Typically, a V
CC
transient that goes 1±±mV below the reset threshold and
lasts for 135µs will not trigger a reset pulse.
A ±.1µF bypass capacitor mounted close to the V
pin provides additional transient immunity.
CC
Figure 14. Interfacing to µPs with Bidirectional Reset I/O
14 ______________________________________________________________________________________
+5V Microprocessor Supervisory Circuits
Watchdog Software Considerations
(MAX817/MAX818)
To help the watchdog timer monitor software execution
START
more closely, set and reset the watchdog input at different
points in the program, rather than “pulsing” the watchdog
SET
input high-low-high or low-high-low. This technique avoids
WDI
a “stuck” loop, in which the watchdog timer would contin-
LOW
ue to be reset within the loop, keeping the watchdog from
timing out. Figure 15 shows an example of a flow diagram
SUBROUTINE
OR PROGRAM LOOP,
SET WDI
where the I/O driving the watchdog input is set high at the
beginning of the program, set low at the beginning of
every subroutine or loop, then set high again when the
program returns to the beginning. If the program should
“hang” in any subroutine, the problem would quickly be
corrected, since the I/O is continually set low and the
watchdog timer is allowed to time out, triggering a reset or
an interrupt. As described in the Watchdog Input Current
section, this scheme results in higher average WDI input
current than does the method of leaving WDI low for the
majority of the timeout period and periodically pulsing it
low-high-low.
HIGH
RETURN
END
Figure 15. Watchdog Flow Diagram
____Pin Configurations (continued)
__________Typical Operating Circuit
TOP VIEW
+5V
REAL-
TIME
CLOCK
1
2
3
4
8
7
6
5
BATT
OUT
CMOS
RAM
0.1µF
RESET
WDI
V
CC
MAX818
GND
V
CC
OUT
BATT
CE IN
CE OUT
0.1µF
MAX817
MAX818
MAX819
0.1µF
DIP/SO/µMAX
A0–A15
RESET
RESET
µP
1
2
3
4
8
7
6
5
BATT
RESET
MR
OUT
I/O
WDI**
CE IN* CE OUT*
GND
V
CC
MAX819
ADDRESS
DECODE
GND
PFI
PFO
*CE IN AND CE OUT APPLY TO MAX818 ONLY.
**WDI APPLIES TO MAX817/MAX818 ONLY.
DIP/SO/µMAX
______________________________________________________________________________________ 15
+5V Microprocessor Supervisory Circuits
Ordering Information (continued)
Chip Information
†
TRANSISTOR COUNTꢁ 719
PART
TEMP. RANGE
-:±°C to +85°C
-:±°C to +85°C
±°C to +7±°C
±°C to +7±°C
±°C to +7±°C
-:±°C to +85°C
-:±°C to +85°C
±°C to +7±°C
±°C to +7±°C
±°C to +7±°C
-:±°C to +85°C
-:±°C to +85°C
PIN-PACKAGE
8 Plastic DIP
8 SO
MAX817_EPA
MAX817_ESA
MAX818_CPA
MAX818_CSA
MAX818_CUA
MAX818_EPA
MAX818_ESA
MAX819_CPA
MAX819_CSA
MAX819_CUA
MAX819_EPA
MAX819_ESA
8 Plastic DIP
8 SO
8 µMAX
8 Plastic DIP
8 SO
8 Plastic DIP
8 SO
8 µMAX
8 Plastic DIP
8 SO
†
These parts offer a choice of reset threshold voltage. From the
table below, select the suffix corresponding to the desired
threshold and insert it into the blank to complete the part number.
Devices are available in both leaded and lead-free packaging.
Specify lead free by adding the + symbol at the end of the part
number when ordering.
SUFFIX
RESET THRESHOLD (V)
L
:.45
:.:±
M
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
INCHES
MILLIMETERS
DIM
MIN
0.036
A1 0.004
MAX
0.044
0.008
0.014
0.007
0.120
0.120
MIN
0.91
0.10
0.25
0.13
2.95
2.95
MAX
1.11
0.20
0.36
0.18
3.05
3.05
A
C
α
A
B
C
D
E
e
0.010
0.005
0.116
0.116
0.101mm
0.004 in
e
B
A1
L
0.0256
0.65
H
L
α
0.188
0.016
0°
0.198
0.026
6°
4.78
0.41
0°
5.03
0.66
6°
21-0036D
E
H
8-PIN µMAX
MICROMAX SMALL-OUTLINE
PACKAGE
D
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600
© 2±±5 Maxim Integrated Products
Printed USA
is a registered trademark of Maxim Integrated Products, Inc.
ENGL ISH • ? ? ? ? • ? ? ? • ? ? ?
WH AT 'S NEW
PR OD UC TS
SO LUTI ONS
D ES IG N
A PPNOTES
SU PPORT
B U Y
COM PA N Y
M EMB ERS
M A X 8 1 9 L
Pa rt Nu m ber T abl e
N o t e s :
1 . S e e t h e M A X 8 1 9 L Q u i c k V i e w D a t a S h e e t f o r f u r t h e r i n f o r m a t i o n o n t h i s p r o d u c t f a m i l y o r d o w n l o a d t h e
M A X 8 1 9 L f u l l d a t a s h e e t ( P D F , 2 6 0 k B ) .
2 . O t h e r o p t i o n s a n d l i n k s f o r p u r c h a s i n g p a r t s a r e l i s t e d a t : h t t p : / / w w w . m a x i m - i c . c o m / s a l e s .
3 . D i d n ' t F i n d W h a t Y o u N e e d ? A s k o u r a p p l i c a t i o n s e n g i n e e r s . E x p e r t a s s i s t a n c e i n f i n d i n g p a r t s , u s u a l l y w i t h i n
o n e b u s i n e s s d a y .
4 . P a r t n u m b e r s u f f i x e s : T o r T & R = t a p e a n d r e e l ; + = R o H S / l e a d - f r e e ; # = R o H S / l e a d - e x e m p t . M o r e : S e e
f u l l d a t a s h e e t o r P a r t N a m i n g C o n v e n t i o n s .
5 . * S o m e p a c k a g e s h a v e v a r i a t i o n s , l i s t e d o n t h e d r a w i n g . " P k g C o d e / V a r i a t i o n " t e l l s w h i c h v a r i a t i o n t h e
p r o d u c t u s e s .
P a r t N u m b e r
F r e e
S a m p l e
B u y
D i r e c t
T e m p
R o H S / L e a d - F r e e ?
M a t e r i a l s A n a l y s i s
P a c k a g e : T Y P E P I N S S I Z E
D R A W I N G C O D E / V A R *
M A X 8 1 9 L C P A
P D I P ; 8 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 8 - 1 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 8 1 9 L C P A +
M A X 8 1 9 L E P A +
M A X 8 1 9 L E P A
P D I P ; 8 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 8 + 1 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
P D I P ; 8 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 8 + 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
P D I P ; 8 p i n ; . 3 0 0 "
D w g : 2 1 - 0 0 4 3 D ( P D F )
U s e p k g c o d e / v a r i a t i o n : P 8 - 1 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 8 1 9 L C S A - T
M A X 8 1 9 L C S A + T
M A X 8 1 9 L C S A +
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 - 2 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 + 2 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 + 2 *
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
M A X 8 1 9 L C S A
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 - 2 *
0 C t o + 7 0 C
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 8 1 9 L E S A + T
M A X 8 1 9 L E S A +
M A X 8 1 9 L E S A - T
M A X 8 1 9 L E S A
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 + 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
S O I C ; 8 p i n ; . 1 5 0 "
D w g : 2 1 - 0 0 4 1 B ( P D F )
U s e p k g c o d e / v a r i a t i o n : S 8 - 2 *
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
M A X 8 1 9 L C U A +
M A X 8 1 9 L C U A
M A X 8 1 9 L C U A + T
M A X 8 1 9 L C U A - T
M A X 8 1 9 L E U A + T
M A X 8 1 9 L E U A - T
M A X 8 1 9 L E U A
u M A X ; 8 p i n ; 3 x 3 m m
D w g : 2 1 - 0 0 3 6 J ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 8 + 1 *
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
0 C t o + 7 0 C
R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
u M A X ; 8 p i n ; 3 x 3 m m
D w g : 2 1 - 0 0 3 6 J ( P D F )
U s e p k g c o d e / v a r i a t i o n : U 8 - 1 *
R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
R o H S / L e a d - F r e e : Y e s
R o H S / L e a d - F r e e : N o
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
u M A X ; 8 p i n ; 3 x 3 m m
D w g : 2 1 - 0 0 3 6 J ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : N o
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : U 8 - 1 *
M A X 8 1 9 L E U A +
u M A X ; 8 p i n ; 3 x 3 m m
D w g : 2 1 - 0 0 3 6 J ( P D F )
- 4 0 C t o + 8 5 C R o H S / L e a d - F r e e : Y e s
M a t e r i a l s A n a l y s i s
U s e p k g c o d e / v a r i a t i o n : U 8 + 1 *
D i d n ' t F i n d W h a t Y o u N e e d ?
C O N T A C T U S : S E N D U S A N E M A I L
C o p y r i g h t 2 0 0 7 b y M a x i m I n t e g r a t e d P r o d u c t s , D a l l a s S e m i c o n d u c t o r • L e g a l N o t i c e s • P r i v a c y P o l i c y
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