MC10E446FNG [ROCHESTER]
10E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28;
| 型号： | MC10E446FNG |
| 厂家： | 
Rochester Electronics |
| 描述： | 10E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28, LEAD FREE, PLASTIC, LCC-28 输出元件 逻辑集成电路 触发器 |
| 文件： | 总13页 (文件大小：831K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC10E446, MC100E446
5VꢀECL 4-Bit Parallel/Serial
Converter
Description
The MC10E/100E446 is an integrated 4-bit parallel to serial data
converter. The device is designed to operate for NRZ data rates of up to
1.3 Gb/s. The chip generates a divide by 4 and a divide by 8 clock for
both 4-bit conversion and a two chip 8-bit conversion function. The
conversion sequence was chosen to convert the parallel data into a serial
stream from bit D0 to D3. A serial input is provided to cascade two
E446 devices for 8 bit conversion applications. Note that the serial
output data clocks off of the negative input clock transition.
The SYNC input will asynchronously reset the internal clock
circuitry. This pin allows the user to reset the internal clock conversion
unit and thus select the start of the conversion process.
The MODE input is used to select the conversion mode of the device.
With the MODE input LOW, or open, the device will function as a 4-bit
converter. When the mode input is driven HIGH the internal load clock
will change on every eighth clock cycle thus allowing for an 8-bit
conversion scheme using two E446’s. When cascaded in an 8-bit
conversion scheme the devices will not operate at the 1.3 Gb/s data rate
of a single device. Refer to the applications section of this data sheet for
more information on cascading the E446.
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PLCC−28
FN SUFFIX
CASE 776
MARKING DIAGRAM*
1 28
MCxxxE446FNG
AWLYYWW
xxx
A
WL
YY
WW
G
= 10 or 100
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
The V pin, an internally generated voltage supply, is available to
BB
this device only. For single-ended input conditions, the unused
differential input is connected to V as a switching reference voltage.
BB
V
V
may also rebias AC coupled inputs. When used, decouple V and
via a 0.01 mF capacitor and limit current sourcing or sinking to
BB
BB
CC
0.5 mA. When not used, V should be left open.
The 100 Series contains temperature compensation.
BB
*For additional marking information, refer to
Application Note AND8002/D.
Features
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 10 of this data sheet.
• On Chip Clock ÷4 and ÷8
• 1.5 Gb/s Typical Data Rate Capability
• Differential Clock and Serial Inputs
• V Output for Single-ended Input Applications
• Asynchronous Data Synchronization
• Mode Select to Expand to 8 Bits
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC
Latchup Test
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
BB
• PECL Mode Operating Range: V = 4.2 V to 5.7 V
CC
• Transistor Count = 525 devices
with V = 0 V
EE
• Moisture Sensitivity Level: Pb = 1; Pb−Free = 3
For Additional Information, see Application Note
AND8003/D
• NECL Mode Operating Range: V = 0 V
CC
with V = −4.2 V to −5.7 V
EE
• Internal Input 50 kW Pulldown Resistors
• Pb−Free Packages are Available*
• ESD Protection: Human Body Model; > 2 kV,
Machine Model; > 100 V
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
November, 2006 − Rev. 8
MC10E446/D
MC10E446, MC100E446
D0 D1 D2 D3 MODE NC NC
Table 1. PIN DESCRIPTION
25
24
23
22
21
20
19
18
PIN
FUNCTION
CLK 26
CLK 27
NC
NC
SIN
ECL Differential Serial Data Input
ECL Parallel Data Inputs
ECL Differential Serial Data Output
ECL Differential Clock Inputs
ECL Differential ÷4 Clock Output
ECL Differential ÷8 Clock Output
Conversion Mode 4-Bit/8-Bit
ECL Conversion Synchronizing Input
Reference Voltage Output
Positive Supply
D0 − D3
17
16
15
14
13
12
SOUT, SOUT
CLK, CLK
CL/4, CL/4
CL/8, CL/8
MODE
V
BB
V
EE
28
1
V
CC
SOUT
SOUT
MC10E446/MC100E446
SYNC
SIN
SIN
2
V
V
V
BB
CC
EE
, V
CCO
3
V
CCO
Negative Supply
No Connect
NC
SYNC
4
NC
5
6
7
8
9
10
11
V
CCO
CL/8 CL/8
V
CCO
CL/4 CL/4
V
CCO
* All V and V
pins are tied together on the die.
CCO
CC
Warning: All V , V
, and V pins must be externally
CCO EE
CC
connected to Power Supply to guarantee proper operation.
Figure 1. Pinout: PLCC−28 (Top View)
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2
MC10E446, MC100E446
SIN
SIN
D3
0
D
D
D
D
Q
Q
Q
Q
1
CLK
CLK
CLK
CLK
V
EE
0
1
D2
D1
D0
V
EE
0
1
V
EE
0
1
SOUT
SOUT
V
EE
LOAD
PULSE
GENERATOR
CL/8
Mode
CLK
CLK
V
0
1
EE
CL/8
P4
R
P8
R
Delay
CL/4
CL/4
V
EE
SYNC
Figure 2. Logic Diagram
Table 2. FUNCTION TABLES
Mode
Conversion
L
H
4-Bit
8-Bit
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3
MC10E446, MC100E446
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
V
V
PECL Mode Power Supply
V
= 0 V
8
V
CC
I
EE
PECL Mode Input Voltage
NECL Mode Input Voltage
V
V
= 0 V
= 0 V
V v V
6
−6
V
V
EE
CC
I
CC
V w V
I
EE
I
I
Output Current
Continuous
Surge
50
100
mA
mA
out
V
Sink/Source
BB
± 0.5
mA
°C
BB
T
A
Operating Temperature Range
0 to +85
T
stg
Storage Temperature Range
−65 to +150
°C
q
Thermal Resistance (Junction−to−Ambient)
0 lfpm
500 lfpm
PLCC−28
PLCC−28
63.5
43.5
°C/W
°C/W
JA
q
Thermal Resistance (Junction−to−Case)
Standard Board
PLCC−28
22 to 26
°C/W
°C
JC
T
sol
Wave Solder
Pb
Pb−Free
265
265
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
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4
MC10E446, MC100E446
Table 4. 10E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 1)
EE
CCx
0°C
Typ
25°C
Typ
85°C
Typ
Min
Max
151
Min
Max
151
Min
Max
151
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 2)
Unit
mA
mV
mV
mV
mV
mV
V
I
126
126
126
EE
V
3980
4070
4160
4210
3370
4160
3520
3.74
150
4020
4020
3050
3870
3050
3.65
4105
4190
4240
3370
4190
3520
3.75
150
4090
4090
3050
3940
3050
3.69
4185
4280
4330
3405
4280
3555
3.81
150
OH
VOH
Output HIGH Voltage SOUT/SOUT 3980
SOUT
V
V
V
V
Output LOW Voltage (Note 2)
Input HIGH Voltage
3050
3830
3050
3.62
3210
3995
3285
3210
4030
3285
3227
4110
3302
OL
IH
Input LOW Voltage
IL
Output Voltage Reference
Input HIGH Current
BB
I
I
mA
IH
Input LOW Current
0.5
0.3
0.5
0.25
0.3
0.2
mA
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
1. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
2. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 5. 10E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 3)
CCx
EE
0°C
Typ
126
25°C
85°C
Typ
Min
Max
151
Min
Typ
126
Max
151
Min
Max
151
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 4)
Output HIGH Voltage SOUT/SOUT −1020
Unit
mA
mV
mV
I
126
EE
V
−1020 −930
−840
−790
−980
−980
−895
−810
−760
−910
−910
−815
−720
−670
OH
VOH
SOUT
V
V
V
V
Output LOW Voltage (Note 4)
Input HIGH Voltage
−1950 −1790 −1630 −1950 −1790 −1630 −1950 −1773 −1595 mV
−1170 −1005 −840 −1130 −970 −810 −1060 −890 −720 mV
−1950 −1715 −1480 −1950 −1715 −1480 −1950 −1698 −1445 mV
OL
IH
Input LOW Voltage
IL
Output Voltage Reference
Input HIGH Current
−1.38
−1.27 −1.35
−1.25 −1.31
−1.19
V
BB
I
I
150
0.5
150
0.3
150
mA
mA
IH
Input LOW Current
0.5
0.3
0.065
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
3. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.06 V.
CC
EE
4. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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5
MC10E446, MC100E446
Table 6. 100E SERIES PECL DC CHARACTERISTICS V
= 5.0 V; V = 0.0 V (Note 5)
EE
CCx
0°C
25°C
Typ
85°C
Typ
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 6)
Min
Typ
126
Max
151
Min
Max
151
Min
Max
174
Unit
mA
mV
mV
mV
mV
mV
V
I
126
145
EE
V
3975
4050
4120
4170
3380
4120
3525
3.73
150
3975
3975
3190
3835
3190
3.62
4050
4120
4170
3380
4120
3525
3.74
150
3975
3975
3190
3835
3190
3.62
4050
4120
4170
3380
4120
3525
3.74
150
OH
VOH
Output HIGH Voltage SOUT/SOUT 3975
SOUT
V
V
V
V
Output LOW Voltage (Note 6)
Input HIGH Voltage
3190
3835
3190
3.62
3295
3975
3355
3255
3975
3355
3260
3975
3355
OL
IH
Input LOW Voltage
IL
Output Voltage Reference
Input HIGH Current
BB
I
I
mA
IH
Input LOW Current
0.5
0.3
0.5
0.25
0.5
0.2
mA
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
5. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
6. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
Table 7. 100E SERIES NECL DC CHARACTERISTICS V
= 0.0 V; V = −5.0 V (Note 7)
CCx
EE
0°C
25°C
85°C
Typ
145
Symbol
Characteristic
Power Supply Current
Output HIGH Voltage (Note 8)
Output HIGH Voltage SOUT/SOUT −1025
Min
Typ
Max
Min
Typ
Max
Min
Max
174
Unit
mA
mV
mV
I
126
151
126
151
EE
V
−1025 −950
−880 −1025 −950
−830 −1025
−880 −1025 −950
−830 −1025
−880
−830
OH
VOH
SOUT
V
V
V
V
Output LOW Voltage (Note 8)
Input HIGH Voltage
−1810 −1705 −1620 −1810 −1745 −1620 −1810 −1740 −1620 mV
−1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV
−1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV
OL
IH
Input LOW Voltage
IL
Output Voltage Reference
Input HIGH Current
−1.38
−1.27 −1.38
−1.26 −1.38
−1.26
V
BB
I
I
150
0.5
150
0.5
150
mA
mA
IH
Input LOW Current
0.5
0.3
0.25
0.2
IL
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V . V can vary −0.46 V / +0.8 V.
CC
EE
8. Outputs are terminated through a 50 W resistor to V − 2.0 V.
CC
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MC10E446, MC100E446
Table 8. AC CHARACTERISTICS V
= 5.0 V; V = 0.0 V or V
= 0.0 V; V = −5.0 V (Note 9)
CCx EE
CCx
EE
0°C
25°C
Typ
1.6
85°C
Typ
1.6
Min
Typ
Max
Min
1.3
Max
Min
Max
Symbol
Characteristic
Max Conversion Frequency
Unit
F
1.3
1.6
1.3
Gb/s
NRZ
MAX
t
t
Propagation Delay to Output
CLK to SOUT (Note 10) 1020 1200 1480 1020 1200 1480 1020 1200 1480
CLK to CL/4 650 850 1050 650 850 1050 650 850 1050
CLK to CL/8 800 1050 1300 800 1050 1300 800 1050 1300
SYNC to CL/4, CL/8 650 850 1100 650 850 1100 650 850 1100
ps
PLH
PHL
t
t
t
t
t
Setup Time (Note 11)
Hold Time (Note 11)
Reset Recovery Time
Min Pulse Width
SIN, Dn -200 -450 -200 −450 −200 −450
900 650
500 300
ps
s
SIN, Dn 900
SYNC 500
650
300
900
500
300
650
300
ps
h
ps
RR
CLK, MR 300
300
ps
ps
PW
JITTER
Random Clock Jitter (RMS)
< 1
< 1
< 1
V
Input Voltage Swing (Differential Configuration)
150
1000 150
1000 150
1000 mV
PP
t
t
Rise/Fall Times (20% - 80%)
Other
SOUT 100
200
225
425
350
650
100
200
225
425
350
650
100
200
225
425
350
650
ps
r
f
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
9. 10 Series: V can vary −0.46 V / +0.06 V.
EE
100 Series: V can vary −0.46 V / +0.8 V.
EE
10.Propagation delays measured from negative going clock edge.
11. Relative to negative clock edge.
CLK
D
Setup
Hold
Valid Data
SYNC
t
rr
t
t
h
s
CLK
Figure 3.
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7
MC10E446, MC100E446
CLK
RESET
D0
D0−1
D1−1
D2−1
D3−1
D0−2
D1
D1−2
D2
D2−2
D3
D3−2
SOUT
CL/4
CL/8
D0−1 D1−1 D2−1 D3−1 D0−2 D1−2 D2−2 D3−2
Timing Diagram A. 4:1 Parallel to Serial Conversion
CLK
RESET
D0
D0−1
D1−1
D2−1
D3−1
D4−1
D5−1
D6−1
D7−1
D0−2
D1
D1−2
D2
D2−2
D3
D3−2
D4 (D0B)
D5 (D1B)
D6 (D2B)
D7 (D3B)
SOUT
CL/4
D4−2
D5−2
D6−2
D7−2
D0−1 D1−1 D2−1 D3−1 D4−1 D5−1 D6−1 D7−1
D0−2
CL/8
Timing Diagram B. 8:1 Parallel to Serial Conversion
Figure 4. Timing Diagrams
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8
MC10E446, MC100E446
Applications Information
The MC10E/100E446 is an integrated 4:1 parallel to serial
delaying the clock feeding E446A relative to the clock of
E446B the frequency of operation can be increased.
converter. The chip is designed to work with the E445 device
to provide both transmission and receiving of a high speed
serial data path. The E446 can convert 4 bits of data into a
1.3 Gb/s NRZ data stream. The device features a SYNC
input which allows the user to reset the internal clock
circuitry and restart the conversion sequence
(see timing diagram A).
The E446 features a differential serial input and internal
divide by 8 circuitry to facilitate the cascading of two
devices to build a 8:1 multiplexer. Figure 1 illustrates the
architecture for a 8:1 multiplexer using two E446’s; the
timing diagram for this configuration can be found on the
following page. Notice the serial outputs (SOUT) of the
higher order converter feed the serial inputs of the the lower
order device. This feed through of the serial inputs bounds
the upper end of the frequency of operation. The clock to
serial output propagation delay plus the setup time of the
serial input pins must fit into a single clock period for the
cascade architecture to function properly. Using the worst
case values for these two parameters from the data sheet,
TPD CLK to SOUT = 1480 ps and tS for SIN = −200 ps,
yields a minimum period of 1280 ps or a clock frequency of
780 MHz.
CLK
CLK
E446B
E446A
Serial
Data
SOUT
SOUT
SIN
SIN
SOUT
SOUT
Q3 Q2 Q1 Q0
Q3 Q2 Q1 Q0
MSB
LSB
Q7 Q6 Q5 Q4
Q3 Q2 Q1 Q0
Parallel Data
1000ps
600ps
CLOCK
CLK
T
pd
to SOUT
1000ps
1600ps
The clock frequency is somewhat lower than that of a
single converter, to increase this frequency some games can
be played with the clock input of the higher order E446. By
Figure 5. Cascaded 8:1 Converter Architecture
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MC10E446, MC100E446
Z = 50 W
Q
Q
D
D
o
Receiver
Device
Driver
Device
Z = 50 W
o
50 W
50 W
V
TT
V
= V − 2.0 V
TT
CC
Figure 6. Typical Termination for Output Driver and Device Evaluation
(See Application Note AND8020/D − Termination of ECL Logic Devices.)
ORDERING INFORMATION
†
Device
Package
Shipping
MC10E446FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC10E446FNG
PLCC−28
(Pb−Free)
MC10E446FNR2
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
MC10E446FNR2G
PLCC−28
(Pb−Free)
MC100E446FN
PLCC−28
37 Units / Rail
37 Units / Rail
MC100E446FNG
PLCC−28
(Pb−Free)
MC100E446FNR2
MC100E446FNR2G
PLCC−28
500 / Tape & Reel
500 / Tape & Reel
PLCC−28
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D
AN1406/D
AN1503/D
AN1504/D
AN1568/D
AN1672/D
AND8001/D
AND8002/D
AND8020/D
AND8066/D
AND8090/D
−
−
−
−
−
−
−
−
−
−
−
ECL Clock Distribution Techniques
Designing with PECL (ECL at +5.0 V)
ECLinPSt I/O SPiCE Modeling Kit
Metastability and the ECLinPS Family
Interfacing Between LVDS and ECL
The ECL Translator Guide
Odd Number Counters Design
Marking and Date Codes
Termination of ECL Logic Devices
Interfacing with ECLinPS
AC Characteristics of ECL Devices
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MC10E446, MC100E446
PACKAGE DIMENSIONS
PLCC−28
FN SUFFIX
PLASTIC PLCC PACKAGE
CASE 776−02
ISSUE E
M
S
S
N
0.007 (0.180)
T L−M
B
Y BRK
D
−N−
M
S
S
N
0.007 (0.180)
T L−M
U
Z
−M−
−L−
W
D
S
S
S
N
0.010 (0.250)
T L−M
X
G1
V
28
1
VIEW D−D
M
S
S
S
A
0.007 (0.180)
0.007 (0.180)
T L−M
T L−M
N
M
S
S
N
0.007 (0.180)
T L−M
H
Z
M
S
N
R
K1
C
E
0.004 (0.100)
G
K
SEATING
PLANE
−T−
J
M
S
S
N
0.007 (0.180)
T L−M
F
VIEW S
G1
S
S
S
N
0.010 (0.250)
T L−M
VIEW S
NOTES:
INCHES
MILLIMETERS
1. DATUMS −L−, −M−, AND −N− DETERMINED
WHERE TOP OF LEAD SHOULDER EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2. DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM −T−, SEATING PLANE.
3. DIMENSIONS R AND U DO NOT INCLUDE
MOLD FLASH. ALLOWABLE MOLD FLASH IS
0.010 (0.250) PER SIDE.
4. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
5. CONTROLLING DIMENSION: INCH.
6. THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE
DETERMINED AT THE OUTERMOST
EXTREMES OF THE PLASTIC BODY
EXCLUSIVE OF MOLD FLASH, TIE BAR
BURRS, GATE BURRS AND INTERLEAD
FLASH, BUT INCLUDING ANY MISMATCH
BETWEEN THE TOP AND BOTTOM OF THE
PLASTIC BODY.
DIM MIN
MAX
0.495
0.495
0.180
0.110
0.019
MIN
12.32
12.32
4.20
MAX
12.57
12.57
4.57
A
B
C
E
F
0.485
0.485
0.165
0.090
0.013
2.29
0.33
2.79
0.48
G
H
J
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.450
0.450
0.042
0.042
0.042
0.032
−−−
−−−
0.66
0.51
0.64
11.43
11.43
1.07
1.07
1.07
−−−
0.81
−−−
K
R
U
V
W
X
Y
Z
−−−
0.456
0.456
0.048
0.048
0.056
11.58
11.58
1.21
1.21
1.42
0.50
10
−−− 0.020
10
2
2
_
_
_
_
G1 0.410
K1 0.040
0.430
−−−
10.42
1.02
10.92
−−−
7. DIMENSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTRUSION(S) SHALL NOT CAUSE THE H
DIMENSION TO BE GREATER THAN 0.037
(0.940). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMENSION TO BE
SMALLER THAN 0.025 (0.635).
http://onsemi.com
11
MC10E446, MC100E446
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC).
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are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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MC10E446/D
相关型号：
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10E SERIES, 4-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, COMPLEMENTARY OUTPUT, PQCC28, PLASTIC, LCC-28
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