MC68HC05C8B [ROCHESTER]
Microcontroller, 8-Bit, MROM, HCMOS, PDIP42, PLASTIC, SHRINK, DIP-42;型号: | MC68HC05C8B |
厂家: | Rochester Electronics |
描述: | Microcontroller, 8-Bit, MROM, HCMOS, PDIP42, PLASTIC, SHRINK, DIP-42 微控制器 光电二极管 |
文件: | 总156页 (文件大小:1755K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MC68HC05C8A/D
REV 4
MC68HC05C8A
MC68HCL05C8A
MC68HSC05C8A
Advance Information
HCMOS
Microcontroller Unit
Motorola reserves the right to make changes without further notice to any products
herein. Motorola makes no warranty, representation or guarantee regarding the
suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential or incidental
damages. "Typical" parameters which may be provided in Motorola data sheets and/or
specifications can and do vary in different applications and actual performance may
vary over time. All operating parameters, including "Typicals" must be validated for
each customer application by customer’s technical experts. Motorola does not convey
any license under its patent rights nor the rights of others. Motorola products are not
designed, intended, or authorized for use as components in systems intended for
surgical implant into the body, or other applications intended to support or sustain life,
or for any other application in which the failure of the Motorola product could create a
situation where personal injury or death may occur. Should Buyer purchase or use
Motorola products for any such unintended or unauthorized application, Buyer shall
indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and
distributors harmless against all claims, costs, damages, and expenses, and
reasonable attorney fees arising out of, directly or indirectly, any claim of personal
injury or death associated with such unintended or unauthorized use, even if such claim
alleges that Motorola was negligent regarding the design or manufacture of the part.
Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
Motorola and
are registered trademarks of Motorola, Inc.
DigitalDNA is a trademark of Motorola, Inc.
© Motorola, Inc., 2000
Advance Information — MC68HC05C8A
List of Sections
Section 1. General Description . . . . . . . . . . . . . . . . . . . .17
Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Section 3. Central Processor Unit (CPU) . . . . . . . . . . . .35
Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Section 6. Low-Power Modes. . . . . . . . . . . . . . . . . . . . . .49
Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . .53
Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Section 9. Serial Communications Interface (SCI). . . . .67
Section 10. Serial Peripheral Interface (SPI). . . . . . . . . .85
Section 11. Operating Modes. . . . . . . . . . . . . . . . . . . . . .95
Section 12. Instruction Set. . . . . . . . . . . . . . . . . . . . . . .101
Section 13. Electrical Specifications. . . . . . . . . . . . . . .119
Section 14. Mechanical Specifications . . . . . . . . . . . . .135
Section 15. Ordering Information . . . . . . . . . . . . . . . . .139
Appendix A. MC68HCL05C8A . . . . . . . . . . . . . . . . . . . .143
Appendix B. MC68HSC05C8A . . . . . . . . . . . . . . . . . . . .147
Appendix C. M68HC05Cx Family Feature
Comparisons . . . . . . . . . . . . . . . . . . . . . .153
MC68HC05C8A — Rev. 4.0
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Table of Contents
Section 1. General Description
1.1
1.2
1.3
1.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Port C (PC0–PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.10 Port D (PD0–PD5 and PD7). . . . . . . . . . . . . . . . . . . . . . . . .25
Section 2. Memory
2.1
2.2
2.3
2.4
2.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .28
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Section 3. Central Processor Unit (CPU)
3.1
3.2
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
Section 4. Interrupts
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .41
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Serial Communications Interrupt (SCI). . . . . . . . . . . . . . . . . . .43
Serial Peripheral Interrupt (SPI) . . . . . . . . . . . . . . . . . . . . . . . .44
Section 5. Resets
5.1
5.2
5.3
5.4
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.5
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .46
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . .47
5.5.1
5.5.2
5.5.3
5.5.4
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Section 6. Low-Power Modes
6.1
6.2
6.3
6.4
6.5
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Section 7. Input/Output (I/O) Ports
7.1
7.2
7.3
7.4
7.5
7.6
7.7
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Section 8. Timer
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
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Section 9. Serial Communications Interface (SCI)
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
9.1
9.2
9.3
9.4
9.5
9.5.1
SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.1.5
9.5.2
9.5.2.1
9.5.2.2
9.5.2.3
9.5.2.4
9.5.2.5
9.5.2.6
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . .69
Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receiver Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . .75
Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
9.6
SCI Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . .76
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
Section 10. Serial Peripheral Interface (SPI)
10.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.4.1 Master In Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . .86
10.4.2 Master Out Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . .86
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10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . .91
10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . .92
10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . .94
Section 11. Operating Modes
11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11.3 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
11.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11.4.1 Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11.4.2 Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
Section 12. Instruction Set
12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .106
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .107
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .108
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12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
Section 13. Electrical Specifications
13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .120
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
13.7 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .123
13.8 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .124
13.9 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
13.10 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.11 5.0-V Serial Peripheral Interface Timing . . . . . . . . . . . . . . .130
13.12 3.3-V Serial Peripheral Interface Timing . . . . . . . . . . . . . . .131
Section 14. Mechanical Specifications
14.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03). . .136
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP)
Package (Case 858-01). . . . . . . . . . . . . . . . . . . . . . . . . . .136
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
14.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01) . . . . . . . . . .138
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Table of Contents
Section 15. Ordering Information
15.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .140
15.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .141
15.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .141
Appendix A. MC68HCL05C8A
A.1
A.2
A.3
A.4
A.5
A.6
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Low-Power Operating Temperature Range . . . . . . . . . . . . . .143
2.5-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . .144
1.8-V to 2.4-V DC Electrical Characteristics. . . . . . . . . . . . . .144
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . .145
Appendix B. MC68HSC05C8A
B.1
B.2
B.3
B.4
B.5
B.6
B.7
B.8
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
High-Speed Operating Temperature Range. . . . . . . . . . . . . .147
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .148
4.5-V to 5.5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .149
2.4-V to 3.6-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .150
4.5-V to 5.5-V High-Speed SPI Timing. . . . . . . . . . . . . . . . . .151
2.4-V to 3.6-V High-Speed SPI Timing. . . . . . . . . . . . . . . . . .152
Appendix C. M68HC05Cx Family Feature Comparisons
MC68HC05C8A — Rev. 4.0
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11
Table of Contents
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12
MC68HC05C8A — Rev. 4.0
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List of Figures
Figure
Title
Page
1-1
1-2
1-3
1-4
1-5
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
40-Pin Dual In-Line Package . . . . . . . . . . . . . . . . . . . . . . . . . .21
42-Pin Plastic Shrink Dual In-Line Package . . . . . . . . . . . . . . .22
44-Lead Plastic Leaded Chip Carrier . . . . . . . . . . . . . . . . . . . .23
44-Lead Quad Flat Pack. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
2-1
2-2
Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Input/Output Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
3-1
3-2
Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
4-1
Interrupt Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42
6-1
6-2
Stop/Wait Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . .51
7-1
7-2
Port B Pullup Option. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
8-1
8-2
8-3
8-4
8-5
Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58
Output Compare Operation . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Input Capture Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62
Timer Control Register (TCR). . . . . . . . . . . . . . . . . . . . . . . . . .63
Timer Status Register (TSR) . . . . . . . . . . . . . . . . . . . . . . . . . .64
9-1
9-2
9-3
SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
SCI Transmitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71
SCI Receiver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73
MC68HC05C8A — Rev. 4.0
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List of Figures
13
List of Figures
Figure
Title
Page
9-4
9-5
9-6
9-7
9-8
SCI Data Register (SCDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Control Register 1 (SCCR1) . . . . . . . . . . . . . . . . . . . . . . .77
SCI Control Register 2 (SCCR2) . . . . . . . . . . . . . . . . . . . . . . .78
SCI Status Register (SCSR). . . . . . . . . . . . . . . . . . . . . . . . . . .80
Baud Rate Register (BAUD). . . . . . . . . . . . . . . . . . . . . . . . . . .82
10-1 Data Clock Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10-2 Serial Peripheral Interface Block Diagram . . . . . . . . . . . . . . . .89
10-3 Serial Peripheral Interface Master-Slave Interconnection . . . .90
10-4 SPI Control Register (SPCR) . . . . . . . . . . . . . . . . . . . . . . . . . .91
10-5 SPI Status Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . .92
10-6 SPI Data Register (SPSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . .94
11-1 User Mode Pinout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
11-2 Self-Check Circuit Schematic . . . . . . . . . . . . . . . . . . . . . . . . . .99
13-1 Test Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122
13-2 Maximum Supply Current versus Internal
Clock Frequency, VDD = 5.5 V. . . . . . . . . . . . . . . . . . . . . .125
13-3 Maximum Supply Current versus Internal
Clock Frequency, VDD = 3.6 V. . . . . . . . . . . . . . . . . . . . . .125
13-4 TCAP Timing Relationships . . . . . . . . . . . . . . . . . . . . . . . . . .127
13-5 External Interrupt Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13-6 External Reset Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128
13-7 STOP Recovery Timing Diagram . . . . . . . . . . . . . . . . . . . . . .129
13-8 Power-On Reset Timing Diagram. . . . . . . . . . . . . . . . . . . . . .129
13-9 SPI Master Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . .132
13-10 SPI Slave Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . .133
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List of Tables
Table
Title
Page
4-1
7-1
Vector Addresses for Interrupts and Reset. . . . . . . . . . . . . . . .40
I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
9-1
9-2
9-3
Baud Rate Generator Clock Prescaling . . . . . . . . . . . . . . . . . .82
Baud Rate Selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83
Baud Rate Selection Examples . . . . . . . . . . . . . . . . . . . . . . . .84
10-1 Serial Peripheral Rate Selection. . . . . . . . . . . . . . . . . . . . . . . .92
11-1 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11-2 Self-Check Circuit LED Codes . . . . . . . . . . . . . . . . . . . . . . . . .98
12-1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . . .106
12-2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . . .107
12-3 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . .109
12-4 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .110
12-5 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12-6 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12-7 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .118
C-1 M68HC05Cx Feature Comparison . . . . . . . . . . . . . . . . . . . . .154
MC68HC05C8A — Rev. 4.0
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List of Tables
15
List of Tables
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16
MC68HC05C8A — Rev. 4.0
List of Tables
MOTOROLA
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Section 1. General Description
1.1 Contents
1.2
1.3
1.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
1.5
Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
VDD and VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
IRQ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
OSC1 and OSC2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
TCAP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
TCMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24
Port A (PA0–PA7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Port B (PB0–PB7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
Port C (PC0–PC7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
1.5.1
1.5.2
1.5.3
1.5.4
1.5.5
1.5.6
1.5.7
1.5.8
1.5.9
1.5.10 Port D (PD0–PD5 and PD7). . . . . . . . . . . . . . . . . . . . . . . . .25
1.2 Introduction
The MC68HC05C8A is an enhanced version of the MC68HC05C8. It
includes keyboard scanning logic, a high current pin, a computer
operating properly (COP) watchdog timer, and read-only memory (ROM)
security feature.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
General Description
17
General Description
1.3 Features
• M68HC05 core
• Single 3.0- to 5.5-volt supply
• Available packages:
– 40-pin dual in-line (DIP)
– 42-pin plastic shrink dual in-line (SDIP)
– 44-lead plastic leaded chip carrier (PLCC)
– 44-lead quad flat pack (QFP)
• On-chip oscillator for crystal/ceramic resonator
• Fully static operation
• 7744 bytes of user ROM
• ROM security feature
• 176 bytes of on-chip random-access memory (RAM)
• Asynchronous serial communications interface (SCI) system
• Synchronous serial peripheral interface (SPI) system
• 16-bit capture/compare timer system
• Computer operating properly (COP) watchdog timer
• 24 bidirectional input/output (I/O) lines
• Seven input-only lines
• User mode
• Self-check mode
• Power-saving stop and wait modes
• High current sink and source on one port pin (PC7)
• Mask selectable external interrupt sensitivity
• Mask-programmable keyscan logic
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18
MC68HC05C8A — Rev. 4.0
General Description
MOTOROLA
General Description
Features
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
USER ROM AND USER VECTORS — 7744 BYTES
SELF-CHECK ROM — 240 BYTES
SRAM — 176 BYTES
PB0*
PB1*
PB2*
PB3*
PB4*
PB5*
PB6*
PB7*
IRQ
RESET
CPU
ALU
CONTROL
M68HC05 CPU
CPU REGISTERS
ACCUMULATOR
PC0
INDEX REGISTER
PC1
0
0
0
0
0
0
1
1
STACK POINTER
PC2
PC3
PROGRAM COUNTER
0
0
PC4
1
1
I
Z
N
C
1
H
CONDITION CODE REGISTER
PC5
PC6
PC7✝½½°
OSC2
OSC1
÷ 2
OSCILLATOR
PD7
PORT D
SCI
RDI(PD0)
TDO(PD1)
MISO(PD2)
MOSI(PD3)
COP
SYSTEM
BAUD RATE
GENERATOR
V
DD
SPI
POWER
V
SCK(PD4)
SS(PD5)
SS
BAUD RATE
GENERATOR
TCMP
TCAP
16-BIT
CAPTURE/COMPARE
TIMER SYSTEM
* Port B pins also function as external interrupts.
✝ PC7 has a high current sink and source capability.
Figure 1-1. Block Diagram
MC68HC05C8A — Rev. 4.0
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19
MOTOROLA
General Description
General Description
1.4 Mask Options
Eight mask options are available to select the pullup/interrupts on port B
on a pin-by-pin basis.
There are also four mask options for:
1. IRQ (edge-sensitive only or edge- and level-sensitive)
2. CLOCK (crystal or RC)
3. COP (enable or disable)
4. STOP (enable or disable).
1.5 Functional Pin Description
The MC68HC05C8A is available in a 40-pin DIP (see Figure 1-2),
42-pin SDIP (see Figure 1-3), 44-pin PLCC (see Figure 1-4), and
44-pin QFP (see Figure 1-5). The following paragraphs describe the
general function of each pin.
NOTE: A line over a signal name indicates an active low signal. For example,
RESET is active high and RESET is active low. Any reference to voltage,
current, resistance, capacitance, time, or frequency specified in the
following paragraphs will refer to the nominal values. The exact values
and their tolerance or limits are specified in Section 13. Electrical
Specifications.
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20
MC68HC05C8A — Rev. 4.0
General Description
MOTOROLA
General Description
Functional Pin Description
1
40
39
38
37
36
35
34
V
DD
RESET
IRQ
2
OSC1
OSC2
TCAP
PD7
3
NC*
PA7
PA6
PA5
PA4
PA3
4
5
6
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
33
32
9
PA2
PA1
10
11
12
13
14
15
16
31
30
29
28
27
26
25
24
23
22
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PC1
PC2
PC3
PC4
17
18
PC5
PC6
19
20
PB7
V
21
PC7
SS
* If MC68HC705C8A OTPs are to be used in the
same application,
Figure 1-2. 40-Pin Dual In-Line Package
MC68HC05C8A — Rev. 4.0
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21
MOTOROLA
General Description
General Description
RESET
IRQ
1
2
3
4
5
6
7
8
9
42 VDD
41 OSC1
40 OSC2
39 TCAP
38 PD7
NC*
PA7
PA6
PA5
PA4
PA3
PA2
37 TCMP
36 PD5/SS
35 PD4/SCK
34 PD3/MOSI
33 PD2/MISO
32 PD1/TDO
31 PD0/RDI
30 PC0
PA1 10
PA0 11
PB0 12
PB1 13
PB2 14
PB3 15
NC 16
29 PC1
28 PC2
27 NC
PB4 17
PB5 18
PB6 19
26 PC3
25 PC4
24 PC5
20
23 PC6
PB7
VSS 21
22 PC7
* If MC68HC705C8A OTPs are to be used in the
same application,
Figure 1-3. 42-Pin Plastic Shrink Dual In-Line Package
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22
MC68HC05C8A — Rev. 4.0
MOTOROLA
General Description
General Description
Functional Pin Description
39
38
37
36
35
34
33
32
PD7
PA5
PA4
PA3
7
8
9
TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PA2 10
11
12
13
14
PA1
PA0
PB0
PB1
PB2 15
31 PC0
PC1
29 PC2
16
17
PB3
PB4
30
* If MC68HC705C8A OTPs are to be used in the
same application,
Figure 1-4. 44-Lead Plastic Leaded Chip Carrier
33 32 31 30 29 28 27 26 25 24 23
PD7
TCAP
OSC2
OSC1
VDD
34
35
36
37
38
39
40
41
42
43
22
21
20
19
18
17
16
15
14
13
12
NC
PC4
PC5
PC6
PC7
VSS
NC
NC
NC
RESET
IRQ
PB7
PB6
PB5
PB4
NC*
44
PA7
1
2
3
4
5
6
7
8
9 10 11
* If MC68HC705C8A OTPs are to be used in the
same application,
Figure 1-5. 44-Lead Quad Flat Pack
MC68HC05C8A — Rev. 4.0
Advance Information
23
MOTOROLA
General Description
General Description
1.5.1 VDD and VSS
Power is supplied to the microcontroller using these two pins. VDD is the
positive supply and VSS is ground.
1.5.2 IRQ
This pin has a mask selectable option that provides two different choices
of interrupt triggering sensitivity. The IRQ pin contains an internal
Schmitt trigger as part of its input to improve noise immunity. Refer to
Section 4. Interrupts for more detail.
1.5.3 OSC1 and OSC2
These pins provide control input for an on-chip clock oscillator circuit. A
crystal, a ceramic resonator, a resistor/capacitor combination, or an
external signal connects to these pins providing a system clock. The
internal bus rate is one-half the external oscillator frequency.
1.5.4 RESET
1.5.5 TCAP
1.5.6 TCMP
This active low pin is used to reset the MCU to a known startup state by
pulling RESET low. The RESET pin contains an internal Schmitt trigger
as part of its input to improve noise immunity.
This pin controls the input capture feature for the on-chip programmable
timer. The TCAP pin contains an internal Schmitt trigger as part of its
input to improve noise immunity.
The TCMP pin provides an output for the output compare feature of the
on-chip timer subsystem.
Advance Information
24
MC68HC05C8A — Rev. 4.0
General Description
MOTOROLA
General Description
Functional Pin Description
1.5.7 Port A (PA0–PA7)
These eight input/output (I/O) lines comprise port A. The state of any pin
is software programmable and all port A lines are configured as input
during power-on or reset. For detailed information on I/O programming,
see 7.7 Input/Output Programming.
1.5.8 Port B (PB0–PB7)
These eight I/O lines comprise port B. The state of any pin is software
programmable, and all port B lines are configured as input during power-
on or reset. Port B has mask option enabled pullup devices and interrupt
capability by pin. The interrupts and pullups are enabled together. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.9 Port C (PC0–PC7)
These eight I/O lines comprise port C. The state of any pin is software
programmable and all port C lines are configured as input during power-
on or reset. PC7 has high current sink and source capability. For a
detailed description on I/O programming, refer to 7.7 Input/Output
Programming.
1.5.10 Port D (PD0–PD5 and PD7)
These seven port lines comprise port D. PD7 and PD5–PD0 are input
only. PD0 and PD1 are shared with the SCI subsystem and PD2–PD5
are shared with the SPI subsystem. For a detailed description on I/O
programming, refer to 7.7 Input/Output Programming.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
General Description
25
General Description
Advance Information
26
MC68HC05C8A — Rev. 4.0
General Description
MOTOROLA
Advance Information — MC68HC05C8A
Section 2. Memory
2.1 Contents
2.2
2.3
2.4
2.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27
Read-Only Memory (ROM). . . . . . . . . . . . . . . . . . . . . . . . . . . .27
ROM Security Feature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
Random-Access Memory (RAM) . . . . . . . . . . . . . . . . . . . . . . .28
2.2 Introduction
The MC68HC05C8A has an 8-Kbyte memory map, consisting of user
read-only memory (ROM), user random-access memory (RAM), self-
check ROM, and input/output (I/O) registers. See Figure 2-1 and
Figure 2-2.
2.3 Read-Only Memory (ROM)
The user ROM consists of 48 bytes of page zero ROM from $0020 to
$004F, 7680 bytes of user ROM from $0100 to $1EFF, and 16 bytes of
user vectors from $1FF0 to $1FFF. The self-check ROM and vectors are
located from $1F00 to $1FEF. See Figure 2-1.
Twelve of the user vectors, $1FF4–$1FFF, are dedicated to user-
defined reset and interrupt vectors. The remaining four bytes from
$1FF0–$1FF3 are not used.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Memory
27
Memory
2.4 ROM Security Feature
A security(1) feature has been incorporated into the MC68HC05C8A to
help prevent externally reading of code in the ROM. This feature aids in
keeping customer developed software proprietary.
2.5 Random-Access Memory (RAM)
The user RAM consists of 176 bytes and is used both for general-
purpose RAM and stack area. The stack begins at address $00FF. The
stack pointer can access 64 bytes of RAM in the range $00FF to $00C0.
See Figure 2-1.
NOTE: Using the stack area for data storage or temporary work locations
requires care to prevent it from being overwritten due to stacking from an
interrupt or subroutine call.
1. No security feature is absolutely secure. However, Motorola’s strategy is to make reading or
copying the ROM difficult for unauthorized users.
Advance Information
28
MC68HC05C8A — Rev. 4.0
Memory
MOTOROLA
Memory
Random-Access Memory (RAM)
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
PORT A DATA REGISTER
PORT B DATA REGISTER
PORT C DATA REGISTER
PORT D DATA REGISTER
PORT A DATA DIRECTION REGISTER
PORT B DATA DIRECTION REGISTER
PORT C DATA DIRECTION REGISTER
UNUSED
I/O REGISTERS
32 BYTES
$001F
$0020
USER ROM
48 BYTES
$004F
$0050
UNUSED
UNUSED
RAM
176 BYTES
SPI CONTROL REGISTER
SPI STATUS REGISTER
SPI DATA REGISTER
$00BF
$00C0
(STACK)
64 BYTES
SCI BAUD RATE REGISTER
SCI CONTROL REGISTER 1
SCI CONTROL REGISTER 2
SCI STATUS REGISTER
SCI DATA REGISTER
$00FF
$0100
TIMER CONTROL REGISTER
TIMER STATUS REGISTER
INPUT CAPTURE REGISTER (HIGH)
INPUT CAPTURE REGISTER (LOW)
OUTPUT COMPARE REGISTER (HIGH)
OUTPUT COMPARE REGISTER (LOW)
TIMER COUNTER REGISTER (HIGH)
TIMER COUNTER REGISTER (LOW)
ALTERNATE COUNTER REGISTER (HIGH)
ALTERNATE COUNTER REGISTER (LOW)
UNUSED
USER ROM
7680 BYTES
UNUSED
UNUSED
UNUSED
COP REGISTER
$1FF0
$1FF1
$1FF2
$1EFF
$1F00
NOT USED (3 BYTES)
$1FF3
$1FF4
$1FF5
$1FF6
$1FF7
$1FF8
$1FF9
$1FFA
$1FFB
$1FFC
$1FFD
$1FFE
$1FFF
SPI VECTOR (HIGH)
SPI VECTOR (LOW)
SELF-CHECK
ROM
SCI VECTOR (HIGH)
AND VECTORS
240 BYTES
SCI VECTOR (LOW)
TIMER VECTOR (HIGH)
TIMER VECTOR (LOW)
IRQ VECTOR (HIGH)
IRQ VECTOR (LOW)
SWI VECTOR (HIGH)
SWI VECTOR (LOW)
$1FEF
$1FF0
USER ROM VECTORS
16 BYTES
RESET VECTOR (HIGH BYTE)
RESET VECTOR (LOW BYTE)
$1FFF
Figure 2-1. Memory Map
MC68HC05C8A — Rev. 4.0
Advance Information
29
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Port A Data Register
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
$0000
(PORTA) Write:
See page 54.
Reset:
Read:
Unaffected by reset
PB4 PB3
Unaffected by reset
PC4 PC3
Unaffected by reset
PD4 PD3
Unaffected by reset
Port B Data Register
PB7
PC7
PD7
PB6
PC6
PB5
PC5
PD5
PB2
PC2
PD2
PB1
PC1
PD1
PB0
PC0
PD0
$0001
$0002
$0003
(PORTB) Write:
See page 54.
Reset:
Read:
Port C Data Register
(PORTC) Write:
See page 55.
Reset:
Read:
Port D Data Register
(PORTD) Write:
See page 55.
Reset:
Read:
Port A Data Direction Register
DDRA7 DDRA6 DDRA5 DDRA4
DDRA3
DDRA2 DDRA1 DDRA0
$0004
$0005
(DDRA) Write:
See page 54.
Reset:
Read:
0
0
0
0
0
DDRB3
0
0
0
0
Port B Data Direction Register
DDRB7 DDRB6 DDRB5 DDRB4
DDRB2 DDRB1 DDRB0
(DDRB) Write:
See page 54.
Reset:
Read:
0
0
0
0
0
0
0
Port C Data Direction Register
DDRC7 DDRC6 DDRC5 DDRC4
DDRC3
0
DDRC2 DDRC1 DDRC0
$0006
$0007
$0008
$0009
(DDRC) Write:
See page 55.
Reset:
0
0
0
0
0
0
0
Unimplemented
Unimplemented
Unimplemented
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 1 of 4)
Advance Information
30
MC68HC05C8A — Rev. 4.0
Memory
MOTOROLA
Memory
Random-Access Memory (RAM)
Addr.
Register Name
Bit 7
SPIE
0
6
SPE
0
5
4
MSTR
0
3
2
1
Bit 0
Read:
SPI Control Register
CPOL
CPHA
SPR1
SPR0
$000A
(SPCR) Write:
See page 91.
Reset:
Read:
0
0
0
0
0
0
U
0
U
0
SPI Status Register
SPIF
0
WCOL
0
MODF
0
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
(SPSR) Write:
See page 92.
Reset:
Read:
0
0
0
U
U
SPI Data Register
SPD7
SPD6
SPD5
SPD4
SPD31
SPD2
SPD1
SPD0
(SPDR) Write:
See page 94.
Reset:
Read:
Unaffected by reset
SCI Baud Rate Register
0
0
0
0
SCP1
SCP0
0
0
0
SCR2
SCR1
SCR0
BAUD Write:
See page 82.
Reset:
0
0
U
0
U
0
U
0
Read: R8
SCI Control Register 1
T8
M
WAKE
(SCCR1) Write:
See page 77.
Reset:
Unaffected by reset
Read:
TIE
SCI Control Register 2
TCIE
RIE
ILIE
TE
RE
RMW
SBK
(SCCR2) Write:
See page 78.
Reset:
0
0
0
0
0
0
0
0
0
Read: TDRE
TC
RDRF
IDLE
OR
NF
FE
SCI Status Register
(SCSR) Write:
See page 80.
Reset:
Read:
0
0
0
0
0
0
0
0
SCI Data Register
SCD7
SDC5
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
(SCDAT) Write:
See page 76.
Reset:
Read:
Unaffected by reset
Timer Control Register
ICIE
0
OCIE
0
TOIE
0
0
0
0
0
IEDGE
U
OLVL
0
(TCR) Write:
See page 63.
Reset:
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 2 of 4)
MC68HC05C8A — Rev. 4.0
Advance Information
31
MOTOROLA
Memory
Memory
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: ICF
OCF
TOF
0
0
0
0
0
Timer Status Register
$0013
(TSR) Write:
See page 64.
Reset:
U
U
U
0
0
0
0
0
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Input Capture Register High
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
(ICR) Write:
See page 61.
Reset:
Unaffected by reset
Bit 4 Bit 3
Read: Bit 7
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Input Capture Register Low
(ICR) Write:
See page 61.
Reset:
Unaffected by reset
Bit 12 Bit 11
Unaffected by reset
Bit 4 Bit 3
Unaffected by reset
Read:
Bit 15
Output Compare Register
Bit 14
Bit 13
Bit 10
High (OCR) Write:
See page 60.
Reset:
Read:
Bit 7
Output Compare Register
Bit 6
Bit 5
Bit 2
Bit 1
Bit 9
Bit 0
Bit 8
Low (OCR) Write:
See page 60.
Reset:
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Timer Counter Register High
(TCNT) Write:
See page 59.
Reset:
1
1
1
1
1
1
1
1
Read: Bit 7
Write:
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Timer Counter Register Low
(TCNT)
See page 59.
Reset:
1
1
1
1
1
1
1
1
Read: Bit 15
Bit 14
Bit 13
Bit 12
Bit 11
Bit 10
Bit 9
Bit 8
Alternate Counter Register
High (ALTCNT) Write:
See page 59.
Reset:
1
1
1
1
1
1
1
1
Read: Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Alternate Counter Register
Low (ALTCNT) Write:
See page 59.
Reset:
1
1
1
1
1
1
1
1
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 3 of 4)
Advance Information
32
MC68HC05C8A — Rev. 4.0
Memory
MOTOROLA
Memory
Random-Access Memory (RAM)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
$001C
Unimplemented
$001D
$001E
Unimplemented
Unimplemented
Reserved
$001F
R
R
R
R
R
R
R
R
↓
↓
Read:
Write:
Reset:
User ROM data
COP Reset Register
See page 46.
$1FF0
COPC
0
0
0
0
0
0
0
0
= Unimplemented
R
= Reserved
U = Unaffected
Figure 2-2. Input/Output Registers (Sheet 4 of 4)
MC68HC05C8A — Rev. 4.0
Advance Information
33
MOTOROLA
Memory
Memory
Advance Information
34
MC68HC05C8A — Rev. 4.0
Memory
MOTOROLA
Advance Information — MC68HC05C8A
Section 3. Central Processor Unit (CPU)
3.1 Contents
3.2
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
3.3
CPU Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Index Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36
Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37
Condition Code Register . . . . . . . . . . . . . . . . . . . . . . . . . . .37
3.3.1
3.3.2
3.3.3
3.3.4
3.3.5
3.2 Introduction
This section describes the central processor unit (CPU) registers.
3.3 CPU Registers
The five CPU registers are shown in Figure 3-1 and the interrupt
stacking order in Figure 3-2.
MC68HC05C8A — Rev. 4.0
Advance Information
35
MOTOROLA
Central Processor Unit (CPU)
Central Processor Unit (CPU)
7
7
A
X
0
0
ACCUMULATOR
INDEX REGISTER
12
12
0
0
PC
1
PROGRAM COUNTER
STACK POINTER
7
1
0
0
0
0
0
SP
CCR
H
I
N
Z
C
CONDITION CODE REGISTER
Figure 3-1. Programming Model
7
0
CONDITION CODE REGISTER
ACCUMULATOR
INDEX REGISTER
PCH
STACK
1
1
1
I
N
T
E
R
R
U
P
R
E
T
U
R
N
INCREASING
MEMORY
ADDRESSES
DECREASING
MEMORY
ADDRESSES
T
PCL
UNSTACK
NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first,
followed by PCH, etc. Pulling from the stack is in the reverse order.
Figure 3-2. Stacking Order
3.3.1 Accumulator
3.3.2 Index Register
The accumulator (A) shown in Figure 3-1 is a general-purpose 8-bit
register used to hold operands and results of arithmetic calculations or
data manipulations.
The index register (X) is an 8-bit register used by the indexed addressing
value to create an effective address. The index register also may be
used as a temporary storage area.
Advance Information
36
MC68HC05C8A — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
Central Processor Unit (CPU)
CPU Registers
3.3.3 Program Counter
3.3.4 Stack Pointer
The program counter (PC) is a 13-bit register that contains the address
of the next byte to be fetched.
The stack pointer (SP) contains the address of the next free location on
the stack. During an MCU reset or the reset stack pointer (RSP)
instruction, the stack pointer is set to location $00FF. The stack pointer
is then decremented as data is pushed onto the stack and incremented
as data is pulled from the stack.
When accessing memory, the seven most significant bits (MSB) are
permanently set to 0000011. These eight bits are appended to the six
least significant register bits (LSB) to produce an address within the
range of $00FF to $00C0. Subroutines and interrupts may use up to 64
(decimal) locations. If 64 locations are exceeded, the stack pointer
wraps around and loses the previously stored information. A subroutine
call occupies two locations on the stack; an interrupt uses five locations.
3.3.5 Condition Code Register
The condition code register (CCR) is a 5-bit register in which four bits are
used to indicate the results of the instruction just executed, and the fifth
bit indicates whether interrupts are masked. These bits can be tested
individually by a program, and specific actions can be taken as a result
of their state. Each bit is explained here.
H — Half Carry
This bit is set during ADD and ADC operations to indicate that a carry
occurred between bits 3 and 4.
I — Interrupt
When this bit is set, the timer and external interrupt are masked
(disabled). If an interrupt occurs while this bit is set, the interrupt is
latched and processed as soon as the interrupt bit is cleared.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Central Processor Unit (CPU)
37
Central Processor Unit (CPU)
N — Negative
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was negative.
Z — Zero
When set, this bit indicates that the result of the last arithmetic, logical,
or data manipulation was 0.
C — Carry/Borrow
When set, this bit indicates that a carry or borrow out of the arithmetic
logical unit (ALU) occurred during the last arithmetic operation. This
bit also is affected during bit test and branch instructions and during
shifts and rotates.
Advance Information
38
MC68HC05C8A — Rev. 4.0
Central Processor Unit (CPU)
MOTOROLA
Advance Information — MC68HC05C8A
Section 4. Interrupts
4.1 Contents
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .41
Software Interrupt (SWI). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41
External Interrupt (IRQ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
Serial Communications Interrupt (SCI). . . . . . . . . . . . . . . . . . .43
Serial Peripheral Interrupt (SPI) . . . . . . . . . . . . . . . . . . . . . . . .44
4.2 Introduction
The microcontroller unit (MCU) can be interrupted five different ways:
• Four maskable hardware interrupts, IRQ (interrupt request), SPI
(serial peripheral interface), SCI (serial communications
interface), and timer
• Non-maskable software interrupt instruction (SWI)
Port B interrupts, if enabled, are combined with the IRQ to form a single
interrupt source.
Interrupts cause the processor to save register contents on the stack
and to set the interrupt mask (I bit) to prevent additional interrupts. The
RTI (return to interrupt) instruction causes the register contents to be
recovered from the stack and normal processing to resume.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Interrupts
39
Interrupts
Unlike reset, hardware interrupts do not cause the current instruction
execution to be halted, but they are considered pending until the current
instruction is complete.
NOTE: The current instruction is the one already fetched and being operated on.
When the current instruction is complete, the processor checks all
pending hardware interrupts. If interrupts are not masked (CCR I bit
clear) and if the corresponding interrupt enable bit is set, the processor
proceeds with interrupt processing; otherwise, the next instruction is
fetched and executed.
If both an external interrupt and a timer interrupt are pending at the end
of an instruction execution, the external interrupt is serviced first. The
SWI is executed the same as any other instruction, regardless of the I-
bit state.
Vector addresses for all interrupts, including reset, are listed in
Table 4-1.
Table 4-1. Vector Addresses for Interrupts and Reset
Register Flag Name
Interrupts
Reset
CPU Interrupt Vector Address
N/A
N/A
N/A
N/A
RESET
SWI
$1FFE–$1FFF
$1FFC–$1FFD
$1FFA–$1FFB
$1FF8–$1FF9
$1FF8–$1FF9
$1FF8–$1FF9
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF6–$1FF7
$1FF4–$1FF5
$1FF4–$1FF5
Software
N/A
N/A
External interrupt
Timer input capture
Timer output compare
Timer overflow
Transmit buffer empty
Transmit complete
Receiver buffer full
Idle line detect
Overrun
IRQ
TSR
ICF
TIMER
TIMER
TIMER
SCI
TSR
OCF
TOF
TDRE
TC
TSR
SCSR
SCSR
SCSR
SCSR
SCSR
SPSR
SPSR
SCI
RDRF
IDLE
OR
SCI
SCI
SCI
SPIF
MODF
Transfer complete
Mode fault
SPI
SPI
Advance Information
40
MC68HC05C8A — Rev. 4.0
Interrupts
MOTOROLA
Interrupts
Hardware Controlled Interrupt Sequence
4.3 Hardware Controlled Interrupt Sequence
Three functions (RESET, STOP, and WAIT) are not in the strictest sense
interrupts; however, they are acted upon in a similar manner. Flowcharts
for hardware interrupts are shown in Figure 4-1.
1. RESET — A low input on the RESET input pin causes the program
to vector to its starting address, which is specified by the contents
of memory locations $1FFE and $1FFF. The I bit in the condition
code register is also set. Much of the MCU is configured to a
known state during this type of reset, as previously described in
Section 5. Resets.
2. STOP — The STOP instruction causes the oscillator to be turned
off and the processor to “sleep” until an external interrupt (IRQ) or
reset occurs.
3. WAIT — The WAIT instruction causes all processor clocks to stop,
but leaves the timer clock running. This “rest” state of the
processor can be cleared by reset, an external interrupt (IRQ),
serial peripheral interface, serial communications interface, or
timer interrupt. These individual interrupts have no special wait
vectors.
4.4 Software Interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a non-
maskable interrupt. It is executed regardless of the state of the I bit in the
CCR. If the I bit is 0 (interrupts enabled), SWI executes after interrupts
which were pending when the SWI was fetched but before interrupts
generated after the SWI was fetched. The interrupt service routine
address is specified by the contents of memory locations $1FFC and
$1FFD.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Interrupts
41
Interrupts
FROM
RESET
I BIT
IN CCR SET?
Y
N
IRQ
EXTERNAL
INTERRUPT
?
Y
CLEAR IRQ
REQUEST LATCH
N
Y
Y
Y
INTERNAL
TIMER
INTERRUPT
?
N
INTERNAL
SCI
INTERRUPT
?
N
INTERNAL
SPI
INTERRUPT
?
N
STACK
PC, X, A, CCR
FETCH NEXT
INSTRUCTION
SET I BIT IN
CC REGISTER
LOAD PC FROM:
SWI: $1FFC-$1FFD
IRQ: $1FFA-$1FFB
TIMER: $1FF8-$1FF9
SCI: $1FF6-$1FF7
SWI
INSTRUCTION
?
Y
N
RTI
INSTRUCTION
?
Y
N
RESTORE REGISTERS
FROM STACK:
EXECUTE
INSTRUCTION
CCR, A, X, PC
Figure 4-1. Interrupt Flowchart
Advance Information
42
MC68HC05C8A — Rev. 4.0
MOTOROLA
Interrupts
Interrupts
External Interrupt (IRQ)
4.5 External Interrupt (IRQ)
If the interrupt mask bit (I bit) of the CCR is set, all maskable interrupts
(internal and external) are disabled. Clearing the I bit enables interrupts.
The interrupt request is latched immediately following the falling edge of
IRQ. It is then synchronized internally and serviced as specified by the
contents of $1FFA and $1FFB.
When any of the port B pullups are enabled, that pin becomes an
additional external interrupt source which is coupled to the IRQ pin logic.
It follows the same edge/edge-level selection that the IRQ pin has. See
Figure 7-1 . Port B Pullup Option.
Either a level-sensitive and edge-sensitive trigger, or an edge-sensitive-
only trigger operation is selectable by mask option.
NOTE: The internal interrupt latch is cleared in the first part of the interrupt
service routine; therefore, one external interrupt pulse could be latched
and serviced as soon as the I bit is cleared.
4.6 Timer Interrupt
Three different timer interrupt flags cause a timer interrupt whenever
they are set and enabled. The interrupt flags are in the timer status
register (TSR), and the enable bits are in the timer control register
(TCR). Any of these interrupts will vector to the same interrupt service
routine, located at the address specified by the contents of memory
locations $1FF8 and $1FF9.
4.7 Serial Communications Interrupt (SCI)
Five different SCI interrupt flags cause an SCI interrupt whenever they
are set and enabled. The interrupt flags are in the SCI status register
(SCSR), and the enable bits are in the SCI control register 2 (SCCR2).
Any of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF6 and $1FF7.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Interrupts
43
Interrupts
4.8 Serial Peripheral Interrupt (SPI)
Two different SPI interrupt flags cause an SPI interrupt whenever they
are set and enabled. The interrupt flags are in the SPI status register
(SPSR), and the enable bits are in the SPI control register (SPCR).
Either of these interrupts will vector to the same interrupt service routine,
located at the address specified by the contents of memory locations
$1FF4 and $1FF5.
Advance Information
44
MC68HC05C8A — Rev. 4.0
Interrupts
MOTOROLA
Advance Information — MC68HC05C8A
Section 5. Resets
5.1 Contents
5.2
5.3
5.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
RESET Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
5.5
Computer Operating Properly (COP) Reset . . . . . . . . . . . . . . .46
Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .46
COP During Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . .47
5.5.1
5.5.2
5.5.3
5.5.4
5.2 Introduction
The microcontroller unit (MCU) can be reset three ways:
1. Initial power-on reset function
2. Active low input to the RESET pin
3. Computer operating properly (COP) reset
5.3 Power-On Reset (POR)
An internal reset is generated on power-up to allow the internal clock
generator to stabilize. The power-on reset is strictly for power turn-on
conditions and should not be used to detect a drop in the power supply
voltage. There is a 4064 internal processor clock cycle (tCYC) oscillator
stabilization delay after the oscillator becomes active. If the RESET pin
is low after the end of this 4064-cycle delay, the MCU will remain in the
reset condition until RESET goes high.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Resets
45
Resets
For additional information, refer to Figure 13-8. Power-On Reset
Timing Diagram.
5.4 RESET Pin
The MCU is reset when a logic 0 is applied to the RESET input for a
period of one and one-half machine cycles (tRL).
5.5 Computer Operating Properly (COP) Reset
This device includes a watchdog COP feature as a mask option. The
COP is implemented with an 18-bit ripple counter. This provides a
timeout period of 64 milliseconds at a bus rate of 2 MHz. If the COP
should time out, a system reset will occur and the device will be
re-initialized in the same fashion as a power-on reset (POR) or external
reset.
5.5.1 Resetting the COP
Preventing a COP reset is done by writing a logic 0 to the COPC bit. This
action will reset the counter and begin the timeout period again. The
COPC bit is bit 0 of address $1FF0. A read of address $1FF0 will result
in the user defined ROM data at that location.
5.5.2 COP During Wait Mode
The COP will continue to operate normally during wait mode. The
software should pull the device out of wait mode periodically and reset
the COP by writing to the COPC bit to prevent a COP reset.
5.5.3 COP During Stop Mode
Stop mode disables the oscillator circuit and thereby turns the clock off
for the entire device. The COP counter will be reset when stop mode is
entered. If a reset is used to exit stop mode, the COP counter will be
reset after the 4064 cycles of delay after stop mode. If an interrupt is
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46
MC68HC05C8A — Rev. 4.0
Resets
MOTOROLA
Resets
Computer Operating Properly (COP) Reset
used to exit stop mode, the COP counter will not be reset after the
4064-cycle delay and will have that many cycles already counted when
control is returned to the program.
5.5.4 COP During Self-Check Mode
The COP is disabled by hardware during self-check mode.
MC68HC05C8A — Rev. 4.0
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47
MOTOROLA
Resets
Resets
Advance Information
48
MC68HC05C8A — Rev. 4.0
Resets
MOTOROLA
Advance Information — MC68HC05C8A
Section 6. Low-Power Modes
6.1 Contents
6.2
6.3
6.4
6.5
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Stop Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51
6.2 Introduction
This section describes the two low-power modes — stop and wait.
Figure 6-1 shows the sequence of events caused by the STOP and
WAIT instructions.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Low-Power Modes
49
Low-Power Modes
STOP
WAIT
STOP OSCILLATOR
AND ALL CLOCKS
OSCILLATOR ACTIVE
TIMER CLOCK ACTIVE
PROCESSOR CLOCKS STOPPED
CLEAR I BIT
CLEAR I BIT
N
N
RESET
Y
RESET
EXTERNAL
INTERRUPT
EXTERNAL
INTERRUPT
(IRQ)
Y
N
(IRQ)
N
TIMER
INTERRUPT
Y
Y
Y
TURN ON OSCILLATOR
WAIT FOR TIME
DELAY TO STABILIZE
N
RESTART
PROCESSOR CLOCK
SCI
INTERRUPT
Y
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
1. FETCH RESET VECTOR
OR
2. SERVICE INTERRUPT
A. STACK
N
B. SET I BIT
C. VECTOR TO
INTERRUPT
B. SET I BIT
C. VECTOR TO
INTERRUPT
SPI
INTERRUPT
N
ROUTINE
ROUTINE
Figure 6-1. Stop/Wait Mode Flowchart
6.3 Stop Mode
The STOP instruction places the microcontroller unit (MCU) in its lowest-
power consumption mode. In stop mode, the internal oscillator is turned
off, halting all internal processing, including timer operation.
During stop mode, the TCR bits are altered to remove any pending timer
interrupt request and to disable any further timer interrupts. The timer
prescaler is cleared. The I bit in the condition code register is cleared to
enable external interrupts. All other registers and memory remain
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MC68HC05C8A — Rev. 4.0
Low-Power Modes
MOTOROLA
Low-Power Modes
Stop Recovery
unaltered. All input/output lines remain unchanged. The processor can
be brought out of stop mode only by an external interrupt or reset.
6.4 Stop Recovery
6.5 Wait Mode
The processor can be brought out of stop mode only by an external
interrupt or reset. See Figure 6-2.
The WAIT instruction places the MCU in a low-power consumption
mode, but the wait mode consumes more power than the stop mode. All
CPU action is suspended, but the timer, serial communications interface
(SCI), serial peripheral interface (SPI), and the oscillator remain active.
Any interrupt or reset will cause the MCU to exit wait mode.
During wait mode, the I bit in the CCR is cleared to enable interrupts. All
other registers, memory, and input/output lines remain in their previous
state. The timer may be enabled to allow a periodic exit from wait mode.
(1)
OSC1
t
RL
RESET
t
ILIH
(2)
IRQ
t
4064 t
ILCH
(3)
IRQ
cyc
INTERNAL CLOCK
INTERNAL ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFF
Notes:
RESET ($1FFE, $1FFF) OR
INTERRUPT ($1FFA, $1FFB)
VECTOR FETCH
1. Represents the internal gating of the OSC1 pin
2. IRQ pin edge-sensitive option
3. IRQ pin level and edge sensitive option
Figure 6-2. Stop Recovery Timing Diagram
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Low-Power Modes
Low-Power Modes
Advance Information
52
MC68HC05C8A — Rev. 4.0
Low-Power Modes
MOTOROLA
Advance Information — MC68HC05C8A
Section 7. Input/Output (I/O) Ports
7.1 Contents
7.2
7.3
7.4
7.5
7.6
7.7
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53
Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54
Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .55
7.2 Introduction
The MC68HC05C8A has three 8-bit input/output (I/O) ports.These 24
port pins are programmable as either inputs or outputs under software
control of the data direction registers. Port D does not have a data
direction register, and its seven pins are input only with the exception of
certain serial communications (SCI)/serial peripheral interface (SPI)
functions.
NOTE: To avoid a glitch on the output pins, write data to the I/O port data
register before writing a 1 to the corresponding data direction register.
MC68HC05C8A — Rev. 4.0
MOTOROLA
Advance Information
53
Input/Output (I/O) Ports
Input/Output (I/O) Ports
7.3 Port A
Port A is an 8-bit bidirectional port which does not share any of its pins
with other subsystems. The port A data register is at $0000 and the data
direction register (DDR) is at $0004. Reset does not affect the data
registers, but clears the data direction registers, thereby returning the
ports to inputs. Writing a 1 to a DDR bit sets the corresponding port bit
to output mode.
7.4 Port B
Port B is an 8-bit bidirectional port. The port B data register is at $0001
and the data direction register (DDR) is at $0005. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port pin to output mode. Each of the port B pins has a
mask programmable interrupt capability. This interrupt option also
enables a pullup device when the pin is configured as an input (see
Figure 7-1). The edge or edge and level sensitivity of the IRQ pin also
will pertain to the enabled port B pins via mask options. Be careful when
using port B pins that have the pullup enabled. Before switching from an
output to an input, the data should be preconditioned to a 1 to prevent
an interrupt from occurring.
VDD
V
DD
MASK OPTION
DDR BIT
SCHMITT
TRIGGER
IRQ
PB0
NORMAL PORT CIRCUITRY
AS SHOWN IN
FIGURE 7-2
TO INTERRUPT
LOGIC
FROM ALL OTHER PORT B PINS
Figure 7-1. Port B Pullup Option
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MC68HC05C8A — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
Input/Output (I/O) Ports
Port C
7.5 Port C
Port C is an 8-bit bidirectional port. The port C data register is at $0002
and the data direction register (DDR) is at $0006. Reset does not affect
the data registers, but clears the data direction registers, thereby
returning the ports to inputs. Writing a 1 to a DDR bit sets the
corresponding port bit to output mode. PC7 has a high current sink and
source capability.
7.6 Port D
Port D is a 7-bit fixed input port. Four of its pins are shared with the SPI
subsystem, two more are shared with the SCI subsystem. Reset does
not affect the data registers. During reset, all seven bits become valid
input ports because all special function output drivers associated with
the SCI, timer, and SPI subsystems are disabled.
7.7 Input/Output Programming
I/O port pins may be programmed as inputs or outputs under software
control. The direction of the pins is determined by the state of the
corresponding bit in the port data direction register (DDR). Each I/O port
has an associated DDR. Any I/O port pin is configured as an output if its
corresponding DDR bit is set to a logic 1. A pin is configured as an input
if its corresponding DDR bit is cleared to a logic 0.
At power-on or reset, all DDRs are cleared, which configures all I/O pins
as inputs. The data direction registers are capable of being written to or
read by the processor. During the programmed output state, a read of
the data register actually reads the value of the output data latch and not
the I/O pin. For further information, refer to Table 7-1 and Figure 7-2.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Input/Output (I/O) Ports
55
Input/Output (I/O) Ports
Table 7-1. I/O Pin Functions
(1)
DDR
I/O Pin Function
R/W
The I/O pin is in input mode. Data is written into the output
data latch.
0
0
0
1
1
1
0
1
Data is written into the output data latch and output to the I/O pin.
The state of the I/O pin is read.
The I/O pin is in an output mode. The output data latch is read.
1. R/W is an internal signal.
READ DDRx
WRITE DDRx
RESET
DATA DIRECTION
REGISTER x BIT
PORT x DATA
REGISTER BIT
(LATCHED OUTPUT)
WRITE PORTx
I/O
PIN
[1]
[3]
READ PORTx
[2]
[1] This output buffer enables the latched output to drive the pin when DDR bit is 1 (output mode).
[2] This input buffer is enabled when DDR bit is 0 (input mode).
[3] This input buffer is enabled when DDR bit is 1 (output mode).
Figure 7-2. I/O Circuitry
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56
MC68HC05C8A — Rev. 4.0
Input/Output (I/O) Ports
MOTOROLA
Advance Information — MC68HC05C8A
Section 8. Timer
8.1 Contents
8.2
8.3
8.4
8.5
8.6
8.7
8.8
8.9
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57
Counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59
Output Compare Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . .60
Input Capture Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61
Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63
Timer Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64
Timer During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
Timer During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65
8.2 Introduction
The timer consists of a 16-bit, software-programmable counter driven by
a fixed divide-by-four prescaler. This timer can be used for many
purposes, including input waveform measurements while
simultaneously generating an output waveform. Pulse widths can vary
from several microseconds to many seconds. Refer to Figure 8-1 for a
timer block diagram.
Because the timer has a 16-bit architecture, each specific functional
segment (capability) is represented by two registers. These registers
contain the high and low byte of that functional segment. Generally,
accessing the low byte of a specific timer function allows full control of
that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Timer
57
Timer
NOTE: The I bit in the condition code register should be set while manipulating
both the high and low byte register of a specific timer function to ensure
that an interrupt does not occur.
INTERNAL BUS
INTERNAL
PROCESSOR
HIGH
BYTE
LOW
BYTE
8-BIT
BUFFER
CLOCK
÷ 4
HIGH
LOW
BYTE BYTE
OUTPUT
COMPARE
REGISTER
$16
$17
HIGH
BYTE
LOW
BYTE
INPUT
CAPTURE
REGISTER
16-BIT FREE
RUNNING
COUNTER
$14
$15
$18
$19
COUNTER
ALTERNATE
REGISTER
$1A
$1B
EDGE
DETECT
CIRCUIT
OUTPUT
COMPARE
CIRCUIT
OVERFLOW
DETECT
CIRCUIT
D
Q
CLK
OUTPUT
LEVEL
$13
TIMER
STATUS
ICF OCF TOF
C
REGISTER
REGISTER
TIMER
CONTROL
RESET
ICIE OCIE
TOIE IEDG OLVL
REGISTER
$12
OUTPUT
LEVEL
EDGE
INPUT
(TCAP)
INTERRUPT
CIRCUIT
(TCMP)
Figure 8-1. Timer Block Diagram
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58
MC68HC05C8A — Rev. 4.0
Timer
MOTOROLA
Timer
Counter
8.3 Counter
The key element in the programmable timer is a 16-bit, free-running
counter or counter register, preceded by a prescaler that divides the
internal processor clock by four. The prescaler gives the timer a
resolution of 2.0 microseconds if the internal bus clock is 2.0 MHz. The
counter is incremented during the low portion of the internal bus clock.
Software can read the counter at any time without affecting its value.
The double-byte, free-running counter can be read from either of two
locations, $18, $19 (counter register) or $1A, $1B (counter alternate
register). A read from only the least significant byte (LSB) of the free-
running counter ($19, $1B) receives the count value at the time of the
read. If a read of the free-running counter or counter alternate register
first addresses the most significant byte (MSB) ($18, $1A), the LSB ($19,
$1B) is transferred to a buffer. This buffer value remains fixed after the
first MSB read, even if the user reads the MSB several times. This buffer
is accessed when reading the free-running counter or counter alternate
register LSB ($19 or $1B) and, thus, completes a read sequence of the
total counter value. In reading either the free-running counter or counter
alternate register, if the MSB is read, the LSB must also be read to
complete the sequence.
The counter alternate register differs from the counter register in one
respect: A read of the counter register MSB can clear the timer overflow
flag (TOF). Therefore, the counter alternate register can be read at any
time without the possibility of missing timer overflow interrupts due to
clearing of the TOF.
The free-running counter is configured to $FFFC during reset and is
always a read-only register. During a power-on reset, the counter is also
preset to $FFFC and begins running after the oscillator start-up delay.
Because the free-running counter is 16 bits preceded by a fixed divide-
by-four prescaler, the value in the free-running counter repeats every
262,144 internal bus clock cycles. When the counter rolls over from
$FFFF to $0000, the TOF bit is set. An interrupt can also be enabled
whenever counter rollover occurs by setting its interrupt enable bit
(TOIE).
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Timer
59
Timer
8.4 Output Compare Register
The 16-bit output compare register is made up of two 8-bit registers at
locations $16 (MSB) and $17 (LSB). The output compare register is
used for several purposes, such as indicating when a period of time has
elapsed. All bits are readable and writable and are not altered by the
timer hardware or reset. If the compare function is not needed, the two
bytes of the output compare register can be used as storage locations.
The output compare register contents are compared with the contents of
the free-running counter continually, and if a match is found, the
corresponding output compare flag (OCF) bit is set and the
corresponding output level (OLVL) bit is clocked to an output level
register. The output compare register values and the output level bit
should be changed after each successful comparison to establish a new
elapsed timeout. An interrupt also can accompany a successful output
compare, provided the corresponding interrupt enable bit (OCIE) is set.
After a processor write cycle to the output compare register containing
the MSB ($16), the output compare function is inhibited until the LSB
($17) is written also. The user must write both bytes (locations) if the
MSB is written first. A write made only to the LSB ($17) will not inhibit the
compare function. The free-running counter is updated every four
internal bus clock cycles. The minimum time required to update the
output compare register is a function of the program rather than the
internal hardware.
The processor can write to either byte of the output compare register
without affecting the other byte. The output level (OLVL) bit is clocked to
the output level register regardless of whether the output compare flag
(OCF) is set or clear. Figure 8-2 shows the logic of the output compare
function.
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MC68HC05C8A — Rev. 4.0
Timer
MOTOROLA
Timer
Input Capture Register
15
15
0
0
COUNTER HIGH BYTE
COUNTER LOW BYTE
PIN
CONTROL
16-BIT COMPARATOR
TCMP
LOGIC
8
7
OUTPUT COMPARE REGISTER HIGH OUTPUT COMPARE REGISTER LOW
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-2. Output Compare Operation
8.5 Input Capture Register
Two 8-bit registers, which make up the 16-bit input capture register, are
read-only and are used to latch the value of the free-running counter
after the corresponding input capture edge detector senses a defined
transition. The level transition which triggers the counter transfer is
defined by the corresponding input edge bit (IEDG). Reset does not
affect the contents of the input capture register except when exiting stop
mode.
The result obtained by an input capture will be one more than the value
of the free-running counter on the rising edge of the internal bus clock
preceding the external transition. This delay is required for internal
synchronization. Resolution is one count of the free-running counter,
which is four internal bus clock cycles.
The free-running counter contents are transferred to the input capture
register on each proper signal transition regardless of whether the input
capture flag (ICF) is set or clear. The input capture register always
contains the free-running counter value that corresponds to the most
recent input capture.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Timer
61
Timer
After a read of the input capture register ($14) MSB, the counter transfer
is inhibited until the LSB ($15) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with
the main program to determine the minimum pulse period.
A read of the input capture register LSB ($15) does not inhibit the free-
running counter transfer, since they occur on opposite edges of the
internal bus clock. Figure 8-3 shows the logic of the input capture
function.
$0018
$0019
15
15
8
7
0
0
TIMER REGISTER HIGH
TIMER REGISTER LOW
8
7
EDGE
SELECT/DETECT
LOGIC
LATCH
TCMP
INPUT CAPTURE REGISTER HIGH INPUT CAPTURE REGISTER LOW
$0014
$0015
TIMER
INTERRUPT
REQUEST
TIMER CONTROL REGISTER
$0012
TIMER STATUS REGISTER
$0013
Figure 8-3. Input Capture Operation
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62
MC68HC05C8A — Rev. 4.0
Timer
MOTOROLA
Timer
Timer Control Register
8.6 Timer Control Register
The timer control register (TCR) is a read/write register containing five
control bits. Three bits control interrupts associated with the timer status
register flags ICF, OCF, and TOF.
Address: $0012
Bit 7
ICIE
0
6
OCIE
0
5
TOIE
0
4
0
0
3
0
0
2
0
0
1
IEDG
U
Bit 0
OLVL
0
Read:
Write:
Reset:
U = Unaffected
Figure 8-4. Timer Control Register (TCR)
ICIE — Input Capture Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
OCIE — Output Compare Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
TOIE — Timer Overflow Interrupt Enable Bit
1 = Interrupt enabled
0 = Interrupt disabled
IEDG — Input Edge Bit
Value of input edge determines which level transition on TCAP pin will
trigger free-running counter transfer to the input capture register.
1 = Positive edge
0 = Negative edge
Reset does not affect the IEDG bit.
OLVL — Output Level Bit
Value of output level is clocked into output level register by the next
successful output compare and will appear on the TCMP pin.
1 = High output
0 = Low output
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Timer
63
Timer
Bits 2, 3, and 4 — Not used
Always read 0
8.7 Timer Status Register
The timer status register (TSR) is a read-only register containing three
status flag bits.
Address: $0013
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
ICF
U
OCF
TOF
0
0
0
0
0
U
U
0
0
0
0
0
= Unimplemented
U = Unaffected
Figure 8-5. Timer Status Register (TSR)
ICF — Input Capture Flag
1 = Flag set when selected polarity edge is sensed by input capture
edge detector
0 = Flag cleared when TSR and input capture low register ($15) are
accessed
OCF — Output Compare Flag
1 = Flag set when output compare register contents match the free-
running counter contents
0 = Flag cleared when TSR and output compare low register ($17)
are accessed
TOF — Timer Overflow Flag
1 = Flag set when free-running counter transition from $FFFF to
$0000 occurs
0 = Flag cleared when TSR and counter low register ($19) are
accessed
Bits 0–4 — Not used
Always read 0
Advance Information
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MC68HC05C8A — Rev. 4.0
Timer
MOTOROLA
Timer
Timer During Wait Mode
Accessing the timer status register satisfies the first condition required to
clear status bits. The remaining step is to access the register
corresponding to the status bit.
A problem can occur when using the timer overflow function and reading
the free-running counter at random times to measure an elapsed time.
Without incorporating the proper precautions into software, the timer
overflow flag could unintentionally be cleared if:
1. The timer status register is read or written when TOF is set.
2. The LSB of the free-running counter is read but not for the purpose
of servicing the flag.
The counter alternate register at addresses $1A and $1B contains the
same value as the free-running counter (at address $18 and $19);
therefore, this alternate register can be read at any time without affecting
the timer overflow flag in the timer status register.
8.8 Timer During Wait Mode
The central processor unit (CPU) clock halts during wait mode, the timer
remains active. If interrupts are enabled, a timer interrupt will cause the
processor to exit the wait mode.
8.9 Timer During Stop Mode
In stop mode, the timer stops counting and holds the last count value if
stop is exited by an interrupt. If reset is used, the counter is forced to
$FFFC. During stop, if at least one valid input capture edge occurs at the
TCAP pin, the input capture detect circuit is armed. This does not set any
timer flags or wake up the microcontroller unit (MCU). But if the MCU
exits stop due to an external interrupt, there is an active input capture
flag and data from the first valid edge that occurred during the stop
mode. If reset is used to exit stop mode, then no input capture flag or
data remains, even if a valid input capture edge occurred.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Timer
65
Timer
Advance Information
66
MC68HC05C8A — Rev. 4.0
Timer
MOTOROLA
Advance Information — MC68HC05C8A
Section 9. Serial Communications Interface (SCI)
9.1 Contents
9.2
9.3
9.4
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68
SCI Data Format. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
9.5
9.5.1
SCI Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
9.5.1.1
9.5.1.2
9.5.1.3
9.5.1.4
9.5.1.5
9.5.2
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69
Character Transmission. . . . . . . . . . . . . . . . . . . . . . . . . .69
Break Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70
Idle Characters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Transmitter Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . .72
Receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72
9.5.2.1
9.5.2.2
9.5.2.3
9.5.2.4
9.5.2.5
9.5.2.6
Character Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Character Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receiver Wakeup. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74
Receiver Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . .75
Framing Errors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
Receiver Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75
9.6
SCI Input/Output (I/O) Registers. . . . . . . . . . . . . . . . . . . . . . . .76
SCI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Control Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .76
SCI Control Register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . .78
SCI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80
Baud Rate Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
9.6.1
9.6.2
9.6.3
9.6.4
9.6.5
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Serial Communications Interface (SCI)
9.2 Introduction
The serial communications interface (SCI) module allows high-speed
asynchronous communication with peripheral devices and other
microcontroller units (MCU).
9.3 Features
Features of the SCI module include:
• Standard mark/space non-return-to-zero format
• Full duplex operation
• 32 programmable baud rates
• Programmable 8-bit or 9-bit character length
• Separately enabled transmitter and receiver
• Two receiver wakeup methods:
– Idle line wakeup
– Address mark wakeup
• Interrupt-driven operation capability with five interrupt flags:
– Transmitter data register empty
– Transmission complete
– Receiver data register full
– Receiver overrun
– Idle receiver input
• Receiver framing error detection
• 1/16 bit-time noise detection
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Serial Communications Interface (SCI)
Serial Communications Interface (SCI)
SCI Data Format
9.4 SCI Data Format
The SCI uses the standard non-return-to-zero mark/space data format
illustrated in Figure 9-1.
8-BIT DATA FORMAT
(BIT M IN SCCR1 CLEAR)
NEXT
START
BIT
START
STOP
BIT 0
BIT 0
BIT 1
BIT 1
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 6
BIT 7
BIT 7
BIT
BIT
9-BIT DATA FORMAT
(BIT M IN SCCR1 SET)
NEXT
START
BIT
START
BIT
STOP
BIT
BIT 2
BIT 3
BIT 4
BIT 5
BIT 8
Figure 9-1. SCI Data Format
9.5 SCI Operation
The SCI allows full-duplex, asynchronous, RS232 or RS422 serial
communication between the MCU and remote devices, including other
MCUs. The SCI’s transmitter and receiver operate independently,
although they use the same baud-rate generator. This subsection
describes the operation of the SCI transmitter and receiver.
9.5.1 Transmitter
Figure 9-2 shows the structure of the SCI transmitter.
9.5.1.1 Character Length
The transmitter can accommodate either 8-bit or 9-bit data. The state of
the M bit in SCI control register 1 (SCCR1) determines character length.
When transmitting 9-bit data, bit T8 in SCCR1 is the ninth bit (bit 8).
9.5.1.2 Character Transmission
During transmission, the transmit shift register shifts a character out to
the PD1/TDO pin. The SCI data register (SCDR) is the write-only buffer
between the internal data bus and the transmit shift register.
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Serial Communications Interface (SCI)
Writing a logic 1 to the TE bit in SCI control register 2 (SCCR2) and then
writing data to the SCDR begins the transmission. At the start of a
transmission, transmitter control logic automatically loads the transmit
shift register with a preamble of logic 1s. After the preamble shifts out,
the control logic transfers the SCDR data into the shift register. A logic 0
start bit automatically goes into the least significant bit position of the
shift register, and a logic 1 stop bit goes into the most significant bit
position.
When the data in the SCDR transfers to the transmit shift register, the
transmit data register empty (TDRE) flag in the SCI status register
(SCSR) becomes set. The TDRE flag indicates that the SCDR can
accept new data from the internal data bus.
When the shift register is not transmitting a character, the PD1/TDO pin
goes to the idle condition, logic 1. If software clears the TE bit during the
idle condition, and while TDRE is set, the transmitter relinquishes control
of the PD1/TDO pin.
9.5.1.3 Break Characters
Writing a logic 1 to the SBK bit in SCCR2 loads the shift register with a
break character. A break character contains all logic 0s and has no start
and stop bits. Break character length depends on the M bit in SCCR1.
As long as SBK is at logic 1, transmitter logic continuously loads break
characters into the shift register. After software clears the SBK bit, the
shift register finishes transmitting the last break character and then
transmits at least one logic 1. The automatic logic 1 at the end of a break
character is to guarantee the recognition of the start bit of the next
character.
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MOTOROLA
Serial Communications Interface (SCI)
SCI Operation
INTERNAL DATA BUS
SCDR ($0011)
TRANSMIT SHIFT REGISTER
1X
PIN BUFFER
AND CONTROL
PD1/
TDO
BAUD RATE
CLOCK
H
8 7 6 5 4 3 2 1 0 L
M
T8
SBK
TRANSMITTER
CONTROL LOGIC
TE
TDRE
TIE
TC
TCIE
SCI
INTERRUPT
REQUEST
SCI
RECEIVE
REQUESTS
BIT 7
0
6
0
4
3
0
2
1
BIT0
5
SCP1
0
BAUD RATE REGISTER (BAUD)
SCP0
M
SCR2 SCR1 SCR0 $000D
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
T8
WAKE
TE
0
0
0
$000E
SBK $000F
$0010
TCIE
TC
RIE
ILIE
RE
RWU
FE
RDRF IDLR
BIT 5 BIT 4
OR
NF
0
BIT 6
BIT 3
BIT 2
BIT 1
BIT 0 $0011
Figure 9-2. SCI Transmitter
MC68HC05C8A — Rev. 4.0
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9.5.1.4 Idle Characters
An idle character contains all logic 1s and has no start or stop bits. Idle
character length depends on the M bit in SCCR1. The preamble is a
synchronizing idle character that begins every transmission.
Clearing the TE bit during a transmission relinquishes the PD1/TDO pin
after the last character to be transmitted is shifted out. The last character
may already be in the shift register, or waiting in the SCDR, or in a break
character generated by writing to the SBK bit. Toggling TE from logic 0
to logic 1 while the last character is in transmission generates an idle
character (a preamble) that allows the receiver to maintain control of the
PD1/TDO pin.
9.5.1.5 Transmitter Interrupts
Two sources can generate SCI transmitter interrupt requests:
1. Transmit data register empty (TDRE) — The TDRE bit in the
SCSR indicates that the SCDR has transferred a character to the
transmit shift register. TDRE is a source of SCI interrupt requests.
The transmission complete interrupt enable bit (TCIE) in SCCR2
is the local mask for TDRE interrupts.
2. Transmission complete (TC) — The TC bit in the SCSR indicates
that both the transmit shift register and the SCDR are empty and
that no break or idle character has been generated. TC is a source
of SCI interrupt requests. The transmission complete interrupt
enable bit (TCIE) in SCCR2 is the local mask for TC interrupts.
9.5.2 Receiver
Figure 9-3 shows the structure of the SCI receiver.
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MOTOROLA
Serial Communications Interface (SCI)
SCI Operation
INTERNAL DATA BUS
SCDR ($0011)
RECEIVE SHIFT REGISTER
16X
BAUD RATE
CLOCK
÷³16
PD0/
RDI
PIN BUFFER
AND CONTROL
DATA
RECOVERY
8
7
6
5
4
3
2
1
0
NF
FE
R8
RE
M
RDRF
RIE
SCI
INTERRUPT
REQUEST
OR
RIE
SCI
TRANSMIT
REQUESTS
IDLE
ILIE
WAKEUP
LOGIC
RWU
BIT7
6
0
5
4
3
2
1
BIT0
BAUD RATE REGISTER (BAUD)
0
SCP1 SCP0
0
SCR2 SCR1 SCR0 $000D
SCI CONTROL REGISTER 1 (SCCR1) R8
SCI CONTROL REGISTER 2 (SCCR2) TIE
SCI STATUS REGISTER (SCSR) TDRE
SCI DATA REGISTER (SCDR) BIT 7
T8
0
M
WAKE
TE
0
0
0
$000E
SBK $000F
$0010
BIT 0 $0011
TCIE
TC
RIE
ILIE
RE
RWU
FE
RDRF
BIT 5
IDLR
BIT 4
OR
NF
0
BIT 6
BIT 3
BIT 2
BIT 1
Figure 9-3. SCI Receiver
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Serial Communications Interface (SCI)
9.5.2.1 Character Length
The receiver can accommodate either 8-bit or 9-bit data. The state of the
M bit in SCI control register 1 (SCCR1) determines character length.
When receiving 9-bit data, bit R8 in SCCR1 is the ninth bit (bit 8).
9.5.2.2 Character Reception
During reception, the receive shift register shifts characters in from the
PD0/RDI pin. The SCI data register (SCDR) is the read-only buffer
between the internal data bus and the receive shift register.
After a complete character shifts into the receive shift register, the data
portion of the character is transferred to the SCDR, setting the receive
data register full (RDRF) flag. The RDRF flag can be used to generate
an interrupt.
9.5.2.3 Receiver Wakeup
So that the MCU can ignore transmissions intended only for other
receivers in multiple-receiver systems, the receiver can be put into a
standby state. Setting the receiver wakeup enable (RWU) bit in SCI
control register 2 (SCCR2) puts the receiver into a standby state during
which receiver interrupts are disabled.
Either of two conditions on the PD0/RDI pin can bring the receiver out of
the standby state:
1. Idle input line condition — If the PD0/RDI pin is at logic 1 long
enough for 10 or 11 logic 1s to shift into the receive shift register,
receiver interrupts are again enabled.
2. Address mark — If a logic 1 occurs in the most significant bit
position of a received character, receiver interrupts are again
enabled.
The state of the WAKE bit in SCCR1 determines which of the two
conditions wakes up the MCU.
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SCI Operation
9.5.2.4 Receiver Noise Immunity
The data recovery logic samples each bit 16 times to identify and verify
the start bit and to detect noise. Any conflict between noise-detection
samples sets the noise flag (NF) in the SCSR. The NF bit is set at the
same time that the RDRF bit is set.
9.5.2.5 Framing Errors
If the data recovery logic does not detect a logic 1 where the stop bit
should be in an incoming character, it sets the framing error (FE) bit in
the SCSR. The FE bit is set at the same time that the RDRF bit is set.
9.5.2.6 Receiver Interrupts
Three sources can generate SCI receiver interrupt requests:
1. Receive data register full (RDRF) — The RDRF bit in the SCSR
indicates that the receive shift register has transferred a character
to the SCDR.
2. Receiver overrun (OR) — The OR bit in the SCSR indicates that
the receive shift register shifted in a new character before the
previous character was read from the SCDR.
3. Idle input (IDLE) — The IDLE bit in the SCSR indicates that 10 or
11 consecutive logic 1s shifted in from the PD0/RDI pin.
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9.6 SCI Input/Output (I/O) Registers
These I/O registers control and monitor SCI operation:
• SCI data register (SCDR)
• SCI control register 1 (SCCR1)
• SCI control register 2 (SCCR2)
• SCI status register (SCSR)
9.6.1 SCI Data Register
The SCI data register is the buffer for characters received and for
characters transmitted.
Address: $0011
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset:
SCD7
SDC5
SCD5
SCD4
SCD3
SCD2
SCD1
SCD0
Unaffected by reset
Figure 9-4. SCI Data Register (SCDR)
9.6.2 SCI Control Register 1
SCI control register 1 has these functions:
• Stores ninth SCI data bit received and ninth SCI data bit
transmitted
• Controls SCI character length
• Controls SCI wakeup method
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SCI Input/Output (I/O) Registers
Address: $000E
Bit 7
6
5
0
4
3
2
0
1
0
Bit 0
0
Read:
Write:
Reset:
R8
T8
M
WAKE
Unaffected by reset
= Unimplemented
Figure 9-5. SCI Control Register 1 (SCCR1)
R8 — Bit 8 (Received)
When the SCI is receiving 9-bit characters, R8 is the ninth bit of the
received character. R8 receives the ninth bit from the receive shift
register at the same time that the SCDR receives the other eight bits.
Reset has no effect on the R8 bit.
T8 — Bit 8 (Transmitted)
When the SCI is transmitting 9-bit characters, T8 is the ninth bit of the
transmitted character. T8 is loaded into the transmit shift register at
the same time that SCDR is loaded into the transmit shift register.
Reset has no effect on the T8 bit.
M — Character Length Bit
This read/write bit determines whether SCI characters are 8 bits long
or 9 bits long. The ninth bit can be used as an extra stop bit, as a
receiver wakeup signal, or as a mark or space parity bit. Reset has no
effect on the M bit.
1 = 9-bit SCI characters
0 = 8-bit SCI characters
WAKE — Wakeup Bit
This read/write bit determines which condition wakes up the SCI: a
logic 1 (address mark) in the most significant bit position of a received
character or an idle condition of the PD0/RDI pin. Reset has no effect
on the WAKE bit.
1 = Address mark wakeup
0 = Idle line wakeup
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9.6.3 SCI Control Register 2
SCI control register 2 has these functions:
• Enables the SCI receiver and SCI receiver interrupts
• Enables the SCI transmitter and SCI transmitter interrupts
• Enables SCI receiver idle interrupts
• Enables SCI transmission complete interrupts
• Enables SCI wakeup
Transmits SCI break characters
Address: $000F
Bit 7
TIE
0
6
TCIE
0
5
RIE
0
4
ILIE
0
3
TE
0
2
RE
0
1
RWU
0
Bit 0
SBK
0
Read:
Write:
Reset:
Figure 9-6. SCI Control Register 2 (SCCR2)
TIE — Transmit Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TDRE bit
becomes set. Reset clears the TIE bit.
1 = TDRE interrupt requests enabled
0 = TDRE interrupt requests disabled
TCIE — Transmission Complete Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the TC bit
becomes set. Reset clears the TCIE bit
1 = TC interrupt requests enabled
0 = TC interrupt requests disabled
RIE — Receive Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the RDRF bit
or the OR bit becomes set. Reset clears the RIE bit.
1 = RDRF interrupt requests enabled
0 = RDRF interrupt requests disabled
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SCI Input/Output (I/O) Registers
ILIE — Idle Line Interrupt Enable Bit
This read/write bit enables SCI interrupt requests when the IDLE bit
becomes set. Reset clears the ILIE bit.
1 = IDLE interrupt requests enabled
0 = IDLE interrupt requests disabled
TE — Transmit Enable Bit
Setting this read/write bit begins the transmission by sending a
preamble of 10 or 11 logic 1s from the transmit shift register to the
PD1/TDO pin. Reset clears the TE bit.
1 = Transmission enabled
0 = Transmission disabled
RE — Receive Enable Bit
Setting this read/write bit enables the receiver. Clearing the RE bit
disables the receiver and receiver interrupts but does not affect the
receiver interrupt flags. Reset clears the RE bit.
1 = Receiver enabled
0 = Receiver disabled
RWU — Receiver Wakeup Enable Bit
This read/write bit puts the receiver in a standby state. Typically, data
transmitted to the receiver clears the RWU bit and returns the receiver
to normal operation. The WAKE bit in SCCR1 determines whether an
idle input or an address mark brings the receiver out of the standby
state. Reset clears the RWU bit.
1 = Standby state
0 = Normal operation
SBK — Send Break Bit
Setting this read/write bit continuously transmits break codes in the
form of 10-bit or 11-bit groups of logic 0s. Clearing the SBK bit stops
the break codes and transmits a logic 1 as a start bit. Reset clears the
SBK bit.
1 = Break codes being transmitted
0 = No break codes being transmitted
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9.6.4 SCI Status Register
The SCI status register contains flags to signal these conditions:
• Transfer of SCDR data to transmit shift register complete
• Transmission complete
• Transfer of receive shift register data to SCDR complete
• Receiver input idle
• Receiver overrun
• Noisy data
• Framing error
Address: $0010
Bit 7
6
5
4
3
2
1
Bit 0
0
Read: TDRE
Write:
TC
RDRF
IDLE
OR
NF
FE
Reset:
0
0
0
0
0
0
0
0
= Unimplemented
Figure 9-7. SCI Status Register (SCSR)
TDRE — Transmit Data Register Empty Bit
This clearable, read-only bit is set when the data in the SCDR
transfers to the transmit shift register. TDRE generates an interrupt
request if the TIE bit in SCCR2 is also set. Clear the TDRE bit by
reading the SCSR with TDRE set, and then writing to the SCDR.
Reset sets the TDRE bit. Software must initialize the TDRE bit to logic
0 to avoid an instant interrupt request when turning on the transmitter.
1 = SCDR data transferred to transmit shift register
0 = SCDR data not transferred to transmit shift register
TC — Transmission Complete Bit
This clearable, read-only bit is set when the TDRE bit is set, and no
data, preamble, or break character is being transmitted. TC generates
an interrupt request if the TCIE bit in SCCR2 is also set. Clear the TC
bit by reading the SCSR with TC set, and then writing to the SCDR.
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Serial Communications Interface (SCI)
SCI Input/Output (I/O) Registers
Reset sets the TC bit. Software must initialize the TC bit to logic 0 to
avoid an instant interrupt request when turning on the transmitter.
1 = No transmission in progress
0 = Transmission in progress
RDRF — Receive Data Register Full Bit
This clearable, read-only bit is set when the data in the receive shift
register transfers to the SCI data register. RDRF generates an
interrupt request if the RIE bit in SCCR2 is also set. Clear the RDRF
bit by reading the SCSR with RDRF set, and then reading the SCDR.
Reset clears the RDRF bit.
1 = Received data available in SCDR
0 = Received data not available in SCDR
IDLE — Receiver Idle Bit
This clearable, read-only bit is set when 10 or 11 consecutive logic 1s
appear on the receiver input. IDLE generates an interrupt request if
the ILIE bit in SCCR2 is also set. Clear the IDLE bit by reading the
SCSR with IDLE set, and then reading the SCDR. Reset clears the
IDLE bit.
1 = Receiver input idle
0 = Receiver input not idle
OR — Receiver Overrun Bit
This clearable, read-only bit is set if the SCDR is not read before the
receive shift register receives the next word. OR generates an
interrupt request if the RIE bit in SCCR2 is also set. The data in the
shift register is lost, but the data already in the SCDR is not affected.
Clear the OR bit by reading the SCSR with OR set and then reading
the SCDR. Reset clears the OR bit.
1 = Receiver shift register full and RDRF = 1
0 = No receiver overrun
NF — Receiver Noise Flag
This clearable, read-only bit is set when noise is detected in data
received in the SCI data register. Clear the NF bit by reading the
SCSR and then reading the SCDR. Reset clears the NF bit.
1 = Noise detected in SCDR
0 = No noise detected in SCDR
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FE — Receiver Framing Error Flag
This clearable, read-only flag is set when there is a logic 0 where a
stop bit should be in the character shifted into the receive shift
register. If the received word causes both a framing error and an
overrun error, the OR bit is set and the FE bit is not set. Clear the FE
bit by reading the SCSR, and then reading the SCDR. Reset clears
the FE bit.
1 = Framing error
0 = No framing error
9.6.5 Baud Rate Register
The baud rate register (BAUD) selects the baud rate for both the receiver
and the transmitter.
Address: $000D
Bit 7
6
0
0
5
SCP1
0
4
SCP0
0
3
0
0
2
SCR2
U
1
SCR2
U
Bit 0
SCR0
U
Read:
Write:
Reset:
0
0
U = Unaffected
Figure 9-8. Baud Rate Register (BAUD)
SCP1 and SCP0 — SCI Prescaler Select Bits
These read/write bits control prescaling of the baud rate generator
clock, as shown in Table 9-1. Resets clear both SCP1 and SCP0.
Table 9-1. Baud Rate Generator Clock Prescaling
SCP0–SCP1
Baud Rate Generator Clock
Internal clock divided by 1
Internal clock divided by 3
Internal clock divided by 4
Internal clock divided by 13
00
01
10
11
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SCR2–SCR0 — SCI Baud Rate Select Bits
These read/write bits select the SCI baud rate, as shown in
Table 9-2. Reset has no effect on the SCR2–SCR0 bits.
Table 9-2. Baud Rate Selection
SCR2–SCR0
000
SCI Baud Rate (Baud)
Prescaled clock divided by 1
Prescaled clock divided by 2
Prescaled clock divided by 4
Prescaled clock divided by 8
Prescaled clock divided by 16
Prescaled clock divided by 32
Prescaled clock divided by 64
Prescaled clock divided by 128
001
010
011
100
101
110
111
Table 9-3 shows all possible SCI baud rates derived from crystal
frequencies of 2 MHz, 4 MHz, and 4.194304 MHz.
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Serial Communications Interface (SCI)
Table 9-3. Baud Rate Selection Examples
SCI Baud Rate
= 4 MHz f = 4.194304 MHz
OSC
SCR
[2:1:0]
SCP[1:0]
f
= 2 MHz
f
OSC
OSC
00
00
00
00
00
00
00
00
01
01
01
01
01
01
01
01
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
000
001
010
011
100
101
110
111
62.50 kBaud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
20.83 kBaud
10.42 kBaud
5208 Baud
2604 Baud
1302 Baud
651.0 Baud
325.5 Baud
162.8 Baud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
244.1 Baud
122.1 Baud
4808 Baud
2404 Baud
1202 Baud
601.0 Baud
300.5 Baud
150.2 Baud
75.12 Baud
37.56 Baud
125 kBaud
131.1 kBaud
65.54 kBaud
32.77 kBaud
16.38 kBaud
8192 Baud
4096 Baud
2048 Baud
1024 Baud
43.69 kBaud
21.85 kBaud
10.92 kBaud
5461 Baud
2731 Baud
1365 Baud
682.7 Baud
341.3 Baud
32.77 kBaud
16.38 kBaud
8192 Baud
4906 Baud
2048 Baud
1024 Baud
512.0 Baud
256.0 Baud
10.08 kBaud
5041 Baud
2521 Baud
1260 Baud
630.2 Baud
315.1 Baud
157.5 Baud
78.77 Baud
62.50 kBaud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
41.67 kBaud
20.83 kBaud
10.42 kBaud
5208 Baud
2604 Baud
1302 Baud
651.0 Baud
325.5 Baud
31.25 kBaud
15.63 kBaud
7813 Baud
3906 Baud
1953 Baud
976.6 Baud
488.3 Baud
244.1 Baud
9615 Baud
4808 Baud
2404 Baud
1202 Baud
601.0 Baud
300.5 Baud
150.2 Baud
75.12 Baud
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Serial Communications Interface (SCI)
MOTOROLA
Advance Information — MC68HC05C8A
Section 10. Serial Peripheral Interface (SPI)
10.1 Contents
10.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85
10.3 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.4 SPI Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86
10.4.1 Master In Slave Out (MISO). . . . . . . . . . . . . . . . . . . . . . . . .86
10.4.2 Master Out Slave In (MOSI). . . . . . . . . . . . . . . . . . . . . . . . .86
10.4.3 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87
10.4.4 Slave Select (SS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.5 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88
10.6 SPI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90
10.6.1 Serial Peripheral Control Register . . . . . . . . . . . . . . . . . . . .91
10.6.2 Serial Peripheral Status Register . . . . . . . . . . . . . . . . . . . . .92
10.6.3 Serial Peripheral Data I/O Register . . . . . . . . . . . . . . . . . . .94
10.2 Introduction
The serial peripheral interface (SPI) is an interface built into the
MC68HC05 microcontroller unit (MCU) which allows several
MC68HC05 MCUs or MC68HC05 MCU plus peripheral devices to be
interconnected within a single printed circuit board. In an SPI, separate
wires are required for data and clock. In the SPI format, the clock is not
included in the data stream and must be furnished as a separate signal.
An SPI system may be configured in a system containing one master
MCU and several slave MCUs or in a system in which an MCU is
capable of being a master or a slave.
MC68HC05C8A — Rev. 4.0
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Serial Peripheral Interface (SPI)
85
Serial Peripheral Interface (SPI)
10.3 Features
• Full duplex, 4-wire synchronous transfers
• Master or slave operation
• Bus frequency divided by 2 (maximum) master bit frequency
• Bus frequency (maximum) slave bit frequency
• Four programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Write collision flag protection
• Master-master mode fault protection capability
10.4 SPI Signal Description
The four basic signals (MOSI, MISO, SCK, and SS) are described in this
subsection. Each signal function is described for both the master and
slave mode.
10.4.1 Master In Slave Out (MISO)
The MISO line is configured as an input in a master device and as an
output in a slave device. It is one of the two lines that transfer serial data
in one direction, with the most significant bit sent first. The MISO line of
a slave device is placed in the high-impedance state if the slave is not
selected.
10.4.2 Master Out Slave In (MOSI)
The MOSI line is configured as an output in a master device and as an
input in a slave device. It is one of the two lines that transfer serial data
in one direction with the most significant bit sent first.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI Signal Description
10.4.3 Serial Clock (SCK)
The master clock is used to synchronize data movement both in and out
of the device through its MOSI and MISO lines. The master and slave
devices are capable of exchanging a byte of information during a
sequence of eight clock cycles. Since SCK is generated by the master
device, this line becomes an input on a slave device.
As shown in Figure 10-1, four possible timing relationships may be
chosen by using control bits CPOL and CPHA in the serial peripheral
control register (SPCR). Both master and slave devices must operate
with the same timing. The master device always places data on the
MOSI line one-half cycle before the clock edge (SCK), so the slave
device can latch the data.
Two bits (SPR0 and SPR1) in the SPCR of the master device select the
clock rate. In a slave device, SPR0 and SPR1 have no effect on the SPI
operation.
SS
SCK
SCK
SCK
SCK
MISO/MOSI
MSB
6
5
4
3
2
1
0
INTERNAL STROBE FOR DATA CAPTURE (ALL MODES)
Figure 10-1. Data Clock Timing Diagram
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
10.4.4 Slave Select (SS)
The slave select (SS) input line is used to select a slave device. It has to
be low prior to data transactions and must stay low for the duration of the
transaction.
The SS line on the master must be tied high. If it goes low, a mode fault
error flag (MODF) is set in the SPSR.
When CPHA = 0, the shift clock is the OR of SS with SCK. In this clock
phase mode, SS must go high between successive characters in an SPI
message. When CPHA = 1, SS may be left low for several SPI
characters. In cases where there is only one SPI slave MCU, its SS line
could be tied to VSS as long as CPHA = 1 clock modes are used.
10.5 Functional Description
Figure 10-2 shows a block diagram of the SPI circuitry. When a master
device transmits data to a slave via the MOSI line, the slave device
responds by sending data to the master device via the master’s MISO
line. This implies full duplex transmission with both data out and data in
synchronized with the same clock signal. Thus, the byte transmitted is
replaced by the byte received and eliminates the need for separate
transmit-empty and receive-full status bits. A single status bit (SPIF) is
used to signify that the input/output (I/O) operation has been completed.
The SPI data register (SPDR) is double buffered on read, but not on
write. If a write is performed during data transfer, the transfer occurs
uninterrupted, and the write will be unsuccessful. This condition will
cause the write collision (WCOL) status bit in the SPSR to be set. After
a data byte is shifted, the SPIF flag of the SPSR is set.
In the master mode, the SCK pin is an output. It idles high or low,
depending on the CPOL bit in the SPCR, until data is written to the shift
register, at which point eight clocks are generated to shift the eight bits
of data and then SCK goes idle again.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
Functional Description
S
MISO
PD2
M
INTERNAL
MCU CLOCK
MSB
LSB
M
MOSI
PD3
S
8-BIT SHIFT REG
READ DATA BUFF
DIVIDER
÷ 2
÷ 4 ÷ 16 ÷ 32
CLOCK
SPI CLOCK
(MASTER)
S
SELECT
CLOCK
SCK
LOGIC
PD4
M
SS
PD5
MSTR
SPE
SPI CONTROL
SPI STATUS REGISTER
SPI CONTROL REGISTER
INTERNAL
DATA BUS
SPI INTERRUPT
REQUEST
Figure 10-2. Serial Peripheral Interface Block Diagram
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Serial Peripheral Interface (SPI)
Serial Peripheral Interface (SPI)
In a slave mode, the slave select start logic receives a logic low at the
SS pin and a clock at the SCK pin. Thus, the slave is synchronized with
the master. Data from the master is received serially at the MOSI line
and loads the 8-bit shift register. After the 8-bit shift register is loaded, its
data is parallel transferred to the read buffer. During a write cycle, data
is written into the shift register, then the slave waits for a clock train from
the master to shift the data out on the slave’s MISO line.
Figure 10-3 illustrates the MOSI, MISO, SCK, and SS master-slave
interconnections.
PD3/MOSI
SPI SHIFT REGISTER
SPI SHIFT REGISTER
PD2/MISO
PD5
SS
I/O PORT
SPDR ($000C)
SLAVE MCU
SPDR ($000C)
PD4/SCK
MASTER MCU
Figure 10-3. Serial Peripheral Interface Master-Slave Interconnection
10.6 SPI Registers
This subsection describes the three registers in the SPI which provide
control, status, and data storage functions. These registers are:
• Serial peripheral control register (SPCR)
• Serial peripheral status register (SPSR)
• Serial peripheral data I/O register (SPDR)
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI Registers
10.6.1 Serial Peripheral Control Register
Address: $000A
Bit 7
SPIE
0
6
SPE
0
5
0
4
MSTR
0
3
CPOL
0
2
CPHA
0
1
SPR1
U
Bit 0
SPR0
U
Read:
Write:
Reset
= Unimplemented
U = Unaffected
Figure 10-4. SPI Control Register (SPCR)
SPIE — Serial Peripheral Interrupt Enable Bit
0 = SPIF interrupts disabled
1 = SPI interrupt is enabled
SPE — Serial Peripheral System Enable Bit
0 = SPI system off
1 = SPI system on
MSTR — Master Mode Select Bit
0 = Slave mode
1 = Master mode
CPOL — Clock Polarity Bit
When the clock polarity bit is cleared and data is not being
transferred, a steady state low value is produced at the SCK pin of the
master device. Conversely, if this bit is set, the SCK pin will idle high.
This bit also is used in conjunction with the clock phase control bit to
produce the desired clock-data relationship between master and
slave. See Figure 10-1.
CPHA — Clock Phase Bit
The clock phase bit, in conjunction with the CPOL bit, controls the
clock-data relationship between master and slave. The CPOL bit can
be thought of as simply inserting an inverter in series with the SCK
line. The CPHA bit selects one of two fundamentally different clocking
protocols. When CPHA = 0, the shift clock is the OR of SCK with SS.
MC68HC05C8A — Rev. 4.0
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Serial Peripheral Interface (SPI)
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Serial Peripheral Interface (SPI)
As soon as SS goes low, the transaction begins and the first edge on
SCK invokes the first data sample. When CPHA = 1, the SS pin may
be thought of as a simple output enable control. See Figure 10-1.
SPR1 and SPR0 — SPI Clock Rate Select Bits
These two bits select one of four baud rates to be used as SCK if the
device is a master; however, they have no effect in the slave mode.
See Table 10-1.
Table 10-1. Serial Peripheral Rate Selection
SPR1
SPR0
Bus Clock Divided By
0
0
1
1
0
1
0
1
2
4
16
32
10.6.2 Serial Peripheral Status Register
Address: $000B
Bit 7
SPIF
0
6
WCOL
0
5
0
4
3
0
2
0
1
0
Bit 0
0
Read:
Write:
Reset
MODF
0
0
0
0
U
U
= Unimplemented
U = Unaffected
Figure 10-5. SPI Status Register (SPSR)
SPIF — SPI Transfer Complete Flag
The serial peripheral data transfer flag bit is set upon completion of
data transfer between the processor and external device. If SPIF
goes high and if SPIE is set, a serial peripheral interrupt is generated.
Clearing the SPIF bit is accomplished by reading the SPSR (with
SPIF set) followed by an access of the SPDR. Unless SPSR is read
(with SPIF set) first, attempts to write to SPDR are inhibited.
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Serial Peripheral Interface (SPI)
MOTOROLA
Serial Peripheral Interface (SPI)
SPI Registers
WCOL — Write Collision Bit
The write collision bit is set when an attempt is made to write to the
serial peripheral data register while data transfer is taking place. If
CPHA is 0, a transfer is said to begin when SS goes low and the
transfer ends when SS goes high after eight clock cycles on SCK.
When CPHA is 1, a transfer is said to begin the first time SCK
becomes active while SS is low. The transfer ends when the SPIF flag
gets set. Clearing the WCOL bit is accomplished by reading the SPSR
(with WCOL set) followed by an access to SPDR.
Bit 5 — Not implemented
This bit always reads as 0.
MODF — Mode Fault Flag
The mode fault flag indicates that there may have been a multi-master
conflict for system control and allows a proper exit from system
operation to a reset or default system state. The MODF bit is normally
clear and is set only when the master device has its SS pin pulled low.
Setting the MODF bit affects the internal serial peripheral interface
system in these ways:
• An SPI interrupt is generated if SPIE = 1.
• The SPE bit is cleared. This disables the SPI.
• The MSTR bit is cleared, thus forcing the device into the slave
mode.
Clearing the MODF bit is accomplished by reading the SPSR (with
MODF set), followed by a write to the SPCR. Control bits SPE and
MSTR may be restored by user software to their original state after
the MODF bit has been cleared.
Bits 3–0 — Not Implemented
These bits always reads as 0.
MC68HC05C8A — Rev. 4.0
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Serial Peripheral Interface (SPI)
93
Serial Peripheral Interface (SPI)
10.6.3 Serial Peripheral Data I/O Register
Address: $000C
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Write:
Reset
SPD7
SPD6
SPD5
SPD4
SPD3
SPD2
SPD1
SPD0
Unaffected by reset
Figure 10-6. SPI Data Register (SPSR)
The serial peripheral data I/O register is used to transmit and receive
data on the serial bus. Only a write to this register will initiate
transmission/reception of another byte, and this will occur only in the
master device. At the completion of transmitting a byte of data, the SPIF
status bit is set in both the master and slave devices.
When the user reads the serial peripheral data I/O register, a buffer is
actually being read. The first SPIF must be cleared by the time a second
transfer of the data from the shift register to the read buffer is initiated or
an overrun condition will exist. In cases of overrun, the byte which
causes the overrun is lost.
A write to the serial peripheral data I/O register is not buffered and places
data directly into the shift register for transmission.
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MC68HC05C8A — Rev. 4.0
Serial Peripheral Interface (SPI)
MOTOROLA
Advance Information — MC68HC05C8A
Section 11. Operating Modes
11.1 Contents
11.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95
11.3 User Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96
11.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11.4.1 Self-Check Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .97
11.4.2 Self-Check Results. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98
11.2 Introduction
The microcontroller unit (MCU) has two modes of operation: user mode
and self-check mode. Table 11-1 shows the conditions required to enter
into each mode, where VTST = 2 x VDD.
Table 11-1. Operating Mode Conditions
RESET
IRQ
TCAP
Mode
User
V
to V
V
to V
DD
SS
DD
SS
V
V
DD
Self-Check
TST
MC68HC05C8A — Rev. 4.0
Advance Information
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MOTOROLA
Operating Modes
Operating Modes
11.3 User Mode
In user mode, the address and data buses are not available externally,
but there are three 8-bit input/output (I/O) ports and one 7-bit input-only
port. This mode allows the MCU to function as a self-contained
microcontroller, with maximum use of the pins for on-chip peripheral
functions. All address and data activity occurs within the MCU. User
mode is entered on the rising edge of RESET if the IRQ pin is within
normal operating range.
1
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
V
DD
RESET
IRQ
NC
2
OSC1
OSC2
TCAP
3
4
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
5
PD7
6
PD6/TCMP
PD5/SS
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
PD0/RDI
PC0
7
8
9
10
11
12
13
14
15
16
17
18
19
20
PC1
PC2
PC3
PC4
PC5
PC6
V
PC7
SS
Figure 11-1. User Mode Pinout
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MC68HC05C8A — Rev. 4.0
MOTOROLA
Operating Modes
Operating Modes
Self-Check Mode
11.4 Self-Check Mode
Self-check mode is entered upon the rising edge of RESET if the IRQ pin
is at VTST and the TCAP pin is at logic 1.
11.4.1 Self-Check Tests
The self-check read-only memory (ROM) at mask ROM location
$1F00–$1FEF determines if the MCU is functioning properly.These tests
are performed:
1. I/O — Functional test of ports A, B, and C
2. Random-access memory (RAM) — Counter test for each RAM
byte
3. Timer — Test of counter register and OCF bit
4. Serial communications interface (SCI) — Transmission test
checks for RDRF, TDRE, TC, and FE flags
5. Read-only memory (ROM) — Exclusive OR with odd ones parity
result
6. Serial peripheral interface (SPI) — Transmission test checks for
SPIF and WCOL flags
The self-check circuit is shown in Figure 11-2.
MC68HC05C8A — Rev. 4.0
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Operating Modes
97
Operating Modes
11.4.2 Self-Check Results
Table 11-2 shows the light-emitting diode (LED) codes that indicate self-
check test results.
Table 11-2. Self-Check Circuit LED Codes
PC3
Off
Off
Off
Off
Off
Off
PC2
On
On
On
Off
Off
Off
PC1
On
Off
Off
On
On
Off
PC0
Off
On
Off
On
Off
On
Remarks
I/O failure
RAM failure
Timer failure
SCI failure
ROM failure
SPI failure
Flashing
All others
No failure
Device failure
Perform these steps to activate the self-check tests:
1. Apply 10 V (2 x VDD) to the IRQ pin.
2. Apply a logic 1 to the TCAP pin.
3. Apply a logic 0 to the RESET pin.
The self-check tests begin on the rising edge of the RESET pin.
RESET must be held low for 4064 cycles after power-on reset (POR) or
for a time, tRL, for any other reset. For the tRL value, see 13.9 5.0-V
Control Timing.
Advance Information
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MC68HC05C8A — Rev. 4.0
Operating Modes
MOTOROLA
Operating Modes
Self-Check Mode
V
V
DD
DD
10 V
V
DD
MC34064
MC68H05C8A
RESET
4.7 kΩ
V
DD
1
2
3
4
5
40
39
38
37
36
IRQ
NC
OSC1
OSC2
TCAP
PD7
4 MHZ
PA7
PA6
V
DD
10 MΩ
20 pF
PA5
PA4
PA3
PA2
PA1
PA0
PB0
PB1
TCMP
6
35
34
33
32
31
30
29
10 kΩ
20 pF
PD5/SS
7
PD4/SCK
PD3/MOSI
PD2/MISO
PD1/TDO
8
9
1 MΩ
10
11
12
13
PD0/RDI
PC0
28
27
26
PB2
PB3
PC1
14
15
CMOS
BUFFER
PC2
(MC74HC125)
PB4
PB5
PB6
PB7
PC3
16
17
18
19
20
25
24
PC4
PC5
PC6
PC7
23
22
21
V
SS
V
DD
Notes:
1. VDD = 5.0 V
2. TCMP = NC
Figure 11-2. Self-Check Circuit Schematic
MC68HC05C8A — Rev. 4.0
Advance Information
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MOTOROLA
Operating Modes
Operating Modes
Advance Information
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MC68HC05C8A — Rev. 4.0
Operating Modes
MOTOROLA
Advance Information — MC68HC05C8A
Section 12. Instruction Set
12.1 Contents
12.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102
12.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.2 Immediate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103
12.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.6 Indexed, 8-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.7 Indexed, 16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .104
12.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105
12.4.1 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . .106
12.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .107
12.4.3 Jump/Branch Instructions. . . . . . . . . . . . . . . . . . . . . . . . . .108
12.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .110
12.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .110
12.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .111
12.6 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117
MC68HC05C8A — Rev. 4.0
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Instruction Set
101
Instruction Set
12.2 Introduction
The microcontroller unit (MCU) instruction set has 62 instructions and
uses eight addressing modes. The instructions include all those of the
M146805 CMOS (complementary metal oxide silicon) Family plus one
more: the unsigned multiply (MUL) instruction. The MUL instruction
allows unsigned multiplication of the contents of the accumulator (A) and
the index register (X). The high-order product is stored in the index
register, and the low-order product is stored in the accumulator.
12.3 Addressing Modes
The central processor unit (CPU) uses eight addressing modes for
flexibility in accessing data. The addressing modes provide eight
different ways for the CPU to find the data required to execute an
instruction. The eight addressing modes are:
• Inherent
• Immediate
• Direct
• Extended
• Indexed, no offset
• Indexed, 8-bit offset
• Indexed, 16-bit offset
• Relative
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Instruction Set
Instruction Set
Addressing Modes
12.3.1 Inherent
Inherent instructions are those that have no operand, such as return
from interrupt (RTI) and stop (STOP). Some of the inherent instructions
act on data in the CPU registers, such as set carry flag (SEC) and
increment accumulator (INCA). Inherent instructions require no operand
address and are one byte long.
12.3.2 Immediate
Immediate instructions are those that contain a value to be used in an
operation with the value in the accumulator or index register. Immediate
instructions require no operand address and are two bytes long. The
opcode is the first byte, and the immediate data value is the second byte.
12.3.3 Direct
Direct instructions can access any of the first 256 memory locations with
two bytes. The first byte is the opcode, and the second is the low byte of
the operand address. In direct addressing, the CPU automatically uses
$00 as the high byte of the operand address.
12.3.4 Extended
Extended instructions use three bytes and can access any address in
memory. The first byte is the opcode; the second and third bytes are the
high and low bytes of the operand address.
When using the Motorola assembler, the programmer does not need to
specify whether an instruction is direct or extended. The assembler
automatically selects the shortest form of the instruction.
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12.3.5 Indexed, No Offset
Indexed instructions with no offset are 1-byte instructions that can
access data with variable addresses within the first 256 memory
locations. The index register contains the low byte of the effective
address of the operand. The CPU automatically uses $00 as the high
byte, so these instructions can address locations $0000–$00FF.
Indexed, no offset instructions are often used to move a pointer through
a table or to hold the address of a frequently used random-access
memory (RAM) or input/output (I/O) location.
12.3.6 Indexed, 8-Bit Offset
Indexed, 8-bit offset instructions are 2-byte instructions that can access
data with variable addresses within the first 511 memory locations. The
CPU adds the unsigned byte in the index register to the unsigned byte
following the opcode. The sum is the effective address of the operand.
These instructions can access locations $0000–$01FE.
Indexed 8-bit offset instructions are useful for selecting the kth element
in an n-element table. The table can begin anywhere within the first 256
memory locations and could extend as far as location 510 ($01FE). The
k value is typically in the index register, and the address of the beginning
of the table is in the byte following the opcode.
12.3.7 Indexed, 16-Bit Offset
Indexed, 16-bit offset instructions are 3-byte instructions that can access
data with variable addresses at any location in memory. The CPU adds
the unsigned byte in the index register to the two unsigned bytes
following the opcode. The sum is the effective address of the operand.
The first byte after the opcode is the high byte of the 16-bit offset; the
second byte is the low byte of the offset.
Indexed, 16-bit offset instructions are useful for selecting the kth element
in an n-element table anywhere in memory.
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Instruction Set
Instruction Types
As with direct and extended addressing, the Motorola assembler
determines the shortest form of indexed addressing.
12.3.8 Relative
Relative addressing is only for branch instructions. If the branch
condition is true, the CPU finds the effective branch destination by
adding the signed byte following the opcode to the contents of the
program counter. If the branch condition is not true, the CPU goes to the
next instruction. The offset is a signed, two’s complement byte that gives
a branching range of –128 to +127 bytes from the address of the next
location after the branch instruction.
When using the Motorola assembler, the programmer does not need to
calculate the offset, because the assembler determines the proper offset
and verifies that it is within the span of the branch.
12.4 Instruction Types
The MCU instructions fall into the following five categories:
• Register/Memory instructions
• Read-Modify-Write instructions
• Jump/Branch instructions
• Bit Manipulation instructions
• Control instructions
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Instruction Set
Instruction Set
12.4.1 Register/Memory Instructions
These instructions operate on CPU registers and memory locations.
Most of them use two operands. One operand is in either the
accumulator or the index register. The CPU finds the other operand in
memory.
Table 12-1. Register/Memory Instructions
Instruction
Add Memory Byte and Carry Bit to Accumulator
Add Memory Byte to Accumulator
AND Memory Byte with Accumulator
Bit Test Accumulator
Mnemonic
ADC
ADD
AND
BIT
Compare Accumulator
CMP
CPX
EOR
LDA
Compare Index Register with Memory Byte
EXCLUSIVE OR Accumulator with Memory Byte
Load Accumulator with Memory Byte
Load Index Register with Memory Byte
Multiply
LDX
MUL
ORA
SBC
STA
OR Accumulator with Memory Byte
Subtract Memory Byte and Carry Bit from Accumulator
Store Accumulator in Memory
Store Index Register in Memory
STX
Subtract Memory Byte from Accumulator
SUB
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MOTOROLA
Instruction Set
Instruction Types
12.4.2 Read-Modify-Write Instructions
These instructions read a memory location or a register, modify its
contents, and write the modified value back to the memory location or to
the register.
NOTE: Do not use read-modify-write operations on write-only registers.
Table 12-2. Read-Modify-Write Instructions
Instruction
Arithmetic Shift Left (Same as LSL)
Arithmetic Shift Right
Bit Clear
Mnemonic
ASL
ASR
(1)
BCLR
(1)
Bit Set
BSET
Clear Register
CLR
COM
DEC
INC
Complement (One’s Complement)
Decrement
Increment
Logical Shift Left (Same as ASL)
Logical Shift Right
LSL
LSR
NEG
ROL
ROR
Negate (Two’s Complement)
Rotate Left through Carry Bit
Rotate Right through Carry Bit
Test for Negative or Zero
(2)
TST
1. Unlike other read-modify-write instructions, BCLR and
BSET use only direct addressing.
2. TST is an exception to the read-modify-write sequence
because it does not write a replacement value.
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Instruction Set
Instruction Set
12.4.3 Jump/Branch Instructions
Jump instructions allow the CPU to interrupt the normal sequence of the
program counter. The unconditional jump instruction (JMP) and the
jump-to-subroutine instruction (JSR) have no register operand. Branch
instructions allow the CPU to interrupt the normal sequence of the
program counter when a test condition is met. If the test condition is not
met, the branch is not performed.
The BRCLR and BRSET instructions cause a branch based on the state
of any readable bit in the first 256 memory locations. These 3-byte
instructions use a combination of direct addressing and relative
addressing. The direct address of the byte to be tested is in the byte
following the opcode. The third byte is the signed offset byte. The CPU
finds the effective branch destination by adding the third byte to the
program counter if the specified bit tests true. The bit to be tested and its
condition (set or clear) is part of the opcode. The span of branching is
from –128 to +127 from the address of the next location after the branch
instruction. The CPU also transfers the tested bit to the carry/borrow bit
of the condition code register.
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MOTOROLA
Instruction Set
Instruction Types
Table 12-3. Jump and Branch Instructions
Instruction
Branch if Carry Bit Clear
Branch if Carry Bit Set
Branch if Equal
Mnemonic
BCC
BCS
BEQ
BHCC
BHCS
BHI
Branch if Half-Carry Bit Clear
Branch if Half-Carry Bit Set
Branch if Higher
Branch if Higher or Same
Branch if IRQ Pin High
Branch if IRQ Pin Low
Branch if Lower
BHS
BIH
BIL
BLO
Branch if Lower or Same
Branch if Interrupt Mask Clear
Branch if Minus
BLS
BMC
BMI
Branch if Interrupt Mask Set
Branch if Not Equal
Branch if Plus
BMS
BNE
BPL
Branch Always
BRA
Branch if Bit Clear
BRCLR
BRN
BRSET
BSR
Branch Never
Branch if Bit Set
Branch to Subroutine
Unconditional Jump
Jump to Subroutine
JMP
JSR
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MOTOROLA
Instruction Set
Instruction Set
12.4.4 Bit Manipulation Instructions
The CPU can set or clear any writable bit in the first 256 bytes of
memory, which includes I/O registers and on-chip RAM locations. The
CPU can also test and branch based on the state of any bit in any of the
first 256 memory locations.
Table 12-4. Bit Manipulation Instructions
Instruction
Mnemonic
BCLR
Bit Clear
Branch if Bit Clear
Branch if Bit Set
Bit Set
BRCLR
BRSET
BSET
12.4.5 Control Instructions
These instructions act on CPU registers and control CPU operation
during program execution.
Table 12-5. Control Instructions
Instruction
Clear Carry Bit
Mnemonic
CLC
CLI
Clear Interrupt Mask
No Operation
NOP
RSP
RTI
Reset Stack Pointer
Return from Interrupt
Return from Subroutine
Set Carry Bit
RTS
SEC
SEI
Set Interrupt Mask
Stop Oscillator and Enable IRQ Pin
Software Interrupt
STOP
SWI
Transfer Accumulator to Index Register
Transfer Index Register to Accumulator
Stop CPU Clock and Enable Interrupts
TAX
TXA
WAIT
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MOTOROLA
Instruction Set
Instruction Set Summary
12.5 Instruction Set Summary
.
Table 12-6. Instruction Set Summary (Sheet 1 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
ADC #opr
IMM
DIR
EXT
IX2
IX1
IX
A9
ii
2
3
4
5
4
3
ADC opr
ADC opr
ADC opr,X
ADC opr,X
ADC ,X
B9 dd
C9 hh ll
D9 ee ff
E9
F9
Add with Carry
A ← (A) + (M) + (C)
✝ — ✝ ✝ ✝
ff
ADD #opr
ADD opr
ADD opr
ADD opr,X
ADD opr,X
ADD ,X
IMM
DIR
EXT
IX2
IX1
IX
AB
ii
2
3
4
5
4
3
BB dd
CB hh ll
DB ee ff
EB
FB
Add without Carry
A ← (A) + (M)
✝ — ✝ ✝ ✝
ff
AND #opr
AND opr
AND opr
AND opr,X
AND opr,X
AND ,X
IMM
DIR
EXT
IX2
IX1
IX
A4
ii
2
3
4
5
4
3
B4 dd
C4 hh ll
D4 ee ff
E4
F4
Logical AND
A ← (A) (M)
— — ✝ ✝ —
ff
ASL opr
ASLA
ASLX
ASL opr,X
ASL ,X
DIR
INH
38 dd
48
58
5
3
3
6
5
Arithmetic Shift Left
(Same as LSL)
— — ✝ ✝ ✝ INH
C
0
IX1
IX
68
78
ff
b7
b7
b0
b0
ASR opr
ASRA
ASRX
ASR opr,X
ASR ,X
DIR
INH
37 dd
47
57
5
3
3
6
5
C
Arithmetic Shift Right
— — ✝ ✝ ✝ INH
IX1
IX
67
77
ff
Branch if Carry Bit
Clear
BCC rel
PC ← (PC) + 2 + rel ? C = 0
— — — — —
REL
24
rr
3
DIR (b0) 11 dd
DIR (b1) 13 dd
DIR (b2) 15 dd
DIR (b3) 17 dd
DIR (b4) 19 dd
DIR (b5) 1B dd
DIR (b6) 1D dd
DIR (b7) 1F dd
5
5
5
5
5
5
5
5
BCLR n opr
Clear Bit n
Mn ← 0
— — — — —
Branch if Carry Bit Set
(Same as BLO)
BCS rel
BEQ rel
PC ← (PC) + 2 + rel ? C = 1
PC ← (PC) + 2 + rel ? Z = 1
— — — — —
— — — — —
REL
REL
25
27
rr
rr
3
3
Branch if Equal
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MOTOROLA
Instruction Set
Instruction Set
Table 12-6. Instruction Set Summary (Sheet 2 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
Branch if Half-Carry
Bit Clear
BHCC rel
PC ← (PC) + 2 + rel ? H = 0
— — — — —
REL
28
rr
3
Branch if Half-Carry
Bit Set
BHCS rel
BHI rel
PC ← (PC) + 2 + rel ? H = 1
PC ← (PC) + 2 + rel ? C Z = 0
PC ← (PC) + 2 + rel ? C = 0
— — — — —
— — — — —
— — — — —
REL
REL
REL
29
22
24
rr
rr
rr
3
3
3
Branch if Higher
Branch if Higher or
Same
BHS rel
BIH rel
BIL rel
Branch if IRQ Pin High
Branch if IRQ Pin Low
PC ← (PC) + 2 + rel ? IRQ = 1
PC ← (PC) + 2 + rel ? IRQ = 0
— — — — —
— — — — —
REL
REL
2F
2E
A5
B5 dd
C5 hh ll
D5 ee ff
rr
rr
ii
3
3
BIT #opr
BIT opr
BIT opr
BIT opr,X
BIT opr,X
BIT ,X
IMM
DIR
EXT
IX2
IX1
IX
2
3
4
5
4
3
Bit Test
Accumulator with
Memory Byte
(A) (M)
— — ✝ ✝ —
E5
F5
ff
p
Branch if Lower
(Same as BCS)
BLO rel
BLS rel
PC ← (PC) + 2 + rel ? C = 1
— — — — —
— — — — —
REL
REL
25
23
rr
rr
3
3
Branch if Lower or
Same
PC ← (PC) + 2 + rel ? C Z = 1
Branch if Interrupt
Mask Clear
BMC rel
BMI rel
BMS rel
PC ← (PC) + 2 + rel ? I = 0
PC ← (PC) + 2 + rel ? N = 1
PC ← (PC) + 2 + rel ? I = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
2C
2B
2D
rr
rr
rr
3
3
3
Branch if Minus
Branch if Interrupt
Mask Set
BNE rel
BPL rel
BRA rel
Branch if Not Equal
Branch if Plus
PC ← (PC) + 2 + rel ? Z = 0
PC ← (PC) + 2 + rel ? N = 0
PC ← (PC) + 2 + rel ? 1 = 1
— — — — —
— — — — —
— — — — —
REL
REL
REL
26
2A
20
rr
rr
rr
3
3
3
Branch Always
DIR (b0) 01 dd rr
DIR (b1) 03 dd rr
DIR (b2) 05 dd rr
DIR (b3) 07 dd rr
DIR (b4) 09 dd rr
DIR (b5) 0B dd rr
DIR (b6) 0D dd rr
DIR (b7) 0F dd rr
5
5
5
5
5
5
5
5
BRCLR n opr rel Branch if bit n clear
PC ← (PC) + 2 + rel ? Mn = 0
— — — — ✝
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MOTOROLA
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 3 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
DIR (b0) 00 dd rr
DIR (b1) 02 dd rr
DIR (b2) 04 dd rr
DIR (b3) 06 dd rr
DIR (b4) 08 dd rr
DIR (b5) 0A dd rr
DIR (b6) 0C dd rr
DIR (b7) 0E dd rr
5
5
5
5
5
5
5
5
BRSET n opr rel Branch if Bit n Set
PC ← (PC) + 2 + rel ? Mn = 1
PC ← (PC) + 2 + rel ? 1 = 0
Mn ← 1
— — — — ✝
BRN rel
Branch Never
Set Bit n
— — — — —
— — — — —
REL
21
rr
3
DIR (b0) 10 dd
DIR (b1) 12 dd
DIR (b2) 14 dd
DIR (b3) 16 dd
DIR (b4) 18 dd
DIR (b5) 1A dd
DIR (b6) 1C dd
DIR (b7) 1E dd
5
5
5
5
5
5
5
5
BSET n opr
PC ← (PC) + 2; push (PCL)
SP ← (SP) – 1; push (PCH)
SP ← (SP) – 1
Branch to
Subroutine
BSR rel
— — — — —
REL
AD rr
6
PC ← (PC) + rel
CLC
CLI
Clear Carry Bit
C ← 0
I ← 0
— — — — 0
— 0 — — —
INH
INH
98
9A
2
2
Clear Interrupt Mask
CLR opr
CLRA
CLRX
CLR opr,X
CLR ,X
M ← $00
A ← $00
X ← $00
M ← $00
M ← $00
DIR
INH
INH
IX1
IX
3F dd
4F
5F
5
3
3
6
5
Clear Byte
— — 0 1 —
— — ✝ ✝ ✝
— — ✝ ✝ 1
6F
7F
ff
CMP #opr
CMP opr
CMP opr
CMP opr,X
CMP opr,X
CMP ,X
IMM
DIR
EXT
IX2
IX1
IX
A1
ii
2
3
4
5
4
3
B1 dd
C1 hh ll
D1 ee ff
Compare
Accumulator with
Memory Byte
(A) – (M)
E1
F1
ff
COM opr
COMA
COMX
COM opr,X
COM ,X
M ← ( ) = $FF – (M)
DIR
INH
INH
IX1
IX
33 dd
43
53
5
3
3
6
5
M
A ← ( ) = $FF – (M)
A
Complement Byte
(One’s Complement)
X ← (X) = $FF – (M)
M ← ( ) = $FF – (M)
63
73
ff
M
M ← ( ) = $FF – (M)
M
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113
MOTOROLA
Instruction Set
Instruction Set
Table 12-6. Instruction Set Summary (Sheet 4 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
CPX #opr
CPX opr
CPX opr
CPX opr,X
CPX opr,X
CPX ,X
IMM
DIR
EXT
IX2
IX1
IX
A3
ii
2
3
4
5
4
3
B3 dd
C3 hh ll
D3 ee ff
E3
F3
Compare Index
Register with
Memory Byte
(X) – (M)
— — ✝ ✝ 1
ff
DEC opr
DECA
DECX
DEC opr,X
DEC ,X
M ← (M) – 1
A ← (A) – 1
X ← (X) – 1
M ← (M) – 1
M ← (M) – 1
DIR
INH
INH
IX1
IX
3A dd
4A
5A
5
3
3
6
5
Decrement Byte
— — ✝ ✝ —
6A
7A
ff
EOR #opr
EOR opr
EOR opr
EOR opr,X
EOR opr,X
EOR ,X
IMM
DIR
EXT
IX2
IX1
IX
A8
ii
2
3
4
5
4
3
B8 dd
C8 hh ll
D8 ee ff
E8
F8
EXCLUSIVE OR
Accumulator with
Memory Byte
A ← (A) (M)
— — ✝ ✝ —
ff
INC opr
INCA
INCX
INC opr,X
INC ,X
M ← (M) + 1
A ← (A) + 1
X ← (X) + 1
M ← (M) + 1
M ← (M) + 1
DIR
INH
INH
IX1
IX
3C dd
4C
5C
5
3
3
6
5
Increment Byte
— — ✝ ✝ —
— — — — —
— — — — —
6C
7C
ff
JMP opr
JMP opr
JMP opr,X
JMP opr,X
JMP ,X
DIR
EXT
IX2
IX1
IX
BC dd
CC hh ll
DC ee ff
2
3
4
3
2
Unconditional Jump
Jump to Subroutine
PC ← Jump Address
EC
FC
ff
JSR opr
JSR opr
JSR opr,X
JSR opr,X
JSR ,X
DIR
EXT
IX2
IX1
IX
BD dd
CD hh ll
DD ee ff
5
6
7
6
5
PC ← (PC) + n (n = 1, 2, or 3)
Push (PCL); SP ← (SP) – 1
Push (PCH); SP ← (SP) – 1
PC ← Conditional Address
ED
FD
ff
LDA #opr
LDA opr
LDA opr
LDA opr,X
LDA opr,X
LDA ,X
IMM
DIR
EXT
IX2
IX1
IX
A6
ii
2
3
4
5
4
3
B6 dd
C6 hh ll
D6 ee ff
E6
F6
Load Accumulator with
Memory Byte
A ← (M)
— — ✝ ✝ —
ff
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MOTOROLA
Instruction Set
Instruction Set Summary
Table 12-6. Instruction Set Summary (Sheet 5 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
LDX #opr
IMM
DIR
EXT
IX2
IX1
IX
AE
ii
2
3
4
5
4
3
LDX opr
LDX opr
LDX opr,X
LDX opr,X
LDX ,X
BE dd
CE hh ll
DE ee ff
EE
FE
Load Index Register
with Memory Byte
X ← (M)
— — ✝ ✝ —
ff
LSL opr
LSLA
LSLX
LSL opr,X
LSL ,X
DIR
INH
INH
IX1
IX
38 dd
48
58
5
3
3
6
5
Logical Shift Left
(Same as ASL)
C
0
— — ✝ ✝
b7
b0
68
78
ff
LSR opr
LSRA
LSRX
LSR opr,X
LSR ,X
DIR
INH
34 dd
44
54
5
3
3
6
5
0
C
Logical Shift Right
Unsigned Multiply
— — 0 ✝ ✝ INH
b7
b0
IX1
IX
64
74
ff
MUL
X : A ← (X) × (A)
0 — — — 0
INH
42
11
NEG opr
NEGA
NEGX
NEG opr,X
NEG ,X
M ← –(M) = $00 – (M)
A ← –(A) = $00 – (A)
X ← –(X) = $00 – (X)
M ← –(M) = $00 – (M)
M ← –(M) = $00 – (M)
DIR
INH
30
40
50
60
70
ii
5
3
3
6
5
Negate Byte
(Two’s Complement)
— — ✝ ✝ ✝ INH
IX1
IX
ff
NOP
No Operation
— — — — —
INH
9D
AA
BA dd
CA hh ll
DA ee ff
2
ORA #opr
ORA opr
ORA opr
ORA opr,X
ORA opr,X
ORA ,X
IMM
DIR
EXT
IX2
IX1
IX
ii
2
3
4
5
4
3
Logical OR
Accumulator with
Memory
A ← (A) (M)
— — ✝ ✝ —
EA
FA
ff
ROL opr
ROLA
ROLX
ROL opr,X
ROL ,X
DIR
INH
39 dd
49
59
5
3
3
6
5
Rotate Byte Left
through Carry Bit
C
— — ✝ ✝ ✝ INH
b7
b0
IX1
IX
69
79
ff
ROR opr
RORA
RORX
ROR opr,X
ROR ,X
DIR
INH
36 dd
46
56
5
3
3
6
5
Rotate Byte Right
through Carry Bit
C
— — ✝ ✝ ✝ INH
b7
b0
IX1
IX
66
76
ff
RSP
Reset Stack Pointer
SP ← $00FF
— — — — —
INH
9C
2
MC68HC05C8A — Rev. 4.0
Advance Information
115
MOTOROLA
Instruction Set
Instruction Set
Table 12-6. Instruction Set Summary (Sheet 6 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
SP ← (SP) + 1; Pull (CCR)
SP ← (SP) + 1; Pull (A)
SP ← (SP) + 1; Pull (X)
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTI
Return from Interrupt
✝ ✝ ✝ ✝ ✝ INH
80
A2
B2 dd
C2 hh ll
D2 ee ff
6
Return from
Subroutine
SP ← (SP) + 1; Pull (PCH)
SP ← (SP) + 1; Pull (PCL)
RTS
INH
SBC #opr
SBC opr
SBC opr
SBC opr,X
SBC opr,X
SBC ,X
IMM
DIR
ii
2
3
4
5
4
3
Subtract Memory Byte
and Carry Bit from
Accumulator
EXT
— — ✝ ✝ ✝
IX2
A ← (A) – (M) – (C)
IX1
IX
E2
F2
ff
SEC
SEI
Set Carry Bit
C ← 1
I ← 1
— — — — 1
— 1 — — —
INH
INH
99
9B
2
2
Set Interrupt Mask
STA opr
STA opr
STA opr,X
STA opr,X
STA ,X
DIR
EXT
IX2
IX1
IX
B7 dd
C7 hh ll
D7 ee ff
4
5
6
5
4
Store Accumulator in
Memory
M ← (A)
— — ✝ ✝ —
— 0 — — —
— — ✝ ✝ —
E7
F7
ff
Stop Oscillator and
Enable IRQ Pin
STOP
INH
8E
2
STX opr
STX opr
STX opr,X
STX opr,X
STX ,X
DIR
EXT
IX2
IX1
IX
BF dd
CF hh ll
DF ee ff
4
5
6
5
4
Store Index
Register In Memory
M ← (X)
EF
FF
ff
SUB #opr
SUB opr
SUB opr
SUB opr,X
SUB opr,X
SUB ,X
IMM
DIR
EXT
IX2
IX1
IX
A0
ii
2
3
4
5
4
3
B0 dd
C0 hh ll
D0 ee ff
E0
F0
Subtract Memory Byte
from
Accumulator
A ← (A) – (M)
— — ✝ ✝ ✝
ff
PC ← (PC) + 1; Push (PCL)
SP ← (SP) – 1; Push (PCH)
SP ← (SP) – 1; Push (X)
SP ← (SP) – 1; Push (A)
SP ← (SP) – 1; Push (CCR)
SP ← (SP) – 1; I ← 1
SWI
Software Interrupt
— 1 — — —
INH
83
10
PCH ← Interrupt Vector High Byte
PCL ← Interrupt Vector Low Byte
Advance Information
116
MC68HC05C8A — Rev. 4.0
Instruction Set
MOTOROLA
Instruction Set
Opcode Map
Table 12-6. Instruction Set Summary (Sheet 7 of 7)
Effect
Source
Form
on CCR
Operation
Description
H I N Z C
Transfer
TAX
Accumulator to Index
Register
X ← (A)
— — — — —
INH
97
2
TST opr
TSTA
TSTX
TST opr,X
TST ,X
DIR
INH
INH
IX1
IX
3D dd
4D
5D
4
3
3
5
4
Test Memory Byte for
Negative or Zero
(M) – $00
A ← (X)
— — — — —
— — — — —
6D
7D
ff
Transfer Index
Register to
Accumulator
TXA
INH
INH
9F
8F
2
2
Stop CPU Clock and
Enable
WAIT
—
✝ — — —
Interrupts
A
C
Accumulator
Carry/borrow flag
opr
PC
Operand (one or two bytes)
Program counter
CCR Condition code register
dd Direct address of operand
dd rr Direct address of operand and relative offset of branch instruction
DIR Direct addressing mode
ee ff High and low bytes of offset in indexed, 16-bit offset addressing
EXT Extended addressing mode
PCH Program counter high byte
PCL Program counter low byte
REL Relative addressing mode
rel
rr
SP
X
Relative program counter offset byte
Relative program counter offset byte
Stack pointer
ff
H
Offset byte in indexed, 8-bit offset addressing
Half-carry flag
Index register
Z
Zero flag
hh ll High and low bytes of operand address in extended addressing
#
Immediate value
Logical AND
I
Interrupt mask
ii
Immediate operand byte
Logical OR
IMM Immediate addressing mode
INH Inherent addressing mode
Logical EXCLUSIVE OR
Contents of
Negation (two’s complement)
Loaded with
( )
–( )
←
?
:
✝
—
IX
IX1
IX2
M
Indexed, no offset addressing mode
Indexed, 8-bit offset addressing mode
Indexed, 16-bit offset addressing mode
Memory location
If
Concatenated with
Set or cleared
Not affected
N
Negative flag
n
Any bit
12.6 Opcode Map
See Table 12-7.
MC68HC05C8A — Rev. 4.0
Advance Information
117
MOTOROLA
Instruction Set
Table 12-7. Opcode Map
Bit Manipulation Branch
Read-Modify-Write
Control
Register/Memory
DIR
DIR
REL
DIR
INH
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
MSB
LSB
MSB
LSB
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
5
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0
BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
SUB
SUB
SUB
SUB
SUB
CMP
SBC
CPX
AND
BIT
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3
DIR
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
5
2
2
2
2
2
REL
3
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
1
INH
6
2
2
2
2
2
2
2
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IX2
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IX
3
5
BRCLR0
BCLR0
BRN
RTS
INH
CMP
CMP
CMP
CMP
IX2
CMP
IX1
3
DIR
DIR
5
REL
3
IMM
2
DIR
3
EXT
4
IX
3
5
11
5
4
BRSET1
BSET1
BHI
MUL
SBC
SBC
SBC
SBC
SBC
CPX
AND
BIT
3
DIR
DIR
REL
1
1
1
INH
IMM
DIR
EXT
IX2
5
IX1
4
IX
3
5
5
3
5
3
3
6
5
10
2
3
4
BRCLR1
BCLR1
BLS
COM
COMA
COMX
COM
COM
LSR
SWI
CPX
CPX
CPX
CPX
3
DIR
DIR
5
REL
3
2
2
DIR
5
INH
3
1
1
INH
3
2
2
IX1
6
1
1
IX
5
1
INH
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
BRSET2
BSET2
BCC
LSR
LSRA
LSRX
LSR
AND
AND
AND
AND
3
DIR
DIR
REL
DIR
INH
INH
IX1
6
IX
IMM
DIR
3
EXT
IX2
IX1
4
IX
3
5
5
3
2
4
5
BRCLR2
BCLR2 BCS/BLO
BIT
IMM
2
BIT
BIT
EXT
4
BIT
LDA
STA
3
DIR
DIR
5
2
2
2
2
2
2
2
2
2
2
2
REL
3
DIR
3
IX2
5
IX1
4
IX
3
5
5
3
3
5
BRSET3
BSET3
BNE
ROR
RORA
RORX
ROR
ROR
ASR
LDA
LDA
LDA
LDA
STA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
3
DIR
DIR
REL
2
2
DIR
1
1
INH
1
1
INH
2
2
IX1
1
1
IX
5
IMM
DIR
EXT
IX2
6
IX1
5
IX
4
5
5
3
5
3
3
6
2
4
5
BRCLR3
BCLR3
BEQ
ASR
ASRA
ASRX
ASR
TAX
STA
STA
3
DIR
DIR
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
1
1
1
1
1
1
1
INH
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
5
2
BRSET4
BSET4
BHCC
ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL
CLC
EOR
EOR
EOR
EOR
EOR
3
DIR
DIR
REL
2
2
2
DIR
1
1
1
INH
1
1
1
INH
2
2
2
IX1
1
1
1
IX
5
INH
2
2
2
2
2
IMM
DIR
EXT
IX2
IX1
IX
3
5
5
3
5
3
3
6
2
3
4
5
4
BRCLR4
BCLR4
BHCS
ROL
ROLA
ROLX
ROL
ROL
DEC
SEC
ADC
ADC
ADC
ADC
ADC
3
DIR
DIR
REL
DIR
INH
INH
IX1
IX
5
INH
2
IMM
DIR
EXT
IX2
IX1
IX
3
5
5
3
5
3
3
6
2
3
4
5
4
BRSET5
BSET5
BPL
DEC
DECA
DECX
DEC
IX1
CLI
ORA
ORA
ORA
ORA
ORA
IX1
3
DIR
DIR
REL
DIR
INH
INH
IX
INH
2
IMM
DIR
EXT
IX2
IX
3
5
5
3
2
3
4
5
4
BRCLR5
BCLR5
BMI
SEI
ADD
ADD
ADD
ADD
ADD
JMP
JSR
LDX
STX
3
DIR
DIR
REL
INH
2
IMM
DIR
EXT
IX2
IX1
3
IX
2
5
5
3
5
3
3
6
5
2
3
4
BRSET6
BSET6
BMC
INC
INCA
INCX
INC
TST
INC
RSP
JMP
JMP
JMP
JSR
LDX
STX
3
DIR
DIR
REL
2
2
DIR
1
1
INH
1
1
INH
2
2
IX1
5
1
1
IX
4
INH
2
DIR
EXT
IX2
7
IX1
6
IX
5
5
5
3
4
3
3
6
5
6
BRCLR6
BCLR6
BMS
TST
DIR
TSTA
TSTX
TST
NOP
BSR
JSR
JSR
3
DIR
DIR
REL
INH
INH
IX1
IX
INH
2
2
REL
DIR
EXT
IX2
5
IX1
4
IX
3
5
5
3
2
2
3
4
BRSET7
BSET7
BIL
REL
STOP
LDX
LDX
LDX
3
DIR
DIR
1
1
INH
IMM
DIR
EXT
IX2
6
IX1
5
IX
4
5
5
3
5
3
3
6
5
2
2
4
5
BRCLR7
BCLR7
DIR
BIH
REL
CLR
CLRA
INH
CLRX
INH
CLR
CLR
WAIT
INH
TXA
INH
STX
DIR
STX
EXT
3
DIR
2
DIR
1
1
2
IX1
1
IX
1
IX2
IX1
IX
INH = Inherent
IMM = Immediate
DIR = Direct
REL = Relative
IX = Indexed, No Offset
IX1 = Indexed, 8-Bit Offset
IX2 = Indexed, 16-Bit Offset
MSB
0
MSB of Opcode in Hexadecimal
LSB
5 Number of Cycles
BRSET0 Opcode Mnemonic
DIR Number of Bytes/Addressing Mode
LSB of Opcode in Hexadecimal
0
EXT = Extended
3
Advance Information — MC68HC05C8A
Section 13. Electrical Specifications
13.1 Contents
13.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
13.3 Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .120
13.4 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .120
13.5 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
13.6 Power Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121
13.7 5.0-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .123
13.8 3.3-V DC Electrical Characteristics. . . . . . . . . . . . . . . . . . . . .124
13.9 5.0-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .126
13.10 3.3-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .127
13.11 5.0-V Serial Peripheral Interface Timing . . . . . . . . . . . . . . .130
13.12 3.3-V Serial Peripheral Interface Timing . . . . . . . . . . . . . . .131
13.2 Introduction
This section contains the electrical and timing specifications.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Electrical Specifications
119
Electrical Specifications
13.3 Maximum Ratings
Maximum ratings are the extreme limits to which the MCU can be
exposed without permanently damaging it.
The MCU contains circuitry to protect the inputs against damage from
high static voltages; however, do not apply voltages higher than those
shown in the table below. Keep VIn and VOut within the range
VSS ≤ (VIn or VOut) ≤ VDD. Connect unused inputs to the appropriate
voltage level, either VSS or VDD.
Rating
Symbol
Value
–0.3 to +7.0
25
Unit
V
V
Supply voltage
DD
Current drain per pin excluding V and V
I
mA
DD
SS
V
–0.3
SS
V
IRQ pin only
to
V
In
2 x V + 0.3
DD
T
Storage temperature range
–65 to +150
°C
stg
NOTE: This device is not guaranteed to operate properly at the maximum
ratings. Refer to 13.7 5.0-V DC Electrical Characteristics and
13.8 3.3-V DC Electrical Characteristics for guaranteed operating
conditions.
13.4 Operating Temperature Range
Characteristic
Symbol
Value
Unit
(1)
T to T
Operating temperature range
L
H
MC68HC05C8AP, FN, B, FB
0 to +70
T
A
°C
MC68HSC05C8CP, CFN, CB, CFB
MC68HC05C8AVP, VN, VB, VFB
MC68HC05C8AMP, MFN, MB, MFB
–40 to +85
–40 to +105
–40 to +125
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line-package (SDIP)
FB = Quad flat pack (QFP)
Advance Information
120
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
Thermal Characteristics
13.5 Thermal Characteristics
Characteristic
Thermal resistance
Symbol
Value
Unit
Plastic dual in-line package
Plastic leaded chip carrier (PLCC)
Quad flat pack (QFP0)
60
70
95
60
θ
°C/W
JA
Plastic shrink DIP (SDIP)
13.6 Power Considerations
The average chip-junction temperature, TJ, in °C, can be obtained from:
TJ = TA + (PD × θJA) (1)
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction to ambient, °C/W.
PD = PINT + PI/O
PINT = IDD × VDD watts (chip internal power)
PI/O = Power dissipation on input and output pins (user-determined)
For most applications PI/O « PINT and can be neglected.
Following is an approximate relationship between PD and TJ (neglecting
PI/O):
PD = K ÷ (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
K = PD × (TA + 273 °C) + θJA × (PD)2
(3)
where K is a constant pertaining to the particular part. K can be
determined from equation (3) by measuring PD (at equilibrium) for a
known TA. Using this value of K, the values of PD and TJ can be obtained
by solving equations (1) and (2) iteratively for any value of TA.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Electrical Specifications
121
Electrical Specifications
V
= 4.5 V
Pins
DD
VDD
R1
R2
C
PA7–PA0
3.26 Ω
2.38 Ω
50 pF
PB7–PB0
PC7–PC0
PD5–PD0, PD7
R2
TEST
POINT
SEE TABLE
C
SEE
TABLE
R1
SEE TABLE
V
= 3.0 V
Pins
DD
R1
R2
C
PA7–PA0
10.91 Ω
6.32 Ω
50 pF
PB7–PB0
PC7–PC0
PD5–PD0, PD7
Figure 13-1. Test Load
Advance Information
122
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
5.0-V DC Electrical Characteristics
13.7 5.0-V DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
I
= 10.0 µA
= –10.0 µA
V
—
—
—
0.1
—
V
Load
Load
OL
V
–0.1
V
DD
OH
Output high voltage
V
V
V
–0.8
–0.8
–0.8
(I
(I
(I
= –0.8 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –1.6 mA) PD4–PD1
= –5.0 mA) PC7
DD
DD
DD
Load
Load
Load
—
—
—
—
—
—
V
V
V
OH
Output low voltage
(I
= 1.6 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
= 10 mA) PC7
Load
V
—
—
—
—
0.4
0.4
OL
(I
Load
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
0.7×V
V
V
—
—
V
V
IH
DD
DD
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
0.2×V
DD
V
IL
SS
Supply current (4.5–5.5 Vdc @ f
= 2.1 MHz)
Bus
(3)
Run
—
—
3.50
1.00
5.25
3.25
mA
mA
(4)
Wait
I
(5)
DD
Stop
—
—
—
1
—
—
20
40
50
µA
µA
µA
25°C
0°C to 70°C (standard)
–40°C to +125°C (standard)
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
I
—
—
—
±10
µA
OZ
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5–PD0
I
—
±1
µA
µA
In
(6)
Input pullup current
PB7–PB0 (with pullup)
I
175
385
750
In
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
C
Out
—
—
—
—
12
8
pF
C
In
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40°C to +125°C, unless otherwise noted.
DD
SS
A
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all
DD
DD
other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; C = 20 pF on OSC2.
IL
IH
DD
L
4. Wait I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all other inputs
DD
DD
V
= 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected linearly
IL
IH DD L DD
by the OSC2 capacitance.
5. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V.
IH
DD
6. Input pullup current measured with V = 0.2 V.
IL
MC68HC05C8A — Rev. 4.0
Advance Information
123
MOTOROLA
Electrical Specifications
Electrical Specifications
13.8 3.3-V DC Electrical Characteristics
(1)
(2)
Symbol
Min
Max
Unit
Characteristic
Typ
Output voltage
I
I
= 10.0 µA
= –10.0 µA
V
—
—
—
0.1
—
V
Load
Load
OL
V
–0.1
V
DD
OH
Output high voltage
V
V
V
–0.3
–0.3
–0.3
(I
(I
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
= –0.4 mA) PD4–PD1
= –1.5 mA) PC7
DD
DD
DD
Load
Load
Load
—
—
—
—
—
—
V
V
V
OH
Output low voltage
(I
= 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
PD4–PD1, TCMP
= 6 mA) PC7
Load
V
—
—
—
—
0.3
0.3
OL
(I
Load
Input high voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
0.7×V
V
V
—
—
V
V
IH
DD
DD
Input low voltage
PA7–PA0, PB7–PB0, PC7–PC0, PD7,
PD5–PD0, TCAP, IRQ, RESET, OSC1
V
0.2×V
DD
V
IL
SS
Supply current (3.0–3.6 Vdc @ f
= 1.0 MHz)
Bus
(3)
Run
—
—
1.00
500
1.60
900
mA
µA
(4)
Wait
I
(5)
DD
Stop
—
—
—
1
—
—
8
16
20
µA
µA
µA
25°C
0°C to +70°C (standard)
–40°C to +125°C (standard)
I/O ports hi-z leakage current
PA7–PA0, PB7–PB0 (without pullup)
PC7–PC0, PD7, PD5–PD0
I
—
—
±10
µA
OZ
Input current
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
I
—
—
±1
µA
µA
In
(6)
Input pullup current
PB7–PB0 (with pullup)
I
75
175
350
In
Capacitance
Ports (as input or output)
RESET, IRQ, OSC1, TCAP, PD7, PD5, PD0
C
Out
—
—
—
—
12
8
pF
C
In
1. V = 3.3 Vdc ± 0.3 Vdc, V = 0 Vdc, T = –40°C to +125°C, unless otherwise noted.
DD
SS
A
2. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
3. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all
DD
DD
other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; CL = 20 pF on OSC2.
IL
IH
DD
4. Wait I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all other inputs
DD
DD
V
= 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected linearly
IL
IH DD L DD
by the OSC2 capacitance.
5. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V.
IH
DD
6. Input pullup current measured with V = 0.2 V.
IL
Advance Information
124
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-V DC Electrical Characteristics
5.00 mA
4.00 mA
3.00 mA
2.00 mA
1.00 mA
V
DD = 5.5 V
T = –40°C TO 125°C
I
T
I
A
W
50 µA
STOP IDD
(MHZ)
0.5 MHz
1.0 MHz
1.5 MHz
2.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-2. Maximum Supply Current versus
Internal Clock Frequency, VDD = 5.5 V
D
D
1.50 mA
VDD = 3.6 V
T = –40°C TO 125°C
1.00 mA
500 mA
STOP IDD
0.5 MHz
1.0 MHz
INTERNAL CLOCK FREQUENCY (XTAL ÷ 2)
Figure 13-3. Maximum Supply Current versus
Internal Clock Frequency, VDD = 3.6 V
MC68HC05C8A — Rev. 4.0
Advance Information
125
MOTOROLA
Electrical Specifications
Electrical Specifications
13.9 5.0-V Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal
External clock
f
—
dc
4.2
4.2
MHz
OSC
Internal operating frequency
Crystal
External clock
f
—
dc
2.1
2.1
MHz
OP
t
Internal clock cycle time
480
—
—
100
100
—
ns
ms
ms
CYC
t
Crystal oscillator startup time
OXOV
t
Stop recovery startup time (crystal oscillator)
—
ILCH
t
t
RESET pulse width
Timer
1.5
RL
CYC
(2)
t
t
4.0
125
RESL
—
—
—
Resolution
CYC
t
, t
ns
TH TL
Input capture pulse width
Input capture pulse period
(3)
t
t
Note
CYC
TLTL
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
125
—
—
—
ns
ILIH
(4)
t
t
Note
90
ILIL
CYC
t
t
OSC1 pulse width
ns
OH, OL
1. V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40°C to +125°C, unless otherwise noted.
DD
SS
A
2. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
CYC
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
CYc
Advance Information
126
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-V Control Timing
13.10 3.3-V Control Timing
(1)
Symbol
Min
Max
Unit
Characteristic
Oscillator frequency
Crystal
External clock
f
—
dc
2.0
2.0
MHz
OSC
Internal operating frequency
Crystal
External clock
f
—
dc
1.00
1.00
MHz
OP
t
Internal clock cycle time
1000
1.5
—
100
100
—
ns
ms
ms
CYC
t
Crystal oscillator startup time
OXOV
t
Stop recovery startup time (crystal oscillator)
ILCH
t
t
RESET pulse width
Timer
RL
CYC
(2)
t
t
4.0
250
RESL
—
—
—
Resolution
CYC
t
, t
ns
TH TL
Input capture pulse width
Input capture pulse period
(3)
t
t
Note
CYC
TLTL
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
250
—
—
—
ns
ILIH
(4)
t
t
Note
ILIL
CYC
t
t
OSC1 pulse width
200
ns
OH, OL
1. V = 3.3 Vdc ± 0.3 Vdc, V = 0 Vdc, T = –40°C to +125°C, unless otherwise noted.
DD
SS
A
2. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
3. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
CYC
4. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
CYC
tTH
tTL
tTLTL
TCAP PIN
Figure 13-4. TCAP Timing Relationships
MC68HC05C8A — Rev. 4.0
Advance Information
127
MOTOROLA
Electrical Specifications
Electrical Specifications
tILIL
tILIH
IRQ PIN
a. Edge-Sensitive Trigger Condition. The minimum pulse width (tILIH) is either 125 ns (fOP = 2.1 MHz)
or 250 ns (fOP = 1 MHz). The period tILIL should not be less than the number of tCYC cycles it takes to
execute the interrupt service routine plus 19 tCYC cycles.
t
IRQ1
ILIH
.
.
.
NORMALLY USED
WITH WIRED-OR
CONNECTION
IRQn
IRQ
(INTERNAL)
b. Level-Sensitive Trigger Condition. If after servicing an interrupt the IRQ remains low, the
next interrupt is recognized.
Figure 13-5. External Interrupt Timing
INTERNAL
(1)
CLOCK
INTERNAL
1FFE
1FFE
1FFE
1FFE
1FFF
NEW PC
ADDRESS BUS(1)
NEW
PCH
NEW
PCL
OP
CODE
INTERNAL
DATA BUS(1)
(2)
tRL
RESET
Notes:
1. Internal clock, internal address bus, and internal data bus are not available externally.
2. The next rising edge of the internal clock after the rising edge of RESET initiates the reset sequence.
Figure 13-6. External Reset Timing
Advance Information
128
MC68HC05C8A — Rev. 4.0
MOTOROLA
Electrical Specifications
Electrical Specifications
3.3-V Control Timing
OSC(1)
RESET
tRL
t
ILIH
(2)
IRQ
4064 tCYC
(3)
IRQ
INTERNAL
CLOCK
INTERNAL
ADDRESS BUS
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF(4)
Notes:
RESET OR INTERRUPT
VECTOR FETCH
1. Represents the internal clocking of the OSC1 pin
2. IRQ pin edge-sensitive mask option
3. IRQ pin level- and edge-sensitive mask option
4. RESET vector address shown for timing example
Figure 13-7. STOP Recovery Timing Diagram
(NOTE 1)
V
DD
(2)
OSC1 PIN
4064 tCYC
INTERNAL
(3)
CLOCK
INTERNAL
1FFE
1FFE
1FFE
1FFE
1FFE
1FFE
1FFF
ADDRESS BUS(3)
INTERNAL
NEW
PCH
NEW
PCL
DATA BUS(3)
NOTES:
1. Power-on reset threshold is typically between 1 V and 2 V.
2. OSC1 line is meant to represent time only, not frequency.
3. Internal clock, internal address bus, and internal data bus are not available externally.
Figure 13-8. Power-On Reset Timing Diagram
MC68HC05C8A — Rev. 4.0
MOTOROLA
Advance Information
129
Electrical Specifications
Electrical Specifications
13.11 5.0-V Serial Peripheral Interface Timing
(1)
Num
Symbol
Min
Max
Unit
Characteristic
Operating frequency
Master
Slave
f
f
dc
dc
0.5
2.1
OP(M)
OP
f
MHz
OP(S)
Cycle time
Master
Slave
t
t
1
2
3
4
5
6
7
2.0
480
—
—
CYC(M)
CYC
t
ns
CYC(S)
Enable lead time
Master
Slave
(2)
t
—
—
ns
Lead(M)
t
240
Lead(S)
Enable lag time
Master
Slave
tLag(M)
tLag(S)
(2)
—
—
ns
ns
ns
ns
ns
720
Clock (SCK) high time
Master
Slave
t
340
190
—
—
W(SCKH)M
t
W(SCKH)S
Clock (SCK) low time
Master
Slave
t
340
190
—
—
W(SCKL)M
t
W(SCKL)S
Data setup time (inputs)
Master
Slave
t
100
100
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
100
100
—
—
H(M)
t
H(S)
Slave access time (time-to-data active from high-
impedance state)
t
8
9
0
120
240
ns
ns
A
t
Slave disable time (hold time to high-impedance state)
—
DIS
Data valid
t
Master (before capture edge)
t
t
10
11
12
13
0.25
—
—
240
V(M)
CYC(M)
(3)
t
ns
Slave (after enable edge)
V(S)
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
t
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
Rise time (20% V to 70% V , C = 200 pF)
DD
DD
L
t
—
—
100
2.0
ns
µs
RM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
RS
Fall time (70% V
DD
to 20% V , C = 200 pF)
DD
L
t
—
—
100
2.0
ns
µs
FM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
FS
1. V = 5.0 Vdc ± 10%; V = 0 Vdc, T = T to T . Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
DD
SS
A
L
H
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
Advance Information
130
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-V Serial Peripheral Interface Timing
13.12 3.3-V Serial Peripheral Interface Timing
(1)
Num
Symbol
Min
Max
Unit
Characteristic
Operating frequency
Master
Slave
f
f
dc
dc
0.5
1.0
OP(M)
OP
f
MHz
OP(S)
Cycle time
Master
Slave
t
t
1
2
3
4
5
6
7
2.0
1.0
—
—
CYC(M)
CYC
t
µs
CYC(S)
Enable lead time
Master
Slave
(2)
t
—
—
ns
Lead(M)
t
500
Lead(S)
Enable lag time
Master
Slave
t
(2)
—
—
ns
µs
Lag(M)
1.5
t
Lag(S)
Clock (SCK) high time
Master
Slave
t
720
400
—
—
ns
ns
ns
ns
W(SCKH)M
t
W(SCKH)S
Clock (SCK) low time
Master
Slave
t
720
400
—
—
W(SCKL)M
t
W(SCKL)S
Data setup time (inputs)
Master
Slave
t
200
200
—
—
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
200
200
—
—
H(M)
t
H(S)
Slave access time (time to data active from high-impedance
state)
t
8
9
0
250
500
ns
ns
A
t
Slave disable time (hold time to high-impedance state)
—
DIS
Data valid
t
Master (before capture edge)
t
t
10
11
12
13
0.25
—
—
500
V(M)
CYC(M)
(3)
t
ns
Slave (after enable edge)
V(S)
Data hold time (outputs)
Master (after capture edge)
Slave (after enable edge)
t
0.25
0
—
—
HO(M)
CYC(M)
t
ns
HO(S)
Rise time (20% V to 70% V , C = 200 pF)
DD
DD
L
t
—
—
200
2.0
ns
µs
RM
SPI outputs (SCK, MOSI, and MISO)
SPI Inputs (SCK, MOSI, MISO, and SS)
t
RS
Fall time (70% V
to 20% V , C = 200 pF)
DD L
DD
t
—
—
200
2.0
ns
µs
FM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
FS
1. V = 3.3 Vdc ± 0.3 Vdc; V = 0 Vdc, T = T to T . Refer to Figure 13-9 and Figure 13-10 for timing diagrams.
DD
SS
A
L
H
2. Signal production depends on software.
3. Assumes 200 pF load on all SPI pins
MC68HC05C8A — Rev. 4.0
Advance Information
131
MOTOROLA
Electrical Specifications
Electrical Specifications
SS
(INPUT)
SS PIN OF MASTER HELD HIGH.
12
13
12
13
1
5
4
SCK (CPOL = 0)
(OUTPUT)
NOTE
NOTE
4
5
12
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10 (REF)
11
MASTER MSB OUT
10
11 (REF)
MOSI
(OUTPUT)
MASTER LSB OUT
12
13
Note: This first clock edge is generated internally, but is not seen at the SCK pin.
a) SPI Master Timing (CPHA = 0)
SS
(INPUT)
SS PIN OF MASTER HELD HIGH.
1
13
12
12
SCK (CPOL = 0)
(OUTPUT)
5
4
NOTE
NOTE
4
5
13
SCK (CPOL = 1)
(OUTPUT)
6
7
MISO
MSB IN
BITS 6–1
BITS 6–1
LSB IN
(INPUT)
10 (REF)
11
MASTER MSB OUT
10
11
MASTER LSB OUT
12
MOSI
(OUTPUT)
13
Note: This last clock edge is generated internally, but is not seen at the SCK pin.
b) SPI Master Timing (CPHA = 1)
Figure 13-9. SPI Master Timing Diagram
Advance Information
132
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Electrical Specifications
3.3-V Serial Peripheral Interface Timing
SS
(INPUT)
1
13
12
3
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
SCK (CPOL = 1)
(INPUT)
8
12
11
13
SLAVE LSB OUT
11
9
MISO
(INPUT)
SLAVE MSB OUT
BITS 6–1
BITS 6–1
NOTE
10
6
7
MOSI
(OUTPUT)
MSB IN
LSB IN
Note: Not defined but normally MSB of character just received.
a) SPI Slave Timing (CPHA = 0)
SS
(INPUT)
13
12
13
1
SCK (CPOL = 0)
(INPUT)
5
4
4
5
2
3
SCK (CPOL = 1)
(INPUT)
10
SLAVE MSB OUT
12
10
9
8
MISO
(OUTPUT)
NOTE
BITS 6–1
BITS 6–1
SLAVE LSB OUT
6
7
11
MOSI
(INPUT)
MSB IN
LSB IN
Note: Not defined but normally LSB of character previously transmitted.
b) SPI Slave Timing (CPHA = 1)
Figure 13-10. SPI Slave Timing Diagram
MC68HC05C8A — Rev. 4.0
Advance Information
133
MOTOROLA
Electrical Specifications
Electrical Specifications
Advance Information
134
MC68HC05C8A — Rev. 4.0
Electrical Specifications
MOTOROLA
Advance Information — MC68HC05C8A
Section 14. Mechanical Specifications
14.1 Contents
14.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135
14.3 40-Pin Plastic Dual In-Line (DIP) Package
(Case 711-03) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package
(Case 858-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .136
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC)
(Case 777-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .137
14.6 44-Lead Quad Flat Pack (QFP)
(Case 824A-01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138
14.2 Introduction
This section describes the dimensions of the dual in-line package (DIP),
plastic shrink dual in-line package (SDIP), plastic leaded chip carrier
(PLCC), and quad flat pack (QFP) MCU packages. Package dimensions
available at time of this publication are provided in this section. To make
sure that you have the latest case outline specifications, contact one of
the following:
• Local Motorola Sales Office
• Worldwide Web (wwweb) at
http://www.motorola.com/semiconductors/
Follow Worldwide Web on-line instructions to retrieve the current
mechanical specifications.
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Mechanical Specifications
135
Mechanical Specifications
14.3 40-Pin Plastic Dual In-Line (DIP) Package (Case 711-03)
NOTES:
1.POSITION TOLERANCE OF LEADS (D), SHALL
BEWITHIN 0.25 (0.010) AT MAXIMUM MATERIAL
CONDITIONS, IN RELATION TO SEATING PLANE
AND EACH OTHER.
2.DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
40
21
20
B
3.DIMENSION B DOES NOT INCLUDE MOLD FLASH.
1
MILLIMETERS
INCHES
DIM MIN
MAX
MIN
MAX
A
B
C
D
F
51.69
13.72
3.94
0.36
1.02
52.45
14.22
5.08
0.56
1.52
2.035
0.540
0.155
0.014
0.040
2.065
0.560
0.200
0.022
0.060
L
A
C
N
2.54 BSC
0.100 BSC
G
H
J
K
L
J
1.65
0.20
2.92
2.16
0.38
3.43
0.065
0.008
0.115
0.085
0.015
0.135
K
M
H
G
F
D
SEATING
PLANE
15.24 BSC
0.600 BSC
0°
1°
0°
1°
M
N
0.51
1.02
0.020
0.040
14.4 42-Pin Plastic Shrink Dual In-Line (SDIP) Package (Case 858-01)
-A-
NOTES:
1. DIMENSIONS AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
42
1
22
21
-B-
4. DIMENSIONS A AND B DO NOT INCLUDE MOLD
FLASH. MAXIMUM MOLD FLASH 0.25 (0.010).
INCHES
MIN MAX
MILLIMETERS
MIN MAX
L
DIM
A
B
C
D
F
1.435 1.465 36.45 37.21
0.540 0.560 13.72 14.22
H
C
0.155 0.200
0.014 0.022
0.032 0.046
0.070 BSC
3.94
0.36
0.81
5.08
0.56
1.17
G
H
J
1.778 BSC
7.62 BSC
0.300 BSC
-T-
SEATING
PLANE
0.008 0.015
0.115 0.135
0.600 BSC
0.20
2.92
0.38
3.43
K
L
N
G
15.24 BSC
M
F
M
N
0° 15°
0.020 0.040
0°
0.51
15°
1.02
K
J 42 PL
0.25 (0.010)
D 42 PL
M
S
B
M
S
A
T
0.25 (0.010)
T
Advance Information
136
MC68HC05C8A — Rev. 4.0
Mechanical Specifications
MOTOROLA
Mechanical Specifications
44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
14.5 44-Lead Plastic Leaded Chip Carrier (PLCC) (Case 777-02)
M
S
S
N
0.007(0.180)
T
L-M
B
D
-N-
YBRK
-M-
M
S
S
0.007(0.180)
T
L-M
N
U
Z
-L-
V
X
G1
W
D
44
1
S
S
S
N
0.010 (0.25)
T
L-M
VIEW D-D
M
M
S
S
S
S
A
R
0.007(0.180)
0.007(0.180)
T
T
L-M
L-M
N
N
M
S
S
N
0.007(0.180)
T
L-M
H
Z
J
K1
E
0.004 (0.10)
G
K
C
SEATING
PLANE
-T-
G1
F
VIEW S
S
S
N
S
M
S
S
0.010 (0.25)
T
L-M
0.007(0.180)
T
L-M
N
VIEW S
NOTES:
INCHES
MILLIMETERS
1.DATUMS -L-, -M-, AND -N- ARE DETERMINED
WHERE TOP OF LEAD SHOLDERS EXITS
PLASTIC BODY AT MOLD PARTING LINE.
2.DIMENSION G1, TRUE POSITION TO BE
MEASURED AT DATUM -T-, SEATING PLANE.
3.DIMENSION R AND U DO NOT INCLUDE MOLD
FLASH. ALLOWABLE MOLD FLASH IS 0.010
(0.25) PER SIDE.
4.DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
5.CONTROLLING DIMENSION: INCH.
6.THE PACKAGE TOP MAY BE SMALLER THAN
THE PACKAGE BOTTOM BY UP TO 0.012
(0.300). DIMENSIONS R AND U ARE DETER-
DIM MIN
MAX
0.695
0.695
0.180
0.110
0.019
MIN
17.40
17.40
4.20
MAX
17.65
17.65
4.57
A
B
C
E
F
G
H
J
K
R
U
V
W
X
Y
Z
0.685
0.685
0.165
0.090
0.013
2.29
2.79
0.33
0.48
0.050 BSC
1.27 BSC
0.026
0.020
0.025
0.650
0.650
0.042
0.042
0.042
0.032
0.66
0.51
0.81
0.64
0.656
0.656
0.048
0.048
0.056
0.020
10°
16.51
16.51
1.07
1.07
1.07
16.66
16.66
1.21
1.21
1.42
0.50
10°
MINED
AT THE OUTERMOST EXTREMES OF THE
PLASTIC BODY EXCLUSIVE OF THE MOLD
FLASH, TIE BAR BURRS, GATE BURRS AND
INTERLEAD FLASH, BUT INCLUDING ANY
MISMATCH BETWEEN THE TOP AND BOTTOM
OF THE PLASTIC BODY.
7.DIMINSION H DOES NOT INCLUDE DAMBAR
PROTRUSION OR INTRUSION. THE DAMBAR
PROTUSION(S) SHALL NOT CAUSE THE H
DIMINSION TO BE GREATER THAN 0.037
(0.940138). THE DAMBAR INTRUSION(S) SHALL
NOT CAUSE THE H DIMINISION TO SMALLER
THAN 0.025 (0.635).
2°
2°
15.50
1.02
G1
K1
0.610
0.040
0.630
16.00
MC68HC05C8A — Rev. 4.0
Advance Information
137
MOTOROLA
Mechanical Specifications
Mechanical Specifications
14.6 44-Lead Quad Flat Pack (QFP) (Case 824A-01)
L
33
23
34
22
B
B
-A,B,D-
-A-
-B-
L
B
V
DETAIL A
DETAIL A
44
12
1
11
F
-D-
A
BASE METAL
M
S
S
S
0.20 (0.008)
A-B
A-B
D
C
0.05 (0.002) A-B
S
J
N
M
S
0.20 (0.008)
D
H
D
M
S
S
D
0.20 (0.008)
C
A-B
M
DETAIL C
SECTION B–B
E
C
DATUM
PLANE
-H-
-C-
SEATING
PLANE
0.01 (0.004)
H
G
M
MILLIMETERS
MIN MAX
INCHES
MIN MAX
NOTES:
DIM
A
B
C
D
E
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
9.90 10.10
9.90 10.10
0.390 0.398
0.390 0.398
0.083 0.096
0.012 0.018
0.079 0.083
0.012 0.016
0.031 BSC
M
2. CONTROLLING DIMENSION: MILLIMETER.
3. DATUM PLANE ĆHĆ IS LOCATED AT BOTTOM OF
LEAD AND IS COINCIDENT WITH THE LEAD WHERE
THE LEAD EXITS THE PLASTIC BODY AT THE
BOTTOM OF THE PARTING LINE.
4. DATUMS ĆAĆ, ĆBĆ AND ĆDĆ TO BE DETERMINED AT
DATUM PLANE ĆHĆ.
5. DIMENSIONS S AND V TO BE DETERMINED AT
SEATING PLANE ĆCĆ.
6. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION. ALLOWABLE PROTRUSION IS 0.25
(0.010) PER SIDE. DIMENSIONS A AND B DO
INCLUDE MOLD MISMATCHAND ARE DETERMINED
AT DATUM PLANE ĆHĆ.
7. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT.
2.10
0.30
2.00
0.30
2.45
0.45
2.10
0.40
T
F
0.80 BSC
G
H
J
Ċ
0.25
0.23
0.95
Ċ
0.010
DATUM
-H-
PLANE
0.13
0.65
0.005 0.009
0.026 0.037
0.315 REF
R
K
L
8.00 REF
M
N
Q
R
S
5°
0.13
10°
0.17
7°
5°
0.005 0.007
0° 7°
10°
0°
0.13
K
0.30
0.005 0.012
0.510 0.530
Q
W
12.95 13.45
T
0.13
0°
Ċ
Ċ
0.005
0°
Ċ
Ċ
X
U
V
12.95 13.45
0.40
1.6 REF
0.510 0.530
0.016
0.063 REF
W
X
Ċ
Ċ
DETAIL C
Advance Information
138
MC68HC05C8A — Rev. 4.0
Mechanical Specifications
MOTOROLA
Advance Information — MC68HC05C8A
Section 15. Ordering Information
15.1 Contents
15.2 Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15.3 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139
15.4 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .140
15.5 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .141
15.6 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .141
15.2 Introduction
This section contains instructions for ordering custom-masked read-only
memory (ROM) microcontroller units (MCU).
15.3 MCU Ordering Forms
To initiate an order for a ROM-based MCU, first obtain the current
ordering form for the MCU from a Motorola representative. Submit these
items when ordering MCUs:
• A current MCU ordering form that is completely filled out
(Contact your Motorola sales office for assistance.)
• A copy of the customer specification if the customer specification
deviates from the Motorola specification for the MCU.
• Customer’s application program on one of the media listed in 15.4
Application Program Media.
MC68HC05C8A — Rev. 4.0
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MOTOROLA
Ordering Information
139
Ordering Information
15.4 Application Program Media
Please deliver the application program to Motorola in one of these
media:
• Macintosh®(1) 3-1/2-inch diskette (double-sided 800 K or
double-sided high-density 1.4 M)
• MS-DOS®(2) or PC-DOSTM(3) 3-1/2-inch diskette (double-sided
720 K or double-sided high-density 1.44 M)
• MS-DOS® or PC-DOSTM 5-1/4-inch diskette (double-sided
double-density 360 K or double-sided high-density 1.2 M)
Use positive logic for data and addresses.
When submitting the application program on a diskette, clearly label the
diskette with this information:
• Customer name
• Customer part number
• Project or product name
• File name of object code
• Date
• Name of operating system that formatted diskette
• Formatted capacity of diskette
On diskettes, the application program must be in Motorola’s S-record
format (S1 and S9 records), a character-based object file format
generated by M6805 cross assemblers and linkers.
Begin the application program at the first user ROM location. Program
addresses must correspond exactly to the available on-chip user ROM
addresses as shown in the memory map. Write $00 in all non-user ROM
locations or leave all non-user ROM locations blank. Refer to the current
MCU ordering form for additional requirements. Motorola may request
pattern re-submission if non-user areas contain any non-zero code.
1. Macintosh is a registered trademark of Apple Computer, Inc.
2. MS-DOS is a registered trademark of Microsoft Corporation.
3. PC-DOS is a trademark of International Business Machines Corporation.
Advance Information
140
MC68HC05C8A — Rev. 4.0
Ordering Information
MOTOROLA
Ordering Information
ROM Program Verification
If the memory map has two user ROM areas with the same addresses,
then write the two areas in separate files on the diskette. Label the
diskette with both filenames.
In addition to the object code, a file containing the source code can be
included. Motorola keeps this code confidential and uses it only to
expedite ROM pattern generation in case of any difficulty with the object
code. Label the diskette with the filename of the source code.
15.5 ROM Program Verification
The primary use for the on-chip ROM is to hold the customer’s
application program. The customer develops and debugs the application
program and then submits the MCU order along with the application
program.
Motorola inputs the customer’s application program code into a
computer program that generates a listing verify file. The listing verify file
represents the memory map of the MCU. The listing verify file contains
the user ROM code and may also contain non-user ROM code, such as
self-check code. Motorola sends the customer a computer printout of the
listing verify file along with a listing verify form.
To aid the customer in checking the listing verify file, Motorola will
program the listing verify file into customer-supplied blank preformatted
Macintosh or DOS disks. All original pattern media are filed for
contractual purposes and are not returned.
Check the listing verify file thoroughly, then complete and sign the listing
verify form and return the listing verify form to Motorola. The signed
listing verify form constitutes the contractual agreement for the creation
of the custom mask.
15.6 ROM Verification Units (RVUs)
After receiving the signed listing verify form, Motorola manufactures a
custom photographic mask. The mask contains the customer’s
application program and is used to process silicon wafers. The
MC68HC05C8A — Rev. 4.0
Advance Information
MOTOROLA
Ordering Information
141
Ordering Information
application program cannot be changed after the manufacture of the
mask begins. Motorola then produces 10 MCUs, called RVUs, and
sends the RVUs to the customer. RVUs are usually packaged in
unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are
not tested to environmental extremes because their sole purpose is to
demonstrate that the customer’s user ROM pattern was properly
implemented. The 10 RVUs are free of charge with the minimum order
quantity. These units are not to be used for qualification or production.
RVUs are not guaranteed by Motorola Quality Assurance.
Advance Information
142
MC68HC05C8A — Rev. 4.0
Ordering Information
MOTOROLA
Advance Information — MC68HC05C8A
Appendix A. MC68HCL05C8A
A.1 Contents
A.2
A.3
A.4
A.5
A.6
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .143
Low-Power Operating Temperature Range . . . . . . . . . . . . . .143
2.5-V to 3.6-V DC Electrical Characteristics . . . . . . . . . . . . .144
1.8-V to 2.4-V DC Electrical Characteristics. . . . . . . . . . . . . .144
Low-Power Supply Current . . . . . . . . . . . . . . . . . . . . . . . . . .145
A.2 Introduction
This appendix introduces the MC68HCL05C8A, a low-power version of
the MC68HC05C8A. The technical data applying to the MC68HC05C8A
applies to the MC68HCL05C8A with the exceptions given here.
A.3 Low-Power Operating Temperature Range
The follow data replaces the corresponding data found in
13.4 Operating Temperature Range.
Rating
Symbol
Value
Unit
(1)
T to T
Operating temperature range
L
H
T
°C
A
0 to +70
MC68HCL05C8AP, FN, B, FB
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
MC68HC05C8A — Rev. 4.0
Advance Information
143
MOTOROLA
MC68HCL05C8A
MC68HCL05C8A
A.4 2.5-V to 3.6-V DC Electrical Characteristics
(1)
Characteristic
Symbol
Typ
Max
Unit
Min
Output high voltage
(I
(I
(I
= –0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
V
V
V
– 0.3
– 0.3
– 0.3
Load
Load
Load
DD
DD
DD
—
—
—
—
—
—
V
= –0.4 mA) PD4–PD1
V
OH
= –1.5 mA) PC7
Output low voltage
(I
= 0.4 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
V
V
PD4–PD1, TCMP
= 5.0 mA) PC7
—
—
—
—
0.3
0.3
OL
(I
Load
Input pullup current
PB7–PB0 (with pullup)
I
40
160
300
µA
in
1. V = 2.5–3.6 Vdc
DD
A.5 1.8-V to 2.4-V DC Electrical Characteristics
(1)
Characteristic
Symbol
Typ
Max
Unit
Min
Output high voltage
(I
(I
(I
= –0.1 mA) PA7–PA0, PB7–PB0, PC6–PC0, TCMP
V
V
V
– 0.3
Load
Load
Load
DD
DD
DD
—
—
—
—
—
—
V
= –0.2 mA) PD4–PD1
V
– 0.3
– 0.3
OH
= –0.75 mA) PC7
Output low voltage
(I
= 0.2 mA) PA7–PA0, PB7–PB0, PC6–PC0,
Load
V
PD4–PD1, TCMP
= 2.0 mA) PC7
—
—
—
—
0.3
0.3
V
I
OL
(I
Load
Input pullup current
PB7–PB0 (with pullup)
15
110
200
µA
In
1. V = 2.5–3.6 Vdc
DD
Advance Information
144
MC68HC05C8A — Rev. 4.0
MC68HCL05C8A
MOTOROLA
MC68HCL05C8A
Low-Power Supply Current
A.6 Low-Power Supply Current
(1)
(1)
Symbol
Min
Max
Unit
Characteristic
Typ
Supply current (4.5–5.5 Vdc @ f
= 2.1 MHz)
= 1.0 MHz)
= 500 kHz)
= 500 kHz)
Bus
Bus
Bus
Bus
(2)
Run
—
—
3.50
1.6
4.25
2.25
mA
mA
(3)
Wait
I
I
I
I
DD
DD
DD
DD
(4)
Stop
—
—
1
—
15
25
µA
µA
25°C
0°C to +70°C (standard)
Supply current (2.4–3.6 Vdc @ f
(2)
Run
—
—
1.00
0.7
1.4
1.0
mA
mA
(3)
Wait
(4)
Stop
—
—
1
—
5
10
µA
µA
25°C
0°C to +70° C (standard)
Supply current (2.5–3.6 Vdc @ f
(2)
Run
—
—
500
300
750
500
µA
µA
(3)
Wait
(4)
Stop
—
—
1
—
5
10
µA
µA
25°C
0°C to +70°C (standard)
Supply current (1.8–2.4 Vdc @ f
(2)
Run
—
—
300
250
600
400
µA
µA
(3)
Wait
(4)
Stop
—
—
1
—
2
5
µA
µA
25°C
0°C to +70°C (standard)
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs,
DD
Port B = V , all other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs;
DD
IL
IH
DD
C = 20 pF on OSC2
L
3. Wait I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V , all other inputs
DD
DD
V
= 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs; C = 20 pF on OSC2. Wait I is affected linearly
IL
IH DD L DD
by the OSC2 capacitance.
4. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = V , all other inputs V = 0.2 V,
DD
DD
IL
V
= V –0.2 V
IH
DD
MC68HC05C8A — Rev. 4.0
Advance Information
145
MOTOROLA
MC68HCL05C8A
MC68HCL05C8A
Advance Information
146
MC68HC05C8A — Rev. 4.0
MC68HCL05C8A
MOTOROLA
Advance Information — MC68HC05C8A
Appendix B. MC68HSC05C8A
B.1 Contents
B.2
B.3
B.4
B.5
B.6
B.7
B.8
Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .147
High-Speed Operating Temperature Range. . . . . . . . . . . . . .147
DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .148
4.5-V to 5.5-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .149
2.4-V to 3.6-V Control Timing . . . . . . . . . . . . . . . . . . . . . . . . .150
4.5-V to 5.5-V High-Speed SPI Timing. . . . . . . . . . . . . . . . . .151
2.4-V to 3.6-V High-Speed SPI Timing. . . . . . . . . . . . . . . . . .152
B.2 Introduction
This appendix introduces the MC68HSC05C8A, a high-speed version of
the MC68HC05C8A. The technical data applying to the MC68HC05C8A
applies to the MC68HSC05C8A with the exceptions given here.
B.3 High-Speed Operating Temperature Range
The follow data replaces the corresponding data found in
13.4 Operating Temperature Range.
Rating
Symbol
Value
Unit
(1)
T to T
Operating temperature range
L
H
T
°C
0 to +70
–40 to +85
MC68HSC05C8AP, FN, B, FB
MC68HSC05C8CP, CFN, CB, CFB
A
1. P = Plastic dual in-line package (PDIP)
FN = Plastic-leaded chip carrier (PLCC)
B = Shrink dual in-line package (SDIP)
FB = Quad flat pack (QFP)
MC68HC05C8A — Rev. 4.0
MOTOROLA
Advance Information
147
MC68HSC05C8A
MC68HSC05C8A
B.4 DC Electrical Characteristics
The data in 13.7 5.0-V DC Electrical Characteristics and 13.8 3.3-V
DC Electrical Characteristics applies to the MC68HSC05C8A with the
exceptions given here.
(1)
Symbol
Min
Typ
Max
Unit
Characteristic
Supply current (4.5–5.5 Vdc @ fBUS = 4.0 MHz)
(2)
Run
—
—
7.00
2.00
11.0
6.50
mA
mA
(3)
Wait
I
(4)
DD
Stop
—
—
—
1
—
—
20
40
50
µA
µA
µA
25°C
0°C to 70°C (Standard)
–40°C to 125°C (Standard)
Supply Current (2.4–3.6 Vdc @ fBUS = 2.0 MHz)
(2)
Run
—
—
2.50
1.00
4.00
2.00
mA
mA
(3)
Wait
I
(4)
DD
Stop
—
—
—
1
—
—
8
16
20
µA
µA
µA
25°C
0°C to 70°C (standard)
–40°C to 125°C (standard)
Input pullup current (V = 4.5–5.5 V)
DD
I
175
50
385
160
750
350
µA
µA
In
PB7–PB0 (with pullup)
Input pullup current (V = 2.4–3.6 V)
DD
I
In
PB7–PB0 (with pullup)
1. Typical values reflect measurements taken on average processed devices at the midpoint of voltage range, 25°C only.
2. Run (operating) I measured using external square wave clock source; all I/O pins configured as inputs, Port B = V
,
DD
DD
all other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs;
IL
IH
DD
C = 20 pF on OSC2
L
3. Wait I measured using external square wave clock source; all I/O pins configured as inputs,
DD
Port B = V , all other inputs V = 0.2 V, V = V –0.2 V; no DC loads; less than 50 pF on all outputs;
DD
IL
IH
DD
C = 20 pF on OSC2. Wait I is affected linearly by the OSC2 capacitance.
L
DD
4. Stop I measured with OSC1 = 0.2 V; all I/O pins configured as inputs, Port B = V , all other inputs
DD
DD
V
= 0.2 V, V = V –0.2 V
IL
IH DD
Advance Information
148
MC68HC05C8A — Rev. 4.0
MOTOROLA
MC68HSC05C8A
MC68HSC05C8A
4.5-V to 5.5-V Control Timing
B.5 4.5-V to 5.5-V Control Timing
The data in 13.9 5.0-V Control Timing applies to the MC68HSC05C8A
with the exceptions given here.
Characteristic
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External Clock
f
—
dc
8.2
8.2
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
4.1
4.1
MHz
Crystal
External clock
OP
t
Cycle time
244
—
100
100
—
ns
ms
ms
CYC
t
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width
Timer
OXOV
t
ILCH
t
t
1.5
4.0
64
(2)
RL
CYC
(1)
t
t
RESL
—
—
—
CYC
Resolution
Input capture pulse width
Input capture pulse width
t
or t
TL
ns
TH
t
t
CYC
THTL
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
64
—
—
—
ns
ILIH
t
(3)
t
ILIL
CYC
t
or t
OSC1 pulse width
50
ns
OH
OL
1. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
2. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
CYC
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
3. The minimum t
ILIL
19 t
.
CYC
MC68HC05C8A — Rev. 4.0
Advance Information
149
MOTOROLA
MC68HSC05C8A
MC68HSC05C8A
B.6 2.4-V to 3.6-V Control Timing
The data in 13.10 3.3-V Control Timing applies to the MC68HSC05C8A
with the exceptions given here.
Characteristic
Symbol
Min
Max
Unit
Oscillator frequency
Crystal
External clock
f
—
dc
4.2
4.2
MHz
OSC
Internal operating frequency (f
÷ 2)
OSC
f
—
dc
2.1
2.1
MHz
Crystal
External clock
OP
t
Cycle time
480
—
100
100
—
ns
ms
ms
CYC
t
Crystal oscillator startup time
Stop recovery startup time
RESET pulse width
Timer
OXOV
t
ILCH
t
t
1.5
4.0
125
(2)
RL
CYC
(1)
t
t
RESL
—
—
—
CYC
Resolution
Input capture pulse width
Input capture pulse width
t
or t
TL
ns
TH
t
t
CYC
THTL
t
Interrupt pulse width low (edge-triggered)
Interrupt pulse period
125
—
—
—
ns
ILIH
t
(3)
t
ILIL
CYC
t
or t
OSC1 pulse width
90
ns
OH
OL
1. Because a 2-bit prescaler in the timer must count four internal cycles (t
determining the timer resolution.
), this is the limiting minimum factor in
CYC
2. The minimum period t
should not be less than the number of cycle times it takes to execute the capture interrupt service
TLTL
routine plus 24 t
.
CYC
3. The minimum t
should not be less than the number of cycle times it takes to execute the interrupt service routine plus
ILIL
19 t
.
CYC
Advance Information
150
MC68HC05C8A — Rev. 4.0
MC68HSC05C8A
MOTOROLA
MC68HSC05C8A
4.5-V to 5.5-V High-Speed SPI Timing
B.7 4.5-V to 5.5-V High-Speed SPI Timing
The data in 13.11 5.0-V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given here.
Num
Characteristic
Symbol
Min Max
Unit
Operating frequency
Master
Slave
f
f
f
dc
dc
0.5
4.1
OP(M)
OP
MHz
OP(S)
Cycle time
Master
Slave
t
t
t
1
2
3
4
5
6
7
2.0
244
—
—
CYC(M)
CYC
ns
CYC(S)
Enable lead time
Master
Slave
(1)
t
—
—
ns
ns
Lead(M)
tLead(S)
122
Enable lag time
Master
Slave
t
(1)
366
—
—
ns
ns
Lag(M)
t
Lag(S)
Clock (SCK) high time
Master
Slave
t
t
166
93
—
—
ns
ns
W(SCKH)M
W(SCKH)S
Clock (SCK) low time
Master
Slave
t
166
93
—
—
ns
ns
W(SCKL)M
t
W(SCKL)S
Data setup time (inputs)
Master
Slave
t
49
49
—
—
ns
ns
SU(M)
t
SU(S)
Data hold time (inputs)
Master
Slave
t
49
49
—
—
ns
ns
H(M)
t
H(S)
t
8
9
Slave access time (time to data active from high-impedance state)
Slave disable time (hold time to high-impedance state)
0
61
ns
ns
A
t
—
122
DIS
Data valid
Master (before capture edge)
t
t
t
t
10
11
12
13
0.25
—
—
122
V(M)
CYC(M)
ns
(2)
Slave (after enable edge)
V(S)
Data hold time (outputs)
Master (after capture edge)
Slave (After Enable Edge)
t
t
0.25
0
—
—
HO(M)
CYC(M)
ns
HO(S)
Rise time (20% V to 70% V , C = 200 pF)
DD
DD
L
t
—
—
50
1.0
ns
µs
RM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
RS
Fall time (70% V to 20% V , C = 200 pF)
DD
DD
L
t
—
—
50
1.0
ns
µs
FM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
FS
1. Signal production depends on software.
2. Assumes 200 pF load on all SPI pins.
MC68HC05C8A — Rev. 4.0
Advance Information
151
MOTOROLA
MC68HSC05C8A
MC68HSC05C8A
B.8 2.4-V to 3.6-V High-Speed SPI Timing
The data in 13.12 3.3-V Serial Peripheral Interface Timing applies to
the MC68HSC05C8A with the exceptions given in the following table.
Num
Characteristic
Symbol
Min Max
Unit
Operating frequency
Master
Slave
f
f
f
dc
dc
0.5
2.1
OP(M)
OP
MHz
OP(S)
Cycle time
Master
Slave
t
t
t
1
2
3
4
5
6
7
2.0
480
—
—
CYC(M)
CYC
ns
CYC(S)
Enable lead time
Master
Slave
(1)
t
—
—
ns
ns
Lead(M)
t
240
Lead(S)
Enable lag time
Master
Slave
t
(1)
720
—
—
ns
ns
Lag(M)
t
Lag(S)
Clock (SCK) High Time
Master
Slave
t
t
340
190
—
—
ns
ns
W(SCKH)M
W(SCKH)S
Clock (SCK) low time
Master
Slave
t
340
190
—
—
ns
ns
W(SCKL)M
t
W(SCKL)S
Data setup time (Inputs)
Master
Slave
t
100
100
—
—
ns
ns
SU(M)
t
SU(S)
Data hold time (Inputs)
Master
Slave
t
100
100
—
—
ns
ns
H(M)
t
H(S)
t
8
9
Slave access time (time to data active from high-impedance state)
Slave disable time (hold time to high-impedance state)
0
120
240
ns
ns
A
t
—
DIS
Data
t
t
Master (before capture edge)
t
t
10
11
12
13
0.25
—
—
240
V(M)
CYC(M)
ns
(2)
Slave (after enable edge)
V(S)
Data Hold Time (outputs)
Master (after capture edge)
Slave (after enable edge)
t
t
0.25
0
—
—
HO(M)
CYC(M)
ns
HO(S)
Rise time (20% V to 70% V , C = 200 pF)
DD
DD
L
t
—
—
100
2.0
ns
µs
RM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
RS
Fall time (70% V to 20% V , CL = 200 pF)
DD
DD
t
—
—
100
2.0
ns
µs
FM
SPI outputs (SCK, MOSI, and MISO)
SPI inputs (SCK, MOSI, MISO, and SS)
t
FS
1. Signal production depends on software.
2. Assumes 20 pF load on all SPI pins.
Advance Information
152
MC68HC05C8A — Rev. 4.0
MC68HSC05C8A
MOTOROLA
Advance Information — MC68HC05C8A
Appendix C. M68HC05Cx Family Feature Comparisons
Refer to Table C-1 for a comparison of the features for all the
M68HC05C Family members.
MC68HC05C8A — Rev. 4.0
Advance Information
153
MOTOROLA
M68HC05Cx Family Feature Comparisons
Table C-1. M68HC05Cx Feature Comparison
C4
4160
—
C4A
4160
—
705C4A
—
C8
7744
—
C8A
7744
—
705C8
—
705C8A
—
C12
12,096
—
C12A
12,096
—
C9
C9A
705C9
705C9A
USER ROM
15,760–15,936 15,760–15,936
—
—
USER EPROM
4160
7596–7740
7596–7740
—
NO
—
YES
15,760–15,936 12,096–15,936
CODE
SECURITY
NO
176
YES
176
YES
176
NO
YES
176
YES
YES
NO
176
YES
176
NO
YES
RAM
176
176–304
176–304
176–352
176–352
176–352
176–352
OPTION
REGISTER
(IRQ/RAM/
SEC)
$1FDF
(IRQ/RAM/
SEC)
$1FDF
(IRQ/SEC)
$1FDF
(IRQ/RAM/SEC)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
$3FDF
(IRQ/RAM)
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
NO
MASK OPTION
REGISTER(S)
$1FF0–1
NO
NO
$1FF0–1
NO
NO
NO
NO
NO
$3FF0–1
PORTB
KEYSCAN
(PULLUP/
YES
MOR
SELECT-
ABLE
YES
MASK
OPTION
YES
MASK
OPTION
YES
MOR
SELECTABLE
YES
MASK
OPTION
YES
MASK
OPTION
YES
MASK
OPTION
YES
MOR
SELECTABLE
NO
INTERRUPT)
HIGH
HIGH
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
HIGH
CURRENT
PC7 DRIVE STANDARD
STANDARD
STANDARD
STANDARD
STANDARD
CURRENT CURRENT
PD7, 5–0
INPUT
ONLY
PD7, 5–0
BIDIREC-
TIONAL
PD7, 5–0
BIDIREC-
TIONAL
PD7, 5–0
BIDIREC-
TIONAL
PD7, 5–0
PD7, 5–0 PD7, 5–0
PD7, 5–0
INPUT ONLY INPUT ONLY
PD7, 5–0
PD7, 5–0
INPUT ONLY
PD7, 5–0
INPUT ONLY INPUT ONLY
PD7, 5–0
PD7, 5–0
BIDIRECTIONAL
PORT D
INPUT ONLY INPUT ONLY INPUT ONLY
COP
NO
YES
YES
NO
YES
YES
TWO TYPES
YES
YES
YES
YES
YES
TWO TYPES
MASK
OPTION
MASK
OPTION
SOFTWARE+
MOR
MASK
OPTION
MASK
OPTION
SOFTWARE+
MOR
COP ENABLE
—
MOR
—
SOFTWARE
SOFTWARE
SOFTWARE
SOFTWARE
64 ms
(@4 MHz
osc)
SOFTWARE+
MOR
SELECTABLE
SOFTWARE+
MOR
SELECTABLE
64 ms
(@4 MHz osc)
64 ms
SOFTWARE
64 ms
64 ms
SOFTWARE
SOFTWARE
SOFTWARE
COP TIMEOUT
COP CLEAR
—
—
(@4 MHz osc) SELECTABLE
(@4 MHz osc) (@4MHz osc) SELECTABLE SELECTABLE SELECTABLE
WRITE $55/$AA
TO $001D
OR
WRITE $55/$AA
TO $001D
OR
WRITE $55/$AA
CLR $1FF0
WRITE $55/$AA WRITE $55/$AA WRITE $55/$AA
—
NO
NO
CLR $1FF0 CLR $1FF0
—
NO
NO
CLR $3FF0
NO
CLR $3FF0
NO
TO $001D
TO $001D
YES
TO $001D
YES
TO $001D
YES
CLR $1FF0
CLR $3FF0
CLOCK
MONITOR
YES
(C9A MODE)
NO
NO
NO
NO
NO
NO
YES
YES
PROGRAM-
MABLE
COP/CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/COP/
CLOCK
MONITOR
POR/C9A COP/
CLOCK
MONITOR
ACTIVE
RESET
COP/CLOCK
MONITOR
NO
NO
MOR
SELECTABLE
(C12A MODE)
MASK
OPTION
MASK
OPTION
MASK
OPTION
MASK
OPTION
STOP DISABLE
NOTES:
NO
NO
NO
NO
NO
NO
NO
NO
1. The expanded RAM map (from $30–$4F and $100–$15F) available on the OTP devices MC68HC705C8 and MC68HC705C8A is not available on the ROM devices MC68HC05C8 and MC68HC05C8A.
2. The programmable COP available on the MC68HC705C8 and MC68HC705C8A is not available on the MC68HC05C8A. For ROM compatibility, use the non-programmable COP.
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MC68HC05C8A/D
REV 4
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