MC74HC273AN [ROCHESTER]
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20;
| 型号： | MC74HC273AN |
| 厂家： | 
Rochester Electronics |
| 描述： | HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDIP20, PLASTIC, DIP-20 光电二极管 输出元件 逻辑集成电路 触发器 |
| 文件： | 总10页 (文件大小：816K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC74HC273A
Octal D Flip-Flop with
Common Clock and Reset
High-Performance Silicon-Gate CMOS
The MC74HC273A is identical in pinout to the LS273. The device
inputs are compatible with standard CMOS outputs; with pullup
resistors, they are compatible with LSTTL outputs.
http://onsemi.com
MARKING
DIAGRAMS
This device consists of eight D flip-flops with common Clock and
Reset inputs. Each flip-flop is loaded with a low-to-high transition of
the Clock input. Reset is asynchronous and active low.
20
20
PDIP-20
N SUFFIX
CASE 738
Features
MC74HC273AN
AWLYYWWG
•ꢀOutput Drive Capability: 10 LSTTL Loads
•ꢀOutputs Directly Interface to CMOS, NMOS and TTL
•ꢀOperating Voltage Range: 2.0 to 6.0 V
•ꢀLow Input Current: 1.0 mA
1
1
20
•ꢀHigh Noise Immunity Characteristic of CMOS Devices
SOIC-20
DW SUFFIX
CASE 751D
20
HC273A
AWLYYWWG
•ꢀIn Compliance with the Requirements Defined by JEDEC Standard
No. 7A
1
1
•ꢀChip Complexity: 264 FETs or 66 Equivalent Gates
•ꢀPb-Free Packages are Available
20
HC
273A
ALYWG
G
TSSOP-20
DT SUFFIX
CASE 948E
20
1
1
20
SOEIAJ-20
F SUFFIX
CASE 967
20
74HC273A
AWLYWWG
1
1
A
WL, L
YY, Y
= Assembly Location
= Wafer Lot
= Year
WW, W = Work Week
G
G
= Pb-Free Package
= Pb-Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©ꢀ Semiconductor Components Industries, LLC, 2008
March, 2008 - Rev. 12
1
Publication Order Number:
MC74HC273A/D
MC74HC273A
PIN ASSIGNMENT
RESET
Q0
1
2
3
4
5
6
7
8
9
20
V
CC
19 Q7
18 D7
17 D6
16 Q6
15 Q5
14 D5
13 D4
12 Q4
11 CLOCK
LOGIC DIAGRAM
D0
2
5
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
D0
D1
D2
D3
D4
D5
D6
D7
D1
4
Q1
7
6
Q2
8
9
DATA
D2
NONINVERTING
OUTPUTS
13
14
17
18
INPUTS
12
15
16
19
D3
Q3
GND 10
11
FUNCTION TABLE
CLOCK
Inputs
Output
Q
PIN 20 = V
CC
PIN 10 = GND
Reset Clock
D
1
RESET
L
X
L
X
H
L
X
X
L
H
L
H
H
H
H
No Change
No Change
Design Criteria
Value
66
Units
ea
Internal Gate Count*
Internal Gate Propagation Delay
Internal Gate Power Dissipation
1.5
ns
5.0
mW
pJ
Speed Power Product
.0075
*Equivalent to a two-input NAND gate.
ORDERING INFORMATION
Device
†
Package
Shipping
MC74HC273AN
PDIP-20
18 Units / Rail
18 Units / Rail
MC74HC273ANG
PDIP-20
(Pb-Free)
MC74HC273ADW
MC74HC273ADWG
SOIC-20 WIDE
38 Units / Rail
38 Units / Rail
SOIC-20 WIDE
(Pb-Free)
MC74HC273ADWR2
MC74HC273ADWR2G
SOIC-20 WIDE
1000 Tape & Reel
1000 Tape & Reel
SOIC-20 WIDE
(Pb-Free)
MC74HC273ADT
MC74HC273ADTG
MC74HC273ADTR2
MC74HC273ADTR2G
MC74HC273AF
TSSOP-20*
TSSOP-20*
TSSOP-20*
TSSOP-20*
SOEIAJ-20
75 Units / Rail
75 Units / Rail
2500 Tape & Reel
2500 Tape & Reel
40 Units / Rail
MC74HC273AFG
SOEIAJ-20
(Pb-Free)
40 Units / Rail
MC74HC273AFEL
MC74HC273AFELG
SOEIAJ-20
2000 Tape & Reel
2000 Tape & Reel
SOEIAJ-20
(Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*This package is inherently Pb-Free.
http://onsemi.com
2
MC74HC273A
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
ꢁThis device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high-impedance cir‐
V
DC Supply Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Output Voltage (Referenced to GND)
DC Input Current, per Pin
– 0.5 to + 7.0
CC
V
– 0.5 to V + 0.5
V
in
CC
V
out
– 0.5 to V + 0.5
V
CC
I
20
25
50
mA
mA
mA
mW
in
cuit. For proper operation, V and
in
I
I
DC Output Current, per Pin
out
V
out
should be constrained to the
range GND v (V or V ) v V
.
DC Supply Current, V and GND Pins
in
out
CC
CC
CC
ꢁUnused inputs must always be
tied to an appropriate logic voltage
P
D
Power Dissipation in Still Air,
Plastic DIP†
SOIC Package†
TSSOP Package†
750
500
450
level (e.g., either GND or V ).
CC
Unused outputs must be left open.
T
Storage Temperature
– 65 to + 150
°C
°C
stg
T
Lead Temperature, 1 mm from Case for 10 Seconds
Plastic DIP, SOIC or TSSOP Package
L
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress
ratings only. Functional operation above the Recommended Operating Conditions is not implied.
Extended exposure to stresses above the Recommended Operating Conditions may affect device
reliability.
†Derating — Plastic DIP: – 10 mW/°C from 65° to 125°C
SOIC Package: – 7 mW/°C from 65° to 125°C
TSSOP Package: - 6.1 mW/°C from 65° to 125°C
For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High-Speed CMOS Data Book (DL129/D).
RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
2.0
0
Max
Unit
V
V
CC
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
Operating Temperature, All Package Types
6.0
V , V
in out
V
CC
V
T
A
– 55
+ 125
°C
ns
t , t
Input Rise and Fall Time
ꢁ(Figure 1)
V
CC
V
CC
V
CC
= 2.0 V
= 4.5 V
= 6.0 V
0
0
0
1000
500
400
r
f
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25°C
Symbol
Parameter
Test Conditions
= V – 0.1 V
|I | v 20 mA
v 85°C
v 125°C
Unit
V
IH
Minimum High-Level Input Voltage
V
2.0
3.0
4.5
6.0
1.5
2.1
3.15
4.2
1.5
2.1
1.5
2.1
V
out
CC
out
3.15
4.2
3.15
4.2
V
Maximum Low-Level Input Voltage
V
= 0.1 V
2.0
3.0
4.5
6.0
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
0.5
0.9
1.35
1.8
V
V
IL
out
|I | v 20 mA
out
V
OH
Minimum High-Level Output
Voltage
V
in
= V
IH
2.0
4.5
6.0
1.9
4.4
5.9
1.9
4.4
5.9
1.9
4.4
5.9
|I | v 20 mA
out
V
= V
|I | v 2.4 mA
3.0
4.5
6.0
2.48
3.98
5.48
2.34
3.84
5.34
2.2
3.7
5.2
in
in
IH
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
V
OL
Maximum Low-Level Output
Voltage
V
= V
2.0
4.5
6.0
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
0.1
V
|I | v 20 mA
out
V
in
= V
|I | v 2.4 mA
3.0
4.5
6.0
0.26
0.26
0.26
0.33
0.33
0.33
0.4
0.4
0.4
IL
out
|I | v 6.0 mA
out
|I | v 7.8 mA
out
http://onsemi.com
3
MC74HC273A
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
– 55 to
V
CC
V
25°C
Symbol
Parameter
Test Conditions
= V or GND
v 85°C
1.0
v 125°C
1.0
Unit
mA
I
in
Maximum Input Leakage Current
V
V
6.0
6.0
0.1
4.0
in
CC
I
Maximum Quiescent Supply
Current (per Package)
= V or GND
40
160
mA
CC
in
CC
I
= 0 mA
out
AC ELECTRICAL CHARACTERISTICS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to
25°C
V
CC
v 85°C
5.0
10
24
28
v 125°C
V
Symbol
Parameter
Unit
f
Maximum Clock Frequency (50% Duty Cycle)
ꢁ(Figures 1 and 4)
2.0
3.0
4.5
6.0
6.0
15
30
35
4.0
8.0
20
MHz
max
24
t
t
Maximum Propagation Delay, Clock to Q
ꢁ(Figures 1 and 4)
2.0
3.0
4.5
6.0
145
90
29
180
120
36
220
140
44
ns
ns
ns
PLH
PHL
25
31
38
t
Maximum Propagation Delay, Reset to Q
ꢁ(Figures 2 and 4)
2.0
3.0
4.5
6.0
145
90
29
180
120
36
220
140
44
PHL
25
31
38
t
t
Maximum Output Transition Time, Any Output
ꢁ(Figures 1 and 4)
2.0
3.0
4.5
6.0
75
27
15
13
95
32
19
16
110
36
22
TLH
THL
19
C
Maximum Input Capacitance
10
10
10
pF
pF
in
Typical @ 25°C, V = 5.0 V
CC
48
C
Power Dissipation Capacitance (Per Enabled Output)*
PD
http://onsemi.com
4
MC74HC273A
TIMING REQUIREMENTS (C = 50 pF, Input t = t = 6.0 ns)
L
r
f
Guaranteed Limit
– 55 to 25°C
v 85°C
v 125°C
V
CC
Volts
Min
Max
Min
Max
Min
Max
Symbol
Parameter
Figure
Unit
t
su
Minimum Setup Time, Data to Clock
3
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
ns
t
Minimum Hold Time, Clock to Data
3
2
1
2
1
2.0
3.0
4.5
6.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
3.0
ns
ns
ns
ns
ns
h
t
Minimum Recovery Time, Reset Inactive to
Clock
2.0
3.0
4.5
6.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
rec
t
w
t
w
Minimum Pulse Width, Clock
Minimum Pulse Width, Reset
Maximum Input Rise and Fall Times
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
2.0
3.0
4.5
6.0
60
23
12
10
75
27
15
13
90
32
18
15
t , t
r
2.0
3.0
4.5
6.0
1000
800
500
400
1000
800
500
400
1000
800
500
400
f
http://onsemi.com
5
MC74HC273A
SWITCHING WAVEFORMS
t
w
t
r
t
f
V
CC
V
CC
90%
50%
10%
50%
RESET
CLOCK
GND
GND
t
t
PHL
w
1/f
max
50%
Q
t
t
PHL
PLH
t
90%
50%
10%
rec
Q
V
CC
CLOCK
50%
GND
t
t
TLH
THL
Figure 1.
Figure 2.
VALID
V
CC
DATA
50%
GND
t
su
t
h
V
CC
CLOCK
50%
C
2
Q
Q
Q
Q
Q
Q
Q
Q
Q0
GND
3
D0
D1
D2
D3
D4
D5
D6
D7
D
D
D
D
D
D
D
D
R
C
Figure 3.
5
Q1
Q2
Q3
Q4
Q5
Q6
Q7
4
R
C
6
7
R
C
9
8
R
NONINVERTING
OUTPUTS
TEST POINT
OUTPUT
DATA
INPUTS
C
12
15
16
19
13
14
17
R
DEVICE
UNDER
TEST
C
C *
L
R
C
R
*Includes all probe and jig capacitance
C
Figure 4. Test Circuit
18
11
1
R
Figure 5. Expanded Logic Diagram
http://onsemi.com
6
MC74HC273A
PACKAGE DIMENSIONS
PDIP-20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738-03
ISSUE E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
-A-
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
20
1
11
10
B
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
L
C
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
0.050 BSC
1.27 BSC
-T-
SEATING
PLANE
K
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
F
G
J
M
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
N
E
K
L
0.300 BSC
7.62 BSC
G
F
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
J 20 PL
_
D 20 PL
M
M
T B
0.25 (0.010)
M
M
T A
0.25 (0.010)
SOIC-20
DW SUFFIX
CASE 751D-05
ISSUE G
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
D
A
q
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
20
11
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
E
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
B
20X B
M
S
S
B
T
0.25
A
e
1.27 BSC
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
A
L
q
_
_
SEATING
PLANE
18X e
A1
C
T
http://onsemi.com
7
MC74HC273A
PACKAGE DIMENSIONS
TSSOP-20
DT SUFFIX
CASE 948E-02
ISSUE C
20X K REF
NOTES:
ꢁă1.DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
M
S
S
V
0.10 (0.004)
T U
S
0.15 (0.006) T U
K
ꢁă2.CONTROLLING DIMENSION: MILLIMETER.
ꢁă3.DIMENSION A DOES NOT INCLUDE MOLD
FLASH, PROTRUSIONS OR GATE BURRS.
MOLD FLASH OR GATE BURRS SHALL
NOT EXCEED 0.15 (0.006) PER SIDE.
ꢁă4.DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER
SIDE.
ꢁă5.DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
K1
20
11
2X L/2
J J1
B
L
-U-
PIN 1
IDENT
SECTION N-N
1
10
0.25 (0.010)
N
S
0.15 (0.006) T U
ꢁă6.TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
ꢁă7.DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE -W-.
M
A
-V-
N
MILLIMETERS
DIM MIN MAX
INCHES
MIN
MAX
0.260
0.177
0.047
0.006
0.030
F
A
B
6.40
4.30
---
6.60 0.252
4.50 0.169
DETAIL E
C
1.20
---
D
0.05
0.50
0.15 0.002
0.75 0.020
-W-
F
C
G
H
0.65 BSC
0.026 BSC
0.27
0.09
0.09
0.19
0.19
0.37
0.011
0.015
0.008
0.006
0.012
0.010
J
0.20 0.004
0.16 0.004
0.30 0.007
0.25 0.007
G
D
J1
K
H
DETAIL E
0.100 (0.004)
-T- SEATING
PLANE
K1
L
6.40 BSC
0.252 BSC
0
M
0
8
8
_
_
_
_
SOLDERING FOOTPRINT
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
*For additional information on our Pb-Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
http://onsemi.com
8
MC74HC273A
PACKAGE DIMENSIONS
SOEIAJ-20
F SUFFIX
CASE 967-01
ISSUE A
NOTES:
ꢀꢁ1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ꢀꢁ2. CONTROLLING DIMENSION: MILLIMETER.
ꢀꢁ3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
L
E
20
11
Q
1
ꢀꢁ4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
ꢀꢁ5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
---
e
A
DIM MIN
MAX
MAX
0.081
0.008
0.020
0.010
0.504
0.215
c
A
---
0.05
0.35
0.15
12.35
5.10
2.05
A
1
0.20 0.002
0.50 0.014
0.25 0.006
b
c
D
E
e
12.80 0.486
5.45 0.201
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20 0.291
0.85 0.020
1.50 0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
0.90 0.028
10
_
0.035
0.032
0
_
_
_
0.70
---
1
Z
0.81
---
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800-282-9855 Toll Free
ꢂUSA/Canada
Europe, Middle East and Africa Technical Support:
ꢂPhone: 421 33 790 2910
Japan Customer Focus Center
ꢂPhone: 81-3-5773-3850
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
ꢂLiterature Distribution Center for ON Semiconductor
ꢂP.O. Box 5163, Denver, Colorado 80217 USA
ꢂPhone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
ꢂFax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
ꢂEmail: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
MC74HC273A/D
相关型号：
MC74HC273ANG
Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC273A_05
Octal D Flip−Flop with Common Clock and Reset High−Performance Silicon−Gate CMOS
ONSEMI
MC74HC273DW
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, SOIC-20
MOTOROLA
MC74HC273DWR2
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, SOIC-20
MOTOROLA
©2020 ICPDF网 联系我们和版权申明