MC9S08AC96MFGE [ROCHESTER]
8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44, ROHS COMPLIANT, LQFP-44;
| 型号： | MC9S08AC96MFGE |
| 厂家： | 
Rochester Electronics |
| 描述： | 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP44, ROHS COMPLIANT, LQFP-44 时钟 外围集成电路 |
| 文件： | 总41页 (文件大小：1489K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Freescale Semiconductor
Data Sheet: Technical Data
Document Number: MC9S08AC128
Rev. 4, 8/2011
MC9S08AC128 8-Bit
Microcontroller Data Sheet
MC9S08AC128
840B-01
824D-02
917A-03
Power-Saving Modes
8-Bit HCS08 Central Processor Unit (CPU)
•
Wait plus two stops
•
•
•
40-MHz HCS08 CPU (central processor unit)
20-MHz internal bus frequency
HC08 instruction set with added BGND, CALL and
RTC instructions
Peripherals
•
ADC — 16-channel, 10-bit resolution, 2.5 s
conversion time, automatic compare function,
temperature sensor, internal bandgap reference
channel
•
•
Memory Management Unit to support paged
memory.
Linear Address Pointer to allow direct page data
accesses of the entire memory map
•
SCIx — Two serial communications interface
modules supporting LIN 2.0 Protocol and SAE J2602
protocols; Full duplex non-return to zero (NRZ);
Master extended break generation; Slave extended
break detection; Wakeup on active edge
SPIx — One full and one master-only serial
peripheral interface modules; Full-duplex or
single-wire bidirectional; Double-buffered transmit
and receive; Master or Slave mode; MSB-first or
LSB-first shifting
IIC — Inter-integrated circuit bus module; Up to 100
kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt
driven byte-by-byte data transfer; supports broadcast
mode and 10 bit addressing
TPMx — One 2-channel and two 6-channel 16-bit
timer/pulse-width modulator (TPM) modules:
Selectable input capture, output compare, and
edge-aligned PWM capability on each channel. Each
timer module may be configured for buffered,
centered PWM (CPWM) on all channels
KBI — 8-pin keyboard interrupt module
Development Support
•
•
Background debugging system
Breakpoint capability to allow single breakpoint
setting during in-circuit debugging (plus two more
breakpoints in on-chip debug module)
•
•
•
•
On-chip in-circuit emulator (ICE) Debug module
containing three comparators and nine trigger
modes. Eight deep FIFO for storing change-of-flow
addresses and event-only data. Supports both tag
and force breakpoints.
Memory Options
•
Up to 128K FLASH — read/program/erase over full
operating voltage and temperature
•
•
Up to 8K Random-access memory (RAM)
Security circuitry to prevent unauthorized access to
RAM and FLASH contents
Clock Source Options
Clock source options include crystal, resonator,
•
external clock, or internally generated clock with
precision NVM trimming using ICG module
•
Input/Output
System Protection
•
•
•
Up to 70 general-purpose input/output pins
•
Optional computer operating properly (COP) reset
Software selectable pullups on input port pins
Software selectable drive strength and slew rate
control on ports when used as outputs
with option to run from independent internal clock
source or bus clock
•
CRC module to support fast cyclic redundancy
checks on system memory
Low-voltage detection with reset or interrupt
Illegal opcode detection with reset
Package Options
•
•
•
•
80-pin low-profile quad flat package (LQFP)
64-pin quad flat package (QFP)
48-pin quad flat no-lead package (QFN)
44-pin low-profile quad flat package (LQFP)
•
•
•
Master reset pin and power-on reset (POR)
This document contains information on a new product. Specifications and information herein
are subject to change without notice.
© Freescale Semiconductor, Inc., 2007-2011. All rights reserved.
Table of Contents
Chapter 1
Device Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
1.1 MCU Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Chapter 2
Pins and Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1 Device Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . .5
Chapter 3
3.9 Internal Clock Generation Module Characteristics . . . 24
3.9.1 ICG Frequency Specifications . . . . . . . . . . . . . 25
3.10 AC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.1 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.10.2 Timer/PWM (TPM) Module Timing. . . . . . . . . . 28
3.11 SPI Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.12 FLASH Specifications . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.13 EMC Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.13.1 Radiated Emissions . . . . . . . . . . . . . . . . . . . . . 34
Electrical Characteristics and Timing Specifications . . . . . . .11
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.2 Parameter Classification . . . . . . . . . . . . . . . . . . . . . . . .11
3.3 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . .11
3.4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . .13
3.5 ESD Protection and Latch-Up Immunity . . . . . . . . . . . .14
3.6 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.7 Supply Current Characteristics . . . . . . . . . . . . . . . . . . .18
3.8 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Chapter 4
Ordering Information and Mechanical Drawings . . . . . . . . . . 35
4.1 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . 35
4.2 Orderable Part Numbering System . . . . . . . . . . . . . . . 35
4.3 Mechanical Drawings. . . . . . . . . . . . . . . . . . . . . . . . . . 35
Chapter 5
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Related Documentation
MC9S08AC128 Series Reference Manual (MC9S08AC128RM)
contains extensive product information including modes of operartion, memory, resets and interrupts, reg-
ister definitions, port pins, CPU, and all peripheral module information.
For the latest version of the documentation, check our website at:
http://www.freescale.com
MC9S08AC128 MCU Series Data Sheet, Rev. 4
2
Freescale Semiconductor
Chapter 1
Device Overview
The MC9S08AC128 is a member of the low-cost, high-performance HCS08 Family of 8-bit
microcontroller units (MCUs). The MC9S08AC128 uses the enhanced HCS08 core.
1.1
MCU Block Diagram
The block diagram in Figure 1-1 shows the structure of the MC9S08AC128 Series MCU.
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
3
Chapter 1 Device Overview
HCS08 CORE
DEBUG
PTA7
MODULE (DBG)
PTA6
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
BDC
CPU
BKGD/MS
CYCLIC REDUNDANCY
CHECK MODULE (CRC)
HCS08 SYSTEM CONTROL
INTERNAL CLOCK
GENERATOR (ICG)
RESET
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
RESETS AND INTERRUPTS
MODES OF OPERATION
POWER MANAGEMENT
EXTAL
XTAL
LOW-POWER OSC
RQ/TPMCLK
RTI
COP
LVD
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
8-BIT KEYBOARD
INTERRUPT MODULE (KBI1)
KBI1P7–KBI1P0
AD1P15–AD1P0
IRQ
VDDAD
PTC6
PTC5/RxD2
PTC4
PTC3/TxD2
PTC2/MCLK
PTC1/SDA1
10-BIT
ANALOG-TO-DIGITAL
CONVERTER (ADC)
VSSAD
VREFL
VREFH
SCL
SDA
USERMEMORY
IIC MODULE (IIC1)
FLASH, RAM
(BYTES)
PTC0/SCL1
(AW128 = 128K, 8K)
(AW96 = 96K, 6K)
RXD1
TXD1
PTD7/KBI1P7/AD1P15
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI1)
PTD6/TPM1CLK/AD1P14
PTD5/AD1P13
PTD4/TPM2CLK/AD1P12
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
PTD1/AD1P9
VDD
VSS
VOLTAGE REGULATOR
RXD2
TXD2
SERIAL COMMUNICATIONS
INTERFACE MODULE (SCI2)
PTJ7
PTJ6
PTJ5
PTJ4
PTJ3
PTJ2
PTJ1
PTJ0
SPSCK1
MOSI1
PTD0/AD1P8
SERIAL PERIPHERAL
INTERFACE MODULE (SPI1)
PTE7/SPSCK1
MISO1
SS1
PTE6/MOSI1
PTE5/MISO1
PTE4/SS1
SPSCK2
MOSI2
SERIAL PERIPHERAL
INTERFACE MODULE (SPI2)
PTH6/MISO2
PTH5/MOSI2
MISO2
PTE3/TPM1CH1
PTE2/TPM1CH0
PTE1/RxD1
PTH4/SPSCK2
PTH3/TPM2CH5
PTH2/TPM2CH4
PTH1/TPM2CH3
PTH0/TPM2CH2
TPM1CLK or TPMCLK
TPM1CH0–TPM1CH5
6-CHANNEL TIMER/PWM
MODULE (TPM1)
PTE0/TxD1
PTF7
PTF6
TPM2CLK or TPMCLK
TPM2CH0–TPM2CH5
6-CHANNEL TIMER/PWM
MODULE (TPM2)
PTG6/EXTAL
PTG5/XTAL
PTF5/TPM2CH1
PTF4/TPM2CH0
PTF3/TPM1CH5
PTF2/TPM1CH4
PTF1/TPM1CH3
PTF0/TPM1CH2
PTG4/KBI1P4
PTG3/KBI1P3
PTG2/KBI1P2
PTG1/KBI1P1
PTG0/KBIP0
TPMCLK
TPM3CH1
TPM3CH0
2-CHANNEL TIMER/PWM
MODULE (TPM3)
- Pin not connected in 64-pin and 48-pin packages
- Pin not connected in 48-pin and 44-pin package
- Pin not connected in 44-pin package
Figure 1-1. MC9S08AC128 Series Block Diagram
MC9S08AC128 MCU Series Data Sheet, Rev. 4
4
Freescale Semiconductor
Chapter 2
Pins and Connections
This section describes signals that connect to package pins. It includes pinout diagrams, recommended
system connections, and detailed discussions of signals.
2.1
Device Pin Assignment
Figure 2-1 shows the 80-pin LQFP package pin assignments for the MC9S08AC128 Series device.
PTG3/KBI1P3
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
VSSAD
VDDAD
PTD1/AD1P9
PTD0/AD1P8
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTH3/TPM2CH5
PTH2/TPM2CH4
PTH1/TPM2CH3
PTH0/TPM2CH2
PTA7
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
1
2
3
4
5
6
7
8
PTC4
IRQ/TPMCLK
RESET
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
9
80-Pin
LQFP
10
11
12
13
14
15
16
17
18
19
20
PTF7
PTF5/TPM2CH1
PTF6
PTJ0
PTJ1
PTJ2
PTJ3
PTE0/TxD1
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
Note: Pin names in bold
are lost in lower pin count
packages.
Figure 2-1. MC9S08AC128 Series in 80-Pin LQFP Package
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
5
Chapter 2 Pins and Connections
Figure 2-2 shows the 64-pin package assignments for the MC9S08AC128 Series devices.
64
49
63 62 61 60 59 58 57 56 55 54 53 52 51 50
PTC4
PTG3/KBI1P3
48
1
PTD3/KBI1P6/AD1P11
47
46
45
IRQ/TPMCLK
RESET
2
3
4
5
6
7
8
9
PTD2KBI1P5/AD1P10
VSSAD
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF2/TPM1CH4
PTF3/TPM1CH5
PTF4/TPM2CH0
PTC6
44
43
42
41
40
39
38
37
VDDAD
PTD1/AD1P9
PTD0/AD1P8
PTB7/AD1P7
PTB6/AD1P6
PTB5/AD1P5
64-Pin QFP
PTF7
10
11
12
13
14
15
PTF5/TPM2CH1
PTB4/AD1P4
PTB3/AD1P3
PTB2/AD1P2
PTF6
PTE0/TxD1
36
35
34
PTE1/RxD1
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTA7
PTE2/TPM1CH0
PTE3/TPM1CH1
16
33
23 24 25 26 27 28 29 30 31
18 19 20 21 22
32
17
Note: Pin names in bold
are lost in lower pin count
packages.
Figure 2-2. MC9S08AC128 Series in 64-Pin QFP Package
MC9S08AC128 MCU Series Data Sheet, Rev. 4
6
Freescale Semiconductor
Chapter 2 Pins and Connections
Figure 2-1 shows the 48-pin package assignments for the MC9S08AC128 Series devices.
48
37
47 46 45 44 43 42 41 40 39 38
PTC4
PTG3/KBI1P3
1
36
PTD3/KBI1P6/AD1P11
PTD2KBI1P5/AD1P10
VSSAD
IRQ/TPMCLK
RESET
2
3
4
5
6
7
8
9
35
34
33
32
31
30
PTF0/TPM1CH2
PTF1/TPM1CH3
VDDAD
48-Pin QFN
PTF4/TPM2CH0
PTF5/TPM2CH1
PTF6
PTD1/AD1P9
PTD0/AD1P8
PTB3/AD1P3
PTB2/AD1P2
29
28
27
26
PTE0/TxD1
10
11
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
PTA7
PTE1/RxD1
PTE2/TPM1CH0
PTE3/TPM1CH1
25
12
19 20 21 22 23
14 15 16 17 18
24
13
Note: Pin names in bold
are lost in lower pin count
packages.
Figure 2-1. MC9S08AC128 Series in 48-Pin QFN Package
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
7
Chapter 2 Pins and Connections
Figure 2-3 shows the 44-pin LQFP pin assignments for the MC9S08AC128 Series device.
34
44
43 42 41 40 39 38 37 36 35
PTC4
1
PTG3/KBI1P3
PTD3/KBI1P6/AD1P11
PTD2/KBI1P5/AD1P10
VSSAD
33
IRQ/TPMCLK
RESET
2
3
4
5
6
7
8
9
32
31
30
29
PTF0/TPM1CH2
PTF1/TPM1CH3
PTF4/TPM2CH0
VDDAD
44-Pin LQFP
28
27
26
PTD1/AD1P9
PTD0/AD1P8
PTB3/AD1P3
PTB2/AD1P2
PTF5/TPM2CH1
PTE0/TxD1
PTE1/RxD1
25
24
PTE2/TPM1CH0
PTE3/TPM1CH1
10
PTB1/TPM3CH1/AD1P1
PTB0/TPM3CH0/AD1P0
11
23
18 19 20 21
13 14 15 16 17
22
12
Figure 2-3. MC9S08AC128 Series in 44-Pin LQFP Package
Table 2-4. Pin Availability by Package Pin-Count
Pin Number
Lowest <-- Priority --> Highest
80
64
48
44
Port Pin
Alt 1
Alt 2
1
2
1
2
1
2
1
2
PTC4
IRQ
TPMCLK1
3
3
3
3
RESET
PTF0
PTF1
PTF2
PTF3
PTF4
PTC6
PTF7
PTF5
PTF6
4
4
4
4
TPM1CH2
TPM1CH3
TPM1CH4
TPM1CH5
TPM2CH0
5
5
5
5
6
6
—
—
6
—
—
6
7
7
8
8
9
9
—
—
7
—
—
7
10
11
12
10
11
12
TPM2CH1
8
—
MC9S08AC128 MCU Series Data Sheet, Rev. 4
8
Freescale Semiconductor
Chapter 2 Pins and Connections
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80
64
48
44
Port Pin
Alt 1
Alt 2
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
—
—
—
—
13
14
15
16
17
18
19
20
21
22
—
—
—
—
23
24
25
26
27
28
29
30
31
32
33
—
—
—
—
34
35
36
37
38
39
40
41
—
—
—
—
9
—
—
—
—
8
PTJ0
PTJ1
PTJ2
PTJ3
PTE0
PTE1
PTE2
PTE3
PTE4
PTE5
PTE6
PTE7
VSS
TxD1
RxD1
10
11
12
13
14
15
16
17
18
—
—
—
—
19
20
21
22
23
24
—
—
—
—
25
—
—
—
—
26
27
28
29
—
—
—
—
9
10
11
12
13
14
15
16
17
—
—
—
—
18
19
20
21
22
—
—
—
—
—
—
—
—
—
—
23
24
25
26
—
—
—
—
TPM1CH0
TPM1CH1
SS1
MISO1
MOSI1
SPSCK1
VDD
PTJ4
PTJ5
PTJ6
PTJ7
PTG0
PTG1
PTG2
PTA0
PTA1
PTA2
PTA3
PTA4
PTA5
PTA6
PTA7
PTH0
PTH1
PTH2
PTH3
PTB0
PTB1
PTB2
PTB3
PTB4
PTB5
PTB6
PTB7
KBI1P0
KBI1P1
KBI1P2
TPM2CH2
TPM2CH3
TPM2CH4
TPM2CH5
TPM3CH0
TPM3CH1
AD1P2
AD1P0
AD1P1
AD1P3
AD1P4
AD1P5
AD1P6
AD1P7
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
9
Chapter 2 Pins and Connections
Table 2-4. Pin Availability by Package Pin-Count (continued)
Pin Number Lowest <-- Priority --> Highest
80
64
48
44
Port Pin
Alt 1
Alt 2
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
—
60
61
—
—
—
62
63
64
30
31
32
33
34
35
36
37
—
—
—
—
38
39
40
41
42
43
—
44
45
—
—
—
46
47
48
27
28
29
30
31
32
33
—
—
—
—
—
34
35
36
37
38
39
—
40
41
—
—
—
42
43
44
PTD0
PTD1
VDDAD
VSSAD
PTD2
PTD3
PTG3
PTG4
PTD4
PTD5
PTD6
PTD7
VREFH
VREFL
BKGD
PTG5
PTG6
VSS
AD1P8
AD1P9
KBI1P5
KBI1P6
KBI1P3
KBI1P4
AD1P10
AD1P11
TPM2CLK AD1P12
AD1P13
TPM1CLK AD1P14
KBI1P7
AD1P15
MS
XTAL
EXTAL
VDD(NC)
PTC0
PTC1
PTH4
PTH5
PTH6
PTC2
PTC3
PTC5
SCL1
SDA1
SPSCK2
MOSI2
MISO2
MCLK
TxD2
RxD2
1
TPMCLK, TPM1CLK, and TPM2CLK options are configured
via software; out of reset, TPM1CLK, TPM2CLK, and
TPMCLK are available to TPM1, TPM2, and TPM3
respectively.
MC9S08AC128 MCU Series Data Sheet, Rev. 4
10
Freescale Semiconductor
Chapter 3
Electrical Characteristics and Timing Specifications
3.1
Introduction
This section contains electrical and timing specifications.
3.2
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 3-1. Parameter Classifications
P
C
Those parameters are guaranteed during production testing on each individual device.
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
3.3
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in Table 3-2 may affect device reliability or cause permanent damage to the device. For functional operating
conditions, refer to the remaining tables in this section.
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either V or V ).
SS
DD
MC9S08AC128 Series Data Sheet, Rev. 4
Freescale Semiconductor
11
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-2. Absolute Maximum Ratings
Rating Symbol
Value
Unit
Supply voltage
Input voltage
V
–0.3 to + 5.8
V
V
DD
V
– 0.3 to VDD + 0.3
In
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
25
mA
Maximum current into V
Storage temperature
IDD
120
mA
DD
T
–55 to +150
C
stg
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2
3
All functional non-supply pins are internally clamped to VSS and VDD
.
Power supply must maintain regulation within operating VDD range during instantaneous and
operating maximum current conditions. If positive injection current (VIn > VDD) is greater than
IDD, the injection current may flow out of VDD and could result in external power supply going
out of regulation. Ensure external VDD load will shunt current greater than maximum injection
current. This will be the greatest risk when the MCU is not consuming power. Examples are: if
no system clock is present, or if the clock rate is very low which would reduce overall power
consumption.
MC9S08AC128 Series Data Sheet, Rev. 4
12
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
3.4
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take P into account in power calculations, determine the difference between
I/O
actual pin voltage and V or V and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
SS
DD
(heavy loads), the difference between pin voltage and V or V will be very small.
SS
DD
Table 3-3. Thermal Characteristics
Rating
Symbol
Value
Unit
C
TL to TH
–40 to 125
TA
TJ
Operating temperature range (packaged)
Maximum junction temperature
Thermal resistance 1,2,3,4
150
C
80-pin LQFP
64-pin QFP
48-pin QFN
44-pin LQFP
1s
2s2p
61
47
1s
2s2p
57
43
JA
C/W
1s
2s2p
81
28
1s
2s2p
73
56
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal
resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation
of other components on the board, and board thermal resistance.
2
3
4
Junction to Ambient Natural Convection
1s - Single Layer Board, one signal layer
2s2p - Four Layer Board, 2 signal and 2 power layers
The average chip-junction temperature (T ) in C can be obtained from:
J
T = T + (P
)
Eqn. 3-1
J
A
D
JA
where:
T = Ambient temperature, C
A
= Package thermal resistance, junction-to-ambient, C/W
JA
P = P P
D
int
I/O
P
P
= I V , Watts — chip internal power
int
I/O
DD DD
= Power dissipation on input and output pins — user determined
For most applications, P P and can be neglected. An approximate relationship between P and T (if P is neglected)
I/O
int
D
J
I/O
is:
P = K (T + 273C)
Eqn. 3-2
D
J
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
13
Chapter 3 Electrical Characteristics and Timing Specifications
Solving equations 1 and 2 for K gives:
2
K = P (T + 273C) + (P )
Eqn. 3-3
D
A
JA
D
where K is a constant pertaining to the particular part. K can be determined from equation 3 by measuring P (at equilibrium)
D
for a known T . Using this value of K, the values of P and T can be obtained by solving equations 1 and 2 iteratively for any
A
D
J
value of T .
A
3.5
ESD Protection and Latch-Up Immunity
Although damage from electrostatic discharge (ESD) is much less common on these devices than on early CMOS circuits,
normal handling precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure
that these devices can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with AEC-Q100 Stress Test Qualification for Automotive Grade Integrated Circuits and
JEDEC Standard for Non-Automotive Grade Integrated Circuits. During the device qualification ESD stresses were performed
for the Human Body Model (HBM), the Machine Model (MM) and the Charge Device Model (CDM).
A device is defined as a failure if after exposure to ESD pulses the device no longer meets the device specification. Complete
DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot
temperature, unless specified otherwise in the device specification.
Table 3-4. ESD and Latch-up Test Conditions
Model
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Human Body
Storage Capacitance
C
–
100
3
pF
Number of Pulse per pin
Series Resistance
R1
0
Machine
Latch-up
Storage Capacitance
C
–
200
3
pF
Number of Pulse per pin
Minimum input voltage limit
Maximum input voltage limit
– 2.5
7.5
V
V
Table 3-5. ESD and Latch-Up Protection Characteristics
Num C
Rating
Symbol
VHBM
VMM
Min
2000
200
500
100
Max
Unit
1
2
3
4
C Human Body Model (HBM)
–
–
–
–
V
V
C Machine Model (MM)
VCDM
ILAT
C Charge Device Model (CDM)
V
Latch-up Current at TA = 125C
C
mA
3.6
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
MC9S08AC128 Series Data Sheet, Rev. 4
14
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-6. DC Characteristics
Parameter Symbol
VDD
Num C
Min
Typ1
Max
Unit
1
2
— Operating Voltage
2.7
—
5.5
V
P Output high voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = –2 mA
VDD – 1.5
—
—
—
—
—
—
—
—
3 V, ILoad = –0.6 mA
VDD – 1.5
5 V, ILoad = –0.4 mA
3 V, ILoad = –0.24 mA
VDD – 0.8
VDD – 0.8
VOH
V
P Output high voltage — High Drive (PTxDSn = 1)
5 V, ILoad = –10 mA
V
DD – 1.5
—
—
—
—
—
—
—
—
3 V, ILoad = –3 mA
5 V, ILoad = –2 mA
3 V, ILoad = –0.4 mA
VDD – 1.5
VDD – 0.8
VDD – 0.8
3
P Output low voltage — Low Drive (PTxDSn = 0)
5 V, ILoad = 2 mA
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
3 V, ILoad = 0.6 mA
5 V, ILoad = 0.4 mA
3 V, ILoad = 0.24 mA
VOL
V
P Output low voltage — High Drive (PTxDSn = 1)
5 V, ILoad = 10 mA
—
—
—
—
—
—
—
—
1.5
1.5
0.8
0.8
3 V, ILoad = 3 mA
5 V, ILoad = 2 mA
3 V, ILoad = 0.4 mA
4
5
6
P Output high current — Max total IOH for all ports
5V IOHT
3V
—
—
—
—
100
60
mA
mA
P Output low current — Max total IOL for all ports
5V IOLT
3V
—
—
—
—
100
60
P Input high
2.7v VDD 4.5v
VIH
VIH
0.70xVDD
0.65xVDD
—
—
—
—
voltage; all
digital inputs
V
4.5v VDD 5.5v
7
8
9
P Input low voltage; all digital inputs
P Input hysteresis; all digital inputs
P Input leakage current; input only pins2
VIL
Vhys
|IIn|
—
—
0.35 x VDD
0.06 x VDD
mV
A
A
k
k
pF
V
—
—
0.1
0.1
45
1
1
10 P High Impedance (off-state) leakage current2
11 P Internal pullup resistors3
12 P Internal pulldown resistors4
13 C Input Capacitance; all non-supply pins
14 D RAM retention voltage
|IOZ|
RPU
RPD
20
20
—
65
65
8
45
CIn
—
VRAM
VPOR
tPOR
—
0.6
1.4
—
1.0
2.0
—
15 P POR rearm voltage
0.9
10
V
16 D POR rearm time
s
17 P Low-voltage detection threshold — high range
VDD falling VLVDH
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
V
V
Low-voltage detection threshold — low range
DD falling VLVDL
VDD rising
18
P
V
2.48
2.54
2.56
2.62
2.64
2.7
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
15
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-6. DC Characteristics (continued)
Num C
Parameter
Symbol
Min
Typ1
Max
Unit
Low-voltage warning threshold — high range
19
20
21
P
P
VDD falling VLVWH
VDD rising
4.2
4.3
4.3
4.4
4.4
4.5
V
Low-voltage warning threshold — low range
DD falling
DD rising
VLVWL
2.48
2.54
2.56
2.62
2.64
2.7
V
V
V
Low-voltage inhibit reset/recover hysteresis
P
5V Vhys
3V
—
—
100
60
—
—
mV
V
22 P Bandgap Voltage Reference5
VBG
1.170
1.200
1.230
1
2
3
4
5
Typical values are based on characterization data at 25C unless otherwise stated.
Measured with VIn = VDD or VSS
Measured with VIn = VSS
Measured with VIn = VDD
.
.
.
Factory trimmed at VDD = 3.0 V, Temperature = 25 C.
VDD–VOH (V)
Average of IOH
–6.0E-3
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
–40C
25C
125C
0
0.3
0.5
0.8
0.9
1.2
1.5
VSupply–VOH
Figure 3-1. Typical I (Low Drive) vs V –V at V = 3 V
OH
DD OH
DD
MC9S08AC128 Series Data Sheet, Rev. 4
16
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
VDD–VOH (V)
Average of IOH
–20.0E-3
–18.0E-3
–16.0E-3
–14.0E-3
–12.0E-3
–10.0E-3
–8.0E-3
–40C
25C
125C
–6.0E-3
–4.0E-3
–2.0E-3
000.0E-3
0
0.3
0.5
0.8
VSupply–VOH
0.9
1.2
1.5
Figure 3-2. Typical I (High Drive) vs V –V at V = 3 V
OH
DD OH
DD
Average of IOH
–7.0E-3
–40C
25C
–6.0E-3
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
125C
–1.0E-3
000E+0
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VDD–VOH (V)
VSupply–VOH
Figure 3-3. Typical I (Low Drive) vs V –V at V = 5 V
OH
DD OH
DD
VDD–VOH (V)
Average of IOH
–30.0E-3
–25.0E-3
–40C
25C
–20.0E-3
–15.0E-3
–10.0E-3
–5.0E-3
125C
000.0E+3
0.00
0.30
0.50
0.80
1.00
1.30
2.00
VSupply–VOH
Figure 3-4. Typical I (High Drive) vs V –V at V = 5 V
OH
DD OH
DD
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
17
Chapter 3 Electrical Characteristics and Timing Specifications
3.7
Supply Current Characteristics
Table 3-7. Supply Current Characteristics
VDD
(V)
Temp
(C)
Typ1
Num
C
Parameter
Symbol
Max
Unit
5
3
1.1
1.0
1.43
1.2
Run supply current2 measured at
(CPU clock = 2 MHz, fBus = 1 MHz)
1
C
RIDD
mA
–40 to 125C
–40 to 125C
5
3
6.7
6
8.05
7.5
Run supply current4 measured at
(CPU clock = 16 MHz, fBus = 8 MHz)
2
3
C
C
RIDD
mA
25
160
–40 to 85C
–40 to 125C
Stop2 mode supply current
5
3
A
A
A
A
nA
nA
A
A
1.0
0.8
1.2
23
150
–40 to 85C
–40 to 125C
S2IDD
S3IDD
27
–40 to 85C
–40 to 125C
5
1803
Stop3 mode supply current
4
5
C
C
25
170
–40 to 85C
–40 to 125C
3
1.0
500
500
–40 to 85C
–40 to 125C
5
300
RTI adder to stop2 or stop36
S23IDDRTI
500
500
–40 to 85C
–40 to 125C
3
300
110
90
180
180
–40 to 85C
–40 to 125C
5
6
7
C
C
LVD adder to stop3 (LVDE = LVDSE = 1)
S3IDDLVD
160
160
–40 to 85C
–40 to 125C
3
Adder to stop3 for oscillator enabled7
(OSCSTEN =1)
–40 to 85C
–40 to 125C
8
8
A
A
5,3
5
S3IDDOSC
1
Typical values are based on characterization data at 25C unless otherwise stated. See Figure 3-5 through Figure 3-7 for
typical curves across voltage/temperature.
2
3
4
5
6
All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
All modules except ADC active, ICG configured for FBE, and does not include any dc loads on port pins
Every unit tested to this parameter. All other values in the Max column are guaranteed by characterization.
Most customers are expected to find that auto-wakeup from stop2 or stop3 can be used instead of the higher current wait
mode. Wait mode typical is 560 A at 3 V with fBus = 1 MHz.
Values given under the following conditions: low range operation (RANGE = 0) with a 32.768kHz crystal, low power mode
(HGO = 0), clock monitor disabled (LOCD = 1).
7
MC9S08AC128 Series Data Sheet, Rev. 4
18
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
18
16
20 MHz, ADC off, FEE, 25C
20 MHz, ADC off, FBE, 25C
14
12
10
8
IDD
8 MHz, ADC off, FEE, 25C
8 MHz, ADC off, FBE, 25C
6
4
1 MHz, ADC off, FEE, 25C
1 MHz, ADC off, FBE, 25C
2
0
3.4
3.8
5.0
5.4
2.2
2.6
3.0
4.2
4.6
VDD
Note: External clock is square wave supplied by function generator. For FEE mode, external reference frequency is 4 MHz
Figure 3-5. Typical Run I for FBE and FEE Modes, I vs. V
DD
DD
DD
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
19
Chapter 3 Electrical Characteristics and Timing Specifications
–40C
25C
55C
85C
Stop2 IDD (A)
Average of Measurement IDD
–8.0E-3
–7.0E-3
–6.0E-3
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
1.8
2
2.5
3
3.5
4
4.5
5
VDD (V)
Figure 3-6. Typical Stop 2 I
DD
–40C
25C
55C
85C
Stop3 IDD (A)
Average of Measurement IDD
–8.0E-3
–7.0E-3
–6.0E-3
–5.0E-3
–4.0E-3
–3.0E-3
–2.0E-3
–1.0E-3
000E+0
1.8
2
2.5
3
3.5
4
4.5
5
VDD (V)
Figure 3-7. Typical Stop3 I
DD
MC9S08AC128 Series Data Sheet, Rev. 4
20
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
3.8
ADC Characteristics
Table 3-8. 5 Volt 10-bit ADC Operating Conditions
Characteristic
Conditions
Symb
Min
Typ1
Max
Unit
Absolute
Delta to VDD (VDD–VDDAD
VDDAD
VDDAD
VSSAD
VREFH
2.7
–100
–100
2.7
—
5.5
V
mV
mV
V
Supply voltage
2
)
0
0
+100
+100
VDDAD
2
Ground voltage
Ref voltage high
Delta to VSS (VSS–VSSAD
Stop, reset, module off
)
VDDAD
VREFL
VSSAD
VSSAD
VSSAD
V
Ref voltage low
Supply current
Input voltage
IDDAD
VADIN
CADIN
RADIN
—
VREFL
—
0.011
—
1
VREFH
5.5
A
V
Input capacitance
Input resistance
4.5
3
pF
k
—
5
10-bit mode
fADCK > 4MHz
fADCK < 4MHz
—
—
—
—
5
10
Analog source resistance
External to MCU
RAS
k
8-bit mode (all valid fADCK
High speed (ADLPC = 0)
Low power (ADLPC = 1)
–40C to 25C
)
—
—
—
10
8.0
4.0
—
0.4
0.4
ADC conversion clock frequency
fADCK
MHz
—
3.266
3.638
Temp Sensor
Slope
mV/
C
m
—
25C to 125C
—
Temp Sensor
Voltage
25C
VTEMP25
1.396
—
V
—
1
2
Typical values assume VDDAD = 5.0 V, Temp = 25C, fADCK = 1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
dc potential difference.
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
21
Chapter 3 Electrical Characteristics and Timing Specifications
SIMPLIFIED
INPUT PIN EQUIVALENT
CIRCUIT
ZADIN
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
Pad
ZAS
leakage
due to
input
ADC SAR
ENGINE
RAS
RADIN
protection
+
VADIN
–
CAS
VAS
+
–
RADIN
RADIN
RADIN
INPUT PIN
INPUT PIN
INPUT PIN
CADIN
Figure 3-8. ADC Input Impedance Equivalency Diagram
MC9S08AC128 Series Data Sheet, Rev. 4
22
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-9. 5 Volt 10-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
DDAD REFL
Characteristic
Supply current
ADLPC = 1
ADLSMP = 1
ADCO = 1
Conditions
C
Symb
Min
Typ1
Max
Unit
T
IDDAD
—
133
218
327
—
A
Supply current
ADLPC = 1
ADLSMP = 0
ADCO = 1
T
T
IDDAD
IDDAD
IDDAD
—
—
—
—
A
A
Supply current
ADLPC = 0
ADLSMP = 1
ADCO = 1
Supply current
ADLPC = 0
ADLSMP = 0
ADCO = 1
T
P
—
—
582
—
—
1
A
mA
V
DDAD < 5.5 V
High speed (ADLPC = 0)
Low power (ADLPC = 1)
Short sample (ADLSMP = 0)
fADACK
2
1.25
—
3.3
2
5
MHz
P
ADC asynchronous clock source
tADACK = 1/fADACK
3.3
—
—
Conversion time
(Including sample time)
P
tADC
20
40
ADCK
cycles
—
Long sample (ADLSMP = 1)
Short sample (ADLSMP = 0)
Long sample (ADLSMP = 1)
10-bit mode
P
P
P
tADS
ETUE
DNL
—
—
—
—
—
—
3.5
23.5
1
—
ADCK
cycles
Sample time
—
2.5
1.0
1.0
0.5
LSB2
LSB2
Total unadjusted error
Includes quantization
8-bit mode
0.5
0.5
0.3
10-bit mode
Differential non-linearity
Integral non-linearity
8-bit mode
Monotonicity and no-missing-codes guaranteed
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
10-bit mode
8-bit mode
C
INL
EZS
EFS
EQ
—
—
—
—
—
—
—
—
0.5
0.3
0.5
0.5
0.5
0.5
—
1.0
0.5
1.5
0.5
1.5
0.5
0.5
0.5
LSB2
LSB2
LSB2
LSB2
P
Zero-scale error
VADIN = VSSA
P
Full-scale error
VADIN = VDDA
D
Quantization error
—
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
23
Chapter 3 Electrical Characteristics and Timing Specifications
Table 3-9. 5 Volt 10-bit ADC Characteristics (V
= V
, V
= V
)
SSAD
REFH
DDAD REFL
Characteristic
Conditions
C
Symb
Min
Typ1
Max
Unit
10-bit mode
8-bit mode
D
EIL
—
—
0.2
0.1
2.5
1
LSB2
Input leakage error
Pad leakage3 * RAS
1
Typical values assume VDDAD = 5.0V, Temp = 25C, fADCK=1.0 MHz unless otherwise stated. Typical values are for reference
only and are not tested in production.
2
3
1 LSB = (VREFH – VREFL)/2N
Based on input pad leakage current. Refer to pad electricals.
3.9
Internal Clock Generation Module Characteristics
ICG
EXTAL
XTAL
RS
RF
Crystal or Resonator
C1
C2
Table 3-10. ICG DC Electrical Specifications (Temperature Range = –40 to 125C Ambient)
Characteristic
Symbol
Min
Typ1
Max
Unit
C1
C2
Load capacitors
See Note 2
Feedback resistor
Low range (32k to 100 kHz)
High range (1M – 16 MHz)
RF
10
1
M
M
Series resistor
Low range
Low Gain (HGO = 0)
High Gain (HGO = 1)
High range
—
—
0
100
—
—
RS
k
Low Gain (HGO = 0)
High Gain (HGO = 1)
8 MHz
—
0
—
—
—
—
0
10
20
—
—
—
4 MHz
MHz
1
2
Typical values are based on characterization data at VDD = 5.0V, 25C or is typical recommended value.
See crystal or resonator manufacturer’s recommendation.
MC9S08AC128 Series Data Sheet, Rev. 4
24
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
3.9.1
ICG Frequency Specifications
Table 3-11. ICG Frequency Specifications
(min) to V (max), Temperature Range = –40 to 125C Ambient)
(V
= V
DDA
DDA
DDA
Num
C
Characteristic
Symbol
Min
Typ1
Max
Unit
Oscillator crystal or resonator (REFS = 1)
(Fundamental mode crystal or ceramic resonator)
Low range
flo
32
—
100
kHz
High range
1
High Gain, FBE (HGO = 1,CLKS = 10)
High Gain, FEE (HGO = 1,CLKS = 11)
Low Power, FBE (HGO = 0, CLKS = 10)
Low Power, FEE (HGO = 0, CLKS = 11)
fhi_byp
fhi_eng
flp_byp
flp_eng
1
2
1
2
—
—
16
10
8
MHz
MHz
MHz
MHz
8
Input clock frequency (CLKS = 11, REFS = 0)
flo
fhi_eng
Low range
High range
2
32
2
—
—
100
10
kHz
MHz
fExtal
fICGIRCLK
tdc
3
4
5
0
182.25
40
—
243
—
40
303.75
60
MHz
kHz
%
Input clock frequency (CLKS = 10, REFS = 0)
Internal reference frequency (untrimmed)
Duty cycle of input clock (REFS = 0)
Output clock ICGOUT frequency
CLKS = 10, REFS = 0
All other cases
fExtal (max)
fICGDCLKmax
max)
fExtal (min)
flo (min)
fICGOUT
6
—
—
(
MHz
fICGDCLKmin
fICGDCLKmax
fSelf
7
8
Minimum DCO clock (ICGDCLK) frequency
Maximum DCO clock (ICGDCLK) frequency
Self-clock mode (ICGOUT) frequency 2
Self-clock mode reset (ICGOUT) frequency
3
—
—
MHz
MHz
MHz
MHz
40
fICGDCLKmin
5.5
fICGDCLKmax
10.5
9
fSelf_reset
10
8
Loss of reference frequency 3
Low range
High range
Loss of DCO frequency 4
Crystal start-up time 5, 6
Low range
High range
FLL lock time , 7
fLOR
fLOD
11
12
13
5
50
25
500
kHz
0.5
1.5
MHz
t
CSTL
—
—
430
4
—
—
t
ms
ms
CSTH
tLockl
tLockh
14
Low range
High range
—
—
2
2
nUnlock
nLock
15
16
FLL frequency unlock range
–4*N
–2*N
4*N
2*N
counts
counts
FLL frequency lock range
ICGOUT period jitter, , 8 measured at fICGOUT Max
Long term jitter (averaged over 2 ms interval)
CJitter
17
% fICG
—
0.2
Internal oscillator deviation from trimmed
frequency9
0.5
0.5
18
—
—
2
2
ACCint
VDD = 2.7 – 5.5 V, (constant temperature)
VDD = 5.0 V 10%, –40 C to 125C
%
1
2
Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
Self-clocked mode frequency is the frequency that the DCO generates when the FLL is open-loop.
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
25
Chapter 3 Electrical Characteristics and Timing Specifications
3
4
Loss of reference frequency is the reference frequency detected internally, which transitions the ICG into self-clocked mode if it
is not in the desired range.
Loss of DCO frequency is the DCO frequency detected internally, which transitions the ICG into FLL bypassed external mode (if
an external reference exists) if it is not in the desired range.
5
6
7
This parameter is characterized before qualification rather than 100% tested.
Proper PC board layout procedures must be followed to achieve specifications.
This specification applies to the period of time required for the FLL to lock after entering FLL engaged internal or external modes.
If a crystal/resonator is being used as the reference, this specification assumes it is already running.
8
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fICGOUT
.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. Noise
injected into the FLL circuitry via VDDA and VSSA and variation in crystal oscillator frequency increase the CJitter percentage for
a given interval.
9
See Figure 3-9
Average of Percentage Error
Variable
3 V
5 V
Figure 3-9. Internal Oscillator Deviation from Trimmed Frequency
MC9S08AC128 Series Data Sheet, Rev. 4
26
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
3.10 AC Characteristics
This section describes ac timing characteristics for each peripheral system.
3.10.1 Control Timing
Table 3-12. Control Timing
Num
C
Parameter
Bus frequency (tcyc = 1/fBus
Symbol
fBus
Min
dc
Typ1
Max
20
Unit
MHz
s
1
2
)
—
tRTI
Real-time interrupt internal oscillator period
External reset pulse width2
600
1500
1.5 x
tSelf_reset
textrst
—
ns
(tcyc = 1/fSelf_reset
)
Reset low drive3
4
trstdrv
tMSSU
tMSH
34 x tcyc
25
—
—
—
ns
ns
ns
5
Active background debug mode latch setup time
Active background debug mode latch hold time
6
25
IRQ pulse width
7
Asynchronous path2
Synchronous path4
tILIH, IHIL
t
100
1.5 x tcyc
—
—
—
—
ns
ns
ns
8
KBIPx pulse width
Asynchronous path2
Synchronous path3
tILIH, IHIL
t
100
1.5 x tcyc
Port rise and fall time (load = 50 pF)5
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise, tFall
9
—
—
3
30
1
2
Typical values are based on characterization data at VDD = 5.0V, 25C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed to
override reset requests from internal sources.
3
4
5
When any reset is initiated, internal circuitry drives the reset pin low for about 34 bus cycles and then samples the level on
the reset pin about 38 bus cycles later to distinguish external reset requests from internal requests.
This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40C to 125C.
textrst
RESET PIN
Figure 3-10. Reset Timing
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
27
Chapter 3 Electrical Characteristics and Timing Specifications
BKGD/MS
RESET
tMSH
tMSSU
Figure 3-11. Active Background Debug Mode Latch Timing
tIHIL
IRQ/KBIP7-KBIP4
IRQ/KBIPx
tILIH
Figure 3-12. IRQ/KBIPx Timing
3.10.2 Timer/PWM (TPM) Module Timing
Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 3-13. TPM Input Timing
Function
External clock frequency
External clock period
Symbol
fTPMext
tTPMext
tclkh
Min
dc
Max
Unit
fBus/4
MHz
tcyc
tcyc
tcyc
tcyc
4
—
External clock high time
External clock low time
Input capture pulse width
1.5
1.5
1.5
—
tclkl
—
tICPW
—
MC9S08AC128 Series Data Sheet, Rev. 4
28
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
tTPMext
tclkh
TPMxCLK
tclkl
Figure 3-13. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 3-14. Timer Input Capture Pulse
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
29
Chapter 3 Electrical Characteristics and Timing Specifications
3.11 SPI Characteristics
Table 3-14 and Figure 3-15 through Figure 3-18 describe the timing requirements for the SPI system.
Table 3-14. SPI Electrical Characteristic
Num1
C
Characteristic2
Symbol
Min
Max
Unit
Operating frequency3
Hz
f
/2048
dc
f
f
/2
/4
Master
Slave
f
Bus
Bus
Bus
op
f
op
1
2
Cycle time
2
4
2048
—
tcyc
tcyc
Master
Slave
tSCK
tSCK
Enable lead time
Enable lag time
—
1/2
Master
Slave
t
t
1/2
—
t
t
Lead
Lead
SCK
SCK
3
—
1/2
Master
Slave
t
t
1/2
—
t
t
Lag
Lag
SCK
SCK
4
5
6
Clock (SPSCK) high time
Master and Slave
1/2 tSCK – 25
1/2 tSCK – 25
—
—
ns
ns
t
SCKH
Clock (SPSCK) low time Master
and Slave
t
SCKL
Data setup time (inputs)
30
30
—
—
ns
ns
Master
Slave
t
t
SI(M)
SI(S)
7
Data hold time (inputs)
30
30
—
—
ns
ns
Master
Slave
t
t
HI(M)
HI(S)
Access time, slave4
Disable time, slave5
8
9
0
40
40
ns
ns
t
A
—
t
dis
10
Data setup time (outputs)
25
25
—
—
ns
ns
Master
Slave
t
t
SO
SO
11
Data hold time (outputs)
–10
–10
—
—
ns
ns
Master
Slave
t
t
HO
HO
1
2
Refer to Figure 3-15 through Figure 3-18.
All timing is shown with respect to 20% V
and 70% V , unless noted; 100 pF load on all SPI
DD
DD
pins. All timing assumes slew rate control disabled and high drive strength enabled for SPI output
pins.
3
4
5
Maximum baud rate must be limited to 5 MHz due to pad input characteristics.
Time to data active from high-impedance state.
Hold time to high-impedance state.
MC9S08AC128 Series Data Sheet, Rev. 4
30
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
SS1
(OUTPUT)
1
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
4
5
SCK
(CPOL = 1)
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN2
10
BIT 6 . . . 1
10
BIT 6 . . . 1
LSB IN
11
MOSI
(OUTPUT)
MSB OUT2
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-15. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
1
2
3
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
5
4
(OUTPUT)
6
7
MISO
(INPUT)
MSB IN(2)
BIT 6 . . . 1
11
BIT 6 . . . 1
LSB IN
10
MOSI
(OUTPUT)
MSB OUT(2)
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 3-16. SPI Master Timing (CPHA = 1)
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
31
Chapter 3 Electrical Characteristics and Timing Specifications
SS
(INPUT)
3
1
SCK
(CPOL = 0)
5
4
5
(INPUT)
2
SCK
(CPOL = 1)
4
(INPUT)
9
8
11
10
MISO
(OUTPUT)
SEE
NOTE
BIT 6 . . . 1
BIT 6 . . . 1
SLAVE LSB OUT
MSB OUT
7
SLAVE
6
MOSI
(INPUT)
MSB IN
LSB IN
NOTE:
1. Not defined but normally MSB of character just received
Figure 3-17. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
1
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
5
4
(INPUT)
10
11
9
MISO
(OUTPUT)
SEE
BIT 6 . . . 1
SLAVE LSB OUT
LSB IN
SLAVE MSB OUT
NOTE
6
7
8
MOSI
(INPUT)
MSB IN
BIT 6 . . . 1
NOTE:
1. Not defined but normally LSB of character just received
Figure 3-18. SPI Slave Timing (CPHA = 1)
MC9S08AC128 Series Data Sheet, Rev. 4
32
Freescale Semiconductor
Chapter 3 Electrical Characteristics and Timing Specifications
3.12 FLASH Specifications
This section provides details about program/erase times and program-erase endurance for the Flash memory.
Program and erase operations do not require any special power sources other than the normal V supply.
DD
Table 3-15. Flash Characteristics
Num
C
P
P
P
P
P
Characteristic
Symbol
Vprog/erase
VRead
fFCLK
Min
2.7
2.7
150
5
Typ1
Max
5.5
Unit
1
2
4
5
6
Supply voltage for program/erase
Supply voltage for read operation
V
5.5
V
Internal FCLK frequency2
200
6.67
kHz
s
tFcyc
Internal FCLK period (1/FCLK)
Byte program time (random location)(2)
Byte program time (burst mode)(2)
Page erase time3
tprog
tFcyc
tFcyc
tFcyc
tFcyc
9
4
C
tBurst
tPage
7
P
4000
Mass erase time(2)
8
P
tMass
20,000
Program/erase endurance4
9
C
C
10,000
—
—
100,000
—
—
cycles
years
TL to TH = –40C to + 125C
T = 25C
Data retention5
tD_ret
10
15
100
—
1
2
3
Typical values are based on characterization data at VDD = 5.0 V, 25C unless otherwise stated.
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information
supplied for calculating approximate time to program and erase.
4
5
Typical endurance for Flash was evaluated for this product family on the 9S12Dx64. For additional information on
how Freescale Semiconductor defines typical endurance, please refer to Engineering Bulletin EB619/D, Typical
Endurance for Nonvolatile Memory.
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and
de-rated to 25C using the Arrhenius equation. For additional information on how Freescale Semiconductor defines
typical data retention, please refer to Engineering Bulletin EB618/D, Typical Data Retention for Nonvolatile Memory.
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
33
Chapter 3 Electrical Characteristics and Timing Specifications
3.13 EMC Performance
Electromagnetic compatibility (EMC) performance is highly dependant on the environment in which the MCU resides. Board
design and layout, circuit topology choices, location and characteristics of external components as well as MCU software
operation all play a significant role in EMC performance. The system designer should consult Freescale applications notes such
as AN2321, AN1050, AN1263, AN2764, and AN1259 for advice and guidance specifically targeted at optimizing EMC
performance.
3.13.1 Radiated Emissions
Microcontroller radiated RF emissions are measured from 150 kHz to 1 GHz using the TEM/GTEM Cell method in accordance
with the IEC 61967-2 and SAE J1752/3 standards. The measurement is performed with the microcontroller installed on a
custom EMC evaluation board while running specialized EMC test software. The radiated emissions from the microcontroller
are measured in a TEM cell in two package orientations (North and East). For more detailed information concerning the
evaluation results, conditions and setup, please refer to the EMC Evaluation Report for this device.
The maximum radiated RF emissions of the tested configuration in all orientations are less than or equal to the reported
emissions levels.
Table 3-16. Radiated Emissions
Level1
Parameter
Symbol
Conditions
Frequency
fOSC/fBUS
Unit
(Max)
VRE_TEM
VDD = 5.0 V
TA = +25oC
package type
80 LQFP
0.15 – 50 MHz
50 – 150 MHz
150 – 500 MHz
500 – 1000 MHz
IEC Level
32kHz crystal
20MHz Bus
30
32
19
7
dBV
Radiated emissions,
electric field and magnetic field
I2
—
—
SAE Level
I2
1
Data based on laboratory test results.
2
IEC and SAE Level Maximums: I=36 dBuV.
MC9S08AC128 Series Data Sheet, Rev. 4
34
Freescale Semiconductor
Chapter 4
Ordering Information and Mechanical Drawings
4.1
Ordering Information
This section contains ordering numbers for MC9S08AC128 Series devices. See below for an example of the device numbering
system.
Table 4-1. Device Numbering System
Memory
Available Packages1
Type
Device Number
FLASH
RAM
MC9S08AC128
MC9S08AC96
128K
96K
8K
6K
80 LQFP, 64 QFP, 48-QFN, 44-LQFP
80 LQFP, 64 QFP, 48-QFN, 44-LQFP
1
See Table 4-2 for package information.
4.2
4.3
Orderable Part Numbering System
128
MC 9 S08 AC
C XX E
Pb free indicator
Status
(MC = Fully Qualified)
Memory
Package designator (See Table 4-2)
Temperature range
(C = –40C to 85C)
(M = –40C to 125C)
(9 = FLASH-based)
Core
Family
Approximate memory size (in KB)
Mechanical Drawings
Table 4-2 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08AC128 Series Product Summary pages at http://www.freescale.com.
To view the latest drawing, either:
•
•
Click on the appropriate link in Table 4-2, or
Open a browser to the Freescale website (http://www.freescale.com), and enter the appropriate document number (from
Table 4-2) in the “Enter Keyword” search box at the top of the page.
®
Table 4-2. Package Information
Pin Count
Type
Designator
Document No.
80
64
48
44
LQFP
QFP
LK
FU
FT
FG
98ASS23237W
98ASB42844B
98ARH99048A
98ASS23225W
QFN
LQFP
MC9S08AC128 Series Data Sheet, Rev. 4
Freescale Semiconductor
35
Chapter 4 Ordering Information and Mechanical Drawings
MC9S08AC128 Series Data Sheet, Rev. 4
36
Freescale Semiconductor
Chapter 5
Revision History
To provide the most up-to-date information, the version of our documents on the World Wide Web will be
the most current. Your printed copy may be an earlier revision. To verify you have the latest information
available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Revision
Number
Revision
Date
Description of Changes
Initial release of a separate data sheet and reference manual. Removed PTH7,
clarified SPI as one full and one master-only, added missing RoHS logo, updated
back cover addresses, and incorporated general release edits and updates.
Added some finalized electrical characteristics.
1
2
9/2008
6/2009
Added the parameter “Bandgap Voltage Reference” in Table 3-6
Updated Section 3.13, “EMC Performance” and corrected Table 3-16.
Updated disclaimer page.
3
4
9/2010
8/2011
Added 48-pin QFN package information.
Updated the t
in the Table 3-12.
RTI
Updated the RI in the Table 3-7.
DD
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
37
MC9S08AC128 MCU Series Data Sheet, Rev. 4
Freescale Semiconductor
38
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MC9S08AC128, Rev. 4
08/2011
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