MCZ33810EKR2_技术文档

Document Number: MC33810

Rev. 10.0, 4/2011

Freescale Semiconductor

Technical Data

Automotive Engine Control IC

33810

The 33810 is an eight channel output driver IC intended for

automotive engine control applications. The IC consists of four

integrated low side drivers and four low side gate pre-drivers. The low

side drivers are suitable for driving fuel injectors, solenoids, lamps,

and relays. The four gate pre-drivers can function either as ignition

IGBT gate pre-drivers or as general purpose MOSFET gate pre-

drivers.

ENGINE CONTROL

When configured as ignition IGBT gate pre-drivers, additional

features are enabled such as spark duration, dwell time, and ignition

coil current sense. When configured as a general purpose gate pre-

driver, the 33810 provides external MOSFETs with short circuit

protection, inductive flyback protection and diagnostics. The device is

packaged in a 32 pin (0.65mm pitch) exposed pad SOIC.

EK SUFFIX (Pb-FREE)

98ASA10556D

32 PIN SOICW EP

Features

• Designed to operate over the range of 4.5V ≤ VPWR ≤ 36V

• Quad ignition IGBT or MOSFET gate pre-driver with Parallel/SPI

and/or PWM control

ORDERING INFORMATION

• Quad injector driver with Parallel/SPI control

• Interfaces directly to MCU using 3.3V/5.0V SPI protocol

• Injector driver current limit - 4.5A max.

Temperature

Package

Device

MCZ33810EK/R2

Range (T )

A

-40°C to 125°C

32 SOICW-EP

• Independent fault protection and diagnostics

• VPWR standby current 10μA max.

• Pb-free packaging designated by suffix code EK

V_BAT

VBAT

33810

V_BAT

VPWR

VDD

OUT0

OUT1

OUT2

OUT3

GND

FB0

V_DD

V_BAT

MCU

V_BAT

MOSI

SCLK

CS

SI

SCLK

CS

GD0

V_BAT

MISO

ETPU

GPIO

ETPU

SO

FB1

DIN0

DIN3

GIN0

GIN3

OUT EN

SPKDUR

NOMI

MAXI

GD1

FB2

GD2

FB3

GD3

RSP

RSN

Figure 1. MC33810 Simplified Application Diagram

Freescale Semiconductor, Inc. reserves the right to change the detail specifications,

as may be required, to permit improvements in the design of its products.

INTERNAL BLOCK DIAGRAM

VPWR

VDD

VPWR, VDD

V8.0 Analog

V2.5 Logic

V

DD

POR, Over-voltage

Under-voltage

~50 µA

CS

SI

LOGIC CONTROL

Oscillator

Bandgap

Bias

SCLK

OUTEN

~15 µA

SPI

INTERFACE

V2.5

OUT0

OUT1

OUT2

OUT3

Outputs 0 to 3

VOC1

V

DD

SO

Gate Control

DIN0

75 µA

Current Limit

Temperature Limit

Short/Open

PARALLEL

CONTROL

~50 µA

DIN1

DIN2

DIN3

+

–

R

S

~50 µA

lLimit

Exposed

Pad

PWM

CONTROLLER

+

–

SPI

NOMI,MAXI

DAC

SPARK DURATION

FB0

FB1

FB2

FB3

+

–

SPI

GIN0

GIN1

GIN2

GIN3

Open Secondary

~50 µA

+

100 µA

VOC

V

−

PWR

GPGD

Only

SPARK

DAC

~50 µA

Low V

Clamp

GPGD

Clamp

GATE DRIVE

CONTROL

GD0

GD1

GD2

GD3

~50 µA

VDD

+

NOMI

MAXI

–

DAC

~5 0µA

SPKDUR

RSP

RSN

+

–

DAC

NOMI

MAXI

Exposed Pad

GND

Figure 2. 33810 Simplified Internal Block Diagram

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

OUT2

FB2

GD2

MAXI

NOMI

RSN

OUT0

FB0

GD0

CS

SCLK

SI

SO

VDD

OUTEN

DIN0

DIN1

DIN2

DIN3

GD1

FB1

1

2

3

4

5

6

7

8

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

RSP

VPWR

GIN0

GIN1

GIN2

GIN3

SPKDUR

GD3

GND

9

10

11

12

13

14

15

16

FB3

OUT3

OUT1

Figure 3. 33810 Pin Connections

Table 1. 33810 Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.

Pin Number Pin Name Pin Function

Formal Name

Definition

The VDD input supply voltage determines the interface voltage levels

between the device and the MCU, and is used to supply power to the

Serial Out buffer (SO), SPKDUR buffer, MAXI, NOMI, and pull-up current

source for the Chip Select (CS).

8

VDD

Input

Digital Logic Supply

Voltage

The SI input pin is used to receive serial data from the MCU.

6

5

SI

Input

Serial Input Data

Serial Clock Input

The SCLK input pin is used to clock in and out the serial data on the SI

and SO pins, while being addressed by the CS.

SCLK

The Chip Select input pin is an active low signal sent by the MCU to

indicate that the device is being addressed. This input requires CMOS

logic levels and has an internal active pull-up current source.

4

7

CS

SO

Input

Chip Select

The SO output pin is used to transmit serial data from the device to the

MCU.

Output

Input

Serial Output Data

Active HIGH input control for injector outputs OUT0 - 3. The parallel input

data is logically OR’d with the corresponding SPI input data register

contents.

10, 11, 12, 13 DIN0,DIN1,

DIN2,DIN3

Driver Input 0, Driver

Input 1, Driver Input 2,

Driver Input 3

These pins are the active HIGH input control for IGBT/General Purpose

Gate Driver outputs 0 - 3. The parallel input data is logically OR'd with the

corresponding SPI input data register contents in General Purpose Mode

Only.

24, 23, 22, 21 GIN0,GIN1,

GIN2,GIN3

Input

Gate Driver Input 0

Gate Driver Input 1

Gate Driver Input 2

Gate Driver Input 3

This pin is the Spark Duration Output. This open drain output is low while

feedback inputs FB0 through FB3 are above the programmed spark

detection threshold.

20

SPKDUR

Output

Spark Duration Output

VPWR is the main voltage input for all internal analog bias circuitry.

25

VPWR

GND

Input

Analog Supply Voltage

Ground

The exposed pad is the only ground reference for analog, digital and

power ground connections. As such, it must be soldered directly to a low

impedance ground plane for both electrical and thermal considerations.

For more information about this package, please see application note

AN2409 on the Freescale Web site, www.freescale.com

Exposed Pad

Ground

(bottom of

package)

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Analog Integrated Circuit Device Data

Freescale Semiconductor

3

PIN CONNECTIONS

Table 1. 33810 Pin Definitions (continued)

A functional description of each pin can be found in the Functional Pin Description section beginning on page 15.

Pin Number Pin Name Pin Function

Formal Name

Definition

The Output Enable pin (OUTEN) is an active low input. When the OUTEN

pin is low, the device outputs are active. The outputs are disabled when

OUTEN is high.

9

OUTEN

MAXI

Input

Output Enable

This pin is the Maximum Ignition Coil Current output flag. This output is

asserted when the IGBT Collector-Emitter current exceeds the selected

level of the DAC. This signal also latches off the gate pre-drive outputs

when configured as a General Purpose Gate pre-Driver. The MAXI

current level is determined by the voltage drop across an external sense

resistor connected to pins RSP and RSN.

29

Output

Maximum Ignition Coil

Current

This pin is the Nominal Ignition Coil Current output flag. This output is

asserted when the IGBT Collector-Emitter current exceeds the level

selected by the DAC.

28

NOMI

Output

Nominal Ignition Coil

Current

In IGBT ignition gate pre-driver mode, these feedback inputs monitor the

IGBT's collector voltage to provide the spark duration timer control signal.

2, 15, 31, 18

3, 14, 30,19

FB0 - FB3

GD0 -GD3

Input

Feedback Voltage

Sense

IGBT/General Purpose Gate pre-driver outputs are controlled by GIN0 -

GIN3. Pull-up and pull-down current sources are used to provide a

controlled slew rate to an external IGBT or MOSFET connected as a low

side driver.

Output

Gate Drive Output

This pin is the Positive input of a current sense amplifier.

This pin is the Negative input of a current sense amplifier.

These pin are the Open drain low side injector driver outputs.

26

27

RSP

RSN

Input

Resistor Sense

Positive

Resistor Sense

Negative

1, 16, 32, 17 OUT0 -OUT3

Output

Low Side Injector

Driver Output

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

VPWR Supply Voltage⁽¹⁾

VDD Supply Voltage⁽¹⁾

V

-1.5 to 45

-0.3 to 7.0

-0.3 to VDD

V

PWR

DC

V

DD

SPI Interface and Logic Input Voltage (CS, SI, SO, SCLK, OUTEN,

DIN0 - DIN3, GIN0 - GIN3, SPKDUR, NOMI, MAXI, RSP,RSN)

V_IL

V_IH

IGBT/General Purpose Gate Pre-driver Drain Voltage (V_FB0to V_FB3

Injector Output Voltage (OUTx)

)

V_FB

-1.5 to 60

-0.3 to 10

100

V

DC

V

OUTX

General Purpose Gate Pre-driver Output Voltage (GDx)

V

GDx

Output Clamp Energy (OUT0 to OUT3)(Single Pulse)

T_JUNCTION= 150°C, I_OUT= 1.5 A

E

mJ

A

CLAMP

Output Clamp Energy (OUT0 to OUT3)(Continuous Pulse)

E

100

2.0

CLAMP

T_JUNCTION= 125°C, I_OUT= 1.0 A (Max Injector frequency is 70 Hz)

Output Continuous Current (OUT0 to OUT3)

T_JUNCTION= 150°C

I_OSSSS

Maximum Voltage for RSN and RSP inputs

Frequency of SPI Operation (VDD = 5.0 V)

V

-0.3 - VDD

6.0

V

DC

RSX

–

MHz

ESD Voltage^{(2), (3)}

V

V_ESD1

V_ESD2

V_ESD3

±2000

±200

±750

Human Body Model (HBM)

Machine Model (MM)

Charge Device Model (CDM)

THERMAL RATINGS

Operating Temperature

Ambient

°C

T_A

T_J

-40 to 125

-40 to 150

-40 to 125

Junction2

Case

T_C

Storage Temperature

T

-55 to 150

1.7

°C

W

STG

Power Dissipation (T = 25°C)

P

D

A

Peak Package flow Temperature During Solder Mounting

T_SOLDER

°C

DWB Suffix

EW Suffix

240

245

Thermal Resistance

Junction-to-Ambient

Junction- to-Lead

Junction-to-Flag

°C/W

R

75

8.0

1.2

JA

θJL

θJC

θ

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted.

Ratings

Symbol

Value

Unit

Notes

1. Exceeding these limits may cause malfunction or permanent damage to the device.

2. ESD data available upon request.

3. ESD testing is performed in accordance with the Human Body Model (HBM) (AEC-Q100-002), the Machine Model (MM) (AEC-Q100-

003), and the Charge Device Model (CDM), Robotic (AEC-Q100-011).

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT (VDD, VPWR)

Supply Voltage⁽⁴⁾

Fully Operational

Full Parameter Specification

V

4.5

6.0

–

36

32

V

(

)

PWR FO

Supply Current

I

mA

VPWR(ON)

All Outputs Disabled (Normal Mode)

–

10.0

14.0

Sleep State Supply Current (Must have V

V_PWR= 32 V

≤ 0.8 V for sleep state),

I

μA

DD

VPWR(SS)

–

15

39

1.5

4.0

200

–

30

42

V

Over-voltage Shutdown Threshold Voltage⁽⁵⁾

V_PWR(OV)

36.5

0.5

3.0

100

5.3

3.0

V

PWR

Over-voltage Shutdown Hysteresis Voltage

V

3.0

4.4

300

8.99

5.5

PWR(OV-HYS)

V_PWR(UV)

Under-voltage Shutdown Threshold Voltage⁽⁶⁾

Under-voltage Shutdown Hysteresis Voltage

Low Operating Voltage (Low-voltage reported via the SPI)⁽⁷⁾

V

V_PWR(UV-HYS)

V_PWR(LOV)

mV

V

VDD Supply Voltage

V

–

V

DD

VDD Supply Current

I

mA

VDD

Static Condition and does not include VDD current out of device

–

1.0

2.8

VDD Supply Under-voltage (Sleep State) Threshold Voltage⁽⁸⁾

INJECTOR DRIVER OUTPUTS (OUT 0:3)

Drain-to-Source ON Resistance

V

0.8

2.5

V

DD(UV)

R

Ω

DS(ON)

–

0.2

–

0.3

–

I

= 1.0 A, T = 125°C, VPWR = 13 V

OUT

J

= 1.0 A, T = 25°C, VPWR = 13 V

J

= 1.0 A, T = -40°C, VPWR = 13 V

–

J

Output Self Limiting Current

I

3.0

–

6.0

A

V

OUT(LIM)

Output Fault Detection Voltage Threshold⁽⁹⁾

Outputs Programmed OFF (Open Load)

Outputs Programmed ON (Short to Battery)

V

OUT(FLT-TH)

2.0

2.5

3.0

Output OFF Open Load Detection Current

I

μA

(OFF)OCO

V

= 18 V, Outputs Programmed OFF

40

20

75

115

DRAIN

= 32 V, Outputs Programmed OFF (-40°C)

Output ON Open Load Detection Current

I

mA

(ON)OCO

Current less then specification value considered open

100

200

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Analog Integrated Circuit Device Data

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

Notes

4. These parameters are guaranteed by design, but not production tested. Fully operational means driver outputs will toggle as expected

with input toggling. SPI is guaranteed to be operational when VPWR > 4.5 V. SPI may not report correctly when VPWR < 4.5 V.

5. Over-voltage thresholds minimum and maximum include hysteresis.

6. Under-voltage thresholds minimum and maximum include hysteresis.

7. Device is functional provided T_Jis less than 150°C. Some table parameters may be out of specification.

8. Device in Sleep State, returns from sleep state with power on reset.

9. Output fault detection thresholds with outputs programmed OFF. Output fault detect thresholds are the same for output open and shorts.

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

INJECTOR DRIVER OUTPUTS (OUT 0:3) (Continued)

Output Clamp Voltage 1

V

OC1

I

= 20 mA

48

53

58

D

Output Leakage Current

I

μA

OUT(LKG)

VDD = 5.0 V, V

DRAIN

= 24 V, Open Load Detection Current Disabled

–

20

3000

10

VDD = 5.0 V, V

= V_OC- 1.0 V, Open Load Detection Current Disabled

DRAIN

VDD = 0 V, V

= 24 V, Sleep State

DRAIN

Over-temperature Shutdown⁽¹⁰⁾

T

155

5.0

–

185

15

°C

LIM

Over-temperature Shutdown Hysteresis⁽¹⁰⁾

T

V

10

LIM(HYS)

IGNITION (IGBT) GATE DRIVER PARAMETERS (GD 0:3 FB0:3)

Gate Driver Output Voltage

I_GD= 500 μA

V

4.8

0

7.0

0.375

9.0

0.5

V

GS(ON)

GS(OFF)

I_GD= -500 μA

Sleep Mode Gate to Source Resistor

R

100

200

–

300

KΩ

μA

GS(PULLDOWN

)

Sleep Mode FBx pin Leakage Current

I

FBX(LKG)

VDD = 0 V, V

= 24 V,

–

1.0

FBx

Feedback Sense Current (FBx Input Current)

FBx = 32 V, Outputs Programmed OFF

I

μA

FBX(FLT-SNS)

1.0

Gate Drive Source Current (1 ≤ V

≤ 3)

I

650

500

780

–

950

μA

GD

GATEDRIVE

Gate Drive Turn Off Resistance

R

Ω

DS(ON)

1000

SOFT SHUTDOWN FUNCTION (VOLTAGES REFERENCED TO IGBT COLLECTOR)

Low Voltage Flyback Clamp

Driver Command Off, Soft Shutdown Enabled, GDx = 2.0 V

V

VPWR

+9.0

VPWR VPWR + 13

+11

V

LVC

Spark Duration Comparator Threshold (referenced to IC Ground Tab)

Rising Edge Relative to VPWR

V_TH-RISE

18

21

24

(11)

Spark Duration Comparator Threshold (referenced to IC Ground Tab)

V_TH-FALL

1.2

4.9

7.4

9.9

2.75

5.5

8.2

3.6

6.1

9.1

V

Falling Edge Relative to VPWR, Default = 5.5 V Assuming ideal external

10:1 voltage divider. Voltage measured at high end of divider, not at pin.

Tolerance of divider not included

11.00

12.1

Open Secondary Comparator Threshold (referenced from primary to

Rising Edge Relative to GND. No hysteresis with 10:1 voltage divider.

V_TH-RISE

V

11.5

-10

–

15.5

10

CURRENT SENSE COMPARATOR (RSP, RSN)

NOMI Trip Threshold Accuracy - Steady State Condition

NOMI_TRIPTA

%

3.0 A across 0.02 Ω (RSP - RSN = 60 mV)

10.75 A across 0.04 Ω (RSP - RSN = 430 mV)

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

Notes

10. This parameter is guaranteed by design, however is not production tested.

11. Assuming Ideal external 10:1 Voltage Divider. Tolerance of 10:1 Voltage Divider is not included. Voltage is measured on the High End

of Divider - not at the pin. 10:1 N.3.A 10:1 Voltage Divider is produced using two resistors with a 9:1 resistance ratio by the basic formula:

VOUT

VIN

R1

R1 + R2

----------------------

----------------- =

Where R2 = 9XR1

CURRENT SENSE COMPARATOR (RSP, RSN) (CONTINUED)

MAXI Trip Threshold Accuracy

7.5

%

Steady State Condition

6.0 A across 0.02 Ω (RSP - RSN = 120 mV)

21 A across 0.04 Ω (RSP - RSN = 840 mV)

MAXI

–

TRIPTA

-7.5

-35

MAXI Trip Point During Overlapping Dwell

–

+35

50

%

TRIPOD

Input Bias Current

RSP and RSN

I

µA

BIASRSX

-50

Comparator Hysteresis Voltage

NOMI

MAXI

NOMI

MAXII

40

–

70

% of VT

HYS

Input Voltage Range (Maximum voltage between RSN and RSP)⁽¹²⁾

VCMVR

VGND

0.0

–

2.0

0.3

V

CMVR

Ground Offset Voltage Range⁽¹²⁾

-0.3

OVR

Maximum offset between RSN pin and IC Ground (Exposed Pad)

GENERAL PURPOSE GATE DRIVER PARAMETERS (GD 0:3)

Gate Drive Sink and Source Current

I_GD

1.0

2.0

5

mA

Gate Drive Output Voltage

I_GD= 1.0 mA

V

4.8

0.0

7.0

0.2

9.0

0.5

V

GS(ON)

V

I_GD= -1.0 mA

GS(OFF)

Short to Battery Fault Detection Voltage Threshold

V

DS(FLT-TH)

V

= 5.0 V, Outputs Programmed ON

-35%

2.0

+35%

3.0

DD

Programmable from 0.5 to 3.0 V in 0.5 V increments. (Table 14)

Open Fault Detection Voltage Threshold (referenced to IC ground tab)

V

DS(FLT-TH)

V

= 5.0 V, Outputs Programmed OFF

2.5

DD

Output OFF Open Load Detection Current

FBx = 18 V, Outputs Programmed OFF

I

μA

FBX(FLT-SNS)

50

48

75

53

120

58

Output Clamp Voltage

V

OC

Driver Command Off, Clamp Enabled, V_GATE= 2.0 V

DIGITAL INTERFACE

Input Logic High-voltage Thresholds

Input Logic Low-voltage Thresholds

Input Logic-voltage Hysteresis

Input Logic Capacitance

V

0.7 x V_DD

GND - 0.3

100

–

V_DD+ 0.3

0.2 x V_DD

400

V

IH

V

IL

V

mV

pF

μA

HYS

C

–

20

IN

LOGIC_SS

Sleep Mode Input Logic Current

I

V

= 0 V

-10

–

10

DD

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Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

Input Logic Pull-down Current

0.8 to 5.0 V (DIN and GIN )

μA

I

30

50

100

X

LOGIC_PD

Notes

12. This parameter is guaranteed by design, however it is not production tested.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. Static Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where typical values reflect the parameter’s approx. average value with VPWR = 13 V, TA =

25°C.

Characteristic

DIGITAL INTERFACE (CONTINUED)

Symbol

Min

Typ

Max

Unit

Input Logic Pull-down Current

0.8 to 5.0 V (SI)

I

μA

SI_PD

5.0

-30

15

25

Input Logic Pull-up Current on OUT_EN

I

OUT_EN_PU

OUT_EN = 0.0 V, V

= 5.0 V

-50

-100

DD

OUT_EN Leakage Current to V_DD

OUT_EN = 5.0 V, V = 0 V

I

μA

OUT_EN(LKG)

–

5

–

50

25

DD

SCLK Pull-down Current

I

SCLK

V_SCLK= V

DD

15

Tri-state SO Output

0 to 5.0 V

I

μA

TRISO

-10

-50

–

10

50

CS Input Current

CS = V_DD

I

CS

CS Pull-up Current

CS = 0 V

I

μA

CS_PU

-30

-50

-100

CS Leakage Current to V_DD

CS = 5.0 V, V = 0 V

I

CS(LKG)

–

50

–

DD

SO Input Capacitance in Tri-state Mode

SO High State Output Voltage

C

20

pF

V

SO

V

SO_HIGH

I

= -1.0 mA

V

- 0.4

–

SO-HIGH

DD

SO Low State Output Voltage

= 1.0 mA

V

μA

V

SO_LOW

I

–

0.4

100

SO-LOW

NOMI, MAXI in V10 Mode Pull-down Current

NOMI, MAXI = 0.8 V V = 5.0 V

I

PD

30

70

,

DD

SPKDUR Output Voltage

V

SPKDUR_LO

I

= 1.0 mA

–

0.4

SPKDUR

Output Pull-up Current for SPKDUR

I

30

50

100

μA

SPKDUR_PV

NOMI, MAXI High State Output Voltage

V

I_HIGH

I

= -1.0 mA

V

- 0.4

–

NOMI-HIGH

MAXI-HIGH

DD

NOMI, MAXI Low State Output Voltage

V

I_LOW

I

= 250 µA

–

0.4

NOMI-LOW

MAXI-LOW

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR

= 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUT

Required Low State Duration on VPWR for Under-voltage Detect

t_UV

μs

V_PWR≤ 0.2 V

1.0

–

Required Low State Duration on VDD for Power On Reset

t

RESET

V_DD≤ 0.2 V

INJECTOR DRIVERS

Output ON Current Limit Fault Filter Timer (Short to Battery Fault)

Output ON Open Circuit Fault Filter Timer

Output Retry Timer

t

30

3.0

–

60

7.5

10

90

12

µs

ms

µs

SC

t_(ON)OC

t

15

REF

Output OFF Open Circuit Fault Filter Timer

Output Slew Rate (No faster than 1.5 μs from off to on and on to off)

t_(OFF)OC

100

400

t_SR(RISE)

V/μs

R

= 14 Ω, V_LOAD= 14 V

1.0

5.0

10

LOAD

Output Slew Rate

= 14 Ω, V_LOAD= 14 V

t_SR(FALL)

V/μs

µs

R

5.0

1.0

10

LOAD

Propagation Delay (Input Rising Edge OR CS to Output Falling Edge)

Input @ 50%V_DDto Output voltage 90% of V_LOAD

t_PHL

5.0

Propagation Delay (Input Falling Edge OR CS to Output Rising Edge)

Input @ 50%V_DDto Output voltage 10% of V_LOAD

t_PLH

1.0

5.0

µs

IGNITION & GENERAL PURPOSE GATE DRIVER PARAMETERS

Propagation Delay (GINx Input Rising Edge OR CS to Output Rising Edge)

t_PLH

0.2

1.0

µs

Input @ 50%V_DDto Output voltage 10% of V

GS(ON)

Propagation Delay (Input Falling Edge OR CS to Output Falling Edge)

t_PHL

Input @ 50%V_DDto Output voltage 90% of V

GS(ON)

IGNITION PARAMETERS

Open Secondary Fault Timer accuracy (uncalibrated)

Maximum Dwell Timer Accuracy (uncalibrated)

End of Spark Filter Accuracy (uncalibrated)⁽¹³⁾

Notes

-35

–

35

%

13. This parameter is guaranteed by design, however it is not production tested.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

12

ELECTRICAL CHARACTERISTICS

DYNAMIC ELECTRICAL CHARACTERISTICS

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions of 3.0 V ≤ VDD ≤ 5.5 V, 6.0 V ≤ VPWR ≤ 32 V, -40°C ≤ TC ≤ 125°C, and calibrated

timers, unless otherwise noted. Where applicable, typical values reflect the parameter’s approximate average value with VPWR

= 13 V, TA = 25°C.

Characteristic

Symbol

Min

Typ

Max

Unit

GENERAL PURPOSE GATE DRIVER PARAMETERS

Short to Battery Fault Detection Filter Timer Accuracy

VDD = High, Outputs Programmed ON

V

%

DS(flt-th)

Programmable from 30 µs to 960 µs in replicating increments

Tolerance of timer after using calibration command

Tolerance of timer before using calibration command

-10

-35

+10

+35

Output OFF Open Circuit Fault Filter Timer

VDD = 5.0 V, Outputs Off

t_(OFF)OC

µs

Tolerance of timer before using calibration command

100

400

PWM Frequency 10 Hz to 1.28 kHz Tolerance after using calibration

command

PWM

-10%

10%

FREQ

PWM Frequency 10 Hz to 1.28 kHz Tolerance before using calibration

command

-35%

35%

3.0

FREQ

Gate Driver Short Fault Duty Cycle

GD

1.0

%

SHRT_DC

SPI DIGITAL INTERFACE TIMING⁽¹⁴⁾

Falling Edge of CS to Rising Edge of SCLK

Required Setup Time

t

ns

LEAD

100

50

–

Falling Edge of SCLK to Rising Edge of CS

Required Setup Time

t

LAG

SI(SU)

SI to Rising Edge of SCLK

Required Setup Time

t

16

Rising Edge of SCLK to SI

Required Hold Time

t

SI(HOLD)

20

–

5.0

–

SI, CS, SCLK Signal Rise Time⁽¹⁵⁾

t

ns

µs

R(SI)

F(SI)

SI, CS, SCLK Signal Fall Time⁽¹⁶⁾

–

Time from Falling Edge of CS Low-impedance⁽¹⁷⁾

Time from Rising Edge off CS to SO High-impedance⁽¹⁸⁾

Time from Falling Edge of SCLK to SO Data Valid⁽¹⁹⁾

t

–

55

–

SO(EN)

t

–

SO(DIS)

t

–

25

–

VALID

t_STR

Sequential Transfer Rate

1.0

Time required between data transfers

DIGITAL INTERFACE

Calibrated Timer Accuracy

Un-calibrated Timer Accuracy

Notes

t

–

10

35

%

TIMER

t

14. These parameters are guaranteed by design. Production test equipment uses 1.0 MHz, 5.0 V SPI interface.

15. This parameter is guaranteed by design, however it is not production tested.

16. Rise and Fall time of incoming SI, CS and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.

17. Time required for valid output status data to be available on SO pin.

18. Time required for output states data to be terminated at SO pin.

19. Time required to obtain valid data out from SO following the fall of SCLK with 200 pF load.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

ELECTRICAL CHARACTERISTICS

TIMING DIAGRAMS

CS

0.2 V

DD

t

LAG

LEAD

0.7 V

0.2 V

DD

SCLK

SI

t

SI(SU)

SI(HOLD)

0.7 V

0.2 V

DD

MSB IN

t_SO(EN)

0.7 V

t

VALID

SO(DIS)

DD

LSB OUT

SO

MSB OUT

0.2 V

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

14

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

ANALOG SUPPLY VOLTAGE (VPWR)

SERIAL INPUT DATA (SI)

The VPWR pin is the battery input to the 33810 IC. The

VPWR pin requires external reverse battery and transient

protection. All IC analog current and internal logic current is

provided from the VPWR pin. With VDD applied to the IC, the

application of VPWR will perform a POR.

The SI pin is used for serial instruction data input. SI

information is latched into the input register on the rising edge

of SCLK. A logic high state present on SI will program a one

in the command word on the rising edge of the CS signal. To

program a complete word, 16 bits of information or multiples

of 8 there of must be entered into the device.

DIGITAL LOGIC SUPPLY VOLTAGE (VDD)

SERIAL OUTPUT DATA (SO)

The VDD input pin is used to determine communication

logic levels between the microprocessor and the 33810 IC.

Current from VDD is used to drive SO output and the pull-up

current for CS. V_DDmust be applied for normal mode

operation. Removing V_DDfrom the IC will place the device in

sleep mode. With VPWR applied to the IC, the application of

V_DDwill perform a POR.

The SO pin is the output from the shift register. The SO pin

remains tri-stated until the CS pin transitions to a logic low

state. All normal operating drivers are reported as zero, all

faulted drivers are reported as one. The negative transition of

CS enables the SO driver.

The SI/SO shifting of the data follows a first-in-first-out

protocol, with both input and output words transferring the

most significant bit (MSB) first.

GROUND (GND)

The bottom pad or FLAG provides the only ground

connection for the IC. The VPWR and VDD supplies are both

referenced to the GND pad. The GND pad is used for both

de-coupling the power supplies as well as power ground for

the output drivers. Although the silicon die is epoxy attached

to the top side of the pad, the pad must be grounded for

proper electrical operation.

OUTPUT ENABLE (OUTEN)

The OUTEN pin is an active low input. When the OUTEN

pin is low, all the device outputs are active. The outputs are

all disabled when OUTEN pin is high. SPI and parallel

communications are still active in either state of OUTEN.

FEEDBACK VOLTAGE SENSOR (FB0-FB3)

SERIAL CLOCK INPUT (SCLK)

The FBx pin has multiple functions for control and

diagnostics of the external MOSFET/IGBT Ignition gate

driver.

The system clock (SCLK) pin clocks the internal shift

register of the 33810. The SI data is latched into the input

shift register on the rising edge of SCLK signal. The SO pin

shifts status bits out on the falling edge of SCLK. The SO data

is available for the MCU to read on the rising edge of SCLK.

With CS in a logic high state, signals on the SCLK and SI pins

will be ignored and the SO pin is tri-state

In Ignition (IGBT) Gate Driver Mode, the feedback inputs

monitor the IGBT's collector voltage to provide the spark

duration timer control signal. The spark duration timer

monitors this input to determine if the secondary clamp

function should be activated. In secondary clamp mode, the

IGBT's collector voltage is internally clamped to V_PWR+11V.

CHIP SELECT (CS)

In the General Purpose Gate Driver mode, this input

monitors the drain of an external MOSFET to provide short-

circuit and open circuit detection by monitoring the

MOSFET's drain to source voltage. The filter timer and

threshold voltage are easily programmed through SPI (See

tables 18 and 19 for SPI messages).

The system MCU selects the 33810 to receive

communication using the chip select (CS) pin. With the CS in

a logic low state, command words may be sent to the 33810

via the serial input (SI) pin, and status information is received

by the MCU via the serial output (SO) pin. The falling edge of

CS enables the SO output and transfers status information

into the SO buffer.

In General Purpose Gate Driver mode the FBx pin also

provides a drain to gate clamp for fast turn off of inductive

loads and external MOSFET protection.

Rising edge of the CS initiates the following operation:

Disables the SO driver (high-impedance)

GATE DRIVER OUTPUT (GD0-GD3)

Activates the received command word, allowing the 33810

to activate/deactivate output drivers.

The GD_Xpins are the gate drive outputs for an external

MOSFET or IGBT. Internal to the device is a Gate to Source

resistor designed to hold the external device in the OFF state

while the device is in the POR or SLEEP state.

To avoid any spurious data, it is essential that the high-to-

low and low-to-high transitions of the CS signal occur only

when SCLK is in a logic low state. Internal to the 33810

device is an active pull-up to VDD on CS.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

FUNCTIONAL DESCRIPTION

FUNCTIONAL PIN DESCRIPTION

LOW SIDE INJECTOR DRIVER OUTPUT (OUT0 -

OUT3)

SPARK DURATION OUTPUT (SPKDUR)

SPKDUR is the Spark Duration output. This open drain

output is low while feedback inputs FB0 through FB3 are

above the programmed spark detection threshold. This

output indicates an ignition flyback event. Each feedback

input (FB0 - FB3) is logically OR'd to drive the SPKDUR

output. There is a 50μA pull up current source connected

internally to the SPKDUR pin.

OUT0 - OUT3 are the Open drain low side (Injector) driver

outputs. The drain voltage is actively clamped during turn off

of inductive loads. These outputs can be connected in

parallel for higher current loads provided the turn off energy

rating is not exceeded.

RESISTOR SENSE POSITIVE (RSP)

MAXIMUM IGNITION COIL CURRENT (MAXI)

Resistor Sense Positive - Positive input of a current sense

amplifier. The ignition coil current is monitored by sensing the

voltage across an external resistor connected between RSP

and RSN. The output of the current sense amplifier feeds the

inputs of the NOMI and MAXI comparators.

Maximum ignition coil current output flag. This output is

asserted when the output ignition coil current exceeds the

selected level of the DAC. This signal also latches off the gate

drive outputs when configured as an ignition gate driver. The

MAXI current level is determined by the voltage drop across

an external sense resistor connected to pins RSP and RSN.

Note: RSN and RSP must be grounded in V10 mode.

MAXI can be configured as an input pin for V10

applications where the gate drive needs to be latched off by

another devices MAXI current sense amplifier output. The

MAXI input will latch off gate drivers 7 and 8 when configured

as ignition gate drive outputs See Figure 10.

RESISTOR SENSE NEGATIVE (RSN)

Resistor Sense Negative - Negative input of a current

sense amplifier. The ignition coil current is monitored by

sensing the voltage across an external resistor connected to

RSP and RSN. The output of the current sense amplifier

feeds the inputs of the NOMI and MAXI comparators.

DRIVER INPUT (DIN0-DIN3), GATE DRIVER INPUT

(GIN0-GIN3)

Note: RSN and RSP must be grounded in V10 mode.

Parallel input pins for OUT0-OUT3 low side drivers and

GD0-GD3 gate drivers. Each parallel input control pin is

active high and has an internal pull-down current sink. The

parallel input data is logically OR’d with the corresponding

SPI input data register contents, except for the ignition mode

IGBT drivers. They are only controlled by the parallel inputs

GIN0-GIN3. In GPGD mode, GIN0-GIN3 are logically OR’d

with SPI input data. All outputs are disabled when the

OUTEN pin is HIGH, regardless of the state of the command

inputs.

NOMINAL IGNITION COIL CURRENT (NOMI)

Nominal ignition coil current output flag. This output is

asserted when the output current exceeds the level selected

by the DAC.

NOMI can be configured as an input pin for V10 mode

applications where the gate drive needs to be latched off by

another device’s MAXI current sense amplifier output. The

NOMI input will latch off gate drivers 5 and 6 when configured

as a V10 mode ignition gate driver See Figure 10.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

FUNCTIONAL DESCRIPTION

FUNCTIONAL INTERNAL BLOCK DESCRIPTION

Figure 4. Functional Internal Block Diagram

with the corresponding SPI input data register contents. All

POWER SUPPLY/POR

outputs are disabled when the OUTEN pin is HIGH,

regardless of the state of the command inputs.

The 33810 is designed to operate from 4.5 to 36 V on the

VPWR pin. The VPWR pin supplies power to all internal

regulators, analog, and logic circuit blocks. The VDD supply

is used for setting communication threshold levels and

supplying power to the SO driver. This IC architecture

provides a low quiescent current sleep mode. Applying

VPWR and VDD to the device will generate a Power On

Reset (POR) and place the device in the Normal State. The

Power On Reset circuit incorporates a timer to prevent high

frequency transients from causing a POR.

INJECTOR DRIVERS: OUT0 – OUT3

These pins are the Open drain low side (Injector) driver

outputs. The drain voltage is actively clamped during turn off

of inductive loads. These outputs can be connected in

parallel for higher current loads, provided the turn off energy

rating is not exceeded.

IGNITION GATE PRE-DRIVERS: GD0 – GD3

MCU INTERFACE AND OUTPUT CONTROL

These pins are the gate drive outputs for an external

MOSFET or IGBT. Internal to the device is a Gate to Source

resistor designed to hold the external device in the OFF state

while the device is in the POR or Sleep State.

This component provides parallel input pins for OUT0-

OUT3 low side drivers and GD0-GD3 gate drivers. Each

parallel input control pin is active high and has an internal

pulldown current sink. The parallel input data is logically OR’d

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Control register settings from a Power-ON Reset (POR)

are as follows:

POWER SUPPLY

The 33810 is designed to operate from 4.5 to 36 V on the

VPWR pin. The VPWR pin supplies power to all internal

regulators, analog and logic circuit blocks. The VDD supply is

used for setting communication threshold levels and

supplying power to the SO driver. This IC architecture

provides flexible microprocessor interfacing and low

quiescent current sleep mode.

• All outputs off

• IGNITION gate driver mode enabled (IGBT Ignition Mode).

• PWM frequency and duty cycle control disabled.

• Off State open load detection enabled (LSD)

• MAXI dac set to 14 A, NOMI DAC set to 5.5A

• Spark detect level VIL DAC set to V_PWR+5.5V

• Open secondary timer set to 100 μs

• Dwell timer set 32ms

POWER-ON RESET (POR)

Applying V_PWRand V_DDto the device will generate a

Power On Reset (POR) and place the device in the Normal

State. The Power On Reset circuit incorporates a filter to

prevent high frequency transients from causing a POR.

• Soft shutdown disabled

• Low-voltage flyback clamp disabled

• Dwell overlap MAXI offset disabled

All outputs are disabled when the OUTEN input pin is

HIGH regardless of the SPI control registers or the logic level

on the parallel input pins. With the OUTEN pin high, SPI

messages may be sent and received by the device. Upon

enabling the device (OUTEN low), outputs will be activated

based on the state of the command register or parallel input.

MODES OF OPERATION

In Normal State, the 33810 gate driver has three modes of

operation, ignition Mode, GPGD (General Purpose Gate

Driver) Mode and V10 mode.The operating mode of each

gate driver may be set individually and is programmed using

the Mode Select Command.

Table 5. Operational States

MODE SELECT COMMAND

VPWR

VDD

OUTEN

OUTPUTS

STATE

The MODE Select Command is used to set the operating

mode for the GDx gate driver outputs, over/under-voltage

operation and to enable V10 Mode and the PWM generators.

The Mode Select Command programmable features are

listed below.

L

X

OFF

Power

Off

L

H

L

X

OFF

POR

SLEEP

POR

• Ignition/GPGD Mode select (gate drivers)

• V10 Mode enable

• Over/Under-voltage operation for all drivers

• GPGD PWM controller enable

H

L

X

OFF

POR

IGNITION/GPGD MODE SELECT

The Ignition/General Purpose Gate Driver Mode select bits

determine independently, the operating mode of each of the

GDx gate driver outputs. Bits 8,9,10,11 correspond to GD0,

GD1, GD2, GD3 respectively. Setting the bit to a logic 0 sets

the GDx driver to the Ignition Mode. Setting the bit to a logic

1 commands the GDX driver to the General Purpose Mode

and disables the ignition features for that particular gate

driver (except the MAXI current shutdown feature). Further

information on GDx gate driver in Ignition Mode and General

Purpose Mode is provided later in this section of the data

sheet.

SLEEP

H

L

ACTIVE

OFF

NORMAL

H

SLEEP STATE

Sleep State is entered when the V_DDsupply voltage is

removed from the VDD pin. In Sleep State all outputs are off.

Applying V_DDwill force the device to exit the Sleep State and

generates a POR.

V10 MODE ENABLE BIT

The V10 Enable bit allows the user to configure the device

for 10 cylinder applications. When the V10 Mode is enabled,

the device configures the NOMI pin and MAXI pin as digital

inputs rather than outputs. The new MAXI input pin receives

NORMAL STATE

The default Normal State is entered when power is applied

to the VPWR and VDD pins.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

18

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

the MAXI shutdown signal for GD0 and GD2 and the new

NOMI input pin receives the MAXI shutdown signal for GD1

and GD3. Further information on V10 Mode is provided in the

V10 Application section.

IGNITION (IGBT) GATE DRIVER MODE

The MC33810 contains dedicated circuitry necessary for

automotive ignition control systems. Each gate driver may be

individually configured as an Ignition Gate Driver with the

following features:

Note: RSN and RSP must be grounded in V10 Mode.

OVER/UNDER-VOLTAGE SHUTDOWN/RETRY BIT

• Spark duration signal

The Over/Under-voltage Shutdown/Retry bit allows the

user to select the global over and under-voltage fault strategy

for all the outputs. In an over-voltage or under-voltage

condition on the VPWR pin, all outputs are commanded off.

The Over/Under-voltage control bit sets the operation of the

outputs when returning from over/under- voltage. Setting the

Over/Under-voltage bit to logic [1] will force all outputs to

remain OFF when V_PWRreturns to normal level. To turn the

output on again, the corresponding input pin or SPI bit must

be reactivated. Setting the Over/Under-voltage bit to logic [0]

will command all outputs to resume their previous state when

VPWR returns to normal level. Table 6 below provides the

output state when returning from over or under-voltage.

• Open secondary timer

• Soft shutdown control

• Low-voltage flyback clamp

• Ignition ignition coil current measurement

• MAXI output and control

• NOMI output

• Maximum dwell timer

In the Ignition Mode, several control strategies are in place

to control the IGBT for enhanced system performance.

Information acquired from the FBx pin allows the device to

produce a spark duration signal output (SPKDUR) and detect

open secondary ignition coils. Based on the FBx signal and

Spark Command register settings, the device performs the

appropriate gate control (Low-voltage Flyback Clamp, Soft

Shutdown) and produces the SPKDUR output.

Table 6. Over-voltage/Under-voltage Truth Table

Over/

The FBx pin is connected to the collector of the IGBT

through an external 9:1 resistor divider network. The

recommended values for the resistor divider network is 36K

and 4.02K, with the 36K resistor connected from the IGBT

collector to the FBx pin and the 4.02K resistor connected

from the FBx pin to ground.

Under-

voltage

Control

Bit

State When

Returning From

Over/Under-voltage

GINx DINx

Input Pin

SPI

Bit

OUTEN

Input pin

OFF

ON

X

0

X

0

X

1

0

Additional controls to the gate driver are achieved by

sensing the current through the external IGBT. The Resistor

Sense Positive (RSP) and Resistor Sense Negative (RSN)

inputs are use to measure the voltage across an external

20 mΩ or 40 mΩ current sense resistor. A gain select bit in

the Spark Command SPI Command messages should be set

to 1 (gain of 2) when using a 20 mΩ current sense resistor.

When using a 40 mΩ current sense resistor, the gain select

bit should be set to 0 (gain of 1 is the default value).

0*

X

1

ON

X

* Default Setting

Note: The SPI bit does not control the Gate Driver outputs in

the Ignition Mode, only in the GPGD Mode.

The ignition coil current is compared with the output of the

DACs which have been programmed via the SPI Commands.

The comparison generates the Nominal Current signal

(NOMI) and the Maximum Current signal (MAXI). Both

signals have a low output when the ignition coil current is

below the programmed DAC value and a high output when

the current is above the programmed DAC value.

An under-voltage condition on VDD results in the global

shutdown of all outputs and reset of all internal control

registers. The V_DDunder-voltage threshold is between 0.8V

and 2.8V

When the GDx output is shutdown because of the control

strategy, the output may be activated again by toggling the

input control.

PWM ENABLE BIT

X

Gate Driver outputs programmed as General Purpose

Gate Drivers may be used as low frequency PWM outputs.

The PWM generators are enabled via bits 0 through 3 in the

Mode Select Command. Bits 0 through 3 correspond to

outputs GD0 through GD3 respectively. Once the frequency

and duty cycle are programmed through the PWM Frequency

& DC command, the PWM output may be turned ON and

OFF through the PWM enable bit. Further information on

PWM control is provided in the General Purpose Gate Driver

Mode section of this data sheet.

SPARK COMMAND

The Spark Command is an ignition mode command used

to program the parameters for the ignition mode features

listed below:

• End spark threshold (EndSparkTh bits)

• Open secondary fault timer (OSFLT bits)

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

• Secondary clamp (secondary clamp bit)

• Soft shutdown enable (SoftShutDn bit)

V_PWR= 16.0V

Default settings

Begin spark threshold V_IH= V_PWR+ 21V

End spark threshold V_IL= V_PWR+5.5V

• Ignition ignition coil current amplifier gain (Gain Sel bit)

• Overlapping dwell disable (Overlap Dwell Disable bit)

• Maximum dwell enable (MaxDwellEn bit)

• Maximum dwell timer (MaxDwellTimer bits)

• End of spark filter timer value

The pulse width of the SPKDUR signal is measured by the

MCU timer/input capture port to determine the actual spark

duration. Spark duration information is then used by the MCU

spark control algorithm to optimize the dwell time.

Spark Command address and data bits are listed in

Table 20

Table 7. End Spark Threshold

NOTE: Gate driver outputs programmed to be General

Purpose Gate Drivers are not affected by the Spark

Commands.

Spark Command

End Spark Threshold (VIL)

Bit<b1,b0>

00

01

10

11

VPWR + 2.75

VPWR + 5.5

VPWR + 8.2

VPWR + 11.0

SPARK DURATION SIGNAL

The Spark Duration is defined as the beginning of current

flow to the end of current flow across the spark plug gap.

Because the extremely high-voltage ignition coil secondary

output is difficult to monitor, corresponding lower voltage

signals generated on the ignition coil primary are often used.

The FBx pins monitor the ignition coil primary voltage (IGBT

Collector) through a 10 to 1 voltage divider. When the IGBT

is disabled, the rise in the FBx signal indicates a sparkout

condition is occurring at the spark plug gap.

OPEN SECONDARY TIMER

A fault due to open in the ignition coil secondary circuit can

be determined by waveforms established on the ignition coil

primary during a spark event. The spark event is initiated by

the turn off of the IGBT. The voltage on the collector of the

IGBT rises up to the IGBT’s internal collector to gate clamp

voltage (typically 400 volts). Collector to gate clamp events

normally last 5.0 to 50μs. In an open ignition coil secondary

fault condition, the collector to gate clamp event lasts much

longer. The oscilloscope waveform in Figure 6 and Figure 7

compare a normal spark signature with that of an open

secondary fault condition signature.

The device considers the initial thresholds for spark

duration to be V_IH= V_PWR+ 21 V for rising edge as measured

on the collector of the IGBT. The spark duration falling edge

reference is programmable via SPI through the End Spark

Threshold bits 0 and 1 (See Table 7).

Figure 5 illustrates a typical ignition event with dwell time

and spark duration indicated.

Figure 5. Ignition Coil Charge and Spark Event

Figure 6. Normal Spark Event

Ignition Coil Current,

5.0A/div

SPKDUR~3.0ms

DWELL Time

Channel 1: GINx IGBT Gate Drive

Channel 2: IGBT Collector Voltage

Channel 3: IGBT Current @ 5.0A/Div

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

20

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

The Low-voltage Clamp spreads out the energy

dissipation over a longer period of time, thus allowing the use

of a lower energy rated IGBTs. The internal low-voltage

clamp is connected between the IGBT's collector (through an

external resistor) and the IGBT's gate. The energy stored in

the ignition coil is dissipated by the IGBT, not the internal

clamp. The internal clamp only provides the bias to the IGBT.

Figure 7. Open Secondary Spark Event

Several logical signals are required as inputs to activate

the GDx Low-voltage Clamp feature. The GDx Low-voltage

Clamp feature may be disabled through bit 4 of the Spark

Command message.

Figure 8. Low-voltage Clamp

+

–

SPI

FB0

FB1

FB2

FB3

+

–

SPARK DURATION

Open Secondary

SPI

100 µA

53 V

+

−

V

PWR

13 V

SPI input

The Open Secondary timer is initiated on the rising edge

of the ignition coil primary spark signal and terminated on the

falling edge. The rising edge Open Secondary Threshold is

V_IH= 135 V at primary, no hysteresis. The falling edge Open

Secondary threshold is V_IL= 135V.

GPGD

Clamp

Low V

Clamp

GATE DRIVE

CONTROL

GD0

GD1

GD2

GD3

Collector to gate clamp durations that last longer than the

selected Open Secondary Fault Time interval (Table 8)

indicates a failed spark event. When the Open Secondary

Fault Time is exceeded and the Low-voltage Clamp is

enabled, the GDx output will activate the Low-voltage Clamp

shown in figure 16. The Logic for this Low-voltage Clamp is

defined in Figure 9

Figure 9. Low-voltage Clamp Logic

OSFLT_En

IGN Mode

OSFLT

Table 8. Open Secondary Timer

Activate

Low-voltage

Clamp

Spark Command

Bits<b3,b2>

Open Secondary Fault Timer

OSFLT (μs)

MaxDwell

MaxDwellEn

00

01

10

11

10

20

SoftShutDnEn

IGN Mode

50

100

VPWR

OVER-VOLTAGE

OUTEN

LOW-VOLTAGE CLAMP

The Low-voltage Clamp is an internal clamp circuit which

biases the IGBT's gate voltage in order to control the collector

to emitter voltage to VPWR+11V. This technique is used to

dissipate the energy stored in the ignition coil over a longer

period of time than if the internal IGBT clamp were used.

SOFT SHUTDOWN ENABLE

The soft shutdown feature is enabled via the SPI by

asserting control bit 5 in the Spark Command message.

In the open secondary fault condition, all of the stored

energy in the ignition coil is dissipated by the IGBT. This fault

condition requires the use of a higher energy rated IGBT than

would otherwise be needed.

When enabled, the following events initiate a soft

shutdown control of the gate driver.

• OUTEN = High (Outputs Disabled)

• Over-voltage on VPWR pin

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

• Max dwell time

The Max Dwell gate turn off signal is a logically ANDed

with the Soft Shutdown bit to activate a Low-voltage Active

Clamp (See Figure 9).

Soft Shutdown is designed to prevent an ignition spark

while turning off the external IGBT. The Low-voltage Clamp

is activated to provide the mechanism for a soft shutdown.

Table 10. Maximum Dwell Timer

GAIN SELECT BIT

Spark Command

Bit<b11,b10,b9>

MAX Dwell Timer

MaxDwell (ms)

The ignition coil current comparators are used to compare

the programmed NOMI and MAXI DAC value with voltage

across the external current sense resistor. When selecting a

gain of two, the ignition coil current sense resistor must be

reduced from 40mΩ to 20mΩ.

000

001

010

011

100

101

110

111

2

4

8

16

OVERLAPPING DWELL ENABLE BIT

32 (default)

Overlapping dwell occurs when two or more ignition mode

drivers are commanded ON at the same time. In this

condition, with the Overlapping Dwell Bit enabled the MAXI

DAC threshold value is increased as a percentage of the

nominal programmed value. The percent increase is

determined by bit 5 through bit 7 of the DAC Command.

64

DAC COMMAND (DIGITAL TO ANALOG

CONVERSION COMMAND)

Table 9. Overlapping Dwell Compensation

The DAC Command is an ignition mode command that

sets the nominal ignition coil current (NOMI) and maximum

ignition coil current (MAXI) DAC values. Bits 0 through 4 set

the NOMI threshold value and, bits 8 through 11 set the MAXI

threshold values. The DAC command and default values are

listed in the SPI Command Summary Table 20. The NOMI

output is used by the MCU as a variable in dwell and spark

control algorithms.

DAC Command

Bits<b7,b6,b5>

Overlap Compensation

(%)

000

001

010

011

100

101

110

111

0%

7%

15%

24%

35% (default)

47%

NOMI DAC BITS

The NOMI output signal is generated by comparing the

external current sense resistor differential voltage (Resistor

Sense Positive, Resistor Sense Negative) with the SPI

programmed NOMI DAC value. When the NOMI event

occurs, the NOMI output pin is asserted (High). The NOMI

output is only a flag to the MCU and it’s output does not affect

the gate driver.

63%

80%

MAXIMUM DWELL ENABLE BIT

Bit 8, the Maximum Dwell Enable bit allows the user to

enable the Maximum Dwell Gate Turnoff Feature. When the

Max Dwell bit is programmed as logic 0 (disabled) the device

will not perform a Low-voltage Clamp due to Max Dwell (See

Figure 9).

When using a 20 mΩ resistor as the current sense resistor,

the gain select of the differential amplifier connected to RSP

and RSN, should be set to a gain of 2, via the SPI Command

Message Spark Command (Command 0100, hex 4), Control

bit 6 =1.

MAXIMUM DWELL GATE TURN OFF FEATURE

When using a 40mΩ resistor as the current sense resistor,

the gain select of the differential amplifier connected to RSP

and RSN, should be set to a gain of 1, via the SPI Command

Message Spark Command (Command 0100, hex 4), Control

bit 6 =0. This is also the default value.

In automotive ignition systems, dwell time is defined as the

duration of time that an ignition coil is allowed to charge. The

MC33810 starts the measure of time from the gate drive ON

command. If the dwell time is greater than the Max Dwell

Timer setting (Table 10), the offending ignition gate driver is

commanded OFF. The Max Dwell Gate Turn Off Feature may

be disabled via bit 8 of the Spark Command. When the

feature is disabled, the Max Dwell fault bits are always logic

0. The Max Dwell Timer feature pertains to Ignition Mode only

and does not affect gate drivers configured as general

purpose gate drivers.

The NOMI output provides a means to alert the MCU when

the ignition coil primary current equals the value programmed

into the NOMI DAC.

In V10 Mode, the NOMI pin is reconfigured as a MAXI

input pin from a third MC33810 device in the system. In this

mode a NOMI input has effectively the same control as an

internal MAXI signal. Further information is provided in the

V10 Mode application section of this data sheet.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 11. Nominal Current DAC Select

Differential Differential

Voltage

(mV

Voltage

(mV

Voltage

(mV

Voltage

(mV

DAC Command

Bits<4,3,2,1,0>

NOMI

DAC Command

Bits<4,3,2,1,0>

NOMI

Current (A) Rs = 20 mΩ Rs = 40 mΩ

(Gain = 2)

160

(Gain = 1)

320

(Gain = 2)

60

(Gain = 1)

120

130

140

150

160

170

180

190

200

210

220

230

240

250

260

270

280

290

300

310

10100

10101

10110

10111

11000

11001

11010

11011

11100

11101

11110

11111

8.00

8.25

00000

00001

00010

00011

00100

00101

00110

00111

01000

01001

01010

01011

01100

01101

01110

01111

10000

10001

10010

10011

3.00

3.25

3.50

3.75

4.00

4.25

4.50

4.75

5.00

5.25

5.50

5.75

6.00

6.25

6.50

6.75

7.00

7.25

7.50

7.75

165

330

65

8.50

170

340

70

8.75

175

350

75

9.00

180

360

80

9.25

185

370

85

9.50

190

380

90

9.75

195

390

95

10.00

10.25

10.50

10.75

200

400

100

105

110

115

120

125

130

135

140

145

150

155

205

410

210

420

215

430

MAXI DAC BITS

The MAXI control block provides a means to shut off all the

ignition coil drivers if the current reaches a SPI

programmable maximum level. Control is achieved by

comparing the output of the current sense amplifier with a SPI

programmed DAC value.

The MAXI comparator disables all gate drivers configured

as ignition drivers when the DAC MAXI setting is exceeded.

When a MAXI event occurs, the MAXI bit in the fault status

register is set and the MAXI pin is asserted (High).

When using a 20mΩ resistor as the current sense resistor,

the gain select of the differential amplifier connected to RSP

and RSN, should be set to a gain of 2, via the SPI Command

Message Spark Command (Command 0100, hex 4), Control

bit 6 =1.

When using a 40mΩ resistor as the current sense resistor,

the gain select of the differential amplifier connected to RSP

and RSN, should be set to a gain of 1, via the SPI Command

Message Spark Command (Command 0100, hex 4), Control

bit 6 =0. This is also the default value.

The MAXI fault bit in the SPI fault status register is cleared

when the MAXI condition no longer exists and the SPI fault

status register has been read by the MCU.

In V10 Mode, the MAXI pin is configured as an input to

receive the MAXI signal from a second MC33810 device in

the system. In this mode a input MAXI signal has effectively

the same control as an internal MAXI signal. Further

information is provided in the V10 Mode application section

of this specification.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

GENERAL PURPOSE GATE DRIVER MODE

Table 12. Maximum Current DAC Select

Each gate driver can be individually configured as a

General Purpose Gate Driver (GPGD) and controlled from

the parallel GINx input pins, SPI Driver ON/OFF Command or

may be programmed through the SPI for a specific frequency

and duty cycle output (PWM).

Differential Differential

Voltage (mV Voltage (mV

Rs = 20 mΩ Rs = 40 mΩ

DAC Command

Bit<b11,b10,b9,b8>

MAXI

Current (A)

0000

0001

0010

0011

0100

0101

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

6.0

7.0

120

140

160

180

200

220

240

260

280

300

320

340

360

380

400

420

240

280

320

360

400

440

480

520

560

600

640

680

720

760

800

840

In General Purpose Gate Driver mode the gate drivers

have the following features:

8.0

• Gate driver for discrete external MOSFET

• Off state open load detect

• On state short circuit protection

• Programmable drain threshold and duration timer for short

fault detection

9.0

10.0

11.0

12.0

13.0

14.0

15.0

16.0

17.0

18.0

19.0

20.0

21.0

• PWM frequency/duty cycle controller

In GPGD Mode the GDx output is a current controlled

output driver with slew rate control, gate to source clamp,

passive pull-down resistor and a drain to gate clamp for

switching inductive loads.

Driver ON/OFF Command

The Driver ON/OFF Command, bits 4 through 7 control

gate drivers that have been Mode Select Command

programmed as GPGD. A logic 1 in bits 4 through 7 will

command the specific output ON. A logic 0 in the appropriate

bit location commands the specific output Off. Also contained

in the Driver ON/OFF Command are SPI control bits for the

integrated LSD output drivers. Further information on LSD

control is provided in the Low Side Injector Driver section of

the data sheet.

NOTE: Gate drivers programmed to IGNITION mode have

parallel input control only, and cannot be turned off and on via

SPI commands.

END OF SPARK FILTER BITS

The ringing at the end of the Spark signatures waveform

can cause erroneous detection of the End of Spark event. To

eliminate the effect of this ringing, a low pass filter with

variable time values can be selected. Four time values for the

low pass filter have been provided with a zero value

indicating that no low pass filtering is to be used. The End of

Spark Filter bits specify a 0, 4µs, 16µs, or 32µs time interval

to sample the spark ignition coil primary current to ignore the

ringing at the end of spark.

GPGD Short Threshold Voltage Command

Each GPGD driver is capable of detecting an open load in

the off state and shorted load in the on state. All faults are

reported through the SPI communication. For open load

detection, a current source is placed between the FBx pin

and ground of the IC. An open load fault is reported when the

FBx voltage is less than the 2.5 V threshold. Open load fault

detect threshold is set internally to 2.5 V and may not be

programmed. A shorted load fault is reported when the FBx

pin voltage is greater than the programmed short threshold

voltage.

Table 13. End of Spark Filter Time Select

Filter Time

End of Spark Filter

Bits<1, 0>

µs

The short to battery fault threshold voltage of the external

MOSFET is programmed via the GPGD Short Threshold

Voltage Command. Table 14 illustrates the bit pattern to

select a particular threshold. Drain voltages less than the

selected threshold are considered normal operation. Drain

voltages greater than the selected threshold voltage are

considered faulted.

00

01

10

11

0.0

4.0

16.0

32.0

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Each gate driver is individually set to either, restore to the

pre-fault state, or shutdown when a short fault is declared. By

setting the Retry/Shutdown bit in the GPGD Fault Operation

Command to logic 1 the specific output will try to go back to

the pre-fault state when the fault is no longer declared, after

a programmed “inhibit time”.

Table 14. FBx Fault Threshold Select

GPGD V_DSFLT

FBx Fault Threshold Select

Bits

000

001

010

011

100

101

110

111

0.5V

1.0V

The retry strategy will cause the output to try to return to

the pre-fault state on a 1% duty cycle basis. For example: If

the fault timer is set to 120μs and a fault is declared (drain

voltage greater than the programmed threshold for greater

than 120μs), the GDx output driver will be forced off for 12ms.

After 12ms has elapsed, if the inputs, GINx or SPI, have not

tried to shut off the particular GDx output in the interim, the

GDx output will try to set the external driver on again (the pre-

fault state). A continued declared fault on the output would

result in another 12ms shutdown period.

1.5V

2.0 (default)

2.5V

3.0V

No Change

By setting the Retry/Shutdown bit in the GPGD Fault

Operation Command to logic 0 the specific output will

shutdown and remain off when the short fault is declared.

Only a reissue of the turn on command, via SPI or GINx, will

force the output to try and turn on again.

GPGD SHORT TIMER COMMAND

The GPGD Short Timer Command allows the user to

select the duration of time that the drain voltage is allowed to

be greater than the programed threshold voltage without

causing shutdown. External MOSFETS with drain voltages

greater than the programed threshold for longer than the

Fault Duration Timer are shutdown. Timer durations are listed

in Table 15.

In the event that a GPGD is selected as a PWM controller

and a short occurs on the output, the output retry strategy

forces the output to a 1% duty cycle based on the fault timer

setting. For example: If the fault timer is set to 120μs and a

fault is detected (drain voltage greater than programmed

threshold), the PWM output will be commanded off for 12ms

and commanded ON again at the next PWM cycle.

Care should be taken to select a fault timer that is shorter

than the minimum duty cycle ON time of the PWM controller.

Selecting a fault timer that is longer will allow the PWM

controller to continue to drive the external MOSFET into a

shorted load.

Table 15. FBx Short Fault Timer

GPGD FLT Timer

Fault Timer Select

Bits

000

001

010

011

100

101

110

111

30µs

60µs

PWM FREQUENCY/DUTY CYCLE COMMAND

The PWMx Freq & Duty Cycle command is use to program

the GDx outputs with a frequency and duty cycle. Table 16

defines the user selectable output frequency. The frequency

and duty cycle may be updated at any time using the PWM

Freq&DC command, however the update will only begin on

the next PWM rising edge time.

120µs

240µs (default)

480µs

960µs

Once the PWM Freq & DC registers are programmed and

the PWM controller is enabled through the Mode Command

the PWM outputs are turned ON and OFF via the GINx pin

OR the SPI GPGD ON/OFF Command control bit. All Parallel

and serial On and Off command updates to the PWM

controller are synchronous with the rising edge of the

previous PWM period.

No Change

Notes: Tolerance on this fault timer setting is ±10% after using the

Calibration Command.

GPGD FAULT OPERATION COMMAND

The truth table for GDx control in general purpose mode is

provided in Table 8.

The GPGD Fault Operation Command sets the operating

parameters for the gate drivers under faulted conditions. A

short fault is said to be “detected” when the drain source

voltage, Vds, of the external MOSFET, exceeds the SPI

programmed short threshold voltage. The short fault is said

to be “declared” when the V_DSover-voltage lasts longer than

the SPI programmed “fault timer.” (short duration time > fault

timer programmed value)

The duty cycle of the PWM outputs is controlled by bits 0-

6, inclusive. The duty cycle value is 1% per binary count from

1-100 with counts of 101-127 defaulting to 100%. For

example, sending SPI command 101001000001100 would

set GD1, PWM output to 10Hz and 12% duty cycle.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

.

V10 MODE

Table 16. Frequency Select

V10 Mode provides a method for monitoring 10 ignition

events while using only two current sense resistors. This is

achieved using three MC33810 devices. Two MC33810

devices are programmed as Normal Ignition mode outputs

and one is programmed as a V10 ignition mode output. The

ignition gate driver outputs are partitioned into two banks of

five outputs each (See Figure 10). Each bank contains one or

two driver(s) from the V10 device.

PWM Freq&DC

Command

Bit<b9,b8,b7>

Frequency Hz

000

001

010

011

100

101

110

111

10 Hz (default)

20 Hz

40 Hz

Drivers in the V10 device are grouped in two’s (GD0&GD2,

GD1&GD3). Current from each V10 mode IGBT group is

monitored by the appropriate Normal Mode device (See

Figure 10). The MAXI signal from one Normal Mode device is

ported to the V10 Mode MAXI input pin. Likewise the MAXI

signal from the second Normal Mode device is ported to the

V10 Mode NOMI input pin. The V10 Mode NOMI/MAXI inputs

are used as MAXI shutdown signals for the appropriate

ignition gate drive group.

80 Hz

160 Hz

320 Hz

640 Hz

1.28 kHz

V10 Mode contains the same features as Ignition Mode

gate drivers with the following exceptions:

Notes: Tolerance on selected frequency is ±10% after using the

Calibration Command. Shorts to battery and open load faults will not

be detected for frequency and duty cycle combinations inconsistent

with fault timers.

• NOMI/MAXI configured as input pins

• MAXI shutdown for GPGD disabled

• NOMI/MAXI comparators disabled

Table 17. Pre-driver GDx Output Control

In V10 Mode, Spark Command bits 7 and 8 (Gain Select,

Overlapping Dwell) are disabled. These two features are

achieved through the Normal Mode devices.

Mode

Driver

On/OFF

IGN/GP Bit GPGD Bit

PWMx

Enable Bit

GINx

terminal

GDx

Command

Output

RSN and RSP must be grounded in V10 Mode.

1

0

1

X

1

X

0

1

0

1

X

1

X

OFF

ON

Freq/DC

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

26

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Bank 1

IC 3 “Child”

GO

Bank 2

IC 1 “Parent”

GO

IC 2 “Parent”

GO

GIN

0

1

2

3

0

1

2

3

0

GIN

0

1

2

3

IGBT1

4

IGBT1

Gate Drive 0

(0-3)

IGBT2

Gate Drive 0

GO

6

GO

GIN

1

GIN

1

IGBT1

5

Gate Drive 1

GO

IGBT 2

(0-3)

2

GIN

2

Gate Drive 2

GO

3

GIN

3

GIN

3

IGBT2

Gate Drive 3

4

7

Gate Drive 3

4 GIN

(0-3)

4

GIN (0-3)

NOMI

GIN (0-3)

LOGIC

NOMI

LOGIC

MAXI

NOMI

MAXI

NOMI

RSP1

RSP

RSP2

VtNI

NOMI

Comparator

Child

VtNI

NOMI

disabled

Ign 1

Comparator

Inputs Tied

to GND

Ign 2

RS1

RS2

Comparator

VtMI

MAXI

VtMI

MAXI

disabled

VtMI

MAXI

Logic

Buffer

Logic

Buffer

Comparator

Logic

Buffer

Logic

Buffer

Logic

Buffer

Logic

Buffer

MAXI

NOMI

MAXI

NOMI

NOMI1 to uP

MAXI1 to uP

MAXI2 to uP

NOMI2 to uP

Note: For “child” input NOMI is for channel 1&3, input MAXI is for channel 0&2

Figure 10. V10 Mode

LOW SIDE INJECTOR DRIVER

ON/OFF CONTROL COMMAND

The four open drain low side injector drivers are designed

to control various automotive loads such as injectors,

solenoids, lamps, relays and unipolar stepper motors. Each

driver includes off and on state open load detection, short

circuit protection and diagnostics. The injector drivers are

individually controlled through the ON/OFF SPI input

command Table 20 or parallel input pins DIN0 to DIN3. Serial

and parallel control of the output state is determined by the

logical OR of the SPI serial bit and the DINx parallel input

pins. All four outputs are disabled when the OUTEN input pin

is high regardless of the state of the SPI control bit or the

state of the DINx pin. All four injector drivers are not affected

by the selection of the gate driver’s three modes of operation

(Ignition Mode, General Purpose Mode, V10 mode).

To program the individual output of the 33810 ON or OFF,

a 16-bit serial stream of data is entered into the SI pin. The

first 4 bits of the control word are used to identify the On/Off

Command. Bit 0 through bit 3 of the ON/OFF Control

Command turn ON or OFF the specific output driver.

INJECTOR DRIVER FAULT COMMANDS

Fault protection strategies for the injector drivers are

programmed by the SPI LSD Fault Command. Bit 8 through

11 determine the type of short circuit protection to be used,

bits 0 through 7 set the open load strategy.

Short-circuit protection consists of three strategies. All

strategies utilize current limiting as an active element to

protect the output driver from failure.The T_LIMand Timer

options are used to enhance the short circuit protection

strategy of the Injector drivers. The timer protection scheme

uses a low duty cycle in the event of a short-circuit. The T

LIM

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

protection circuit uses the junction temperature of the output

driver to determine the fault. Both methods may be used

together or individually.

Table 18. Injector Driver (OUTx) Fault Operation

Shutdn

Retry

Fault

Timer

Bit 9

TLIM

Operation During Short Fault

Bit 11 Bit 10

TIMER PROTECTION

Timer only, Outputs will retry on period

1

0

X

The first protection scheme uses a low ON to OFF duty

cycle to protect the output driver. The low duty cycle allows

the device to cool so that the maximum junction temperatures

are not exceeded. During a short condition, the device enters

current limit. The driver will shutdown for short conditions

lasting longer than the current limit timer (~60μs)

OUT0-OUT3 = 60μs ON, ~10ms OFF

T

only, Outputs will retry on T

LIM

1

0

1

LIM

hysteresis.

Timer and T , Outputs will retry on

LIM

period and driver temperature below

threshold.

TEMPERATURE LIMIT (T_LIM

)

OUT0-OUT3= 60μs ON, ~10ms OFF

The second scheme senses the temperature of the

individual output driver. During a short event the device

enters current limit and will remain in current limit until the

output driver temperature limit is exceeded (T_LIM). At this

point, the device will shutdown until the junction temperature

Timer only, Outputs will not retry on

period

0

X

OUT0-OUT3 = 60μs ON, OFF

T

only, Outputs will not retry on TLim

0

1

0

1

LIM

falls below the hysteresis temperature value. The T

hysteresis.

LIM

hysteresis value is listed in the previous specification tables.

Timer and T , Outputs will not retry on

LIM

The third method combines both protection schemes into

one. During a short event the device will enter current limit.

The output driver will shutdown for short conditions lasting

longer than the current limit timer. In the event that the output

driver temperature is higher than maximum specified

temperature the output will shutdown.

period or T

.

LIM

OUT0-OUT3 = 60μs ON, OFF

OUTPUT DRIVER DIAGNOSTICS.

Short to battery, Temperature Limit (T_LIM) and open load

faults are reported through the All Status Response message

Table 21.

The Shutdown/Retry bit allows the user to determine how

the drivers will respond to each short circuit strategy.

Table 18 provides fault operation for all three strategies.

Outputs may be used in parallel to drive higher current

loads provided the turn-off energy of the load does not

exceed the energy rating of a single output driver (100mJ

maximum).

OFF OPEN LOAD PULL-DOWN CURRENT ENABLE

BITS

An open load on the output driver is detected by the

voltage level on the drain of the MOSFET in the off state.

Internal to the device is a 75μA pull-down current sink. In the

event of an open load the drain voltage is pulled low. When

the voltage crosses the threshold, and open load is detected.

The pull-down current source may be disabled by bit 0

through bit 3 in the LSD Fault Command. With the driver off

and the Off Open Load bit disabled, the Off Open Load fault

status bit will be logic 0.

ON OPEN LOAD ENABLE BITS

The On State Open Load enable bit allows the user to

determine an On State Open Load. When the On State Open

Load bit disabled, the On State Fault bit is always logic 0. On

Open Load is determined by monitoring the current through

the OUTx MOSFET. In the ON state, currents less than 20 to

200mA are considered open.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

28

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 19. InjectorDriver Diagnostics

temperature, calibration is required for an accurate time

base. The calibration command should be used to update the

device on a periodic basis.

Program State

Fault

Fault Bits

Off

On

State

Open

Load

Pull

Output OUTx OUTx OUTx

STB Batt OFF ON

On/Off STG Short Open Open

OPEN Fault

State

Open

Load

En Bit

Driver

SPI COMMAND SUMMARY

Fault Reported

The SPI commands are defined as 16 bits with 4 address

control bits and 12 command data bits. There are 12 separate

commands that are used to set operational parameters of

device. The operational parameters are stored internally in

16 bit registers.

Fault

Dwn

No Fault

0

1

X

Off

STB

STG

0

1

0

No Fault

Table 20 defines the commands and default state of the

internal registers at POR. SPI commands may be sent to the

device at any time in NORMAL STATE.

No Fault

Off OPEN

No Fault

Off

STB

STG

Messages sent are acted upon on the rising edge of the

CS input.

Open Load

Off OPEN

Short to Batt

No Fault

X

0

1

On

STB

STG

1

0

1

0

1

No Fault

On OPEN

Short to Batt

Open Load

On

STB

STG

On OPEN

CLOCK CALIBRATION COMMAND

In cases where an accurate time base is required, the user

must calibrate the internal timers using the clock calibration

command (refer to Table 20). After the 33810 device

receives the calibration command, the device expects to

receive a 32μs logic [0] calibration pulse on the CS pin. The

pulse is used to calibrate the internal clock. Any SPI message

may be sent during the 32μs calibration chip select. Because

the oscillator frequency may shift up to 35% with

.

Table 20. SPI Command Message Set and Default State

Command

Control Address Bits

Command Bits

hex

0

15

0

14

0

13

0

12

0

11

1

10

0

9

1

8

0

7

6

5

4

3

0

2

0

1

0

Read Registers Command

<0000>

Internal Register Address

All Status Command

SPI Check Command

Mode Select Command

0

1

0

1

0

1

0

1

0

X

0

X

0

<0000>

<0> <0>

V10 OVR/

En Undr

Vtg

<0> <0> <0> <0>

pwm3 pwm2 pwm1 pwm0

EN

IGN/GP Mode Select

EN

Set to IGN Mode

Disab

Disab Disab Disab Disab

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 20. SPI Command Message Set and Default State

Command

Control Address Bits

Command Bits

hex

2

15

0

14

0

13

1

12

0

11

10

9

8

7

6

5

4

3

2

1

0

LSD Fault Command

<10X>

X

<1> <1> <1> <1> <1> <1> <1> <1>

OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0

ON

LSD Flt Operation

shutdn,Tlim,Timer

ON

ON OFF OFF OFF OFF

Open Open Open Open Open Open Open Open

Load Load Load Load Load Load Load Load

Enabl Enabl Enabl Enabl Enabl Enabl Enabl Enabl

Retry on timer

and No Tlim

Driver ON/OFF Command

0 = OFF, 1 = ON

3

4

0

1

0

1

0

X

<0000>

GPGD

OFF

<0000>

OUTx Driver

OFF

(ignored in Ignition Mode)

Spark Command

<100>

<0> <0> <0> <0> <0>

Max Over Gain Soft Open

Dwell lap

En Dwell Gain Dn En Clmp

Disab Disab = 1 Disab Disab =100 μs

<11>

Open

<01>

End Spark

Max Dwell Timer

MaxDwell

Default=32 ms

Sel Shut 2^edSecondary Threshold

OSFLT

VPWR

+5.5 V

(In Ignition Mode

Only)

End Spark Filter

DAC Command

5

6

0

1

0

1

0

X

<01>

End Spark

Filter

4.0 μs

<1000>

<100>

<01010>

MAXI DAC Threshold

MAXI=14 A

NOMI DAC Threshold

NOMI=5.5 A

Overlap Setting

Overlap 50%

GPGD Short Threshold

Voltage Command

7

8

9

A

0

1

0

1

0

1

0

1

0

<011>

Short to Batt V_FB3Short to Batt V_FB2Short to Batt V_FB1Short to Batt V_FB0

Vth = 2.0 V

GPGD Short Duration

Timer Command

<011>

Short to Batt t_FB3

Timer = 240 μs

<011>

Short to Batt t_FB2Short to Batt t_FB1Short to Batt t_FB0

Timer = 240 μs

GPGD Fault Operation

Select Command

<1111>

Retry/Shutdown Bit

Retry on Fault

X

<0000>

Shutdown Drivers on MAXI

Disabled

PWM0 to PWM3 Freq &

DC Command

<00>

PWMx

address

PWM0

<000>

<0000000>

PWM Duty Cycle

0% Duty Cycle

PWM Frequency

10 Hz

INVALID COMMAND

B

C

D

E

1

0

1

0

1

0

X

Clock Calibration

Command

INVALID COMMAND

F

1

X

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

30

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

faults. Timing between two write words must be greater than

the fault timer to allow adequate time to sense and report the

proper fault status.

SPI RESPONSE REGISTERS

Fault reporting is accomplished through the SPI interface.

All logic [1]s received by the MCU via the SO pin indicate

faults. All logic [0]s received by the MCU via Pin indicate no

.

Table 21. SPI Response Messages

15

0

14

0

13

0

12

0

11

1

10

1

9

0

8

1

7

0

6

0

5

0

4

0

3

1

2

0

1

0

Next SO Response to:

SPI Check Command

Next SO Response to

HEX1 to HEX A

Reset COR SOR

NMF IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0

Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

Commands and Read All

Status Command

ALL STATUS

RESPONSE

Next SO Response to

READ REGISTER

COMMAND

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Address <0000>

All Status Register

0 = No Fault, 1 = Fault

Reset COR SOR

NMF IGN3 IGN2 IGN1 IGN0 GP3 GP2 GP1 GP0 OUT3 OUT2 OUT1 OUT0

Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault Fault

Address <0001>

OUT1, OUT0 Fault

Register

Reset COR OVER LOW

Voltage Voltage

0

OUT1 OUT1 OUT1 OUT1 OUT0 OUT0 OUT0 OUT0

TLIM Batter OFF ON TLIM Batter OFF ON

Fault

y

Open Open Fault

y

Open Open

0 = No Fault, 1 = Fault

Short Fault Fault

Fault

Short Fault Fault

Fault

Address <0010>

OUT3, OUT2 Fault

Register

Reset COR OVER LOW

Voltage Voltage

OUT3 OUT3 OUT3 OUT3 OUT2 OUT2 OUT2 OUT2

TLIM Batter OFF ON TLIM Batter OFF ON

Fault

y

Open Open Fault

y

Open Open

0 = No Fault, 1 = Fault

Short Fault Fault

Fault

Short Fault Fault

Fault

Address <0011>

GPGD Mode Fault

Register

Reset COR OVER LOW

Voltage Voltage

GP3 GP3 GP2 GP2 GP1 GP1 GP0 GP0

Short Open Short Open Short Open Short Open

Circuit Load Circuit Load Circuit Load Circuit Load

Fault Fault Fault Fault Fault Fault Fault Fault

0 = No Fault, 1 = Fault

Address <0100>

IGN Mode Fault Register

0 = No Fault, 1 = Fault

Reset COR OVER LOW IGN3 IGN3 IGN3 IGN2 IGN2 IGN2 IGN1 IGN1 IGN1 IGN0 IGN0 IGN0

Voltage Voltage MAXI Max Open MAXI Max Open MAXI Max Open MAXI Max Open

Fault Dwell Secon Fault Dwell Secon Fault Dwell Secon Fault Dwell Secon

Fault

d

Fault

d

Fault

d

Fault

d

Fault

Address <0101>

Mode Command Register

Reset COR OVER LOW

Voltage Voltage

IGN/GP Mode Select

V10 OVR

En Vtg

X

PWM PWM PWM PWM

3

2

1

0

EN

Address <0110>

LSD Fault Command

Register

Reset COR OVER LOW LSD Flt Operation

Voltage Voltage shutdn,Tlim,Timer

X

OUT3 OUT2 OUT1 OUT0 OUT3 OUT2 OUT1 OUT0

ON ON ON ON OFF OFF OFF OFF

Open Open Open Open Open Open Open Open

Load Load Load Load Load Load Load Load

Reset COR OVER LOW

Voltage Voltage

X

GPGD⁽²⁰⁾

OUTx Driver⁽²⁰⁾

Address <0111>

Drvr ON/OFF Command

Reg

Address <1000>

Spark Command Register

Reset COR OVER LOW

Voltage Voltage

Max Dwell Timer

MaxDwell

Max Over Gain Soft Open

Dwell lap

En Dwell

Open

Secondary

End Spark

Threshold

Sel Shut 2^ed

Dn En Clmp

Notes

20. These bits refer to command On or Off state in the command registers, not the state of the respective output lines. These bits are not to be

confused with the ignition mode state which is controlled only by the parallel inputs and their state is not reflected in these bits.

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

FUNCTIONAL DEVICE OPERATION

OPERATIONAL MODES

Table 21. SPI Response Messages

Address <0101>

End Spark filter Register

Reset COR OVER under

Voltage voltage

X

End spark

Filter

Address <1010>

DAC Command Register

Reset COR OVER LOW

Voltage Voltage

MAXI DAC Threshold

Overlap Setting

NOMI DAC Threshold

Address <1011>

GPGD FBx Short to

Battery Threshold Voltage

Register

Reset COR OVER LOW Short to Batt V_FB3

Voltage Voltage

Short to Batt V_FB2

Short to Batt V_FB1

Short to Batt V_FB0

Short to Batt t_FB0

Address <1100>

GPGD FBx Short to

Battery Threshold Timer

Register

Reset COR OVER LOW

Voltage Voltage

Short to Batt t_FB3

Short to Batt t_FB2

Short to Batt t_FB1

Address <1101>

GPGD Fault Operation

Register

Reset COR OVER LOW

Voltage Voltage

Retry/Shutdown Bit

X

Shutdown Drivers on IMAX

Address <1110>

PWM Freq&DC Register

(last channel

Reset COR OVER LOW

Voltage Voltage

PWMx

address

PWM Frequency

PWM Duty Cycle

programmed)

Address <1111>

Revision ID, Trim, Clock

Cal.

Reset COR OVR

LOW

REV

ID

CAL CAL

Too Too

TRIM TRIM

Parity Lock

Error Out

Vtg Voltage

3

2

1

0

X

HI

LOW

Legend

COR = Command Out of Range

SOR = Supply Out of Range

NMF = Set When Faults Occur on V10 Mode MAXI and NOMI Inputs and V10 Mode Ignition Driver are OFF.

33810

Analog Integrated Circuit Device Data

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32

PACKAGING

PACKAGE DIMENSIONS

PACKAGING

PACKAGE DIMENSIONS

For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” listed below.

EK (Pb-FREE) SUFFIX

32-PIN

98ASA10556D

ISSUE D

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

PACKAGING

PACKAGE DIMENSIONS

.

EK (Pb-FREE) SUFFIX

32-PIN

98ASA10556D

ISSUE D

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

PACKAGING

PACKAGE DIMENSIONS

EK (Pb-FREE) SUFFIX

32-PIN

98ASA10556D

ISSUE D

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

REVISION HISTORY

REVISION

3.0

DATE

DESCRIPTION OF CHANGES

10/2007

2/2008

• Initial Release

• Fixed several typos throughout document

• Changed Static Electrical Characteristics, Table 3, Digital Interface, OUT_EN Leakage

Current to V_DD,maximum from 10 to 50μA.

4.0

• Reworded Table 15.

• Added Table 16 back (it was inadvertently deleted.

• Added “Ignition &” to tile in Table 4.

8/2008

• Updated package drawing.

5.0

6.0

• Parameter changes to Gate Drive Source Current, Spark Duration Comparator Threshold,

NOMI Trip Threshold Accuracy, MAXI Trip Point During Overlapping Dwell, Comparator

Hysteresis Voltage, Short to Battery Fault Detection Voltage Threshold, Output OFF Open

Load Detection Current, and Input Logic-voltage Hysteresis.

12/2008

• Made change to End of Spark Filter Time Select

• Changed orderable Part Number from PCZ33810EK/R2 to MCZ33810EK/R2 on Page 1.

• Revised Exposed Pad pin definition in Table 1, page 3.

• Changed Package outline drawing to 98ASA10556D.

• Changed introduction paragraph to Tables 3 and 4 from “9.0 V ≤ VPWR ≤ 18 V” to “6.0 V ≤

VPWR ≤ 32 V”

7/2010

7.0

•

Changed Gate Driver Parameters of V_GS(ON)from 5.0 to 4.8.

7/2010

2/2011

• Changed Table 3 Characteristics from 18V to 32V for: I_VPWR(SS),I_(OFF)OCOand I_FBX(FLT-SNS)

8.0

9.0

• Changed See Output OFF Open Load Detection Current on page 6 from 100 μA to 115 μA for

the maximum value.

• Corrected Table 13, End of Spark Filter Time Select.

4/2011

10.0

• Corrected Table 20, SPI Command Message Set and Default State (Command: End Spark

Filter).

33810

Analog Integrated Circuit Device Data

Freescale Semiconductor

36

How to Reach Us:

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Information in this document is provided solely to enable system and

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no express or implied copyright licenses granted hereunder to design or

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MC33810

Rev. 10.0

4/2011


型号：	MCZ33810EKR2
厂家：	Rochester Electronics
描述：	6A BUF OR INV BASED PRPHL DRVR, PDSO32, 0.65 MM PITCH, ROHS COMPLIANT, SOIC-32 驱动光电二极管接口集成电路
文件：	总38页 (文件大小：2585K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MCZ33810EKR2 [ROCHESTER]

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