MM74HC4316N [ROCHESTER]
SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16;
| 型号： | MM74HC4316N |
| 厂家： | 
Rochester Electronics |
| 描述： | SPST, 4 Func, 1 Channel, CMOS, PDIP16, 0.300 INCH, PLASTIC, MS-001, DIP-16 光电二极管 |
| 文件： | 总11页 (文件大小：808K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
February 1984
Revised March 2001
MM74HC4316
Quad Analog Switch with Level Translator
General Description
Features
The MM74HC4316 devices are digitally controlled analog
switches implemented in advanced silicon-gate CMOS
technology. These switches have low “ON” resistance and
low “OFF” leakages. They are bidirectional switches, thus
any analog input may be used as an output and vice-versa.
Three supply pins are provided on the MM74HC4316 to
implement a level translator which enables this circuit to
operate with 0–6V logic levels and up to ±6V analog switch
levels. The MM74HC4316 also has a common enable input
in addition to each switch's control which when HIGH will
disable all switches to their OFF state. All analog inputs
and outputs and digital inputs are protected from electro-
static damage by diodes to VCC and ground.
■ Typical switch enable time: 20 ns
■ Wide analog input voltage range: ±6V
■ Low “ON” resistance:
50 typ. (VCC−VEE = 4.5V) 30 typ. (VCC−VEE = 9V)
■ Low quiescent current: 80 µA maximum (74HC)
■ Matched switch characteristics
■ Individual switch controls plus a common enable
Ordering Code:
Order Number
MM74HC4316M
MM74HC4316SJ
MM74HC4316MTC
MM74HC4316N
Package Number
M16A
Package Description
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
M16D
MTC16
N16E
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Logic Diagram
Connection Diagram
Top View
Truth Table
Inputs
Switch
En
H
L
CTL
X
I/O–O/I
“OFF”
“OFF”
“ON”
L
L
H
© 2001 Fairchild Semiconductor Corporation
DS005369
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Absolute Maximum Ratings(Note 1)
(Note 2)
Recommended Operating
Conditions
Supply Voltage (VCC
Supply Voltage (VEE
DC Control Input Voltage (VIN
DC Switch I/O Voltage (VIO
Clamp Diode Current (IIK, IOK
DC Output Current, per pin (IOUT
DC VCC or GND Current, per pin (ICC
)
−0.5 to +7.5V
+0.5 to −7.5V
−1.5 to VCC +1.5V
EE−0.5 to VCC +0.5V
±20 mA
Min
Max
6
Units
)
Supply Voltage (VCC
Supply Voltage (VEE
DC Input or Output Voltage
(VIN, VOUT
)
2
0
V
V
)
)
−6
)
V
)
)
0
VCC
V
)
±25 mA
Operating Temperature Range (TA) −40
Input Rise or Fall Times
+85
°C
)
±50 mA
Storage Temperature Range (TSTG
Power Dissipation (PD)
(Note 3)
)
−65°C to +150°C
(tr, tf) VCC = 2.0V
1000
500
400
250
ns
ns
ns
ns
VCC = 4.5V
VCC = 6.0V
VCC = 12.0V
600 mW
500 mW
S.O. Package only
Lead Temperature (TL)
(Soldering 10 seconds)
Note 1: Absolute Maximum Ratings are those values beyond which dam-
age to the device may occur.
260°C
Note 2: Unless otherwise specified all voltages are referenced to ground.
Note 3: Power Dissipation temperature derating — plastic “N” package: −
12 mW/°C from 65°C to 85°C.
DC Electrical Characteristics (Note 4)
T
A = 25°C
TA = −40 to 85°C TA = −55 to 125°C
VEE
VCC
Symbol
Parameter
Conditions
Units
Typ
Guaranteed Limits
VIH
Minimum HIGH Level
Input Voltage
2.0V
4.5V
6.0V
2.0V
4.5V
6.0V
4.5V
1.5
3.15
4.2
0.5
1.35
1.8
170
85
1.5
3.15
4.2
0.5
1.35
1.8
200
105
85
1.5
3.15
4.2
0.5
1.35
1.8
220
110
90
V
V
V
VIL
Maximum LOW Level
Input Voltage
V
V
V
RON
Minimum “ON” Resistance
V
CTL = VIH, IS = 2.0 mA
IS = VCC to VEE
GND
100
40
30
100
40
50
20
10
5
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
Ω
µA
(Note 5)
V
−4.5V 4.5V
−6.0V 6.0V
(Figure 1)
70
GND
GND
2.0V
4.5V
180
80
215
100
75
240
120
80
V
CTL = VIH, IS = 2.0 mA
IS = VCC or VEE
V
−4.5V 4.5V
−6.0V 6.0V
60
(Figure 1)
40
60
70
RON
Maximum “ON” Resistance
VCTL = VIH
GND
4.5V
15
20
20
Matching
VIS = VCC to VEE
−4.5V 4.5V
−6.0V 6.0V
10
15
15
5
10
15
15
IIN
Maximum Control
Input Current
VIN = VCC or GND
GND
6.0V
±0.1
±1.0
±1.0
IIZ
Maximum Switch “OFF”
Leakage Current
V
V
V
V
V
OS = VCC or VEE
IS = VEE or VCC
CTL = VIL (Figure 2)
IS = VCC to VEE
GND
6.0V
±60
±600
±600
nA
nA
−6.0V 6.0V
±100
±1000
±1000
IIZ
Maximum Switch “ON”
GND
6.0V
±40
±60
±150
±300
±150
±300
nA
nA
Leakage Current
CTL = VIH, VOS = OPEN −6.0V 6.0V
(Figure 3)
IN = VCC or GND
OUT = 0 µA
ICC
Maximum Quiescent
Supply Current
V
GND
6.0V
2.0
8.0
20
80
40
µA
µA
I
−6.0V 6.0V
160
Note 4: For a power supply of 5V ±10% the worst case on resistances (RON) occurs for HC at 4.5V. Thus the 4.5V values should be used when designing
with this supply. Worst case VIH and VIL occur at VCC = 5.5V and 4.5V respectively. (The VIH value at 5.5V is 3.85V.) The worst case leakage current occurs
for CMOS at the higher voltage and so the 5.5V values should be used.
Note 5: At supply voltages (VCC–VEE) approaching 2V the analog switch on resistance becomes extremely non-linear. Therefore it is recommended that
these devices be used to transmit digital only when using these supply voltages.
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2
AC Electrical Characteristics
VCC = 2.0V−6.0V, VEE = 0V−6V, CL = 50 pF (unless otherwise specified)
T
A = +25°C
TA = −40°C to +85°C TA = −55°C to +125°C
VEE VCC
Symbol
Parameter
Conditions
Units
Typ
25
5
Guaranteed Limits
tPHL
,
Maximum Propagation
Delay Switch
GND 2.0V
GND 4.5V
−4.5V 4.5V
−6.0V 6.0V
GND 2.0V
GND 4.5V
−4.5V 4.5V
−6.0V 6.0V
GND 2.0V
GND 4.5V
−4.5V 4.5V
−6.0V 6.0V
GND 2.0V
GND 4.5V
−4.5V 4.5V
−6.0V 6.0V
GND 2.0V
GND 4.5V
−4.5V 4.5V
−6.0V 6.0V
50
10
8
63
13
75
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tPLH
In to Out
4
12
14
3
7
11
13
tPZL
,
Maximum Switch
Turn “ON” Delay
(Control)
R
L = 1 kΩ
30
20
15
14
45
25
20
20
35
20
19
18
58
28
23
21
40
100
165
35
32
30
250
50
44
44
205
41
38
36
265
53
47
47
206
43
250
53
tPZH
39
48
37
45
tPHZ
,
Maximum Switch
Turn “OFF” Delay
(Control)
R
L = 1 kΩ
312
63
375
75
tPLZ
55
66
55
66
tPZL
,
Maximum Switch
Turn “ON” Delay
(Enable)
256
52
308
62
ns
ns
tPZH
48
57
ns
45
54
ns
tPLZ
,
Maximum Switch
Turn “OFF” Delay
(Enable)
330
67
400
79
ns
tPHZ
ns
59
70
ns
59
70
ns
fMAX
Minimum Frequency
Response (Figure 7)
R
L = 600Ω, VIS = 2VPP
0V
4.5
MHz
MHz
at (VCC−VEE/2)
−4.5V 4.5V
20 log (VOS/VIS)= −3 dB (Note 6) (Note 7)
Control to Switch
Feedthrough Noise
(Figure 8)
R
L = 600Ω, F = 1 MHz
L = 50 pF
0V 4.5V
100
250
mV
mV
C
−4.5V 4.5V
(Note 7) (Note 8)
Crosstalk Between
any Two Switches
(Figure 9)
R
L = 600Ω, F = 1 MHz
0V 4.5V
−52
−50
dB
dB
−4.5V 4.5V
Switch OFF Signal
Feedthrough Isolation
(Figure 10)
R
L = 600Ω, F = 1 MHz
V
CTL = VIL
(Note 7) (Note 8)
L = 10 KΩ, CL = 50 pF,
F = 1 KHz
,
0V 4.5V
−42
−44
dB
dB
−4.5V 4.5V
THD
Sinewave Harmonic
Distortion
R
(Figure 11)
V
IS = 4VPP 0V 4.5V 0.013
%
%
VIS = 8VPP −4.5V 4.5V 0.008
CIN
CIN
CIN
CPD
Maximum Control
Input Capacitance
Maximum Switch
Input Capacitance
Maximum Feedthrough
Capacitance
5
pF
35
0.5
15
pF
pF
pF
VCTL = GND
Power Dissipation
Capacitance
Note 6: Adjust 0 dBm for F = 1 KHz (Null RL/Ron Attenuation).
Note 7: VIS is centered at VCC–VEE/2.
Note 8: Adjust for 0 dBm.
3
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AC Test Circuits and Switching Time Waveforms
FIGURE 1. “ON” Resistance
FIGURE 2. “OFF” Channel Leakage Current
FIGURE 3. “ON” Channel Leakage Current
FIGURE 4. tPHL, tPLH Propagation Delay Time Signal Input to Signal Output
FIGURE 5. tPZL, tPLZ Propagation Delay Time Control to Signal Output
FIGURE 6. tPZH, tPHZ Propagation Delay Time Control to Signal Output
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4
AC Test Circuits and Switching Time Waveforms (Continued)
FIGURE 7. Frequency Response
FIGURE 8. Crosstalk: Control Input to Signal Output
FIGURE 9. : Crosstalk Between Any Two Switches
FIGURE 10. Switch OFF Signal Feedthrough Isolation
FIGURE 11. Sinewave Distortion
5
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Typical Performance Characteristics
Typical “ON” Resistance
Typical Crosstalk Between
Any Two Switches
Typical Frequency Response
Special Considerations
In certain applications the external load-resistor current
the analog switch input pins, the voltage drop across the
switch must not exceed 0.6V (calculated from the On
Resistance).
may include both VCC and signal line components. To
avoid drawing VCC current when switch current flows into
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6
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow
Package Number M16A
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M16D
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC16
9
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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10
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