MT55V512V32PT-10_技术文档

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

MT55L1MY18P, MT55V1MV18P,

MT55L512Y32P, MT55V512V32P,

MT55L512Y36P, MT55V512V36P

3.3V VDD, 3.3V or 2.5V I/O; 2.5V VDD, 2.5V I/O

18Mb ZBT^®SRAM

Features

Figure 1: 100-Pin TQFP

JEDEC-Standard MS-026 BHA (LQFP)

•

High frequency and 100 percent bus utilization

Single 3.3V ±± percent or 2.±V ±± percent power supply

Separate 3.3V ±± percent or 2.±V ±± percent isolated

output buffer supply (VDDQ)

•

Advanced control logic for minimum control signal

interface

•

Individual byte write controls may be tied LOW

Single R/W# (read/write) control pin/ball

CKE# pin/ball to enable clock and suspend operations

Three chip enables for simple depth expansion

Clock-controlled and registered addresses, data

I/Os, and control signals

Internally self-timed, fully coherent WRITE

Internally self-timed, registered outputs to eliminate

the need to control OE#

•

SNOOZE MODE for reduced-power standby

Common data inputs and data outputs

Linear or Interleaved Burst Modes

Figure 2: 165-Ball FBGA

JEDEC-Standard MS-216 (Var. CAB-1)

Burst feature (optional)

Pin and ball/function compatibility with 2Mb, 4Mb,

and 8Mb ZBT SRAM

TQFP

Options

Marking

•

Timing (Access/Cycle/MHz)

3.2ns/±ns/200 MHz

3.±ns/6ns/166 MHz

4.2ns/7.±ns/133 MHz

±ns/10ns/100 MHz

Configurations

3.3V VDD, 3.3V, or 2.±V I/O

1 Meg x 18

-±

-6

-7.±

-10

•

MT±±L1MY18P

MT±±L±12Y32P

MT±±L±12Y36P

Part Number Example:

±12K x 32

±12K x 36

MT55L512Y36PT-10

2.±V VDD, 2.±V I/O

1 Meg x 18

±12K x 32

±12K x 36

Packages

100-pin TQFP

MT±±V1MV18P

MT±±V±12V32P

MT±±V±12V36P

General Description

The Micron^®Zero Bus Turnaround™ (ZBT^®) SRAM

family employs high-speed, low-power CMOS designs

using an advanced CMOS process.

•

T

F¹

Micron’s 18Mb ZBT SRAMs integrate a 1 Meg x 18,

±12K x 32, or ±12K x 36 SRAM core with advanced syn-

16±-ball, 13mm x 1±mm FBGA

Operating Temperature Range

chronous peripheral circuitry and

a 2-bit burst

Commercial (0ºC

?

T_A

?

+70ºC)

None

IT²

counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles for

READ to WRITE, or WRITE to READ, transitions. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input (CLK).

The synchronous inputs include all addresses, all data

inputs, chip enable (CE#), two additional chip enables

Industrial (-40ºC

?

T_A

?

+8±ºC)

NOTE:

1. A Part Marking Guide for the FBGA devices can be found on

Micron’s Web site—http://www.micron.com/numberguide.

2. Contact Factory for availability of Industrial Temperature

devices.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

1

PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

for easy depth expansion (CE2, CE2#), cycle start input

(ADV/LD#), synchronous clock enable (CKE#), byte

write enables (BWa#, BWb#, BWc# and BWd#), and

read/write (R/W#).

cycle one, the address is present on rising edge one.

BYTE WRITEs need to be asserted on the same cycle as

the address. The data associated with the address is

required two cycles later, or on the rising edge of clock

cycle three.

Address and write control are registered on-chip to

simplify WRITE cycles. This allows self-timed write

cycles. Individual byte enables allow individual bytes

to be written. During a BYTE WRITE cycle, BWa# con-

trols DQa pins/balls; BWb# controls DQb pins/balls;

BWc# controls DQc pins/balls; and BWd# controls

DQd pins/balls. Cycle types can only be defined when

an address is loaded, i.e., when ADV/LD# is LOW. Par-

ity/ECC bits are only available on the x18 and x36 ver-

sions.

Asynchronous inputs include the output enable

(OE#, which may be tied LOW for control signal mini-

mization), clock (CLK) and snooze enable (ZZ, which

may be tied LOW if unused). There is also a burst mode

pin/ball (MODE) that selects between interleaved and

linear burst modes. MODE may be tied HIGH, LOW or

left unconnected if burst is unused. The data out (Q) is

enabled by OE#. WRITE cycles can be from one to four

bytes wide as controlled by the write control inputs.

All READ, WRITE, and DESELECT cycles are initi-

ated by the ADV/LD# input. Subsequent burst

addresses can be internally generated as controlled by

the burst advance pin/ball (ADV/LD#). Use of burst

mode is optional. It is allowable to give an address for

each individual READ and WRITE cycle. BURST cycles

wrap around after the fourth access from a base

address.

The device is ideally suited for systems requiring

high bandwidth and zero bus turnaround delays.

Please refer to Micron’s Web site (www.micron.com/

sramds) for the latest data sheet.

Dual Voltage I/O

To allow for continuous, 100 percent use of the data

bus, the pipelined ZBT SRAM uses a late LATE WRITE

cycle. For example, if a WRITE cycle begins in clock

The 3.3V VDD device is tested for 3.3V and 2.±V I/O

function. The 2.±V VDD device is tested for only 2.±V

I/O function.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

2

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 3: Functional Block Diagram

1 Meg x 18

18

20

ADDRESS

SA0, SA1, SA

REGISTER 0

SA1

SA0

SA1'

SA0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

K

ADV/LD#

K

CLK

CKE#

20

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

20

O

U

T

O

U

T

P

S

E

N

S

P

D

A

T

U

T

U

T

ADV/LD#

BWa#

1 Meg x 9 x 2

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A

R

E

G

I

E

B

U

F

WRITE

DRIVERS

S

T

E

R

I

DQs

DQPa

DQPb

18

A

M

P

MEMORY

ARRAY

F

S

T

E

R

S

E

R

S

BWb#

R/W#

S

N

G

E

18

INPUT

REGISTER 1

INPUT

REGISTER 0

E

OE#

CE#

READ LOGIC

CE2

CE2#

Figure 4: Functional Block Diagram

512K x 32/36

17

19

ADDRESS

SA0, SA1, SA

REGISTER 0

SA1

SA0

SA1'

SA0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

K

ADV/LD#

K

CLK

CKE#

19

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

19

O

U

T

O

U

T

P

S

E

N

S

P

D

A

T

U

T

ADV/LD#

BWa#

BWb#

BWc#

U

T

512K x 8 x 4

(x32)

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A

R

E

G

I

E

B

U

F

DQs

512K x 9 x 4

(x36)

WRITE

DRIVERS

36

S

36

A

M

P

DQPa

DQPb

DQPc

DQPd

T

E

R

I

F

S

T

E

R

S

MEMORY

ARRAY

E

R

S

BWd#

R/W#

N

G

E

36

E

INPUT

REGISTER 1

INPUT

REGISTER 0

OE#

CE#

READ LOGIC

CE2

CE2#

NOTE:

1. Functional block diagrams illustrate simplified device operation. See truth tables, pin/ball descriptions, and timing dia-

grams for detailed information.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

3

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 5: Pin Layout (Top View)

100-Pin TQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

SA

3

DNU

V

SS

DD

V

DD

SS

V

x18

CE2#

BWa#

BWb#

NC

DNU

SA0

SA1

SA

NC

CE2

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81

SA

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

SA

3

DNU

V^DD

VSS

V^SS

VDD

x32/x36

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

SA

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

2. Pins 14, 16, and 66 do not have to be connected directly to VDD if the input voltage is O VIH.

3. Pins 43 and 42 are reserved for address expansion; 36Mb and 72Mb, respectively.

.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

4

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 1:

TQFP Pin Descriptions

SYMBOL

TYPE

DESCRIPTION

ADV/LD#

Input

Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal

burst counter, controlling burst access after the external address is loaded. When ADV/LD# is

HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be

written when a WRITE cycle is active and must meet the setup and hold times around the

rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are

associated with addresses and apply to subsequent data. BWa# controls DQa pins; BWb#

controls DQb pins; BWc# controls DQc pins; BWd# controls DQd pins.

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW).

CE2#

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

CKE#

Synchronous Clock Enable: This active LOW input permits CLK to propagate throughout the

device. When CKE# is HIGH, the device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet setup and hold times around the rising

edge of CLK.

CLK

Input

Clock: This signal registers the address, data, chip enables, byte write enables, and burst

control inputs on its rising edge. All synchronous inputs must meet setup and hold times

around the clock’s rising edge.

MODE (LBO#)

Mode: This input selects the burst sequence. A LOW on this pin selects linear burst. NC or

HIGH on this pin selects interleaved burst. Do not alter input state while device is operating.

LBO# is the JEDEC-standard term for MODE.

OE# (G#)

R/W#

Input

Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#

is the JEDEC-standard term for OE#.

Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only

means for determining READs and WRITEs. READ cycles may not be converted into WRITEs

(and vice versa) other than by loading a new address. A LOW on this pin permits BYTE WRITE

operations and must meet the setup and hold times around the rising edge of CLK. Full bus-

width WRITEs occur if all byte write enables are LOW.

SA0

SA1

SA

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of

the address field and set the internal burst counter if burst is desired.

ZZ

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This pin has an internal pull-down and can be left unconnected.

DQa

DQb

DQc

DQd

Input/

Output

SRAM Data I/Os: Byte “a” associated with is DQa pins; byte “b” is associated with DQb pins;

byte “c” is associated with DQc pins; byte “d” is associated withDQd pins. Input data must

meet setup and hold times around the rising edge of CLK.

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF

I/O

No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18

version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity

is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.

VDD

Supply

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

VDDQ

Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for

range.

VSS

Supply

Ground: GND.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

5

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 1:

TQFP Pin Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

DNU

–

Do Not Use: These pins are internally connected to the die. They may be left floating or

connected to ground to improve package heat dissipation.

NC

NF

No Connect: These pins are not internally connected to the die. They may be left floating,

driven by signals, or connected to ground to improve package heat dissipation.

No Function: These pins are internally connected to the die and have the capacitance of an

input pin. They may be left floating, driven by signals, or connected to ground to improve

package heat dissipation.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

6

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 6: Ball Layout (Top View)

165-Ball FBGA

x18

x32/x36

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

NC

SA

NC

CE# BWc# BWb# CE2# CKE# ADV/LD# SA

CE2 BWd# BWa# CLK R/W# OE# (G#) SA

SA

NC

SA

NC

CE# BWb#

NC

CE2# CKE# ADV/L D# SA

SA

NC

SA

NC

CE2

NC

VSS

BWa# CLK R/W# OE# (G#) SA

1

NC NF/DQPb

NF/DQPc

DQc

VDD

VDDQ

VSS

VDD

VSS

NC

VSS

NF

VSS

VDD

TDO

TCK

VSS

VDD

VSS

VDDQ

NC

VDDQ

VSS

NC

VSS

NF

VSS

VDD

TDO

TCK

VSS

VDD

VSS

VDDQ

NC

DQPa

DQa

ZZ

DQc VDDQ

VDDQ DQb DQb

NC

DQb VDDQ

VDD

VSS

NC

F

NC

G

H

J

G

H

J

G

H

J

G

H

J

NC

VDD

NC

ZZ

VDD

DQb

DQPb

NC

VDD

NC

DQd DQd VDDQ

VDDQ DQa DQa

VDDQ

SA

VDDQ DQa

NC

K

L

K

L

K

L

K

L

NC

M

N

P

M

N

P

M

N

P

M

N

P

DQd DQd VDDQ

NC

1

NC NF/DQPa

NF/DQPd

NC

VDDQ

SA

VDDQ

SA

VDDQ

SA

NC

SA

NC

2

NC

2

NC

SA

TDI

TMS

SA1

SA0

SA

NF

SA

TDI

TMS

SA1

SA0

SA

NF

R

2

MODE NC

(LBO#)

SA

MODE NC

(LBO#)

SA

TOP VIEW

NOTE:

1. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

2. Balls 2R and 2P are reserved for address expansion; 36Mb and 72Mb, respectively.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

7

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 2:

FBGA Ball Descriptions

SYMBOL

TYPE

DESCRIPTION

ADV/LD#

Input

Synchronous Address Advance/Load: When HIGH, this input is used to advance the internal

burst counter, controlling burst access after the external address is loaded. When ADV/LD# is

HIGH, R/W# is ignored. A LOW on ADV/LD# clocks a new address at the CLK rising edge.

BWa#

BWb#

BWc#

BWd#

Input

Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be

written when a WRITE cycle is active and must meet the setup and hold times around the

rising edge of CLK. BWs need to be asserted on the same cycle as the address. BWs are

associated with addresses and apply to subsequent data. BWa# controls DQa balls; BWb#

controls DQb balls; BWc# controls DQc balls; BWd# controls DQd balls.

CE#

Input

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW).

CE2#

Synchronous Chip Enable: This active LOW input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

CE2

Input

Synchronous Chip Enable: This active HIGH input is used to enable the device and is sampled

only when a new external address is loaded (ADV/LD# LOW). This input can be used for

memory depth expansion.

CKE#

Synchronous Clock Enable: This active LOW input permits CLK to propogate throughout the

device. When CKE# is HIGH, the device ignores the CLK input and effectively internally

extends the previous CLK cycle. This input must meet the setup and hold times around the

rising edge of CLK.

CLK

Input

Clock: This signal registers the address, data, chip enables, byte write enables, and burst

control inputs on its rising edge. All synchronous inputs must meet setup and hold times

around the clock’s rising edge.

MODE (LBO#)

Mode: This input selects the burst sequence. A LOW on this input selects “linear burst.” NC or

HIGH on this input selects “interleaved burst.” Do not alter input state while device is

operating. LBO# is the JEDEC-standard term for MODE.

OE# (G#)

R/W#

Input

Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. G#

is the JEDEC-standard term for OE#.

Read/Write: This input determines the cycle type when ADV/LD# is LOW and is the only

means for determining READs and WRITEs. READ cycles may not be converted into WRITEs

(and vice versa) other than by loading a new address. A LOW on this ball permits BYTE WRITE

operations to meet the setup and hold times around the rising edge of CLK. Full bus-width

WRITEs occur if all byte write enables are LOW.

SA0

SA1

SA

Input

Synchronous Address Inputs: These inputs are registered and must meet the setup and hold

times around the rising edge of CLK. SA0 and SA1 are the two least significant bits (LSB) of

the address field and set the internal burst counter if burst is desired.

TMS

TDI

TCK

IEEE 1149.1 Test Inputs: JEDEC-standard 3.3V and 2.5V I/O levels. These balls may be left not

connected if the JTAG function is not used in the circuit.

ZZ

Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power

standby mode in which all data in the memory array is retained. When ZZ is active, all other

inputs are ignored. This ball has an internal pull-down and can be left unconnected.

DQa

DQb

DQc

DQd

Input/

Output

SRAM Data I/Os: For the x18 version, byte “a” is associated with DQa balls; byte “b” is

associated with DQb balls. For the x32 and x36 versions, byte “a” is associated with DQa

balls; byte “b” is associated with DQb balls; byte “c” is associated with DQc balls; byte “d” is

associated with DQd balls. Input data must meet setup and hold times around the rising

edge of CLK.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

8

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 2:

FBGA Ball Descriptions (continued)

SYMBOL

TYPE

DESCRIPTION

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF

I/O

No Function/Parity Data I/Os: On the x32 version, these are No Function (NF). On the x18

version, byte “a” parity is DQPa; byte “b” parity is DQPb. On the x36 version, byte “a” parity

is DQPa; byte “b” parity is DQPb; byte “c” parity is DQPc; byte “d” parity is DQPd.

TDO

VDD

Output

Supply

IEEE 1149.1 Test Output: JEDEC-standard 3.3V and 2.5V I/O levels.

Power Supply: See DC Electrical Characteristics and Operating Conditions for range.

VDDQ

Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for

range.

VSS

NC

Supply

–

Ground: GND.

No Connect: These balls are not internally connected to the die. They may be left floating,

driven by signals, or connected to ground to improve package heat dissipation.

NF

–

No Function: These balls are internally connected to the die and have the capacitance of an

input ball. They may be left floating, driven by signals, or connected to ground to improve

package heat dissipation.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

9

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 3:

Interleaved Burst Address Table (Mode = NC or HIGH)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

(INTERNAL)

FOURTH ADDRESS

(INTERNAL)

X…X00

X…X01

X…X10

X…X11

X…X01

X…X00

X…X11

X…X10

X…X11

X…X00

X…X01

X…X11

X…X10

X…X01

X…X00

Table 4:

Linear Burst Address Table (Mode = LOW)

FIRST ADDRESS

(EXTERNAL)

SECOND ADDRESS

(INTERNAL)

THIRD ADDRESS

FOURTH ADDRESS

(INTERNAL)

X…X00

X…X01

X…X10

X…X11

X…X01

X…X10

X…X11

X…X00

X…X10

X…X11

X…X00

X…X01

X…X11

X…X00

X…X01

X…X10

Table 5:

Partial Truth Table For READ/WRITE Commands (x18)

FUNCTION

R/W#

BWa#

BWb#

H

L

X

L

X

H

L

READ

WRITE Byte “a”

WRITE Byte “b”

WRITE All Byte

WRITE ABORT/NOP

H

L

H

NOTE:

Using R/W# and byte write(s), any one or more bytes may be written.

Table 6:

Partial Truth Table For READ/WRITE Commands (x32/x36)

FUNCTION

R/W#

BWa#

BWb#

BWc#

BWd#

H

L

X

L

X

H

L

X

H

L

X

H

L

READ

WRITE Byte “a”

WRITE Byte “b”

WRITE Byte “c”

WRITE Byte “d”

WRITE All Byte

WRITE ABORT/NOP

H

L

H

L

H

L

H

NOTE:

Using R/W# and byte write(s), any one or more bytes may be written.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

10

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 7:

State Diagram For ZBT SRAM

DS

BURST

DS

DESELECT

WRITE

READ

BEGIN

READ

BEGIN

WRITE

BURST

READ

BURST

WRITE

BURST

READ

BURST

WRITE

BURST

KEY:

COMMAND OPERATION

DS

DESELECT

READ

WRITE

BURST

New READ

New WRITE

BURST READ,

BURST WRITE, or

CONTINUE DESELECT

NOTE:

1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

11

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 7:

Notes: 5–10

Truth Table

ADDRESS

USED

ADV/

LD# R/W# BWx OE# CKE# CLK

OPERATION

CE# CE2# CE2

ZZ

DQ

NOTES

None

H

X

H

X

L

X

L

LJH High-Z

DESELECT CYCLE

DESELECT Cycle

L

X

H

1

CONTINUE

DESELECT Cycle

READ Cycle (Begin

Burst)

External

X

L

X

L

H

X

H

X

H

X

H

X

L

H

L

H

L

H

X

H

X

L

X

L

H

X

LJH

Q

1, 11

2

READ Cycle

(Continue Burst)

External

H

X

LJH High-Z

NOP/DUMMY READ

(Begin Burst)

DUMMY READ

(Continue Burst)

X

L

X

L

H

L

LJH High-Z 1, 2, 11

External

LJH

D

3

WRITE Cycle (Begin

Burst)

X

L

X

L

H

L

X

L

1, 3, 11

2, 3

WRITE Cycle

(Continue Burst)

NOP/WRITE ABORT

(Begin Burst)

None

H

X

LJH High-Z

X

H

X

LJH High-Z 1, 2, 3,

WRITE ABORT

(Continue Burst)

11

Current

None

LJH

–

4

IGNORE CLOCK

EDGE (Stall)

SNOOZE MODE

X

High-Z

NOTE:

1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ

or WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT

cycle is executed first.

2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external opera-

tion. A WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn

off the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet

an application’s requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it

occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the

IGNORE CLOCK EDGE cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc#, and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to byte “a” (DQa pins/balls); BWb# enables WRITEs to byte “b” (DQb pins/balls); BWc#

enables WRITEs to byte “c” (DQc pins/balls); BWd# enables WRITEs to byte “d” (DQd pins/balls).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

8. Wait states are inserted by setting CKE# HIGH.

9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth BURST CYCLE.

11. The address counter is incremented for all CONTINUE BURST cycles.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

12

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Stresses greater than those listed may cause perma-

nent damage to the device. This is a stress rating only,

and functional operation of the device at these or any

other conditions above those indicated in the opera-

tional sections of this specification is not implied.

Exposure to absolute maximum rating conditions for

extended periods may affect reliability.

Absolute Maximum Ratings

3.3V VDD

Voltage on VDD Supply

Relative to VSS ..................................-0.±V to +4.6V

Voltage on VDDQ Supply

Relative to VSS .................................... -0.±V to VDD

VIN (Inputs) ............................. -0.±V to VDD + 0.±V

VIN (DQs) .............................. -0.±V to VDDQ + 0.±V

Storage Temperature (TQFP).................-±±ºC to +1±0ºC

Storage Temperature (FBGA).................-±±ºC to +12±ºC

Junction Temperature .......................................... +1±0ºC

Short Circuit Output Current ...............................100mA

Junction temperature depends upon package type,

cycle time, loading, ambient temperature, and airflow.

2.5V VDD

Voltage on VDD Supply

Relative to VSS ..................................-0.3V to +3.6V

Voltage on VDDQ Supply Relative

to VSS ................................................-0.3V to +3.6V

VIN (Inputs) ............................. -0.3V to VDD + 0.3V

VIN (DQs) .............................. -0.3V to VDDQ + 0.3V

Storage Temperature (TQFP).................-±±ºC to +1±0ºC

Storage Temperature (FBGA).................-±±ºC to +12±ºC

Junction Temperature .......................................... +1±0ºC

Short Circuit Output Current ...............................100mA

Table 8:

3.3V VDD, 3.3V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; VDD and VDDQ = 3.3V 0.165V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

VIH

VIL

ILI

2.0

-0.3

-1.0

VDD + 0.3

0.8

V

1, 2

4

0V ? VIN ? VDD

1.0

µA

Output Leakage Current

Output(s) disabled,

ILO

1.0

0V ? VIN ? VDD

Output High Voltage

Output Low Voltage

Supply Voltage

IOH = -4.0mA

IOL = 8.0mA

VOH

VOL

2.4

V

1

0.4

3.465

VDD

3.135

1

Isolated Output Buffer Supply

VDDQ

1, 5

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

13

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 9:

3.3V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V and VDDQ = 2.5V 0.125V unless

otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Data bus (DQx)

Inputs

VIHQ

VIH

VIL

1.7

VDDQ + 0.3

VDD + 0.3

0.7

V

1, 2

4

-0.3

-1.0

V

Input Low (Logic 0) Voltage

Input Leakage Current

0V ? VIN ? VDD

ILI

1.0

µA

Output(s) disabled,

0V ? VIN ? VDDQ

(DQX)

ILO

1.0

Output Leakage Current

IOH = -2.0mA

IOH = -1.0mA

IOL = 2.0mA

IOL = 1.0mA

VOH

VOL

1.7

2.0

–

V

1

Output High Voltage

Output Low Voltage

–

0.7

1

VOL

–

0.4

1

VDD

VDDQ

3.135

2.375

3.465

2.625

1

Supply Voltage

1, 5

Isolated Output Buffer Supply

Table 10: 2.5V VDD, 2.5V I/O DC Electrical Characteristics and Operating Conditions

Notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; VDD and VDDQ = 2.5V 0.125V unless otherwise

noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Data bus (DQx)

Inputs

VIHQ

VIH

VIL

1.7

VDDQ + 0.3

VDD + 0.3

0.7

V

1, 3

4

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

-0.3

-1.0

V

0V ? VIN ? VDD

ILI

1.0

µA

Output Leakage Current

Output(s) disabled,

0V ? VIN ? VDDQ

(DQX)

ILO

1.0

IOH = -2.0mA

IOH = -1.0mA

IOL = 2.0mA

IOL = 1.0mA

VOH

VOL

1.7

2.0

–

V

1

Output High Voltage

Output Low Voltage

–

0.7

1

VOL

–

0.4

1

Supply Voltage

VDD

VDDQ

2.375

2.625

1

Isolated Output Buffer Supply

1, 5

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

14

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 11: TQFP Capacitance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

CI

CO

CA

4.2

3.5

4

5

4

5

pF

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Input Capacitance

Clock Capacitance

T_A= 25°C; f = 1 MHz

VDD = 3.3V

CCK

4.2

Table 12: FBGA Capacitance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

MAX

UNITS

CI

CO

CA

4

5

pF

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Input Capacitance

Clock Capacitance

4.5

5

T_A= 25°C; f = 1 MHz

VDD = 3.3V

CCK

5.5

Table 13: TQFP Thermal Resistance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

Junction to Ambient

(Airflow of 1m/s, two-layer

board)

ꢀ

28.9

°C/W

Test conditions follow standard test methods

JA

and procedures for measuring thermal

impedance, per EIA/JESD51.

Thermal Resistance

Junction to Case (Top)

ꢀ

4.2

°C/W

JC

Table 14: FBGA Thermal Resistance

Note 10; notes appear following parameter tables on page 18

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS

Junction to Ambient

(Airflow of 1m/s, two-layer

board)

ꢀ

32

°C/W

JA

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

ꢀ

Junction to Case (Top)

1.7

°C/W

JC

ꢀ

Junction to Board (Bottom)

10.4

JB

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

15

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 15: 3.3V VDD, IDD Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 32/36)

Notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; VDD and VDDQ = 3.3V 0.165V or 2.5V 0.125V

unless otherwise noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-5

-6

-7.5

-10

UNITS NOTES

Device selected; All inputs ?ꢁVIL

Power Supply

Current:

Operating

t

IDD

300

420

380

340

300

mA

6, 7, 8

7, 8

or OꢁVIH; Cycle time Oꢁ KC (MIN);

VDD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; VDD = MAX;

CKE# OꢁVIH; All inputs ?ꢁVSS + 0.2

IDD1

ISB2

120

8

180

30

170

30

160

30

150

30

t

or OꢁVDD - 0.2; Cycle time Oꢁ KC (MIN)

Device deselected; VDD = MAX;

All inputs ?ꢁVSS + 0.2 or OꢁVDD - 0.2;

All inputs static; CLK frequency = 0

CMOS Standby

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# OꢁVIH; All inputs ?ꢁVSS + 0.2

ISB4

120

8

180

30

170

30

160

30

150

30

mA

7, 8

8

t

or OꢁVDD - 0.2; Cycle time Oꢁ KC (MIN)

ZZ OꢁVIH

ISB2Z

Table 16: 2.5V VDD, IDD Operating Conditions and Maximum Limits

(1 Meg x 18 and 512K x 32/36)

Notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; VDD and VDDQ = 2.5V 0.125V unless otherwise

noted

MAX

DESCRIPTION

CONDITIONS

SYM

TYP

-5

-6

-7.5

-10

UNITS NOTES

Power Supply

Current:

Operating

Device selected; All inputs ?ꢁVIL

t

IDD

250

370

330

290

250

mA

6, 7, 9

7, 9

or OꢁVIH; Cycle time Oꢁ KC (MIN);

VDD = MAX; Outputs open

Device selected; VDD = MAX;

Power Supply

Current: Idle

CKE# OꢁVIH; All inputs ?ꢁVSS + 0.2

IDD1

ISB2

100

8

170

30

150

30

130

30

120

30

t

or OꢁVDD - 0.2; Cycle time Oꢁ KC (MIN)

Device deselected; VDD = MAX;

All inputs ?ꢁVSS + 0.2 or OꢁVDD - 0.2;

All inputs static; CLK frequency = 0

CMOS Standby

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# OꢁVIH; All inputs ?ꢁVSS + 0.2

ISB4

100

8

170

30

150

30

130

30

120

30

mA

7, 9

9

t

or OꢁVDD - 0.2; Cycle time Oꢁ KC (MIN)

ZZ OꢁVIH

ISB2Z

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

16

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 17: AC Electrical Characteristics and Recommended Operating Conditions

Notes 11-13 ; notes appear following parameter tables on page 18; 0ºC ? T_A? +70ºC; T_J?ꢁ95ºC (commercial); T_J?ꢁ110ºC

(industrial); VDD = 3.3V 0.165V unless otherwise noted

-5

-6

-7.5

-10

DESCRIPTION

SYMBOL MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES

Clock

^tKHKH

^fKF

^tKHKL

^tKLKH

5.0

6.0

7.5

10.0

ns

MHz

ns

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

200

3.2

166

3.5

133

4.2

100

5.0

2.0

2.2

3.0

3.2

14

ns

Output Times

^tKHQV

^tKHQX

^tKHQX1

^tKHQZ

^tGLQV

^tGLQX

Clock to output valid

ns

1.0

1.5

15

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE# to output valid

10, 15, 16

11

3.0

3.5

4.2

3.5

5.0

0

10, 15, 16

OE# to output in

Low-Z

^tGHQZ

OE# to output in

High-Z

3.2

3.5

5.0

ns

10, 15, 16

Setup Times

^tAVKH

^tEVKH

^tCVKH

^tDVKH

1.4

1.5

2.0

ns

17

Address

Clock enable (CKE#)

Control signals

Data-in

Hold Times

^tKHAX

^tKHEX

^tKHCX

^tKHDX

0.4

0.5

ns

17

Address

Clock enable (CKE#)

Control signals

Data-in

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

17

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Notes

9. Typical values are measured at 2.±V, 2±^ºC, and

10ns cycle time.

10. This parameter is sampled.

1. All voltages referenced to VSS (GND).

2. For 3.3V VDD:

t

Overshoot:

VIH ? +4.6V for t ? KHKH/2 for

I ? 20mA

11. OE# can be considered a “Don’t Care” during

WRITEs; however, controlling OE# can help fine-

tune a system for turnaround timing.

t

Undershoot: VIL O -0.7V for t ? KHKH/2 for

I ? 20mA

12. Test conditions as specified with the output load-

ing shown in Figures 11 and 12 for 3.3V I/O and

Figures 13 and 14 for 2.±V I/O unless otherwise

noted.

13. A WRITE cycle is defined by R/W# LOW, having

been registered into the device at ADV/LD# LOW.

A READ cycle is defined by R/W# HIGH with ADV/

LD# LOW. Both cases must meet setup and hold

times.

14. Measured as HIGH above V^IHand LOW below VIL.

1±. Refer to Technical Note TN-±±-01, “Designing

with ZBT SRAMs,” for a more thorough discussion

of these parameters.

16. This parameter is measure with the output load-

ing shown in Figure 12 for 3.3V I/O and Figure 14

for 2.±V I/O.

Power-up: VIH ? +3.6V and VDD ? 3.13±V for

t ? 200ms

3. For 2.±V VDD:

t

Overshoot: VIH ? +3.6V for t ? KHKH/2 for

I ? 20mA

t

Undershoot: VIL O -0.±V for t ? KHKH/2 for

I ? 20mA

Power-up:

VIH ? +2.6±V and VDD ? 2.37±V for

t ? 200ms

4. The MODE and ZZ pins/balls have an internal

pull-up/pull-down and input leakage = ±10µA.

±. VDDQ should never exceed VDD. VDD and VDDQ

can be externally wired together to the same

power supply.

6. I^DDis specified with no output current and

increases with faster cycle times. I^DDQ increases

with faster cycle times and greater output loading.

7. “Device deselected” means device is in power-

down mode as defined in the truth table. “Device

selected” means device is active (not in power-

down mode).

17. This is a synchronous device. All addresses must

meet the specified setup and hold times with sta-

ble logic levels for all rising edges of CLK when the

chip is enabled. To remain enabled, chip enable

must be valid at each rising edge of CLK when

ADV/LD# is LOW.

8. Typical values are measured at 3.3V, 2±^ºC, and

10ns cycle time.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

18

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 8:

READ/WRITE Timing

1

2

3

4

5

6

7

8

9

10

t

KHKH

t

CLK

t

EVKH KHEX

KLKH

KHKL

CKE#

t

CVKH KHCX

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A4

A3

A5

A6

A7

ADDRESS

DQ

t

KHQV

t

AVKH KHAX

t

KHQZ

KHQX

GLQV

KHQX1

D(A1)

t

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

D(A7)

t

GHQZ

t

DVKH KHDX

t

KHQX

t

GLQX

OE#

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

NOTE:

1. For these waveforms, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

19

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 9:

NOP, STALL, and DESELECT Cycles

1

2

3

4

5

6

7

8

9

10

CLK

CKE#

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A3

A4

A5

ADDRESS

t

KHQZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

KHQX

DQ

t

COMMAND

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

NOTE:

1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not

performed during this cycle.

2. For these waveforms, ZZ and OE# are tied LOW.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

20

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

SNOOZE MODE

SNOOZE MODE is a low-current, “power-down”

mode in which the device is deselected and current is

reduced to ISB2Z. The duration of SNOOZE MODE is

dictated by the length of time the ZZ is in a HIGH state.

After the device enters SNOOZE MODE, all inputs

except ZZ become disabled and all outputs go

to High-Z.

The ZZ is an asynchronous, active HIGH input that

causes the device to enter SNOOZE MODE. When the

ZZ becomes a logic HIGH, ISB2Z is guaranteed after the

time ^tZZI is met. Any READ or WRITE operation pend-

ing when the device enters SNOOZE MODE is not

guaranteed to complete successfully. Therefore,

SNOOZE MODE must not be initiated until valid pend-

ing operations are completed. Similarly, when exiting

SNOOZE MODE during ^tRZZ, only a DESELECT or

READ cycle should be given.

Table 18: SNOOZE MODE Electrical CharacteristicS

DESCRIPTION

CONDITIONS

SYMBOL

ISB2Z

^tZZ

^tRZZ

^tZZI

^tRZZI

MIN

MAX

30

2(^tKHKH)

UNITS

NOTES

Current during SNOOZE MODE

ZZ active to input ignored

ZZ O VIH

mA

ns

1

2(^tKHKH)

0

ns

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

2(^tKHKH)

NOTE:

1. This parameter is sampled.

Figure 10:

SNOOZE MODE Waveform

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

I

ISB2Z

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

21

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

3.3V VDD, 3.3V I/O AC Test Conditions

Input pulse levels ........................VIH = (VDD/2.2) + 1.±V

.........................VIL = (VDD/2.2) - 1.±V

2.5V VDD, 2.5V I/O AC Test Conditions

Input pulse levels..........................VIH = (VDD/2) + 1.2±V

.......................... VIL = (VDD/2) - 1.2±V

Input rise and fall times ............................................. 1ns

Input timing reference levels............................. VDD/2.2

Output reference levels....................................VDDQ/2.2

Output load...................................See Figures 11 and 12

Input rise and fall times ............................................. 1ns

Input timing reference levels.................................VDD/2

Output reference levels.......................................VDDQ/2

Output load................................... See Figures 13 and 14

3.3V VDD, 2.5V I/O AC Test Conditions

Input pulse levels ....................VIH = (VDD/2.64) + 1.2±V

..................... VIL = (VDD/2.64) - 1.2±V

Input rise and fall times ..............................................1ns

Input timing reference levels............................VDD/2.64

Output reference levels.......................................VDDQ/2

Output load................................... See Figures 13 and 14

3.3V I/O Output Load Equivalent

2.5V I/O Output Load Equivalent

Figure 11:

Figure 13:

V_T= VDDQ/2

V_T= VDDQ/2.2

50Ω

Q

Z_O= 50Ω

30pF

Figure 12:

Figure 14:

+2.5V

+3.3V

317

225Ω

Q

5pF

351

5pF

225Ω

NOTE:

For Figures 11 and 13, 30pF = distributive test jig capacitance.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

22

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

IEEE 1149.1 Serial Boundary Scan (JTAG)

The SRAM incorporates a serial boundary scan test

access port (TAP). This port operates in accordance

with IEEE Standard 1149.1-1990 but does not have the

set of functions required for full 1149.1 compliance.

These functions from the IEEE specification are

excluded because their inclusion places an added

delay in the critical speed path of the SRAM. Note that

the TAP controller functions in a manner that does not

conflict with the operation of other devices using

1149.1 fully compliant TAPs. The TAP operates using

JEDEC-standard 3.3V or 2.±V I/O logic levels.

Test Access Port (TAP)

Test Clock (TCK)

The test clock is used only with the TAP controller.

All inputs are captured on the rising edge of TCK. All

outputs are driven from the falling edge of TCK.

Test MODE SELECT (TMS)

The TMS input is used to give commands to the TAP

controller and is sampled on the rising edge of TCK. It

is allowable to leave this ball unconnected if the TAP is

not used. The ball is pulled up internally, resulting in a

logic HIGH level.

The SRAM contains a TAP controller, instruction

register, boundary scan register, bypass register, and

ID register.

Test Data-In (TDI)

The TDI ball is used to serially input information

into the registers and can be connected to the input of

any of the registers. The register between TDI and TDO

is chosen by the instruction that is loaded into the TAP

instruction register. For information on loading the

instruction register, see Figure 1±. TDI is internally

pulled up and can be unconnected if the TAP is unused

in an application. TDI is connected to the most signifi-

cant bit (MSB) of any register. (See Figure 16.)

Disabling the JTAG Feature

These balls can be left floating (unconnected), if the

JTAG function is not to be implemented. Upon power-

up, the device will come up in a reset state which will

not interfere with the operation of the device.

Figure 15:

TAP Controller State Diagram

Test Data-Out (TDO)

TEST-LOGIC

1

The TDO output ball is used to serially clock data-

out from the registers. The output is active depending

upon the current state of the TAP state machine. (See

Figure 1±.) The output changes on the falling edge of

TCK. TDO is connected to the least significant bit

(LSB) of any register. (See Figure 16.)

RESET

0

1

RUN-TEST/

IDLE

SELECT

DR-SCAN

SELECT

IR-SCAN

0

1

CAPTURE-DR

CAPTURE-IR

0

SHIFT-DR

0

SHIFT-IR

0

Figure 16:

1

TAP Controller Block Diagram

1

EXIT1-DR

EXIT1-IR

0

PAUSE-DR

1

0

PAUSE-IR

1

0

Bypass Register

2

1 0

0

Selection

Circuitry

Selection

Circuitry

EXIT2-DR

1

EXIT2-IR

1

Instruction Register

31 30 29

Identification Register

TDI

TDO

.

. 2 1 0

UPDATE-DR

UPDATE-IR

x

.

. 2 1 0

1

0

1

0

Boundary Scan Register*

NOTE:

TCK

TMS

The 0/1 next to each state represents the value

of TMS at the rising edge of TCK.

TAP CONTROLLER

NOTE:

X = 74 for all configurations.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

23

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

The boundary scan register is loaded with the con-

tents of the RAM I/O ring when the TAP controller is in

the Capture-DR state and is then placed between the

TDI and TDO balls when the controller is moved to the

Shift-DR state. The EXTEST, SAMPLE/PRELOAD and

SAMPLE Z instructions can be used to capture the

contents of the I/O ring.

Performing a TAP Reset

A RESET is performed by forcing TMS HIGH (VDD)

for five rising edges of TCK. This RESET does not affect

the operation of the SRAM and may be performed

while the SRAM is operating.

At power-up, the TAP is reset internally to ensure

that TDO comes up in a High-Z state.

The Boundary Scan Order tables show the order in

which the bits are connected. Each bit corresponds to

one of the balls on the SRAM package. The MSB of the

register is connected to TDI, and the LSB is connected

to TDO.

TAP REGISTERS

Registers are connected between the TDI and TDO

balls and allow data to be scanned into and out of the

SRAM test circuitry. Only one register can be selected

at a time through the instruction register. Data is seri-

ally loaded into the TDI ball on the rising edge of TCK.

Data is output on the TDO ball on the falling edge of

TCK.

Identification (ID) Register

The ID register is loaded with a vendor-specific, 32-

bit code during the Capture-DR state when the

IDCODE command is loaded in the instruction regis-

ter. The IDCODE is hardwired into the SRAM and can

be shifted out when the TAP controller is in the Shift-

DR state. The ID register has a vendor code and other

information described in the Identification Register

Definitions table.

Instruction Register

Three-bit instructions can be serially loaded into

the instruction register. This register is loaded when it

is placed between the TDI and TDO balls as shown in

Figure 16. Upon power-up, the instruction register is

loaded with the IDCODE instruction. It is also loaded

with the IDCODE instruction if the controller is placed

in a reset state as described in the previous section.

When the TAP controller is in the Capture-IR state,

the two LSBs are loaded with a binary “01” pattern to

allow for fault isolation of the board-level serial test

data path.

TAP Instruction Set

Overview

Eight different instructions are possible with the

three-bit instruction register. All combinations are

listed in the Instruction Codes table. Three of these

instructions are listed as RESERVED and should not be

used. The other five instructions are described in detail

below.

Bypass Register

The TAP controller used in this SRAM is not fully

compliant to the 1149.1 convention because some of

the mandatory 1149.1 instructions are not fully imple-

mented. The TAP controller cannot be used to load

address, data or control signals into the SRAM and

cannot preload the I/O buffers. The SRAM does not

implement the 1149.1 commands EXTEST or INTEST

or the PRELOAD portion of SAMPLE/PRELOAD;

rather, it performs a capture of the I/O ring when these

instructions are executed.

To save time when serially shifting data through reg-

isters, it is sometimes advantageous to skip certain

chips. The bypass register is a single-bit register that

can be placed between the TDI and TDO balls. This

allows data to be shifted through the SRAM with mini-

mal delay. The bypass register is set LOW (VSS) when

the BYPASS instruction is executed.

Boundary Scan Register

The boundary scan register is connected to all the

input and bidirectional balls on the SRAM. The SRAM

as a 7± bit-long register.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

24

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Instructions are loaded into the TAP controller dur-

ing the Shift-IR state when the instruction register is

placed between TDI and TDO. During this state,

instructions are shifted through the instruction regis-

ter through the TDI and TDO balls. To execute the

instruction once it is shifted in, the TAP controller

needs to be moved into the Update-IR state.

the Capture-DR state, a snapshot of data on the inputs

and bidirectional balls is captured in the boundary

scan register.

The user must be aware that the TAP controller

clock can only operate at a frequency up to 10 MHz,

while the SRAM clock operates more than an order of

magnitude faster. Because there is a large difference in

the clock frequencies, it is possible that during the

Capture-DR state, an input or output will undergo a

transition. The TAP may then try to capture a signal

while in transition (metastable state). This will not

harm the device, but there is no guarantee as to the

value that will be captured. Repeatable results may not

be possible.

EXTEST

EXTEST is a mandatory 1149.1 instruction which is

to be executed whenever the instruction register is

loaded with all 0s. EXTEST is not implemented in this

SRAM TAP controller, and therefore this device is not

compliant to 1149.1.

To guarantee that the boundary scan register will

capture the correct value of a signal, the SRAM signal

must be stabilized long enough to meet the TAP con-

The TAP controller does recognize an all-0 instruc-

tion. When an EXTEST instruction is loaded into the

instruction register, the SRAM responds as if a SAM-

PLE/PRELOAD instruction has been loaded. There is

one difference between the two instructions. Unlike

the SAMPLE/PRELOAD instruction, EXTEST places

the SRAM outputs in a High-Z state.

t

troller’s capture setup plus hold time (^tCS plus CH).

The SRAM clock input might not be captured correctly

if there is no way in a design to stop (or slow) the clock

during a SAMPLE/PRELOAD instruction. If this is an

issue, it is still possible to capture all other signals and

simply ignore the value of the CLK captured in the

boundary scan register.

Once the data is captured, it is possible to shift out

the data by putting the TAP into the Shift-DR state.

This places the boundary scan register between the

TDI and TDO balls.

Note that since the PRELOAD part of the command

is not implemented, putting the TAP to the Update-DR

state while performing a SAMPLE/PRELOAD instruc-

tion will have the same effect as the Pause-DR com-

mand.

IDCODE

The IDCODE instruction causes a vendor-specific,

32-bit code to be loaded into the instruction register. It

also places the instruction register between the TDI

and TDO balls and allows the IDCODE to be shifted

out of the device when the TAP controller enters the

Shift-DR state. The IDCODE instruction is loaded into

the instruction register upon power-up or whenever

the TAP controller is given a test logic reset state.

SAMPLE Z

The SAMPLE Z instruction causes the boundary

scan register to be connected between the TDI and

TDO balls when the TAP controller is in a Shift-DR

state. It also places all SRAM outputs into a High-Z

state.

BYPASS

When the BYPASS instruction is loaded in the

instruction register and the TAP is placed in a Shift-DR

state, the bypass register is placed between the TDI

and TDO balls. The advantage of the BYPASS instruc-

tion is that it shortens the boundary scan path when

multiple devices are connected together on a board.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruc-

tion. The PRELOAD portion of this instruction is not

implemented, so the device TAP controller is not fully

1149.1-compliant.

Reserved

These instructions are not implemented but are

reserved for future use. Do not use these instructions.

When the SAMPLE/PRELOAD instruction is loaded

into the instruction register and the TAP controller is in

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

25

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 17:

TAP Timing

1

2

3

4

5

6

Test Clock

(TCK)

t

THTH

THTL

TLTH

t

MVTH

DVTH

THMX

Test Mode Select

(TMS)

t

THDX

Test Data-In

(TDI)

t

TLOV

t

TLOX

Test Data-Out

(TDO)

DON’T CARE

UNDEFINED

Table 19: TAP AC Electrical Characteristics

Notes 1, 2; 0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V or 2.5V 0.125V

DESCRIPTION

SYMBOL

MIN

MAX

UNITS

Clock

^tTHTH

^fTF

^tTHTL

^tTLTH

Clock cycle time

100

ns

MHz

ns

10

Clock frequency

Clock HIGH time

Clock LOW time

40

ns

Output Times

^tTLOX

^tTLOV

^tDVTH

^tTHDX

0

ns

TCK LOW to TDO unknown

20

TCK LOW to TDO valid

TDI valid to TCK HIGH

TCK HIGH to TDI invalid

10

Setup Times

^tMVTH

^tCS

10

ns

TMS setup

Capture setup

Hold Times

^tTHMX

^tCH

10

ns

TMS hold

Capture hold

NOTE:

t

1. CS and ^tCH refer to the setup and hold time requirements of latching data from the boundary scan register.

2. Test conditions are specified using the loads in Figures Table 18 and 19.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

26

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

3.3V TAP AC Test Conditions

2.5V TAP AC Test Conditions

Input Pulse Levels .......................................... Vss to 3.0V

Input rise and fall times ..............................................1ns

Input timing reference levels.................................... 1.±V

Output reference levels............................................. 1.±V

Test load termination supply voltage ...................... 1.±V

Input Pulse Levels........................................... Vss to 2.±V

Input rise and fall times ............................................. 1ns

Input timing reference levels.................................. 1.2±V

Output reference levels........................................... 1.2±V

Test load termination supply voltage .................... 1.2±V

Figure 18:

3.3V TAP AC Output Load Equivalent

Figure 19:

2.5V TAP AC Output Load Equivalent

1.25V

1.5V

50Ω

TDO

Z_O= 50Ω

20pF

Z_O= 50Ω

20pF

Table 20: 3.3V VDD, TAP DC Electrical Characteristics and Operating Conditions

0ºC ? T_A? +70ºC; VDD = 3.3V 0.165V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

VIH

VIL

ILI

2.0

-0.3

-10

VDD + 0.3

V

1, 2

2

0.8

10

0V ? VIN ? VDD

µA

Output Leakage Current

Output(s) disabled,

ILO

2

0V ? VIN ? VDD (TDO)

Output Low Voltage

Output High Voltage

IOLC = 100µA

IOLT = 2mA

VOL1

VOL2

VOH1

VOH2

0.7

0.8

V

1, 2

IOHC = -100µA

IOHT = -2mA

2.9

2.0

Table 21: 2.5V VDD, TAP DC Electrical Characteristics and Operating Conditions

0ºC ? T_A? +70ºC;ꢁVDD = 2.5V 0.125V unless otherwise noted

DESCRIPTION

CONDITIONS

SYMBOL

MIN

MAX

UNITS

NOTES

VIH

VIL

ILI

1.7

-0.3

-10

VDD + 0.3

V

1, 2

2

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

0.7

10

0V ? VIN ? VDD

µA

Output(s) disabled,

ILO

2

Output Leakage Current

0V ? VIN ? VDD (TDO)

IOLC = 100µA

IOLT = 2mA

VOL1

VOL2

VOH1

VOH2

0.2

0.7

V

1, 2

Output Low Voltage

Output High Voltage

IOHC = -100µA

IOHT = -2mA

2.1

1.7

NOTE:

1. All voltages referenced to VSS (GND).

2. TAP control balls only. For boundary scan ball specifications, please refer to the I/O DC Electrical Characteristics and

Operation Conditions tables.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

27

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 22: Identification Register Definitions

BIT

INSTRUCTION FIELD

CONFIGURATION DESCRIPTION

0000

Revision Number

(31:28)

Reserved for version number.

00111

00110

Device Depth

(27:23)

Defines depth of 1Mb.

Defines depth of 512K.

Device Width

(22:18)

00011

00100

Defines width of x18 bits.

Defines width of x 32 or x36 bits.

xxxxxx

00000101100

1

Micron Device ID

(17:12)

Reserved for future use.

Micron JEDEC ID Code

(11:1)

Allows unique identification of SRAM vendor.

Indicates the presence of an ID register.

ID Register Presence

Indicator (0)

Table 23: Scan Register Sizes

REGISTER NAME

BIT SIZE

Instruction

3

1

Bypass

ID

32

75

Boundary Scan: x18, x32, x36

Table 24: Instruction Codes

INSTRUCTION

CODE

DESCRIPTION

000

EXTEST

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM outputs to High-Z state. This instruction is not 1149.1-compliant.

IDCODE

001

010

Loads the ID register with the vendor ID code and places the register between TDI and

TDO. This operation does not affect SRAM operations.

SAMPLE Z

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Forces all SRAM output drivers to a High-Z state.

011

100

RESERVED

Do Not Use: This instruction is reserved for future use.

SAMPLE/PRELOAD

Captures I/O ring contents. Places the boundary scan register between TDI and TDO.

Does not affect SRAM operation. This instruction does not implement 1149.1 preload

function and is therefore not 1149.1-compliant.

101

110

111

RESERVED

BYPASS

Do Not Use: This instruction is reserved for future use.

Places the bypass register between TDI and TDO. This operation does not affect SRAM

operations.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

28

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 25: 165-Ball FBGA Boundary Scan Order (x18)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

1

2

3

4

5

6

7

8

MODE (LBO#)

NF

1R

6N

11P

8R

8P

9R

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

CE2#

BWa#

NC

BWb#

NC

CE2

CE#

SA

NC

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

1N

2K

2L

NF

SA

ZZ

NC

DQa

DQPa

NC

SA

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

11C

10F

10E

10D

10G

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

NC

DQb

DQPb

NC

SA

SA1

SA0

2M

2J

3P

3R

4P

4R

6P

6R

9B

8A

8B

7A

ADV/LD#

OE# (G#)

CKE#

R/W#

7B

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

29

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 26: 165-Ball FBGA Boundary Scan Order (x32)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

1

2

3

4

5

6

7

8

MODE (LB0#)

NF

1R

6N

11P

8R

8P

9R

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

2J

NF

SA

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

ZZ

NF

SA

NC

NF

DQa

DQb

NF

DQc

DQd

NF

2K

2L

NC

SA

2M

1N

3P

3R

4P

4R

6P

6R

SA

SA1

SA0

SA

9B

8A

8B

7A

ADV/LD#

OE# (G#)

CKE#

R/W#

7B

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

30

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Table 27: 165-Ball FBGA Boundary Scan Order (x36)

BIT#

SIGNAL NAME

BALL ID

BIT#

SIGNAL NAME

BALL ID

1

2

3

4

5

6

7

8

MODE (LB0#)

NF

1R

6N

11P

8R

8P

9R

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

CLK

NC

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

CE#

SA

NC

DQPc

DQc

DQd

DQPd

SA

6B

11B

1A

6A

5B

5A

4A

4B

3B

3A

2A

2B

1B

1C

1D

1E

1F

1G

2D

2E

2F

2G

1J

1K

1L

1M

2J

NF

SA

9P

10R

10P

11R

11H

11N

11M

11L

11K

11J

10M

10L

10K

10J

11G

11F

11E

11D

10G

10F

10E

10D

11C

11A

10B

10A

9A

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

ZZ

DQPa

DQa

DQb

DQPb

NC

2K

2L

2M

1N

3P

3R

4P

4R

6P

6R

SA

SA1

SA0

9B

8A

8B

7A

ADV/LD#

OE# (G#)

CKE#

R/W#

7B

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

31

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 20: 100-Pin Plastic TQFP

(JEDEC LQFP)

+0.10

-0.20

22.10

20.10 0.10

0.65 TYP

0.32

+0.06

-0.10

0.625

SEE DETAIL A

14.00 0.10

16.00 0.20

PIN #1 ID

+0.03

0.15

1.40 0.05

-0.02

GAGE PLANE

0.60 0.15

1.60 MAX

0.10

+0.10

-0.05

0.10

1.00 TYP

0.25

DETAIL A

NOTE:

1. All dimensions in inches (millimeters) ------------- or typical where noted.

MAX

MIN

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

32

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Figure 21:

165-Ball FBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

LL DIAMETER REFERS

EFLOW CONDITION. THE

W DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

13.00 0.10

SOLDER BALL MATERIAL: EUTECTIC 62% Sn, 36%

SOLDER BALL PAD: Ø .33mm

NOTE:

MAX

1. All dimensions in inches (millimeters) ------------- or typical where noted.

MIN

Data Sheet Designation

No Marking: This data sheet contains minimum and maximum limits specified over the complete power

supply and temperature range for production devices. Although considered final, these specifications are sub-

ject to change, as further product development and data characterization sometimes occur.

®

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992

Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc., and the architecture is supported by Micron Technology, Inc.,

and Motorola, Inc.

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

33

18Mb: 1 MEG x 18, 512K x 32/36

PIPELINED ZBT SRAM

Document Revision History

•

Rev D; Pub. 2/03..........................................................................................................................................................2/03

Changed designation from Preliminary to Production

•

Rev C; Pub. 12/02 ......................................................................................................................................................12/02

Added T_Jspecifications to the AC Electrical Characteristics table

Corrected Boundary Scan errors

Updated TQFP and FBGA Thermal Resistance values

Corrected grammatical errors

•

Rev B; PRELIMINARY ...............................................................................................................................................11/02

Changed designation from ADVANCE to PRELIMINARY

Corrected grammatical errors

New ADVANCE data sheet for 0.16µm process; Rev A; Pub. 6/02...........................................................................6/02

18Mb: 1 Meg x 18, 512K x 32/36 Pipelined ZBT SRAM

MT55L1MY18P_16_D.fm – Rev. D, Pub. 2/03

Micron Technology, Inc., reserves the right to change products or specifications without notice.

34


型号：	MT55V512V32PT-10
厂家：	Rochester Electronics
描述：	512KX32 ZBT SRAM, 5ns, PQFP100, PLASTIC, TQFP-100 静态存储器
文件：	总35页 (文件大小：1144K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MT55V512V32PT-10 [ROCHESTER]

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