NC7SZ66L6X [ROCHESTER]
1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, 1 X 1 MM, MO-252UAAD, MICROPAK-6;
| 型号： | NC7SZ66L6X |
| 厂家： | 
Rochester Electronics |
| 描述： | 1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO6, 1 X 1 MM, MO-252UAAD, MICROPAK-6 光电二极管 |
| 文件： | 总10页 (文件大小：1239K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
December 2010
NC7SZ66
Low Voltage Single SPST Normally Open Bus Switch
Features
Description
The NC7SZ66 is a ultra high-speed (UHS) CMOS
compatible single-pole/single-throw (SPST) bus switch.
The LOW on resistance of the switch allows inputs to
be connected to out-puts with minimal propagation
delay and without generating additional ground bounce
noise. The device is organized as a 1- bit switch with a
switch enable (OE) signal. When OE is HIGH, the
switch is on and port A is connected to port B. When
OE is LOW, the switch is open and a high-impedance
state exists between the two ports..
Broad VCC Operating Range: 1.65V to 5.5V
Rail-to-Rail Signal Handling
Power Down High-Impedance Inputs/Outputs
5Ω Switch Connection between Two Ports
Minimal Propagation Delay through the Switch
Low ICC
Zero Bounce in Flow-Through Mode
Control Input Compatible with CMOS Input Levels
Ultra-Small MicroPak™ Packages
Space-Saving SOT23 and SC70 Packages
Ordering Information
Part Number
NC7SZ66M5X
NC7SZ66P5X
NC7SZ66L6X
Top Mark
Package
Packing Method
7Z66
Z66
EE
5-Lead SOT23, JEDEC MO-178 1.6mm
5-Lead SC70, EIAJ SC-88a, 1.25mm Wide
6-Lead, MicroPak™, 1x1mm Wide
3000 Units on Tape & Reel
3000 Units on Tape & Reel
5000 Units on Tape & Reel
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
Connection Diagrams
Figure 1. Logic Symbol
Pin Configurations
Figure 2. SC70 and SOT23 (Top View)
Figure 3. MicroPak™ (Top Through View)
Pin Definitions
Pin # SC70 / SOT23
Pin # MicroPak™
Name
A
Description
Bus A I/O
1
2
3
4
5
1
2
3
4
6
5
B
Bus B I/O
GND
OE
VCC
NC
Ground
Switch Enable Input
Supply Voltage
No Connect
Function Table
OE
L
B0
High Z-State
A0
Function
Disconnected
Connect
H
H = HIGH Logic Level
L = LOW Logic Level
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device
reliability. The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Min.
-0.5
-0.5
-0.5
Max.
7.0
Unit
V
VCC
VS
Supply Voltage
DC Switch Voltage(1)
VCC to 0.5
7.0
V
VIN
DC Input Voltage
V
IIK
DC Input Diode Current
DC Output Sink Current
DC VCC or Ground Current
VIN < 0V
-50
mA
mA
mA
°C
°C
°C
IOUT
ICC or IGND
TSTG
TJ
128
±100
+150
+150
+260
200
Storage Temperature Range
-65
Junction Temperature Under Bias
TL
Junction Lead Temperature (Soldering, 10 Seconds)
SOT-23
Power Dissipation at +85°C
SC70-5
PD
mW
V
150
Human Body Model, JEDEC:JESD22-A114
Charge Device Model: JEDEC:JESD22-C101
4000
1500
ESD
Note:
1. The input and output negative voltage ratings may be exceeded if the input and output diode current ratings are
observed.
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
VCC
Parameter
Supply Voltage Operating
Input Voltage
Conditions
Min.
Max.
5.50
5.5
Unit
V
1.65
0
VIN
V
VS
Switch Input Voltage
Output Voltage
0
VCC
VCC
10
V
VOUT
0
V
VCC=2.3V - 3.6V
0
tr, tf
Input Rise and Fall Times
VCC=4.5V – 5.5V
Switching I/O
0
5
ns/V
0
DC
+85
300
425
TA
Operating Temperature
Thermal Resistance
-40
°C
SOT-23
SC70-5
°C/W
θJA
Note:
2. Unused inputs must be held HIGH or LOW; they may not float.
© 1996 Fairchild Semiconductor Corporation
www.fairchildsemi.com
NC7SZ66 • Rev. 1.0.4
3
DC Electrical Characteristics
All typical values are at the specified VCC, and TA = 25°C.
TA=-40 to +85°C
TA=+25°C
Symbol Parameter
VCC
Conditions
Units
Min.
0.75VCC
0.7VCC
Typ.
Max. Min. Typ.
1.65 to 1.95
2.30 to 5.50
1.65 to 1.95
2.30 to 5.50
HIGH Level
VIH
V
V
Input Voltage
0.25VCC
0.3VCC
LOW Level
VIL
Input Voltage
Control Input
IIN
Leakage
Current
0 to 5.5
±0.05
±1.00
µA
µA
0 ≤ VIN ≤ 5.5V
0 ≤ A, B ≤ VCC
Off Leakage
Current
IOFF
1.65 to 5.50
±0.05 ±10.00
VIN=0V, IIN=30mA
VIN=2.4V, IIN=15mA
VIN=4.5V, IIN=30mA
VIN=0V, IIN=24mA
VIN=3V, IIN=24mA
VIN=0V, IIN=8mA
VIN=2.3V, IIN=8mA
VIN=0V, IIN=4mA
VIN=1.8V, IIN=4mA
3
5
7
4.5
12
15
9
7
4
3.0
2.30
1.8
Switch On
RON
10
5
20
12
30
28
60
Ω
Resistance(3)
13
7
25
IA=-30mA,
0 ≤ VBn ≤ VCC
5.0
3.3
2.5
1.8
6
IA=-24mA,
0 ≤ VBn ≤ VCC
12
On
Rflat
Resistance
Ω
Flatness(3,4,5)
IA=-8mA,
0 ≤ VBn ≤ VCC
128
125
IA=-4mA,
0 ≤ VBn ≤ VCC
Quiescent
Supply
Current
VIN= VCC or GND,
ICC
1.65 to 5.50
0.05
10.00
µA
I
OUT=0
Notes:
3. Measured by the voltage drop between pins A and B at the indicated current through the switch. On resistance
is determined by the lower of the voltages on the two (A or B) pins.
4. Parameter is characterized but not tested in production.
5. Flatness is defined as the difference between the maximum and minimum value of on resistance over the
specified range of conditions.
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
4
AC Electrical Characteristics
All typical values are at the specified VCC, and TA = 25°C.
TA=-40 to +85°C,
CL=50Pf. RU=RD=500Ω
Symbol
Parameter
VCC
Conditions
Units
Figure
Min.
Typ.
Max.
4.3
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
1.65 to 1.95
2.3 to 2.7
3.0 to 3.6
4.5 to 5.5
1.2
Propagation Delay
Bus-to-Bus(6)
Figure 5
Figure 6
tPHL, tPLH
VIN=0PEN
ns
0.8
0.3
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
7.0
3.3
2.4
2.0
9.2
5.3
4.0
2.7
14.2
7.0
VIN=2 x VCC for
Figure 5
Figure 6
tPZL, tPZH Output Enable Time
tPZL
,
ns
ns
5.5
VIN=0V for tPZH
4.5
18.2
9.0
VIN=2 x VCC for
tPLZ,
Figure 5
Figure 6
tPLZ, tPHZ Output Disable Time
7.0
VIN = 0V for tPHZ
5.0
Control Pin Input
Capacitance
CIN
V
CC=0
2
6
pF
pF
Input / Output
CI/O
VCC=05.0V
Capacitance
Note:
6. This parameter is guaranteed by design but is not tested. The switch contributes no propagation delay other
than the RC delay of the typical on resistance of the switch and the 50pF load capacitance, when driven by an
ideal voltage source (zero output impedance).
Notes:
7. Input driven by 50Ω; source terminated in 50Ω.
8. CL includes load and stray capacitance.
9. Input PRR=1.0MHz; tw=500ns.
Figure 4. AC Test Circuit
Figure 5. AC Waveforms
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
5
Physical Dimensions
SYMM
C
L
3.00
2.80
0.95
0.95
A
5
4
B
3.00
2.60
1.70
1.50
2.60
1
2
3
(0.30)
1.00
0.50
0.30
0.95
0.20
C
A B
1.90
0.70
TOP VIEW
LAND PATTERN RECOMMENDATION
SEE DETAIL A
1.30
0.90
1.45 MAX
C
0.15
0.05
0.22
0.08
0.10 C
NOTES: UNLESS OTHEWISE SPECIFIED
A) THIS PACKAGE CONFORMS TO JEDEC
MO-178, ISSUE B, VARIATION AA,
B) ALL DIMENSIONS ARE IN MILLIMETERS.
GAGE PLANE
0.25
C) MA05Brev5
8°
0°
0.55
0.35
SEATING PLANE
0.60 REF
Figure 6. 5-Lead SOT23, JEDEC MO-178 1.6mm
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/packaging/SOT23-5L_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
M5X
Trailer (Hub End)
75 (Typical)
Empty
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
6
Physical Dimensions
Figure 7. 5-Lead, SC70, EIAJ SC-88a, 1.25mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/analog/pdf/sc70-5_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
3000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
P5X
Trailer (Hub End)
75 (Typical)
Empty
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
7
Physical Dimensions
2X
0.05 C
1.45
B
(1)
2X
0.05 C
(0.49)
5X
(0.254)
1.00
(0.75)
(0.52)
1X
A
TOP VIEW
PIN 1 IDENTIFIER
5
0.55MAX
(0.30)
6X
PIN 1
0.05 C
0.05
0.00
RECOMMENED
LAND PATTERN
0.05 C
C
0.45
0.35
0.10
6X
0.00
0.25
6X
0.15
1.0
DETAIL A
0.10
C B A
0.40
0.30
0.05
C
0.35
0.25
5X
5X
0.40
0.30
DETAIL A
PIN 1 TERMINAL
0.075 X 45
CHAMFER
0.5
BOTTOM VIEW
(0.05)
6X
(0.13)
4X
Notes:
1. CONFORMS TO JEDEC STANDARD M0-252 VARIATION UAAD
2. DIMENSIONS ARE IN MILLIMETERS
3. DRAWING CONFORMS TO ASME Y14.5M-1994
4. FILENAME AND REVISION: MAC06AREV4
5. PIN ONE IDENTIFIER IS 2X LENGTH OF ANY
OTHER LINE IN THE MARK CODE LAYOUT.
Figure 8. 6-Lead, MicroPak™, 1.0mm Wide
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify
or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically
the warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
Tape and Reel Specifications
Please visit Fairchild Semiconductor’s online packaging area for the most recent tape and reel specifications:
http://www.fairchildsemi.com/products/logic/pdf/micropak_tr.pdf.
Package Designator
Tape Section
Leader (Start End)
Carrier
Cavity Number
125 (Typical)
5000
Cavity Status Cover Type Status
Empty
Filled
Sealed
Sealed
Sealed
L6X
Trailer (Hub End)
75 (Typical)
Empty
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
8
© 1996 Fairchild Semiconductor Corporation
NC7SZ66 • Rev. 1.0.4
www.fairchildsemi.com
9
相关型号：
NC7SZ66P5X
1-CHANNEL, SGL POLE SGL THROW SWITCH, PDSO5, 1.25 MM, EIAJ, SC-88A, SC-70, 5 PIN
ROCHESTER
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