NCP1034DR2G [ROCHESTER]
SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16, LEAD FREE, SOIC-16;
| 型号： | NCP1034DR2G |
| 厂家： | 
Rochester Electronics |
| 描述： | SWITCHING CONTROLLER, 500kHz SWITCHING FREQ-MAX, PDSO16, LEAD FREE, SOIC-16 开关 光电二极管 |
| 文件： | 总24页 (文件大小：1001K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1034
100V Synchronous PWM
Buck Controller
Description
The NCP1034 is a high voltage PWM controller designed for high
performance synchronous Buck DC/DC applications with input
voltages up to 100 V. The NCP1034 drives a pair of external
N−MOSFETs. The switching frequency is programmable from
25 kHz up to 500 kHz allowing the flexibility to tune for efficiency
and size. A synchronization feature allows the switching frequency to
be set by an external source or output a synchronization signal to
multiple NCP1034 controllers. The output voltage can be precisely
regulated using the internally trimmed 1.25 V reference voltage for
low voltage applications. Protection features include user
programmable undervoltage lockout and hiccup current limit.
Features
http://onsemi.com
MARKING
DIAGRAM
SOIC−16
D SUFFIX
CASE 751B
NCP1034D
AWLYWWG
A
WL
Y
WW
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
• High Voltage Operating up to 100 V
• Programmable Switching Frequency up to 500 kHz
• 2 A Output Drive Capability
PIN CONNECTIONS
• Precision Reference Voltage (1.25 V)
OCset
FB
1
UVLO
RT
16
15
14
13
12
11
10
9
• Programmable Soft−Start with Prebiased Load Capability
• Programmable Overcurrent Protection
• Programmable Undervoltage Protection
2
3
4
5
6
Comp
SS/SD
SYNC
PGND
LDRV
DRVCC
GND
OCIN
VCC
VS
• Hiccup Current Limit Using MOSFET R
• External Frequency Synchronization
• 16 Pin SOIC Package
Sensing
DS(on)
HDRV
VB
7
8
• This is a Pb−Free Device
Applications
(Top View)
• 48 V Non−Isolated DC−DC Converter
• Embedded Telecom Systems
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 22 of this data sheet.
• Networking and Computing Voltage Regulator
• Distributed Point of Load Power Architectures
• General High Voltage DC−DC Converters
V
: 48 V
IN
V
: 12 V
D1
CC
C1A
C1B
2u2
2u2
R4
1N4148
110k
C4
C2
C3
8
9
GND
100n
100n 100n
R10
DRVVCC VB
Q1
12
5
10
VCC
SYNC
RT
HDRV
VS
NTD3055
L1
V
OUT
GND GND
11
13
7
5 V @ 5 A, 200 kHz
R8
10k
10k
15
4
OCIN
LDRV
PGND
FB
13
ꢀ
GND
C9
47
C9B C9C
47 47
R9
SS/SD
UVLO
Q2
ꢀ
ꢀ
ꢀ
1k2
R1
NTD24N06
16
1
6
16k9
2
C8
OCSET
GND
14
3
1n8
COMP
C5
C6
R5
3k9
R6
20k
R7
11k
IC1
NCP1034
12n
220n
R3
4k7
R2
5k6
C7
330p
GND GND GND GND GND
GND
Figure 1. Typical Application Circuit
1
© Semiconductor Components Industries, LLC, 2013
Publication Order Number:
February, 2013 − Rev. 6
NCP1034/D
NCP1034
T
A F U L
Figure 2. Internal Block Diagram
http://onsemi.com
2
NCP1034
PIN FUNCTION DESCRIPTION
PIN
1
PIN NAME
OC
DESCRIPTION
Current limit set point. A resistor from this pin to GND will set the positive and negative current limit threshold
set
2
FB
Inverting input to the error amplifier. This pin is connected directly to the output of the regulator via resistor
divider to set the output voltage and provide feedback to the error amplifier.
3
4
COMP
SS/SD
Output of error amplifier. An external resistor and capacitor network is typically connected from this pin to ground
to provide loop compensation.
Soft−Start / Shutdown. This pin provides user programmable soft−start function. External capacitor connected
from this pin to ground sets the startup time of the output voltage. The converter can be shutdown by pulling this
pin below 0.3 V.
5
6
SYNC
The internal oscillator can be synchronized to an external clock via this pin and other IC’s can be synchronized
via this pin to internal oscillator. If it is not used this pin should be connected via 10 kꢁ resistor to ground.
P
GND
Power Ground. This pin serves as a separate ground for the MOSFET driver and should be connected to the
system’s power ground plane.
7
8
LDRV
Output driver for low side MOSFET.
DRVV
This pin provides biasing for the internal low side driver. A minimum of 0.1 ꢀ F, high frequency capacitor must be
connected from this pin to power ground.
CC
9
VB
This pin powers the high side driver and must be connected to a voltage higher than input voltage. A minimum of
0.1 ꢀ F, high frequency capacitor must be connected from this pin to switch node.
10
11
HDRV
Output driver for high side MOSFET
V
S
Switch Node. This pin is connected to the source of the upper MOSFET and the drain of the lower MOSFET.
This pin is return path for the upper gate driver.
12
13
V
This pin provides power for the internal blocks of the IC. A minimum of 0.1 ꢀ F, high frequency capacitor must be
CC
connected from this pin to ground.
OC
Overcurrent sensing input. A serial resistor from this pin to drain of low MOSFET must be used to limit the
current into this pin.
IN
14
15
16
GND
Signal ground for internal reference and control circuitry.
R
T
Connecting a resistor from this pin to ground sets the oscillator frequency.
An external voltage divider is used to set the undervoltage threshold levels.
UVLO
http://onsemi.com
3
NCP1034
ABSOLUTE MAXIMUM RATINGS
Rating
Symbol
Min
−0.3
−0.3
NA
Max
10
Unit
V
FB, V , R , OC
UVLO T set
COMP, SS/SD, SYNC, OC
5
V
IN
P
GND
NA
V
LDRV
−0.3
−0.3
V
+ 0.3
V
CC
DRVV , V
20
+ 20
V
CC
CC
VB
V
S
V
V
S
HDRV
V
S
− 0.3
V
B
+ 0.3
V
V
−1.0
NA
150
V
S
GND
OC Input Current
NA
20
V
mA
in
All voltages referenced to GND
Rating
Symbol
Value
Unit
°C/W
°C
Thermal Resistance, Junction−to−Ambient
Operating Ambient Temperature Range
Storage Temperature Range
R
130
ꢂ
JA
T
A
−40 to 125
−55 to 150
−40 to 150
T
STG
°C
Junction Operating Temperature
T
J
°C
ESD Withstand Voltage (Note 1)
Human Body Model
V
ESD
2.0
200
kV
Machine Model
Latchup Capability per Jedec JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. Excluding pins V , V and H .
b
S
DRV
TYPICAL ELECTRICAL PARAMETERS
RECOMMENDED OPERATING CONDITIONS
Symbol
Definition
Min
Max
100
18
Unit
V
V
IN
Converting Voltage
Supply Voltage
V
CC
10
10
V
DRV
Supply Voltage
18
V
CC
V
B
to V
Supply Voltage
10
18
V
S
F
SW
T
J
Operating Frequency
Junction Temperature
25
500
125
kHz
°C
−40
http://onsemi.com
4
NCP1034
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over V = 12 V,
CC
DRVV = V = 12 V, −40°C < TJ < 125°C)
CC
B
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
REFERENCE VOLTAGE
Feedback Voltage
V
1.25
V
%
FB
Accuracy
−40°C < TJ < 125°C
−1.5
+1.5
2.0
FB Voltage Line Regulation
SUPPLY CURRENT
L
REG
10 V < V < 18 V (Note 3)
mV
CC
V
CC
Supply Current (Stat)
I
S
S
= 0 V, No Switching, R = 10 kꢁ,
2.0
3.0
mA
CC(Static)
T
R
= 10 kꢁ
OCSET
DRVV Supply Current (Stat)
I
S
S
= 0 V, No Switching
= 0 V, No Switching
0.1
0.1
0.3
0.3
mA
mA
CC
C(Static)
S
V
B
Supply Current (Stat)
I
B(Static)
S
UNDERVOLTAGE LOCKOUT
V
V
V
−Start−Threshold
−Stop−Threshold
−Hysteresis
V
(R)
(F)
Supply Ramping Up
7.9
7.3
8.9
8.2
0.7
8.9
8.2
0.7
8.9
8.2
0.7
1.25
1.15
9.8
9.0
V
V
V
V
V
V
V
V
V
V
V
CC
CC
CC
CC_UVLO
V
Supply Ramping Down
CC_UVLO
Supply Ramping Up and Down
Supply Ramping Up
DRV −Start−Threshold
DRV
DRV
(R)
7.9
7.3
9.8
9.0
CC
CC_UVLO
DRV −Stop−Threshold
(F)
Supply Ramping Down
CC
CC_UVLO
DRV −Hysteresis
Supply Ramping Up and Down
Supply Ramping Up
CC
V −Start−Threshold
B
V
(R)
7.9
7.3
9.8
9.0
B_UVLO
V −Stop−Threshold
B
V
(F)
Supply Ramping Down
B_UVLO
V −Hysteresis
B
Supply Ramping Up and Down
Undervoltage Threshold Value
Undervoltage Threshold Value
OSCILLATOR
U
(Rising)
(Falling)
1.19
1.10
1.31
1.20
UVLO
U
UVLO
Frequency
F
S
R
T
R
T
= 20 kꢁ
= 10 kꢁ
170
320
200
375
230
430
kHz
Ramp Amplitude
Min Duty Cycle
V
(Note 3)
2.0
V
%
ramp
D
FB = 2 V
0
min
Min Pulse Width
Max Duty Cycle
D
F
= 200 kHz, (Note 3)
200
ns
%
min(ctrl)
S
D
F
S
= 400 kHz, FB = 1.2 V
80
max
SYNC Frequency Range
SYNC(F )
20% Above Free Running
Frequency
500
0.8
kHz
S
SYNC Pulse Duration
SYNC High Level
SYNC
200
2.0
ns
V
(pulse)
SYNC
(H)
SYNC Low Level
SYNC
V
(L)
SYNC Input Threshold
SYNC Input Hysteresis
SYNC Input Impedance
SYNC Output Impedance
SYNC Output Pulse Width
ERROR AMPLIFIER
Input Bias Current
SYNC
SYNC
1.6
V
(Thre)
(Hyst)
300
mV
kꢁ
kꢁ
ns
SYNC
(Note 3)
(Note 3)
16
2.5
300
(ZIN)
(OUT)
SYNC
SYNC
F = 500 kHz, (Note 3)
S
(Pulse Width)
I
FB
S
S
= 3 V, FB = 1 V
−0.1
−0.4
ꢀ
A
2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
3. Guaranteed by design but not tested in production.
http://onsemi.com
5
NCP1034
ELECTRICAL CHARACTERISTICS (Unless otherwise specified, these specifications apply over V = 12 V,
CC
DRVV = V = 12 V, −40°C < TJ < 125°C)
CC
B
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ERROR AMPLIFIER
Source/Sink Current
Bandwidth
I
50
100
10
120
ꢀ A
MHz
dB
(Source/Sink)
(Note 3)
(Note 3)
(Note 3)
4.0
DC gain
55
Transconductance
SOFT−START/SD
Soft−Start Current
Shutdown Output Threshold
OVERCURRENT PROTECTION
OCSET Voltage
g
m
1500
15
3150
4000
ꢀ
m
h
o
I
SS
S
S
= 0 V
20
25
ꢀ
A
S
D
0.3
0.4
V
V
1.25
1.0
V
ꢀ A
%
OCSET
Hiccup Current
I
(Note 3)
/I , (Note 3)
Hiccup SS
Hiccup
Hiccup Duty Cycle
OUTPUT DRIVERS
LO, Drive Rise Time
HI Drive Rise Time
LO Drive Fall Time
HI Drive Fall Time
Dead Band Time
Hiccup
I
5.0
(duty)
t (Lo)
r
C = 1.5 nF (See Figure 3)
17
17
10
10
60
1.4
ns
ns
ns
ns
ns
A
L
t (Hi)
r
C = 1.5 nF (See Figure 3)
L
t (Lo)
f
C = 1.5 nF (See Figure 3)
L
t (Hi)
f
C = 1.5 nF (See Figure 3)
L
t
(See Figure 3)
30
120
dead
LO Output High Short Circuit
Pulsed Current
t
V
= 0 V, P v 10 ꢀ s,
LDRVhigh
LDRV W
T = 25°C (Note 3)
J
HI Output High Short Circuit
Pulsed Current
t
V
= 0 V, P v 10 ꢀ s,
2.2
1.4
2.2
A
A
A
HDRVhigh
HDRV
W
T = 25°C (Note 3)
J
LO Output Low Short Circuit
Pulsed Current
t
V
= DRVV , P v 10 ꢀ s,
T = 25°C (Note 3)
LDRVhigh
LDRV CC W
J
HI Output Low Short Circuit
Pulsed Current
t
V
= V , P v 10 ꢀ s,
HDRVhigh
HDRV B W
T = 25°C (Note 3)
J
LO Output Resistor, Source
LO Output Resistor, Sink
HI Output Resistor, Source
HI Output Resistor, Sink
R
Typical Value @ 25°C, (Note 3)
Typical Value @ 25°C, (Note 3)
Typical Value @ 25°C, (Note 3)
Typical Value @ 25°C, (Note 3)
7
2
7
2
12
8
ꢁ
ꢁ
ꢁ
ꢁ
LOH
R
LOL
R
12
8
HIH
R
HIL
2. Cold temperature performance is guaranteed via correlation using statistical quality control. Not tested in production.
3. Guaranteed by design but not tested in production.
http://onsemi.com
6
NCP1034
t
r
t
f
9 V
High−Side
Driver
(HDrv)
2 V
t
r
t
f
9 V
Low−Side
Driver
(LDrv)
2 V
Deadband
H to L
Deadband
L to H
Figure 3. Definition of Rise−Fall Time and Deadband Time
http://onsemi.com
7
NCP1034
TYPICAL OPERATING CHARACTERISTICS
1.3
1.28
1.26
1.24
1.22
1.2
9.0
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
8.0
7.9
Rising
Falling
40
−40 −20
0
20
40
60
80
80
80
100 120
100 120
100 120
−40 −20
0
20
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 4. VFB
Figure 5. UVLOVB
9.2
9.0
8.8
8.6
8.4
8.2
8.0
9.2
9.1
9.0
8.9
8.8
8.7
8.6
8.5
8.4
8.3
8.2
8.1
Rising
Rising
Falling
Falling
−40
−20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 6. UVLOVCC
Figure 7. UVLODRVVCC
1.4
1.35
1.3
2.3
2.2
2.1
2.0
1.9
1.8
Rising
Falling
1.25
1.2
1.15
1.1
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 8. UVLO
Figure 9. ICC (Stat)
http://onsemi.com
8
NCP1034
220
215
210
205
200
195
190
185
180
90
88
86
84
82
80
78
76
74
72
70
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 10. Switching Frequency @ RT = 20 kW
Figure 11. Maximum Duty Cycle @ f = 400 kHz
210
205
200
195
190
185
180
175
170
4500
4000
3500
3000
2500
2000
1500
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 12. Minimum on Time
Figure 13. Error Amplifier Transconductance
90
85
80
75
70
65
60
55
50
45
40
12
11
10
9
Low to High
High to Low
DRVV = VB = 10 V
CC
8
12 V
18 V
7
6
5
4
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 14. Deadtime
Figure 15. Driver Pullup Resistance
http://onsemi.com
9
NCP1034
4.0
3.5
3.0
2.5
2.0
1.5
1.0
−0.2
−0.21
−0.22
−0.23
−0.24
−0.25
−0.26
−0.27
−0.28
−0.29
−0.3
DRVV = VB = 10 V
CC
12 V
18 V
−40 −20
0
20
40
60
80
100 120
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
TEMPERATURE (°C)
Figure 16. Driver Pulldown Resistance
Figure 17. OCP @ R8 = 10 kW, ROCIN = 10 kW
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
−40 −20
0
20
40
60
80
100 120
TEMPERATURE (°C)
Figure 18. POSOCP @ R8 = 10 kW,
OCIN = 10 kW
R
http://onsemi.com
10
NCP1034
500
450
400
350
300
250
200
150
100
50
Undervoltage Lock−out
There are four undervoltage lock−out circuits. Two of
them protect external high−side and low−side drivers, the
third ensures that the IC does not start until V is under a
CC
set threshold. The last one can be programmed by the user.
It has a rising threshold at 1.25 V and a falling threshold at
1.15 V, and the user can define the undervoltage level by an
external resistor divider. If the voltage is not over the
threshold value, the device stops operating. The high−side
driver UVLO only stops switching the high−side MOSFET
Programmed falling and rising UVLO voltage can be
calculated by Equations 1 and 2:
0
+ 1.15 @ ǒ1 ) R4Ǔ
0
50
100
150
200
250
(eq. 1)
VUVLO,falling
R5
R (kꢁ)
t
Figure 20. Frequency Dependence of Rt Value
and
ǒ
R4Ǔ
(eq. 2)
V
UVLO,rising + 1.25 @ 1 )
R5
Frequency Synchronization
The NCP1034 can be synchronized to an external clock
signal. The input synchronization signal should be a TTL
logic level. The oscillator is synchronized to the rising edge
of the synchronizing signal. When synchronization is used,
the free running frequency must be set by the timing resistor
to a frequency at least 80% of the external synchronization
Shutdown
The output voltage can be disabled by pulling the
SS/SD pin below 0.3 V. A small transistor can be used to pull
it down as shown in Figure 19. During this time, both
external MOSFETs are turned off. After the SS/SD pin is
released, the IC starts its operation with a soft−start
sequence.
frequency (Example: R = 20 kꢁ / 200 kHz and external
T
TTL = 220 kHz).
The NCP1034 can also output synchronization pulses on
the SYNC pin. Pulses are generated when the internal
oscillator ramp reaches the high threshold voltage. The
SS/SD
SS/SD
frequency of these pulses is set by an external R resistor. Up
T
to five NCP1034 controllers can be connected directly to the
SYNC pin, all of which are synchronized to the controller
with the highest frequency. The lowest frequency must be at
least 80% of the highest one.
The equivalent internal circuit of the Sync pin is shown in
Figure 21.
Figure 19. Shutdown Interface
V
BIAS
Operating Frequency Selection
The operating frequency is set by an external resistor
connected from the R Pin to ground. The value of this
t
resistor can be selected from Figure 20, which shows
switching frequency versus the timing resistor value.
SYNC
R
t
Oscillator
R
t
C
t
Figure 21. Equivalent Connection of the Sync Pin
http://onsemi.com
11
NCP1034
Figure 22 shows the part with no synchronization. In this
circuit the internal clock is fixed by the external timing
SYNC
NCP1034
(Master #1)
SYNC
NCP1034
(Slave #1)
resistor R . The SYNC pin can be tied to GND through a
T
series resistor to prevent false triggering in a noisy
environment.
R
F
R
T
T
= 200 kHz
F
SW
= 180 kHz
SW
20 kꢁ
22 kꢁ
SYNC
10 kꢁ
(optional)
SYNC
NCP1034
(Slave #2)
NCP1034
Synchronized System
Frequency = 200 kHz
R
T
R
T
F
SW
= 180 kHz
20 kꢁ
F
SW
= 200 kHz
22 kꢁ
Figure 22. Fixed Frequency
Figure 24. Master Slave Synchronization
Figure 23 shows the part synchronized to an external
clock through the SYNC pin. The synchronization
frequency can be up to 20% greater then the programmed
Output Voltage
Output voltage can be set by an external resistor divider
according to this Equation 3:
fixed frequency (Example: R = 20 kꢁ / 200 kHz and the
T
SYNC input frequency can range from 200−220 kHz). The
clock frequency at the SYNC pin replaces the master clock
generated by the internal oscillator circuit. Pulling the
SYNC pin low programs the part to run freely at the
ǒ
R1Ǔ
(eq. 3)
V
OUT + Vref @ 1 )
R2
Where V is the internal reference voltage 1.25 V. Absolute
values of resistors R1 and R2 depend on compensation
network type. See compensation paragraph for details.
ref
frequency programmed by R . When pulling the SYNC pin
T
low a 4.7 kΩ resistor should be used.
Inductor Selection
TTL
The inductor selection is based on the output power,
frequency, input and output voltage and efficiency
requirements. High inductor values cause low current
ripple, slower transient response, higher efficiency and
increased size. Inductor design can be reduced to desire
maximum current ripple in the inductor. It is good to have
Logic
SYNC
4.7 kꢁ
(optional)
NCP1034
Input: = 220 kHz
R
T
current ripple (ꢃI
) between 20% and 50% of the output
Lmax
current.
20 kꢁ
F
SW
= 220 kHz
For buck converter, the inductor should be chosen
according to Equation 4.
VOUT
VOUT
Figure 23. External Synchronization
(eq. 4)
L + ǒ Ǔǒ1 * Ǔ
f @ ꢃ ILmax
VINmax
Figure 24 shows the part operating in the master slave
synchronization configuration. In this configuration all
three parts are connected together through the SYNC pin in
order to synchronize the system switching frequency. The
R timing resistor can be the same value for all three parts
(R = 20 kꢁ / 20 kꢁ / 20 kꢁ) which would make the highest
Output Capacitor Selection
The output voltage ripple and transient requirements
determine the output capacitor type and value. The
important parameter for the selection of the output capacitor
is equivalent serial resistance (ESR). If the capacitor has low
ESR, it often has sufficient capacity for filtering as well as
an adequate RMS current rating.
T
T
frequency part the master, or to guarantee one part is the
master the timing resistor can be slightly lower in value. (R
T
= 20 kꢁ / 22 kꢁ / 22 kꢁ)
http://onsemi.com
12
NCP1034
VOUT
VIN
The value of the output capacitor should be calculated
using the following equation:
(eq. 8)
(eq. 9)
P
COND*HIGHFET + I2OUT @ RDS(on)
@
ꢃ IL
VOUT
C
OUT w
(eq. 5)
@ ǒ1 * Ǔ
P
COND*LOWFET + I2OUT @ RDS(on)
8 @ f @ ǒꢃ V
Ǔ
OUT * ꢃ IL @ ESR
VIN
For higher switching frequency, it is suitable to use
multi−layer ceramic capacitor (MLCC) with very low ESR.
The advantages are small size, low output voltage ripple and
fast transient response. The disadvantage of MLCC type is
the requirement to use a Type III compensation network.
Switching losses are depended on drain−to−source
voltage at turn−off state, output current and switch−on and
switch−off time as is shown by Equation 10.
VDS(off)
(eq. 10)
@ ǒt Ǔ
ON ) tOFF @ f @ IOUT
PSW
+
2
Input Capacitor Selection
t
and t
times are dependent on the transistor gate.
ON
OFF
The input capacitor is used to supply current pulses while
high−side MOSFET is on. When the MOSFET is off, the
input capacitor is being charged. The value of this capacitor
can be selected with Equation 6:
The MOSFET output capacitance loss is caused by the
charging and discharging during the switching process and
can be computed using Equation 11.
C
OSS @ VIN 2 @ f
VOUT
VIN
VOUT
@ ǒ1 * Ǔ
VIN
(eq. 11)
PCOSS
+
IOUT
@
2
(eq. 6)
Where C
= C + C
.
C
IN w
OSS
DS
GS
f @ ꢃ VIN
Significant power dissipation is caused by the reverse
recovery charge in the low−side MOSFET body diode,
which conducts at dead time. This charge is needed to close
the diode. The current from the input power supply flows
through the high−side MOSFET to the low−side MOSFET
body diode. This power dissipation can be calculated using
Equation 12.
Where ꢃV
is the input voltage ripple and the
IN
recommended value is about 2% − 5% of V . The input
IN
capacitor must be large enough to handle the input ripple
current. Its value should be calculated using Equation 7:
VOUT
VIN
@ ǒ1 * Ǔ
VOUT
(eq. 7)
P
QRR + QRR @ VIN @ f
Ǹ
(eq. 12)
I
RMS + IOUT @
VIN
Q
is the diode recovery charge as given in the
RR
manufacturer’s datasheet. For some types of MOSFETs, this
dissipation may be dominant at high input voltages. It is
necessary to take care when selecting a MOSFET. An
external Schottky diode across the low−side MOSFET can
be used to eliminate the reverse recovery charge power loss.
The Schottky diode’s forward voltage should be lower than
Power MOSFET Selection
The NCP1034 uses two N−channel MOSFET’s. They can
be primary selected by R , maximum drain−to−source
DS(on)
voltage and gate charge. R
impacts conductive losses
DS(on)
and gate charge impacts switching losses. The low side
MOSFET is selected primarily for conduction losses, and
the high−side MOSFET is selected to reduce switching
losses especially when the output voltage is less than 30% of
the input voltages. The drain−to−source breakdown voltage
must be higher than the maximum input voltage. Conductive
power losses can be calculated using the Equations 8 and 9:
that of the body diode, and reverse recovery time (t ) should
rr
be lower then that of the body diode. The Schottky diode’s
capacitance loss can be calculated as shown in Equation .
C
Schottky @ VIN 2 @ f
(eq. 13)
PC(Schottky)
+
2
http://onsemi.com
13
NCP1034
t
t
dead
dead
High−Side
Logic Signal
Low−Side
Logic Signal
t
t
f
d(on)
R
DSmax
High−Side
MOSFET
R
R
DS(on)min
t
r
t
d(off)
t
t
f
r
R
DSmax
Low−Side
MOSFET
DS(on)min
t
d(on)
t
d(off)
Figure 25. MOSFETs Timing Diagram
MOSFETs delays, turn−on and turn−off times must be
short enough to prevent cross conduction. If not, there will
be cross conduction from the input through both MOSFETs
to ground. Due to this fact, the following conditions must be
true:
supply voltage, low side drive supply voltage and external
UVLO are over the set thresholds. The soft−start capacitor
is charged by 20 ꢀ A current source. If POR is low, the SS/SD
Pin is internally pulled to GND, which means that the
NCP1034 is in a shutdown state. The SS/SD Pin voltage
(0 V to 2.6 V) controls internal current source (64 ꢀ A to
0 ꢀ A) with negative linear characteristic. This current
source injects current into the resistor (25 kꢁ) connected
between the Fb pin and negative input of the error amplifier
and into the external feedback resistor network. Voltage
drop on these resistors is over 1.6 V, which is enough to force
the error amplifier into negative saturation state and to block
switching.
When the soft−start pin reaches around 1.2 V (exact value
depends on feedback and compensation network and on
soft−start capacitor; a larger soft−start capacitor and a lower
compensation capacity decrease this level) the IC starts
switching. The impact of controlled current source
decreases and the output voltage starts to rise. When the
soft−start capacitor voltage reaches 2.6 V, the output voltage
is at nominal value.
t
d(on)high ) tdead u td(off)low ) tf low
(eq. 14)
t
d(on)low ) tdead u td(off)high ) tf high
Where t
is the controller dead band time, t , t , t
d(on) r d(off)
dead
and t are MOSFETs parameters. These parameters can be
f
found in the datasheet for specific conditions.
Bootstrap Circuit
This circuit is used to obtain a voltage higher than the
input voltage in order to switch−on high side N MOSFET.
The bootstrap capacitor is charged from the IC’s supply
voltage through D1, when the low side MOSFET is
switched−on up to the IC’s supply voltage. It must have
enough capacity to supply power for the high−side circuit
when the high−side MOSFET is being switched on. The
minimum value recommended for the bootstrap capacitor is
100 nF. Diode D1 has to be designed to withstand a reverse
voltage given by the following equation:
The soft−start time must be at least 10 times longer than
the time needed to charge the compensation network from
the output of the error amplifier. If the soft−start time is not
long enough, the soft−start sequence would be faster than the
charging compensation network and the IC would start
without slowly increasing the output voltage. The soft−start
capacitance can be calculated using Equation 16.
D1VRmin + VIN * VCC
(eq. 15)
Soft−Start
The soft−start time is set by capacitor connected between
SS/SD Pin and ground. This function is used for controlling
the output voltage slope and limiting startup currents. The
start−up sequence initiates when Power On Ready (POR)
internal signal rises to logic high level. That means the
(eq. 16)
C
SS + 15 @ 10−6 @ TSS
http://onsemi.com
14
NCP1034
POR
SS
5V
~2.6V
~1.2V
0V
V
OUT
64ꢀ A
I
FB
>1.6V
1.25V
1.25V
FB
Voltage
0V
Figure 26. Soft−Start
Start to Prebiased Output
time, the energy is not discharged by the low−side MOSFET
until the soft−start sequence crosses the programmed output
voltage.
The NCP1034 is able to startup into a prebiased output
capacitor. The low−side MOSFET does not turn on before
high−side MOSFET gets the first turn−on pulse. During this
V
OUT
~5V
~2.6V
~1.2V
SS
LDRV
HDRV
Figure 27. Startup to Prebiased Output
Overcurrent Protection
The voltage drop across the low side MOSFET R
connected through resistor R8 and into the IC though pin 13
a current equal to 5% of the charging current. The capacitor
continues to discharge until the voltage reaches 0.25 V, and
then the IC initiates a standard soft start sequence.
The recommended value for the protection resistor R8 is
10 kꢁ. The R7 resistance value can be calculated using
Equation 17:
is
DS(on)
OC . Within the IC, this value is compared with the value
in
programmed by resistor R7 to set the overcurrent limit. The
programmed current limit is set by selecting the value of R7,
which is connected between pin 1 OCset and GND. If the
voltage drop is larger than the set value, the NCP1034 goes
into hiccup mode. During this time, both external MOSFETs
are turned off and the soft start capacitor is discharged with
R8
R7 +
(eq. 17)
3.56 @ RDS(on) @ Ipk
http://onsemi.com
15
NCP1034
5V
~1.2V
~1.9V
5V
~1.2V
0.3V
~1.9V
0.3V
0.3V
~2.6V
~1.2V
~2.6V
~1.2V
SS
V
I
OUT
OUT
OUT
R
Figure 28. Overcurrent Protection (Hi−Cup Mode)
1
The NCP1034 provides protection of the low−side
MOSFET against positive overcurrent (from output to this
MOSFET). Its value can be calculated using Equation 18:
fP0
+
(eq. 19)
2 @ ꢄ @ Ǹ
L @ COUT
One zero of this LC filter is given by the output capacitance
and output capacitor ESR. Its value can be calculated by
using the following equation:
5125 * 0.184 @ R8 @ 1.25
IPos
+
(eq. 18)
R7 @ RDS(on)
1
Compensation Circuit
fZ0
+
(eq. 20)
2 @ ꢄ @ COUT @ ESR
The NCP1034 is a voltage mode buck convertor with a
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°).
The next parameter that must be chosen is the zero
crossover frequency f . It can be chosen to be 1/10 − 1/5 of
the switching frequency. These three parameters show the
necessary type of compensation that can be selected from
Table 1.
0
The transfer function of the power stage (the output LC
filter) is a double pole system. The resonance frequency of
this filter is expressed as follows:
Table 1. COMPENSATION TYPES
Zero Crossover Frequency Condition
Compensation Type
Type II (PI)
Typical Output Capacitor Type
Electrolytic, Tantalum
Tantalum, Ceramic
Ceramic
f
< f < f < f /2
Z0 0 S
P0
P0
f
< f < f < f /2
Type III (PID) Method I
Type III (PID) Method II
0
Z0
S
f
P0
< f < f /2 < f
0 S Z0
Compensation Type II (PI)
of the switching frequency. Components of the PI
compensation (Figure 29) network can be specified by the
following equations:
This compensation is suitable for low−cost electrolytic
capacitor. The zero created by the capacitor’s ESR is a few
kHz and the zero crossover frequency is chosen to be 1/10
http://onsemi.com
16
NCP1034
V
OUT
for tantalum output capacitors, which have a higher ESR
than ceramic, and its zeros and poles can be calculated
shown below:
R1
fZ1 + 0.75 @ fP0
−
fZ2 + fP0
OTA
(eq. 22)
+
fP2 + fZ0
V
ref
R
C
R2
C1
C1
fS
fP3
+
2
C
*
C2
The second one (method II) is for ceramic capacitors:
1 * sinꢂ max
fZ2 + f0 @
fP2 + f0 @
Ǹ
1 ) sinꢂ max
1 ) sinꢂ max
*Optional
Ǹ
Figure 29. PI compensation (II Type)
(eq. 23)
1 * sinꢂ max
fZ1 + 0.5 @ fZ2
2 @ ꢄ @ f0 @ L @ VRAMP @ VOUT
RC1
CC1
CC2
+
+
+
fP3 + 0.5 @ fS
ESR @ VIN @ Vref @ gm
1
The remaining calculations are the same for both methods.
0.75 @ 2 @ ꢄ @ fP0 @ RC1
2
gm
(eq. 21)
RC1 uu
1
1
ꢄ @ RC1 @ fS
CC1
CC2
+
+
V
OUT * Vref
2 @ ꢄ @ fZ1 @ RC1
R1 +
@ R2
1
Vref
2 @ ꢄ @ fP3 @ RC1
V
RAMP
is the peak−to−peak voltage of the oscillator ramp
and gm is the transconductance error amplifier gain.
2 @ ꢄ @ f0 @ L @ VRAMP @ COUT
CFB1
RFB1
+
+
Capacitor C is optional.
C2
(eq. 24)
V
IN @ RC1
Compensation Type III (PID)
1
Tantalum and ceramics capacitors have lower ESR than
electrolytic, so the zero of the output LC filter goes to a
higher frequency above the zero crossover frequency. This
situation needs to be compensated by the PID compensation
network that is show in Figure 30.
2ꢄ @ CFB1 @ fP2
1
R1 +
R2 +
* RFB1
2 @ ꢄ @ CFB1 @ fZ2
Vref
@ R1
V
OUT * Vref
V
OUT
To check the design of this compensation network, the
equation must be true
C
C2
R
C
FB1
FB1
R1 @ R2 @ RFB1
1
gm
(eq. 25)
u
R1 @ RFB1 ) R2 @ RFB1 @ R1 @ R2
R 1
R
C
C1
C1
If it is not true, then a higher value of R must be selected.
C1
Input Power Supply
−
The NCP1034 controller and built−in drivers need to be
OTA
+
powered through V , DRVV and V pins with a voltage
CC
CC
b
R 2
V
REF
between 10 V – 18 V. The supply current requirement is a
summation of the static and dynamic currents. Static current
consumption can be calculated by the following equation:
Figure 30. PID Compensation (III Type)
I
CS + ICC ) IC ) IB
(eq. 26)
There are two methods to select the zeros and poles of
compensation network. The first one (method I) is useable
http://onsemi.com
17
NCP1034
Dynamic current consumption is calculated using the
following equation, base on the switching frequency and
MOSFET gate charge.
shunt voltage regulator and a shunt voltage regulator with
transistor, as shown in Figure 31. A voltage regulator
without a transistor can be used when the power
consumption is low and zener diode power dissipation is
acceptable. Otherwise, a shunt regulator with transistor can
be used.
ǒ Ǔ@ f
CD + QG(low) ) QG(high)
I
(eq. 27)
To power the device, an external power supply or voltage
regulator from V can be used. Two options are a linear
IN
V
IN
V
CC
V
IN
V
CC
R
D
C
D
C
Figure 31. Linear Shunt
Voltage Regulator
Figure 32. Shunt Voltage
Regulator with Transistor
For the linear shunt voltage regulator (option a) the V
voltage is the same as the zener diode reverse voltage V .
The value of the resistor R can be calculated using
DC current gain. The maximum power dissipation of the
resistor, zener diode and transistor are calculated by
Equations 32 to 34. The transistor reverse breakdown
voltage must be selected to be able to withstand the voltage
difference between maximum input voltage and VCC.
CC
Z
Equation 28, where I is the minimum reverse current at
ZT
V . The value selected should be lower than the calculated
Z
value. The maximum power losses of resistor R and the
zener diode D can be calculated by Equations 29 and 30.
V
INmin * VZT
R t
(eq. 31)
I
)I
CS
CD ) IZT
V
INmin * VCC
CS ) ICD ) IZT
R + (VINmax * VCC) @ (ICS ) ICD
ꢅ
(eq. 28)
(eq. 29)
R t
I
I
CS ) ICD
ǒ
Ǔ @
(eq. 32)
(eq. 33)
ǒ
Ǔ
P
R + VINmax * VCC
) IZT
P
)
ꢅ
V
INmax * VCC
V
V
INmax * VZT ICS
ICS
*
(eq. 30)
+ ǒ
Ǔ
PD
+ ǒ
Ǔ
PD
PD
*
@ VZT
R
R
ꢅ
The shunt voltage regulator with transistor (option b) is
advantageous when the zener diode loss is too high or when
input voltage varies across a wide range and it is difficult to
INmax * VZT ICS
(eq. 34)
(eq. 35)
+ ǒ
Ǔ
*
@ VZT
R
ꢅ
set a bias point. The output voltage is lower than V due to
Z
ǒ
Ǔ @ ǒI
Ǔ
P
T + VINmax * VCC
CS ) ICD
the V of the transistor. The maximum resistor value of R
BE
can be calculated by Equation 31, where ꢅ is the transistor
Table 2. POWER SUPPLY REGULTOR EXAMPLES
R
BIAS
Q
f
V
INmax
V
INmin
I
G(TOT)
SUPPLYmax
(nC)
(kHz)
(V)
(V)
(mA)
Components
LS−FET
MOSFETs
NTD24N06
NTD3055
(kW)
ZD
Transistor
24
7.1
24
24
200
300
60
60
36
20
8.7
2.6
MMSZ4699
−
HS−FET
LS−FET
NTD24N06
NTD24N06
16.9
10
MMSZ4699
MJD31
HS−FET
PCB Layout
important, therefore, to pay close attention to the PCB
layout.
The layout of high−frequency and high−current switching
converters has a large impact on the circuit parameters. It is
http://onsemi.com
18
NCP1034
The input capacitor, MOSFETs, inductor and output
and the IC should be very short with wide traces and
optimally using two layers to achieve minimum inductance
between them.
The blocking and bootstrap capacitors should be placed as
close as possible to the IC. The feedback and compensation
network should be close to the IC to minimize noise.
capacitor should be placed as close as possible to one
another. This is suitable to reduce EMI and to minimize VS
overshoots. Connecting the signal and power ground at one
point near the output connector improves load regulation.
Connection between the source pin of the low side MOSFET
TYPICAL APPLICATION
X1−1
R11A
10k
C1A
2u2
R11B
R11C
R11D
R11E
10k
10k
10k
10k
D1
1N4148
C1B
2u2
C10
D2
100n
C2
100n
X1−2
X2−2
C4
GND GND
MMSZ4699
100n
8
9
DRVVCC VB
Q2
12
5
10
11
13
7
C3
100n
GND
VCC
SYNC
RT
HDRV
VS
NTD3055
L1
R8
15
4
OCIN
LDRV
PGND
FB
13
ꢀ
GND
C9
47
C9B C9C
47 47
10k
R4
110k
R9
SS/SD
UVLO
ꢀ
ꢀ
ꢀ
1k2
Q3
NTD24N06
R1
16k9
16
1
6
2
C8
1n8
OCSET
GND
14
3
COMP
C5
R10
R3
4k7
X2−1
R5
3k9
R6
20k
R7
10k
C6
R15
0R
IC1
NCP1034SMD
10k 220n
R2
5k6
12n
C7
330p
GND GND GND GND GND GND
GND
Figure 33. Single Output Buck Converter from 38 V − 58 V to 5 V/5 A @ 200 kHz
90
38 V
85
80
75
70
65
60
55
50
48 V
V
= 58 V
IN
0
0.5
1
1.5
2
2.5
(A)
3
3.5
4
4.5
5
I
OUT
Figure 34. Efficiency and Power Loss of Circuit at Figure 33
http://onsemi.com
19
NCP1034
Bill of Materials
Manufacturer
Part Number
Designator
Qty
1
Description
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Resistor
Value
1k2
Tolerance Footprint
Manufacturer
Vishay
R9
R5
R3
R2
R1
R6
1%
1%
1%
1%
1%
1%
1%
1206
1206
1206
1206
1206
1206
1206
CRCW10261K20FKEA
CRCW10263K90FKEA
CRCW10264K60FKEA
CRCW10265K60FKEA
CRCW102616K9FKEA
CRCW102620K0FKEA
CRCW102612K0FKEA
1
3k9
Vishay
1
4k7
Vishay
1
5k6
Vishay
1
16k9
20k
Vishay
1
Vishay
R11A, R11B,
R11C, R11D,
R11E
5
12k
Vishay
R4
1
3
1
1
1
1
4
3
2
1
1
1
1
1
1
Resistor
110k
10k
1%
1%
10%
10%
10%
10%
10%
20%
10%
20%
−
1206
1206
1206
1206
1206
1206
1206
1210
1210
13x13
Vishay
Vishay
Kemet
Kemet
Kemet
Kemet
Kemet
Kemet
Murata
Würth
CRCW1206110KFKEA
CRCW120610K0FKEA
C1206C182K5FA−TU
C1206C123K5FACTU
C1206C224K5RACTU
−
R7, R8, R10
Resistor
C8
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Ceramic Capacitor
Inductor SMD
1n8
C6
12n
C5
220n
C7
330p
C2, C3, C4, C10
100n
C1206F104K1RACTU
C1210C476M9PAC7800
GRM32ER72A225KA35L
744355131
C9A, C9B, C9C
47ꢀ /6.3V
2.2ꢀ /100V
13ꢀ
C1A, C1B
L1
D1
Switching Diode
Zener Diode 12V
Power N−MOSFET
Power N−MOSFET
MMSD4148
MMSZ4699
NTD3055
NTD24N06
NCP1034
SOD123 ON Semiconductor
SOD123 ON Semiconductor
MMSD4148T1G
D2
−
MMSZ4699T1G
Q2
−
DPAK
DPAK
ON Semiconductor
ON Semiconductor
NTD3055−150G
Q3
−
NTD24N06T4G
IO1
Synchronous PWM
Buck Controller
−
SOIC16 ON Semiconductor
NCP1034DR2G
http://onsemi.com
20
NCP1034
Figure 35. Top Layer
Figure 36. Bottom Layer
Figure 37. Top Side Components
Figure 38. Bottom Side Components
http://onsemi.com
21
NCP1034
44 mm_
Figure 39. Typical Application Board Photos
ORDERING INFORMATION
Device
†
Package
Shipping
NCP1034DR2G
SOIC−16
(Pb−Free)
2500 / Tape & Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
http://onsemi.com
22
NCP1034
PACKAGE DIMENSIONS
SOIC−16
CASE 751B−05
ISSUE K
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION
SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D
DIMENSION AT MAXIMUM MATERIAL CONDITION.
16
9
8
−B−
P 8 PL
M
S
B
0.25 (0.010)
1
MILLIMETERS
INCHES
MIN
0.386
DIM MIN
MAX
MAX
0.393
0.157
0.068
0.019
0.049
A
B
C
D
F
9.80
3.80
1.35
0.35
0.40
10.00
G
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
F
R X 45
K
_
G
J
1.27 BSC
0.050 BSC
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
K
M
P
R
C
7
0
_
_
_
_
−T−
SEATING
PLANE
5.80
0.25
6.20 0.229
0.50 0.010
0.244
0.019
J
M
D
16 PL
M
S
S
A
0.25 (0.010)
T
B
SOLDERING FOOTPRINT*
8X
6.40
16X
1.12
1
16
16X
0.58
1.27
PITCH
8
9
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates,
and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death
associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
N. American Technical Support: 800−282−9855 Toll Free
USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81−3−5817−1050
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada
Email: orderlit@onsemi.com
For additional information, please contact your local
Sales Representative
NCP1034/D
相关型号：
©2020 ICPDF网 联系我们和版权申明