NCP1529ASNT1G [ROCHESTER]
SWITCHING REGULATOR, 2200kHz SWITCHING FREQ-MAX, PDSO5, LEAD FREE, TSOP-5;
| 型号： | NCP1529ASNT1G |
| 厂家： | 
Rochester Electronics |
| 描述： | SWITCHING REGULATOR, 2200kHz SWITCHING FREQ-MAX, PDSO5, LEAD FREE, TSOP-5 开关 光电二极管 |
| 文件： | 总17页 (文件大小：931K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
NCP1529
1.7MHz, 1A, High Efficiency,
Low Ripple, Adjustable
Output Voltage Step-down
Converter
The NCP1529 step−down DC−DC converter is a monolithic
integrated circuit for portable applications powered from one cell
Li−ion or three cell Alkaline/NiCd/NiMH batteries. The device is able
to deliver up to 1.0 A on an output voltage range externally adjustable
from 0.9 V to 3.9 V or fixed at 1.2 V or 1.35 V. It uses synchronous
rectification to increase efficiency and reduce external part count. The
device also has a built−in 1.7 MHz (nominal) oscillator which reduces
component size by allowing a small inductor and capacitors. Automatic
switching PWM/PFM mode offers improved system efficiency.
Additional features include integrated soft−start, cycle−by−cycle
current limiting and thermal shutdown protection.
The NCP1529 is available in a space saving, low profile
2x2x0.5 mm UDFN6 package and TSOP−5 package.
Features
• Up to 96% Efficiency
• Best In Class Ripple, including PFM mode
• Source up 1.0 A
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MARKING
DIAGRAM
5
TSOP−5
SN SUFFIX
CASE 483
DXJAYWG
G
5
1
1
DXJ
A
= Specific Device Code
= Assembly Location
= Year
= Work Week
= Pb−Free Package
Y
W
G
(Note: Microdot may be in either location)
UDFN6
MU SUFFIX
CASE 517AB
1
2
3
6
5
4
XXMG
G
• 1.7 MHz Switching Frequency
• Adjustable from 0.9 V to 3.9 V or Fixed at 1.2 V or 1.35 V
• Synchronous rectification for higher efficiency
• 2.7 V to 5.5 V Input Voltage Range
• Low Quiescent Current 28 mA
• Shutdown Current Consumption of 0.3 mA
• Thermal Limit Protection
XX
M
G
= Specific Device Code
= Date Code
= Pb−Free Package
(Note: Microdot may be in either location)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 14 of this data sheet.
• Short Circuit Protection
• All Pins are Fully ESD Protected
• These are Pb−Free Devices
Typical Applications
• Cellular Phones, Smart Phones and PDAs
• Digital Still Cameras
• MP3 Players and Portable Audio Systems
• Wireless and DSL Modems
• USB Powered Devices
• Portable Equipment
L
L
V
V
OUT
OUT
V
IN
V
IN
VIN
SW
FB
VIN
EN
SW
FB
C
C
IN
IN
C
C
OUT
OUT
R1
R2
C
ff
OFF ON
OFF ON
EN
GND
GND
Figure 1. Typical Application for Adjustable Version
Figure 2. Typical Application for Fixed Version
© Semiconductor Components Industries, LLC, 2010
1
Publication Order Number:
September, 2010 − Rev. 5
NCP1529/D
NCP1529
PIN FUNCTION DESCRIPTION
Pin
Pin
TSOP−5
UDFN6
Pin Name
Type
Description
1
6
EN
Analog Input
Enable for switching regulators. This pin is active HIGH and is turned off by
logic LOW on this pin.
2
2,4,7
(Note 1)
GND
Analog /
This pin is the GND reference for the NFET power stage and the analog
Power Ground section of the IC. The pin must be connected to the system ground.
3
4
5
3
SW
VIN
Analog Output Connection from power MOSFETs to the Inductor.
Analog /
Power supply input for the PFET power stage, analog and digital blocks. The
pin must be decoupled to ground by a 4.7 mF ceramic capacitor.
Power Input
5
1
FB
Analog Input
Feedback voltage from the output of the power supply. This is the input to the
error amplifier.
1. Exposed pad for UDFN6 package, named Pin 7, must be connected to system ground.
PIN CONNECTIONS
FB
EN
EN
GND
SW
1
2
5
4
FB
GND
VIN
1
2
6
5
7
SW
GND
3
VIN
3
4
(Top View)
(Top View)
Figure 3. Pin Connections − TSOP−5
Figure 4. Pin Connections − UDFN6
PERFORMANCES
100
90
80
70
60
50
40
30
20
10
0
0
500
1000
I
(mA)
OUT
Figure 5. Efficiency vs Output Current
V
IN = 3.6 V, VOUT = 3.3 V
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NCP1529
FUNCTIONAL BLOCK DIAGRAM
Q1
Q2
2.2 mH
V
battery
VIN
SW
PWM/PFM
CONTROL
10 mF
4.7 mF
18 pF
GND
EN
R1
I
LIMIT
LOGIC
CONTROL
& THERMAL
SHUTDOWN
Enable
FB
REFERENCE
VOLTAGE
R2
Figure 6. Simplified Block Diagram
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3
NCP1529
MAXIMUM RATINGS
Rating
Symbol
Value
−0.3
7.0
Unit
V
Minimum Voltage All Pins
V
min
max
max
Maximum Voltage All Pins (Note 2)
Maximum Voltage EN
V
V
V
V
+ 0.3
V
IN
Thermal Resistance, Junction−to−Air (TSOP−5 Package)
Thermal Resistance using TSOP−5 Recommended Board Layout (Note 9)
R
300
110
°C/W
q
JA
Thermal Resistance, Junction−to−Air (UDFN6 Package)
Thermal Resistance using UDFN6 Recommended Board Layout (Note 9)
R
220
40
°C/W
q
JA
Operating Ambient Temperature Range (Notes 7 and 8)
Storage Temperature Range
T
−40 to 85
−55 to 150
−40 to 150
$100
°C
°C
A
T
stg
Junction Operating Temperature (Notes 7 and 8)
T
°C
j
Latchup Current Maximum Rating (T = 85°C) (Note 5) Other Pins
Lu
mA
A
ESD Withstand Voltage (Note 4)
Human Body Model
Machine Model
V
esd
2.0
200
kV
V
Moisture Sensitivity Level (Note 6)
MSL
1
per IPC
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
2. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at T = 25°C.
A
3. According to JEDEC standard JESD22−A108B.
4. This device series contains ESD protection and exceeds the following tests:
Human Body Model (HBM) per JEDEC standard: JESD22−A114.
Machine Model (MM) per JEDEC standard: JESD22−A115.
5. Latchup current maximum rating per JEDEC standard: JESD78.
6. JEDEC Standard: J−STD−020A.
7. In applications with high power dissipation (low V , high I
), special care must be paid to thermal dissipation issues. Board design
IN
OUT
considerations − thermal dissipation vias, traces or planes and PCB material − can significantly improve junction to air thermal resistance
R
(for more information, see design and layout consideration section). Environmental conditions such as ambient temperature T brings
q
JA
A
thermal limitation on maximum power dissipation allowed.
The following formula gives calculation of maximum ambient temperature allowed by the application:
T
= T
− (R
x P )
JA d
q
A MAX
J MAX
Where: T is the junction temperature,
J
P is the maximum power dissipated by the device (worst case of the application),
d
and R
is the junction−to−ambient thermal resistance.
q
JA
8. To prevent permanent thermal damages, this device include a thermal shutdown which engages at 180°C (typ).
9. Board recommended TSOP−5 and UDFN6 layouts are described on Layout Considerations section.
1200
1000
800
600
400
200
0
1200
1000
800
600
400
200
0
UDFN6
UDFN6
TSOP−5
TSOP−5
−40
−20
0
20
40
60
80
2.7
3.2
3.7
V , INPUT VOLTAGE (V)
IN
4.2
4.7
5.2
T , AMBIENT TEMPERATURE (°C)
A
Figure 8. Power Derating
Figure 7. Maximum Output Current, TA = 455C
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NCP1529
ELECTRICAL CHARACTERISTICS (Typical values are referenced to T = +25°C, Min and Max values are referenced −40°C to
A
+85°C ambient temperature, unless otherwise noted, operating conditions V = 3.6 V, V
= 1.2 V, unless otherwise noted.)
IN
OUT
Rating
Conditions
Symbol Min
Typ
Max
Unit
INPUT VOLTAGE
Input Voltage Range
V
2.7
−
−
5.5
39
V
mA
mA
V
in
Quiescent Current
No Switching, No load
EN Low
Falling
I
Q
28
Standby Current
I
−
0.3
2.4
100
1.0
2.55
−
STB
Under Voltage Lockout
V
IN
V
2.2
−
UVLO
Under Voltage Hysteretis
ANALOG AND DIGITAL PIN
Positive going Input High Voltage Threshold
Negative going Input High Voltage Threshold
EN Threshold Hysteresis
EN High Input Current
V
mV
UVLOH
V
IH
1.2
−
−
−
−
0.4
−
V
V
V
IL
V
ENH
ENH
−
100
1.5
mV
mA
EN = 3.6 V
I
−
−
OUTPUT
Feedback Voltage Level
Adjustable Version
Fixed Version at 1.2 V
Fixed Version at 1.35 V
V
−
−
−
0.6
1.2
−
−
−
V
V
FB
1.35
Output Voltage Range (Notes 10, 11)
V
OUT
0.9
0.9
−
−
3.3
3.9
USB or 5 V Rail Powered Applications
(V from 4.3 V to 5.5 V) (Note 12)
IN
Output Voltage Accuracy
Room Temperature (Note 13)
Overtemperature Range
DV
−
−3
$1
$2
−
+3
%
OUT
Maximum Output Current (Note 10)
I
1
−
−
A
OUTMAX
Output Voltage Load Regulation
Overtemperature
Load = 100 mA to 1000 mA (PWM Mode)
Load = 0 mA to 100 mA (PFM Mode)
V
−
−
−0.9
1.1
−
−
%
LOADR
Load Transient Response
Rise/Fall Time 1 ms
10 mA to 100 mA Load Step
(PFM to PWM Mode)
200 mA to 600 mA Load Step
(PWM to PWM Mode)
V
−
−
40
85
−
−
mV
LOADT
Output Voltage Line Regulation Load = 100 mA
Line Transient Response Load = 100 mA
Output Voltage Ripple
V
= 2.7 V to 5.5 V
V
−
−
0.05
6.0
−
−
%
IN
LINER
3.6 V to 3.2 V Line Step (Fall Time = 50 ms)
V
mV
mV
LINET
PP
I
I
= 0 mA
= 300 mA
V
−
−
8.0
3.0
−
−
OUT
OUT
RIPPLE
PP
Switching Frequency
F
1.2
−
1.7
−
2.2
100
500
MHz
%
SW
Duty Cycle
D
Soft−Start Time
Time from EN to 90% of Output Voltage
t
−
310
ms
START
POWER SWITCHES
High−Side MOSFET On−Resistance
Low−Side MOSFET On−Resistance
High−Side MOSFET Leakage Current
Low−Side MOSFET Leakage Current
PROTECTION
R
−
−
−
−
400
300
−
−
−
−
mW
mW
mA
ONHS
R
ONLS
I
0.05
0.01
LEAKHS
I
mA
LEAKLS
DC−DC Short Circuit Protection
Thermal Shutdown Threshold
Thermal Shutdown Hysteresis
Peak Inductor Current
I
−
−
−
1.6
180
40
−
−
−
A
PK
T
°C
°C
SD
T
SDH
10.Functionality guaranteed per design and characterization.
11. Whole output voltage range is available for adjustable versions only. By topology, the maximum output voltage will be equal or lower than
the input voltage.
12.See chapter ”USB or 5 V Rail Powered Applications”.
13.For adjustable versions only, the overall output voltage tolerance depends upon the accuracy of the external resistor (R1 and R2). Specified
value assumes that external resistor have 0.1% tolerance.
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NCP1529
TABLE OF GRAPHS
Typical Characteristics for Step−down Converter
Figure
h
Efficiency
vs. Output Current
vs. Input Voltage
10, 11, 12
I
Quiescent Current, PFM no load
Standby Current, EN Low
Switching Frequency
Load Regulation
9
8
q ON
I
vs. Input Voltage
q OFF
F
vs. Ambient Temperature
vs. Load Current
13
SW
V
14
LOADR
V
Load Transient Response
Line Regulation
16, 17
15
LOADT
V
vs. Output Current
LINER
V
Line Transient Response
Soft Start
18, 19
20
LINET
t
START
I
Short Circuit Protection
Under Voltage Lockout Threshold
Enable Threshold
21
PK
V
vs. Ambient Temperature
vs. Ambient Temperature
22
UVLO
V , V
IL
23
IH
P, G
Phase & Gain Performance
24
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NCP1529
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
31
30
29
28
27
2.5
3.0
3.5
4.0
4.5
5.0
5.5
2.5
3.0
3.5
V , INPUT VOLTAGE (V)
IN
4.0
4.5
5.0
5.5
V
IN
, INPUT VOLTAGE (V)
Figure 9. Standby Current vs. Input Voltage
Figure 10. Quiescent Current vs. Input Voltage
(Open Loop, Feedback = 1,
(Enable = 0, Temperature = 255C)
Temperature = 255C)
100
90
80
70
60
50
40
30
20
10
0
100
90
80
70
60
50
40
30
20
10
0
−40°C
5.5 V
25°C
V
= 2.7 V
BAT
3.3 V
85°C
0
200
400
600
800
1000
0
200
400
600
800
1000
I , OUTPUT CURRENT (mA)
OUT
I , OUTPUT CURRENT (mA)
OUT
Figure 11. Efficiency vs. Output Current
(VIN = 3.3 V, VOUT = 1.2 V)
Figure 12. Efficiency vs. Output Current
(Vout = 1.2 V, Temperature = 255C)
2.2
2.1
2
100
90
80
70
60
50
40
30
20
10
0
3.3 V
1.2 V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
V
IN
= 2.7 V
V
= 0.9 V
OUT
3.6 V
5.5 V
60
0
200
400
600
800
1000
−60
−20
20
100
I , OUTPUT CURRENT (mA)
OUT
T , AMBIENT TEMPERATURE (°C)
A
Figure 13. Efficiency vs. Output Current
Figure 14. Switching Frequency vs. Ambient
Temperature (Vout = 1.2 V, Iout = 200 mA)
(VIN = 3.6 V, Temperature = 255C)
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NCP1529
3.0
2.0
3.0
2.0
1.0
1.0
100 mA
−40°C
0.0
0
−1.0
−2.0
−3.0
−1.0
−2.0
−3.0
1 mA
I
= 800 mA
OUT
25°C
85°C
0
200
400
600
800
1000
2.7
3.2
3.7
4.2
4.7
5.2
I , OUTPUT CURRENT (mA)
OUT
V , INPUT VOLTAGE (V)
IN
Figure 15. Load Regulation vs. Output Current
(VIN = 5.5 V, VOUT = 1.2 V)
Figure 16. Line Regulation vs. Input Voltage
(VOUT = 1.2 V, Temperature = 255C)
Figure 17. 10 mA to 100 mA Load Transient in 1 ms
(VIN = 3.6 V, VOUT = 1.2 V, Temperature = 255C)
Figure 18. 200 mA to 600 mA Load Transient in 1 ms
(VIN = 3.6 V, VOUT = 1.2 V, Temperature = 255C)
Figure 19. 3.0 V to 3.6 V Line Transient, Rise = 50 ms
(VIN = 1.2 V, IOUT = 100 mA, Temperature = 255C)
Figure 20. 3.6 V to 3.0 V Line Transient, Fall = 50 ms
(VIN = 1.2 V, IOUT = 100 mA, Temperature = 255C)
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NCP1529
Figure 21. Typical Soft−Start (VIN = 3.6 V, VOUT = 1.2 V,
Figure 22. Short−Circuit Protection (VIN = 3.6 V,
IOUT = 100 mA, Temperature = 255C)
V
OUT = 1.2 V, IOUT = CC, Temperature = 255C)
2.60
2.55
2.50
2.45
2.40
2.35
2.30
2.25
2.20
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
UVLOrise
UVLOfall
V
IH
V
IL
−50
−25
0
25
50
75
100
125
−40
−15
10
35
60
85
T , AMBIENT TEMPERATURE (°C)
A
T , AMBIENT TEMPERATURE (°C)
A
Figure 23. Undervoltage Lockout Threshold
vs. Ambient Temperature
Figure 24. Enable Threshold Voltages vs.
Ambient Temperature
70
200
160
120
50
30
80
Phase
40
0
10
Gain
−10
−30
−50
−40
−80
−120
−160
10
100
1000
10000
100000
1000000
FREQUENCY (Hz)
Figure 25. Phase and Gain Performance
(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 200 mA, Temperature = 255C)
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NCP1529
DC/DC OPERATION DESCRIPTION
Detailed Description
V
OUT
The NCP1529 uses a constant frequency, current mode
step−down architecture. Both the main (P−channel
MOSFET) and synchronous (N−channel MOSFET)
switches are internal.
The output voltage is set by an external resistor divider in
the range of 0.9 V to 3.9 V and can source at least 1A.
The NCP1529 works with two modes of operation;
PWM/PFM depending on the current required. In PWM
mode, the device can supply voltage with a tolerance of
$3% and 90% efficiency or better. Lighter load currents
cause the device to automatically switch into PFM mode to
reduce current consumption and extended battery life.
Additional features include soft−start, undervoltage
protection, current overload protection and thermal
shutdown protection. As shown on Figure 1, only six
external components are required. The part uses an internal
reference voltage of 0.6 V. It is recommended to keep
NCP1529 in shutdown mode until the input voltage is 2.7 V
or higher.
I
SW
V
SW
Figure 26. PWM Switching Waveforms
(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 600 mA,
Temperature = 255C)
PFM Operating Mode
Under light load conditions, the NCP1529 enters in low
current PFM mode of operation to reduce power
consumption. The output regulation is implemented by
pulse frequency modulation. If the output voltage drops
below the threshold of PFM comparator a new cycle will be
initiated by the PFM comparator to turn on the switch Q1.
Q1 remains ON during the minimum on time of the structure
while Q2 is in its current source mode. The peak inductor
current depends upon the drop between input and output
voltage. After a short dead time delay where Q1 is switched
OFF, Q2 is turned in its ON state. The negative current
detector will detect when the inductor current drops below
zero and sends a signal to turn Q2 to current source mode to
prevent a too large deregulation of the output voltage. When
the output voltage falls below the threshold of the PFM
comparator, a new cycle starts immediately.
PWM Operating Mode
In this mode, the output voltage of the device is regulated
by modulating the on−time pulse width of the main switch
Q1 at a fixed 1.7 MHz frequency.
The switching of the PMOS Q1 is controlled by a flip−flop
driven by the internal oscillator and a comparator that
compares the error signal from an error amplifier with the
sum of the sensed current signal and compensation ramp.
The driver switches ON and OFF the upper side transistor
(Q1) while the lower side transistor is switched OFF then
ON.
At the beginning of each cycle, the main switch Q1 is
turned ON by the rising edge of the internal oscillator clock.
The inductor current ramps up until the sum of the current
sense signal and compensation ramp becomes higher than
the error amplifier’s voltage. Once this has occurred, the
PWM comparator resets the flip−flop, Q1 is turned OFF
while the synchronous switch Q2 is turned ON. Q2 replaces
the external Schottky diode to reduce the conduction loss
and improve the efficiency. To avoid overall power loss, a
certain amount of dead time is introduced to ensure Q1 is
completely turned OFF before Q2 is being turned ON.
V
OUT
V
SW
I
SW
Figure 27. PFM Switching Waveforms
(VIN = 3.6 V, VOUT = 1.2 V, IOUT = 0 mA,
Temperature = 255C)
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NCP1529
Soft−Start
temperature exceeds 180°C, the device shuts down. In this
mode all power transistors and control circuits are turned
off. The device restarts in soft−start after the temperature
drops below 140°C. This feature is provided to prevent
catastrophic failures from accidental device overheating.
The NCP1529 uses soft−start to limit the inrush current
when the device is initially powered up or enabled. Soft start
is implemented by gradually increasing the reference
voltage until it reaches the full reference voltage. During
startup, a pulsed current source charges the internal
soft−start capacitor to provide gradually increasing
reference voltage. When the voltage across the capacitor
ramps up to the nominal reference voltage, the pulsed
current source will be switched off and the reference voltage
will switch to the regular reference voltage.
Short Circuit Protection
When the output is shorted to ground, the device limits the
inductor current. The duty−cycle is minimum and the
consumption on the input line is 550 mA (typ). When the
short circuit condition is removed, the device returns to the
normal mode of operation.
Cycle−by−cycle Current Limitation
From the block diagram, an I
USB or 5 V Rail Powered Applications
comparator is used to
LIM
For USB or 5 V rail powered applications, NCP1529 is
able to supply voltages up to 3.9 V, 600 mA, operating in
PWM mode only, with high efficiency (Figure 28), low
output voltage ripple and good load regulation results over
all current range (Figure 29).
realize cycle−by−cycle current limit protection. The
comparator compares the SW pin voltage with the reference
voltage, which is biased by a constant current. If the inductor
current reaches the limit, the I
comparator detects the
LIM
SW voltage falling below the reference voltage and releases
the signal to turn off the switch Q1. The cycle−by−cycle
current limit is set at 1600 mA (nom).
100
95
−40°C
90
85
Low Dropout Operation
The NCP1529 offers a low input to output voltage
difference. The NCP1529 can operate at 100% duty cycle.
In this mode the PMOS (Q1) remains completely ON. The
minimum input voltage to maintain regulation can be
calculated as:
25°C
80
75
70
65
60
55
50
45
40
85°C
ǒ
Ǔ
Ǔ
ǒ
(eq. 1)
Vout + VOUT(max) ) IOUT RDS(on)_RINDUCTOR
• V
: Output Voltage (V)
: Max Output Current
OUT
• I
OUT
0
200
400
600
800
1000
• R
• R
: P−Channel Switch R
DS(on)
DS(on)
I
, OUTPUT CURRENT (mA)
OUT
: Inductor Resistance (DCR)
INDUCTOR
Figure 28. Efficiency vs. Output Current
(VIN = 5.0 V, VOUT = 3.9 V)
Undervoltage Lockout
3.0
2.5
2.0
The Input voltage V must reach 2.4 V (typ) before the
IN
NCP1529 enables the DC/DC converter output to begin the
start up sequence (see soft−start section). The UVLO
threshold hysteresis is typically 100 mV.
1.5
1.0
Shutdown Mode
0.5
−40°C
Forcing this pin to a voltage below 0.4 V will shut down
the IC. In shutdown mode, the internal reference, oscillator
and most of the control circuitries are turned off. Therefore,
the typical current consumption will be 0.3 mA (typical
value). Applying a voltage above 1.2 V to EN pin will enable
the DC/DC converter for normal operation. The device will
go through soft−start to normal operation.
0.0
−0.5
−1.0
−1.5
−2.0
−2.5
−3.0
25°C
85°C
0
200
I
400
600
800
1000
Thermal Shutdown
, OUTPUT CURRENT (mA)
OUT
Internal Thermal Shutdown circuitry is provided to
protect the integrated circuit in the event that the maximum
junction Temperature is exceeded. If the junction
Figure 29. Load Regulation vs. Output Current
(VIN = 5.0 V, VOUT = 3.9 V)
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11
NCP1529
APPLICATION INFORMATION
Output Voltage Selection
Input Capacitor Selection
In case of adjustable versions, the output voltage is
programmed through an external resistor divider connected
In PWM operating mode, the input current is pulsating
with large switching noise. Using an input bypass capacitor
can reduce the peak current transients drawn from the input
supply source, thereby reducing switching noise
significantly. The capacitance needed for the input bypass
capacitor depends on the source impedance of the input
supply.
from V
to FB then to GND.
OUT
For low power consumption and noise immunity, the
resistor from FB to GND (R2) should be in the [100k−600k]
range. If R2 is 200 k given the V is 0.6 V, the current
FB
through the divider will be 3.0 mA.
The formula below gives the value of V
desired R1 and the R1 value:
, given the
The maximum RMS current occurs at 50% duty cycle
with maximum output current, which is IO, max/2.
For NCP1529, a low profile ceramic capacitor of 4.7 mF
should be used for most of the cases. For effective bypass
results, the input capacitor should be placed as close as
possible to the VIN Pin
OUT
Vout + VFB (1 ) R1ńR2)
(eq. 2)
• V
: Output Voltage (V)
• V : Feedback Voltage = 0.6 V
OUT
FB
• R1: Feedback Resistor from V
• R2: Feedback Resistor from FB to GND
to FB
OUT
Table 1. LIST OF INPUT CAPACITORS
Manufacturer
Part Number
Case Size
Value
(mF)
DC Bias
(V)
Technology
MURATA
MURATA
TDK
GRM15 series
GRM18 series
C1608 series
C1608 series
0402
0603
0603
0603
4.7
4.7
4.7
4.7
6.3
10
X5R
X5R
X5R
X5R
6.3
10
TDK
Output L−C Filter Design Considerations
Inductor Selection
The NCP1529 operates at 1.7 MHz frequency and uses
current mode architecture. The correct selection of the
output filter ensures good stability and fast transient
response.
The inductor parameters directly related to device
performances are saturation current and DC resistance and
inductance value. The inductor ripple current (DI )
L
decreases with higher inductance:
Due to the nature of the buck converter, the output L−C
filter must be selected to work with internal compensation.
For NCP1529, the internal compensation is internally fixed
and it is optimized for an output filter of L = 2.2 mH and
VOUT
VOUT
ǒ1 * Ǔ
VIN
(eq. 4)
DIL +
L fSW
• DI : Peak to peak inductor ripple current
L
C
OUT
= 10 mF.
• L: Inductor value
The corner frequency is given by:
• f : Switching frequency
SW
1
1
The saturation current of the inductor should be rated
higher than the maximum load current plus half the ripple
current:
f +
+
+ 34 kHz
Ǹ
2p 2.2 mH 10 mF
Ǹ
2p L COUT
(eq. 3)
The device operates with inductance value of 2.2 mH. If
the corner frequency is moved, it is recommended to check
the loop stability depending of the accepted output ripple
voltage and the required output current. Take care to check
the loop stability. The phase margin is usually higher than
45°.
DIL
(eq. 5)
IL(max) + IO(max)
)
2
• I
• I
: Maximum inductor current
: Maximum Output current
The inductor’s resistance will factor into the overall
efficiency of the converter. For best performances, the DC
resistance should be less than 0.3 W for good efficiency.
L(max)
O(max)
Table 2. L−C FILTER EXAMPLE
Inductance (L)
2.2 mH
Output Capacitor (C
)
OUT
10 mF
4.7 mH
4.7 mF
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12
NCP1529
Table 3. LIST OF INDUCTORS
Manufacturer
Part Number
Case
Size
(mm)
Height
Max
(mm)
L
(mH)
DCR
Typ
(W)
DCR
Max
(W)
Rated
Current (mA)
Inductance
Drop
Rated
Current (mA)
Temperature
Drop
Structure
COILCRAFT
COILCRAFT
COILCRAFT
MURATA
MURATA
MURATA
TDK
DO1605T-222
EPL3015-222
EPL2014-222
LQM2HPN2R2
LQH3NPN2R2
LQH44PN2R2
MLP2520S2R2L
VLS252010T2R2
5.5 x 4.2
3.0 x 3.0
2.0 x 2.0
2.5 x 2.0
3.0 x 3.0
4.0 x 4.0
2.5 x 2.0
2.0 x 1.6
2.8 x 2.8
1.8
1.5
1.4
1.0
1.2
1.8
1.0
1.2
1.35
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
2.2
NA
0.070
0.094
0.132
0.100
0.085
0.059
0.104
0.190
0.105
1800 (-10%)
1600 (-30%)
1300 (-30%)
NA
1700 (+40°C)
2000 (+40°C)
1810 (+40°C)
1300 (+40°C)
1460 (+40°C)
1800 (+40°C)
NA
Wire Wound
Wire Wound
Wire Wound
Multilayer
0.082
0.120
0.080
0.065
0.049
0.080
0.158
0.088
1150 (-30%)
2500 (-30%)
1300 (-30%)
1400 (-30%)
1150 (-35%)
Wire Wound
Wire Wound
Multilayer
TDK
1100 (+40°C)
1700 (+40°C)
Wire Wound
Wire Wound
WURTH ELEC 744 029 002
Output Capacitor Selection
The output ripple voltage in PWM mode is given by:
Selecting the proper output capacitor is based on the
desired output ripple voltage. Ceramic capacitors with low
ESR values will have the lowest output ripple voltage and
are strongly recommended. The output capacitor requires
either an X7R or X5R dielectric.
1
(eq. 6)
ǒ
) ESRǓ
DVOUT + DIL
4 fSW COUT
Table 4. LIST OF OUTPUT CAPACITORS
Manufacturer
Part Number
Case Size
Value
(mF)
DC Bias
(V)
Technology
MURATA
MURATA
MURATA
TDK
GRM15 series
GRM18 series
GRM18 series
C1608 series
C1608 series
C1608 series
0402
0603
0603
0603
0603
0603
4.7
4.7
10
6.3
10
X5R
X5R
X5R
X5R
X5R
X5R
6.3
6.3
10
4.7
4.7
10
TDK
TDK
6.3
Feed−Forward Capacitor Selection (Adjustable Only)
The feed-forward capacitor sets the feedback loop
response and acts on soft-start time. A minimum 18 pF
feed-forward capacitor is needed to ensure loop stability.
Having feed-forward capacitor of 1 nF or higher can
increase soft−start time and reduce inrush current. Choose a
small ceramic capacitor X7R or X5R or COG dielectric.
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13
NCP1529
LAYOUT CONSIDERATIONS
Electrical Layout Considerations
capacitor is recommended to meet compensation
requirements.
A four layer PCB with a ground plane and a power plane
will help NCP1529 noise immunity and loop stability.
Implementing a high frequency DC−DC converter
requires respect of some rules to get a powerful portable
application. Good layout is key to prevent switching
regulators to generate noise to application and to
themselves.
Thermal Layout Considerations
High power dissipation in small package leads to thermal
consideration such as:
Electrical layout guide lines are:
• Use short and large traces when large amount of current
is flowing.
• Keep the same ground reference for input and output
capacitors to minimize the loop formed by high current
path from the battery to the ground plane.
• Isolate feedback pin from the switching pin and the
current loop to protect against any external parasitic
signal coupling. Add a feed−forward capacitor between
• Enlarge V trace and added several vias connected to
IN
power plane.
• Connect GND pin to top plane.
• Join top, bottom and each ground plane together using
several free vias in order to increase radiator size.
For high ambient temperature and high power dissipation
requirements, UDFN6 package using exposed pad
connected to main radiator is recommended. Refer to
Notes 7, 8, and 9.
V
OUT
and FB which adds a zero to the loop and
participates to the good loop stability. A 18 pF
EN Trace
FB Trace
V
Trace
OUT
V
IN
Trace
SW
Trace
SW
Trace
V
IN
Trace
FB Trace
V
OUT
Trace
GND Plane
GND Plane
EN Trace
Figure 30. TSOP−5 Recommended Board Layout
Figure 31. UDFN6 Recommended Board Layout
ORDERING INFORMATION
Nominal
Output Voltage
Device
Marking
DXJ
TL
Package
Shipping†
NCP1529ASNT1G
Adj
Adj
TSOP−5
3000 / Tape & Reel
NCP1529MUTBG
NCP1529MU12TBG
NCP1529MU135TBG
1.2 V
1.35 V
TC
UDFN6
3000 / Tape & Reel
RC
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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14
NCP1529
PACKAGE DIMENSIONS
TSOP−5
CASE 483−02
ISSUE G
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. MAXIMUM LEAD THICKNESS INCLUDES
LEAD FINISH THICKNESS. MINIMUM LEAD
THICKNESS IS THE MINIMUM THICKNESS
OF BASE MATERIAL.
4. DIMENSIONS A AND B DO NOT INCLUDE
MOLD FLASH, PROTRUSIONS, OR GATE
BURRS.
5. OPTIONAL CONSTRUCTION: AN
ADDITIONAL TRIMMED LEAD IS ALLOWED
IN THIS LOCATION. TRIMMED LEAD NOT TO
EXTEND MORE THAN 0.2 FROM BODY.
NOTE 5
5X
D
0.20 C A B
2X
2X
0.10
T
T
M
5
4
3
0.20
B
S
1
2
K
L
DETAIL Z
G
A
MILLIMETERS
DIM
A
B
C
D
MIN
3.00 BSC
1.50 BSC
MAX
DETAIL Z
J
0.90
1.10
0.50
C
0.25
SEATING
PLANE
0.05
G
H
J
K
L
M
S
0.95 BSC
H
0.01
0.10
0.20
1.25
0
0.10
0.26
0.60
1.55
10
3.00
T
_
_
2.50
SOLDERING FOOTPRINT*
1.9
0.074
0.95
0.037
2.4
0.094
1.0
0.039
0.7
0.028
mm
inches
ǒ
Ǔ
SCALE 10:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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15
NCP1529
PACKAGE DIMENSIONS
UDFN6 2x2, 0.65P
CASE 517AB−01
ISSUE A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.15 AND 0.20mm FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
D
A
B
MILLIMETERS
E
PIN ONE
REFERENCE
DIM
A
MIN
0.45
0.00
MAX
0.55
0.05
A1
A3
b
0.127 REF
2X
0.10
C
0.25
1.50
0.35
D
2.00 BSC
D2
E
1.70
2.00 BSC
2X
0.10
C
E2
e
0.80
1.00
0.65 BSC
K
0.20
0.25
---
A3
L
0.35
0.10
C
C
A
SOLDERING FOOTPRINT*
6X
0.08
6X
0.47
A1
0.95
SEATING
PLANE
C
6X
0.40
1
D2
4X
e
6X
L
1
6
3
1.70
E2
0.65
4
6X
K
PITCH
6X
b
2.30
0.10
C
C
A
B
BOTTOM VIEW
DIMENSIONS: MILLIMETERS
NOTE 3
0.05
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
The product described herein (NCP1529), may be covered by the following U.S. patents: TBD. There may be other patents pending.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications
intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should
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associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal
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NCP1529/D
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