NE80546RE072256_技术文档

®

∆

Intel Celeron D Processor 3xx

Sequence

Datasheet

– On 90 nm Process in the 478-pin Package

June 2005

Document Number: 302353-005

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INTELLECTUAL PROPERTY RIGHT. INTEL PRODUCTS ARE NOT INTENDED FOR USE IN MEDICAL, LIFE SAVING, OR LIFE SUSTAINING

APPLICATIONS.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked "reserved" or "undefined." Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel^®Celeron^®D processors 3xx sequence on 90 nm process and in the 478-pin package may contain design defects or errors known as errata

which may cause the product to deviate from published specifications. Current characterized errata are available on request.

^∆Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families. See www.intel.com/products/processor_number for details.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, Pentium, Celeron, Intel Xeon, Intel NetBurst and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in

the United States and other countries.

*Other names and brands may be claimed as the property of others.

2

Datasheet

Contents

1

Introduction................................................................................................................11

1.1

Terminology.........................................................................................................11

1.1.1 Processor Packaging Terminology.........................................................12

References..........................................................................................................13

1.2

2

Electrical Specifications........................................................................................15

2.1

2.2

2.3

FSB and GTLREF ...............................................................................................15

Power and Ground Pins ......................................................................................15

Decoupling Guidelines ........................................................................................15

2.3.1

V_CCDecoupling......................................................................................16

2.3.2 FSB GTL+ Decoupling ...........................................................................16

2.3.3 FSB Clock (BCLK[1:0]) and Processor Clocking....................................16

Voltage Identification...........................................................................................17

2.4.1 Phase Lock Loop (PLL) Power and Filter...............................................18

Reserved, Unused, and TESTHI Pins.................................................................19

FSB Signal Groups..............................................................................................20

Asynchronous GTL+ Signals...............................................................................21

Test Access Port (TAP) Connection....................................................................21

FSB Frequency Select Signals (BSEL[1:0])........................................................22

Absolute Maximum and Minimum Ratings..........................................................22

Processor DC Specifications...............................................................................23

2.4

2.5

2.6

2.7

2.8

2.9

2.10

2.11

2.12

V

_CCOvershoot Specification...............................................................................28

2.12.1 Die Voltage Validation............................................................................29

GTL+ FSB Specifications....................................................................................30

2.13

3

Package Mechanical Specifications.................................................................31

3.1

3.2

3.3

3.4

3.5

3.6

3.7

3.8

3.9

Package Mechanical Drawing.............................................................................31

Processor Component Keep-Out Zones .............................................................34

Package Loading Specifications .........................................................................34

Package Handling Guidelines .............................................................................35

Package Insertion Specifications ........................................................................35

Processor Mass Specification .............................................................................35

Processor Materials.............................................................................................35

Processor Markings.............................................................................................36

Processor Pinout Coordinates.............................................................................37

4

5

Pin Listing and Signal Descriptions.................................................................39

4.1

4.2

Processor Pin Assignments ................................................................................39

Alphabetical Signals Reference ..........................................................................54

Thermal Specifications and Design Considerations.................................63

5.1

5.2

Processor Thermal Specifications.......................................................................63

5.1.1 Thermal Specifications...........................................................................63

5.1.2 Thermal Metrology .................................................................................64

Processor Thermal Features...............................................................................65

5.2.1 Thermal Monitor .....................................................................................65

5.2.2 On-Demand Mode..................................................................................65

Datasheet

3

5.2.3 PROCHOT# Signal Pin..........................................................................66

5.2.4 THERMTRIP# Signal Pin .......................................................................66

5.2.5

T_CONTROLand Fan Speed Reduction (Optional) ...................................67

5.2.6 Thermal Diode........................................................................................67

6

7

Features.......................................................................................................................69

6.1

6.2

Power-On Configuration Options ........................................................................69

Clock Control and Low Power States..................................................................69

6.2.1 Normal State—State 1 ...........................................................................69

6.2.2 AutoHALT Powerdown State—State 2 ..................................................70

6.2.3 Stop-Grant State—State 3 .....................................................................71

6.2.4 HALT/Grant Snoop State—State 4 ........................................................71

6.2.5 Sleep State—State 5..............................................................................72

Boxed Processor Specifications.......................................................................73

7.1

Mechanical Specifications...................................................................................74

7.1.1 Boxed Processor Cooling Solution Dimensions.....................................74

7.1.2 Boxed Processor Fan Heatsink Weight..................................................75

7.1.3 Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly .............................................................................75

Electrical Requirements ......................................................................................76

7.2.1 Fan Heatsink Power Supply...................................................................76

Thermal Specifications........................................................................................77

7.3.1 Boxed Processor Cooling Requirements ...............................................77

7.3.2 Variable Speed Fan ...............................................................................79

7.2

7.3

8

Debug Tools Specifications.................................................................................81

8.1

Logic Analyzer Interface (LAI).............................................................................81

8.1.1 Mechanical Considerations....................................................................81

8.1.2 Electrical Considerations........................................................................81

4

Datasheet

Figures

2-1

2-2

2-3

3-1

3-2

3-3

3-4

3-5

3-6

4-1

4-2

5-1

6-1

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

Phase Lock Loop (PLL) Filter Requirements ......................................................18

V

_CCStatic and Transient Tolerance....................................................................25

_CCOvershoot Example Waveform....................................................................29

Processor Package Assembly Sketch.................................................................31

Processor Package Drawing (Sheet 1 of 2) ........................................................32

Processor Package Drawing (Sheet 2 of 2) ........................................................33

Processor Top-Side Marking Example (with Processor Number).......................36

Processor Top-Side Marking Example................................................................36

Processor Pinout Coordinates (Top View) ..........................................................37

Pinout Diagram (Top View—Left Side) ...............................................................40

Pinout Diagram (Top View—Right Side).............................................................41

Case Temperature (TC) Measurement Location.................................................64

Stop Clock State Machine...................................................................................70

Mechanical Representation of the Boxed Intel^®Celeron^®D Processor .............73

Requirements for the Boxed Processor (Side View)...........................................74

Space Requirements for the Boxed Processor (Top View).................................74

Boxed Processor Fan Heatsink Power Cable Connector Description.................76

Baseboard Power Header Placement Relative to Processor Socket..................77

Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)78

Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)78

Boxed Processor Fan Heatsink Set Points .........................................................79

Datasheet

5

Tables

1-1

2-1

2-2

2-3

2-4

2-5

2-6

2-7

References..........................................................................................................13

Core Frequency to FSB Multiplier Configuration.................................................16

Voltage Identification Definition...........................................................................17

FSB Pin Groups ..................................................................................................20

Signal Characteristics .........................................................................................21

Signal Reference Voltages..................................................................................21

BSEL[1:0] Frequency Table for BCLK[1:0] .........................................................22

Processor DC Absolute Maximum Ratings.........................................................22

Voltage and Current Specifications.....................................................................23

2-8

2-9

V_CCStatic and Transient Tolerance....................................................................24

2-10

2-11

2-12

2-13

2-14

2-15

2-16

2-17

2-18

3-1

3-2

3-3

4-1

4-2

4-3

5-1

5-2

5-3

GTL+ Signal Group DC Specifications................................................................26

Asynchronous GTL+ Signal Group DC Specifications........................................26

PWRGOOD and TAP Signal Group DC Specifications ......................................27

VCCVID DC Specifications .................................................................................27

VIDPWRGD DC Specifications...........................................................................27

BSEL [1:0] and VID[5:0] DC Specifications.........................................................28

BOOTSELECT DC Specifications.......................................................................28

V_CCOvershoot Specifications.............................................................................28

GTL+ Bus Voltage Definitions.............................................................................30

Processor Loading Specifications.......................................................................34

Package Handling Guidelines.............................................................................35

Processor Materials ............................................................................................35

Alphabetical Pin Assignment...............................................................................42

Numerical Pin Assignment..................................................................................48

Signal Description ...............................................................................................54

Processor Thermal Specifications.......................................................................64

Thermal Diode Parameters.................................................................................67

Thermal Diode Interface......................................................................................68

Power-On Configuration Option Pins..................................................................69

Fan Heatsink Power and Signal Specifications...................................................76

Boxed Processor Fan Heatsink Set Points .........................................................79

6-1

7-1

7-2

6

Datasheet

Revision History

Revision

Number

Description

Date

-001

-002

-003

-004

-005

•

Initial release

June 2004

Minor updates for clarity

Added 2.93 GHz processor

Added 3.06 GHz processor

July 2004

September 2004

November 2004

June 2005

Added 3.20 GHz processor (processor number 350)

Datasheet

7

8

Datasheet

®

Intel Celeron D Processor 3xx Sequence

Features

T Available at 3.20 GHz, 3.06 GHz,

2.93 GHz, 2.80 GHz, 2.66 GHz, 2.53 GHz,

and 2.40 GHz

T Binary compatible with applications

running on previous members of the Intel

microprocessor line

T FSB frequencies at 533 MHz

T Hyper-Pipelined Technology

—Advance Dynamic Execution

—Very deep out-of-order execution

T Enhanced branch prediction

T 16-KB Level 1 data cache

T 256-KB Advanced Transfer Cache (on-die,

full-speed Level 2 (L2) cache) with 4-way

associativity and Error Correcting Code

(ECC)

T 144 Streaming SIMD Extensions 2 (SSE2)

instructions

T 13 Streaming SIMD Extensions 3 (SSE3)

instructions

T Power Management capabilities

—System Management mode

—Multiple low-power states

T Optimized for 32-bit applications running

on advanced 32-bit operating systems

T 478-Pin Package

The Intel^®Celeron^®D processor family expands Intel’s processor family into the value-priced PC

market segment. Celeron D processors provide the value that offers the customer the capability to

affordably get onto the Internet, and use educational programs, home-office software, and

productivity applications. All of the Celeron D processors include an integrated L2 cache, and are

built on Intel’s advanced CMOS process technology. The Celeron D processor is backed by over

30 years of Intel experience in manufacturing high-quality, reliable microprocessors.

§

Datasheet

9

10

Datasheet

Introduction

1 Introduction

The Intel^®Celeron^®D processor on 90 nm process and in the 478-pin package uses Flip-Chip Pin

Grid Array 4 (FC-mPGA4) package technology, and plugs into a 478-pin surface mount, Zero

Insertion Force (ZIF) socket, referred to as the mPGA478B socket. The Celeron D processor on

90 nm process and in the 478-pin package is based on the same Intel 32-bit microarchitecture and

maintains the tradition of compatibility with IA-32 software.

Note: In this document the Celeron D processor on 90 nm process in the 478-pin package will be referred

to as the “Celeron D processor,” or simply “the processor.”

Note: In this document, unless otherwise specified, the Intel^®Celeron^®D processor 3xx sequence refers

to Intel Celeron D processors 350, 345, 340, 335, 330, 325, and 320.

In addition to supporting all the existing Streaming SIMD Extensions 2 (SSE2), there are 13 new

instructions that further extend the capabilities of Intel processor technology. These new

instructions are called Steaming SIMD Extensions 3 (SSE3).

The Celeron D processor’s Front Side Bus (FSB) uses a split-transaction, deferred reply protocol

like the Intel^®Pentium 4 processor. The FSB uses Source-Synchronous Transfer (SST) of address

and data to improve performance by transferring data four times per bus clock (4X data transfer

rate, as in AGP 4X). Along with the 4X data bus, the address bus can deliver addresses two times

per bus clock and is referred to as a “double-clocked” or 2X address bus. Working together, the 4X

data bus and 2X address bus provide a data bus bandwidth of up to 4.2 GB/s.

Intel will enable support components for the Celeron D processor including heatsink, heatsink

retention mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly

may be completed from the top of the baseboard and should not require any special tooling.

The processor includes an address bus powerdown capability that removes power from the address

and data pins when the FSB is not in use. This feature is always enabled on the processor.

1.1

Terminology

A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active

state when driven to a low level. For example, when RESET# is low, a reset has been requested.

Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where

the name does not imply an active state but describes part of a binary sequence (such as address or

data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a

hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).

“Front Side Bus (FSB)” refers to the interface between the processor and system core logic (a.k.a.

the chipset components). The FSB is a multiprocessing interface to processors, memory, and I/O.

Datasheet

11

Introduction

1.1.1

Processor Packaging Terminology

Commonly used terms are explained here for clarification:

• Intel^®Celeron^®D processor on 90 nm process and in the 478-pin package — Celeron D

processor in the FC-mPGA4 package with a 256-KB L2 cache.

• Processor — For this document, the term processor is the generic form of the Celeron D

processor.

• Keep-out zone — The area on or near the processor that system design can not use.

• Intel^£865G/865GV/865PE/865P chipset — Chipset that supports DDR memory technology

for the Celeron D processor.

• Intel^®845G chipset — Chipset with embedded graphics that supports DDR memory

technology. Changes are required to support the Celeron D processor on 90 nm micron

process.

• Intel^®852 GME/PM/GMV chipsets — Intel’s Portability chipsets that support DDR

memory technology for the Celeron D processor

• Processor core — Processor core die with integrated L2 cache.

• FC-mPGA4 package — The Celeron D processor is available in a Flip-Chip Micro Pin Grid

Array 4 package, consisting of a processor core mounted on a pinned substrate with an

integrated heat spreader (IHS). This packaging technology employs a 1.27 mm [0.05 in] pitch

for the substrate pins.

• mPGA478B socket — The Celeron D processor mates with the system board through a

surface mount, 478-pin, zero insertion force (ZIF) socket.

• Integrated heat spreader (IHS) —A component of the processor package used to enhance

the thermal performance of the package. Component thermal solutions interface with the

processor at the IHS surface.

• Retention mechanism (RM)—Since the mPGA478B socket does not include any mechanical

features for heatsink attach, a retention mechanism is required. Component thermal solutions

should attach to the processor via a retention mechanism that is independent of the socket.

12

Datasheet

Introduction

1.2

References

Material and concepts available in the following documents may be beneficial when reading this

document:

Table 1-1. References

Document Number/

Location

Document

http://developer.intel.com/

design/chipsets/designex/

252518.htm

®

Intel 865G/865GV/865PE/865P Chipset Platform Design Guide

http://developer.intel.com/

design/chipsets/designex/

298654.htm

®

Intel Pentium 4 Processor in 478-pin Package and

®

Intel 845G/845GL Chipset Platform Design Guide

http://developer.intel.com/

design/chipsets/designex/

298654.htm

®

Intel Pentium 4 Processor in 478-pin Package and Intel 845G/845GL/

845GV Chipset Platform Design Guide

http://developer.intel.com/

design/Pentium4/guides/

300564.htm

®

Intel Pentium 4 Processor on 90 nm Process Thermal Design Guidelines

Voltage Regulator-Down (VRD) 10.0: for Desktop Socket 478 Design Guide

VRM 9.0 DC-DC Converter Design Guidelines

http://developer.intel.com/

design/Pentium4/guides/

252885.htm

http://developer.intel.com/

design/Pentium4/guides/

249205.htm

http://developer.intel.com/

design/Pentium4/guides/

249891.htm

®

Intel Pentium 4 Processor VR-Down Design Guidelines

®

Intel Architecture Software Developer's Manual

®

IA-32 Intel Architecture Software Developer's Manual Volume 1: Basic

Architecture

®

IA-32 Intel Architecture Software Developer's Manual Volume 2A:

http://developer.intel.com/

design/pentium4/manuals/

index_new.htm

Instruction Set Reference Manual A–M

®

IA-32 Intel Architecture Software Developer's Manual Volume 2B:

Instruction Set Reference Manual, N–Z

®

IA-32 Intel Architecture Software Developer's Manual Volume 3: System

Programming Guide

http://developer.intel.com/

design/pentium4/manuals/

index_new.htm

®

IA-32 Intel Architecture and Intel Extended Memory 64 Software Developer's

Manual Documentation Changes

http://www.intel.com/

design/Xeon/guides/

249679.htm

ITP700 Debug Port Design Guide

§

Datasheet

13

Introduction

14

Datasheet

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1

FSB and GTLREF

Most Celeron D processor FSB signals use Gunning Transceiver Logic (GTL+) signaling

technology. The termination voltage level for the Celeron D processor GTL+ signals is V_CC, which

is the operating voltage of the processor core. Because of the speed improvements to data and

address bus, signal integrity and platform design methods have become more critical than with

previous processor families.

The GTL+ inputs require a reference voltage (GTLREF) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF must be generated on the system board

(see Table 2-18 for GTLREF specifications). Termination resistors are provided on the processor

silicon and are terminated to its core voltage (V_CC). Intel chipsets will also provide on-die

termination, thus eliminating the need to terminate the bus on the system board for most GTL+

signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

See Table 2-4 for details regarding these signals.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+

signals are based on flight time instead of capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2

2.3

Power and Ground Pins

For clean on-chip power distribution, the Celeron D processor has 85 VCC (power) and 179 VSS

(ground) pins. All power pins must be connected to V_CC, while all VSS pins must be connected to

a system ground plane.The processor VCC pins must be supplied by the voltage determined by the

VID (Voltage identification) pins.

Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-8. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and design guidelines, refer to the applicable VRD

design guide.

Datasheet

15

Electrical Specifications

2.3.1

V

Decoupling

CC

Regulator solutions need to provide bulk capacitance with a low Effective Series Resistance (ESR)

and keep a low interconnect resistance from the regulator to the socket. Bulk decoupling for the

large current swings when the part is powering on, or entering/exiting low power states, must be

provided by the voltage regulator solution (VR). For more details on this topic, refer to the

applicable VRD design guide.

2.3.2

2.3.3

FSB GTL+ Decoupling

The Celeron D processor integrates signal termination on the die as well as incorporating high

frequency decoupling capacitance on the processor package. Decoupling must also be provided by

the system baseboard for proper GTL+ bus operation.

FSB Clock (BCLK[1:0]) and Processor Clocking

BCLK[1:0] directly controls the FSB interface speed as well as the core frequency of the processor.

As in previous generation processors, the Celeron D processor core frequency is a multiple of the

BCLK[1:0] frequency. The processor bus ratio multiplier will be set at its default ratio during

manufacturing.

The Celeron D processor uses a differential clocking implementation. For more information on the

Celeron D processor clocking, refer to the CK409 Clock Synthesizer/Driver Specification or

CK408 Clock Synthesizer/Driver Specifications.

Table 2-1. Core Frequency to FSB Multiplier Configuration

Core Frequency

(133 MHz BCLK/

533 MHz FSB)

Multiplication of System Core

Frequency to FSB Frequency

Processor

Number

1

Notes

1/24

350

345

340

335

330

325

320

3.20 GHz

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

2.53 GHz

2.40 GHz

—

1/23

1/22

1/21

1/20

1/19

1/18

NOTES:

1.

Individual processors operate only at or below the rated frequency.

16

Datasheet

Electrical Specifications

2.4

Voltage Identification

The VID specification for the Celeron D processor is supported by the applicable VRD design

guide. The voltage set by the VID pins is the maximum voltage allowed by the processor. A

minimum voltage is provided in Table 2-8 and changes with frequency. This allows processors

running at a higher frequency to have a relaxed minimum voltage specification. The specifications

have been set such that one voltage regulator can work with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two devices at

the same speed may have different VID settings.

The Celeron D processor uses six voltage identification pins, VID[5:0], to support automatic

selection of power supply voltages. Table 2-2 specifies the voltage level corresponding to the state

of VID[5:0]. A ‘1’ in this table refers to a high voltage level and a ‘0’ refers to low voltage level. If

the processor socket is empty (VID[5:0] = x11111), or the voltage regulation circuit cannot supply

the voltage that is requested, it must disable itself. See the applicable VRD design guide for more

details.

Power source characteristics must be guaranteed to be stable whenever the supply to the voltage

regulator is stable.

The Celeron D processor’s Voltage Identification circuit requires an independent 1.2 V supply and

some other power sequencing considerations.

Table 2-2. Voltage Identification Definition

VID5

VID4

VID3

VID2

VID1

VID0

VID

VID5

VID4

VID3

VID2

VID1

VID0

VID

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

0.850

0.875

0.900

0.925

0.950

0.975

1.000

1.025

1.050

1.075

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1.225

1.250

1.275

1.300

1.325

1.350

1.375

1.400

1.425

1.450

VRoutput

off

1

0

1

1.475

1

0

1

0

1

0

1

0

1

0

1.100

1.125

1.150

1.175

1.200

1

0

1

0

1

0

1

0

1

0

1

0

1.500

1.525

1.550

1.575

1.600

Datasheet

17

Electrical Specifications

2.4.1

Phase Lock Loop (PLL) Power and Filter

V_CCAand V_CCIOPLLare power sources required by the PLL clock generators on the Celeron D

processor silicon. Since these PLLs are analog, they require low noise power supplies for minimum

jitter. Jitter is detrimental to the system: it degrades external I/O timings as well as internal core

timings (i.e., maximum frequency). To prevent this degradation, these supplies must be low pass

filtered from V_CC

.

The AC low-pass requirements, with input at V_CCare as follows:

• < 0.2 dB gain in pass band

• < 0.5 dB attenuation in pass band < 1 Hz

• > 34 dB attenuation from 1 MHz to 66 MHz

• > 28 dB attenuation from 66 MHz to core frequency

The filter requirements are illustrated in Figure 2-1.

.

Figure 2-1. Phase Lock Loop (PLL) Filter Requirements

0.2 dB

0 dB

–0.5 dB

Forbidden

Zone

Forbidden

Zone

–28 dB

–34 dB

DC

1 Hz

Passband

fpeak

1 MHz

66 MHz

fcore

High

Frequency

Band

NOTES:

1. Diagram not to scale.

2. No specification exists for frequencies beyond fcore (core frequency).

3. fpeak, if existent, should be less than 0.05 MHz.

18

Datasheet

Electrical Specifications

2.5

Reserved, Unused, and TESTHI Pins

All RESERVED pins must remain unconnected. Connection of these pins to V_CC, V_SS, or to any

other signal (including each other) can result in component malfunction or incompatibility with

future processors. See Chapter 4 for a pin listing of the processor and the location of all

RESERVED pins.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system-level design, on-die termination has been included on the Celeron D

processor to allow signals to be terminated within the processor silicon. Most unused GTL+ inputs

should be left as no connects, as GTL+ termination is provided on the processor silicon. However,

see Table 2-4 for details on GTL+ signals that do not include on-die termination. Unused active

high inputs should be connected through a resistor to ground (V_SS). Unused outputs can be left

unconnected; however, this may interfere with some test access port (TAP) functions, complicate

debug probing, and prevent boundary scan testing. A resistor must be used when tying

bidirectional signals to power or ground. When tying any signal to power or ground, a resistor will

also allow for system testability. For unused GTL+ input or I/O signals, use pull-up resistors of the

same value as the on-die termination resistors (R_TT). See Table 2-18.

TAP, Asynchronous GTL+ inputs, and Asynchronous GTL+ outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left unconnected. Note that leaving unused outputs

unterminated may interfere with some TAP functions, complicate debug probing, and prevent

boundary scan testing.

The TESTHI pins must be tied to the processor V_CCusing a matched resistor, where a matched

resistor has a resistance value within ±20% of the impedance of the board transmission line traces.

For example, if the trace impedance is 60 Ω, then a value between 48 Ω and 72 Ω is required.

The TESTHI pins may use individual pull-up resistors or be grouped together as detailed below. A

matched resistor must be used for each group:

• TESTHI[1:0]

• TESTHI[7:2]

• TESTHI8 – cannot be grouped with other TESTHI signals

• TESTHI9 – cannot be grouped with other TESTHI signals

• TESTHI10 – cannot be grouped with other TESTHI signals

• TESTHI11 – cannot be grouped with other TESTHI signals

• TESTHI12 – cannot be grouped with other TESTHI signals

Datasheet

19

Electrical Specifications

2.6

FSB Signal Groups

The FSB signals have been combined into groups by buffer type. GTL+ input signals have

differential input buffers that use GTLREF as a reference level. In this document, the term "GTL+

Input" refers to the GTL+ input group as well as the GTL+ I/O group when receiving. Similarly,

"GTL+ Output" refers to the GTL+ output group as well as the GTL+ I/O group when driving.

With the implementation of a source synchronous data bus comes the need to specify two sets of

timing parameters. One set is for common clock signals that are dependent upon the rising edge of

BCLK0 (ADS#, HIT#, HITM#, etc.) and the second set is for the source synchronous signals that

are relative to their respective strobe lines (data and address) as well as the rising edge of BCLK0.

Asychronous signals are still present (A20M#, IGNNE#, etc.) and can become active at any time

during the clock cycle. Table 2-3 identifies which signals are common clock, source synchronous,

and asynchronous.

Table 2-3. FSB Pin Groups

1

Signal Group

Type

Signals

GTL+ Common Clock

Input

Synchronous to

BCLK[1:0]

BPRI#, DEFER#, RS[2:0]#, RSP#, TRDY#

GTL+ Common Clock

I/O

Synchronous to

BCLK[1:0]

AP[1:0]#, ADS#, BINIT#, BNR#, BPM[5:0]#, BR0#, DBSY#,

DP[3:0]#, DRDY#, HIT#, HITM#, LOCK#, MCERR#

Signals

Associated Strobe

ADSTB0#

2

REQ[4:0]#, A[16:3]#

2

A[35:17]#

ADSTB1#

GTL+ Source

Synchronous I/O

Synchronous to

Associated strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#, DSTBN0#

DSTBP1#, DSTBN1#

DSTBP2#, DSTBN2#

DSTBP3#, DSTBN3#

Synchronous to

BCLK[1:0]

GTL+ Strobes

ADSTB[1:0]#, DSTBP[3:0]#, DSTBN[3:0]#

Asynchronous GTL+

Input

A20M#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#,

SLP#, STPCLK#, RESET#

Asynchronous GTL+

Output

FERR#/PBE#, IERR#, THERMTRIP#

PROCHOT#

Asynchronous GTL+

Input/Output

TAP Input

TAP Output

FSB Clock

Synchronous to TCK TCK, TDI, TMS, TRST#

Synchronous to TCK TDO

3

Clock

BCLK[1:0], ITP_CLK[1:0]

VCC, VCCA, VCCIOPLL, VID[5:0], VSS, VSSA,

GTLREF[3:0], COMP[1:0], RESERVED, TESTHI[12:0],

THERMDA, THERMDC, VCC_SENSE, VSS_SENSE,

Power/Other

3

VCCVID, VCCVIDLB, BSEL[1:0], SKTOCC#, DBR# ,

,

VIDPWRGD, BOOTSELECT, OPTIMIZED/COMPAT#

PWRGOOD

NOTES:

1. Refer to Section 4.2 for signal descriptions.

2. The value of these pins during the active-to-inactive edge of RESET# defines the processor configuration

options. See Section 6.1 for details.

3. In processor systems where there is no debug port implemented on the system board, these signals are used

to support a debug port interposer. In systems with the debug port implemented on the system board, these

signals are no connects.

20

Datasheet

Electrical Specifications

Table 2-4. Signal Characteristics

Signals with R_TT

Signals with no R_TT

A20M#, BCLK[1:0], BPM[5:0]#, BR0#, BSEL[1:0],

COMP[1:0], FERR#/PBE#, IERR#, IGNNE#, INIT#,

LINT0/INTR, LINT1/NMI, PWRGOOD, RESET#,

SKTOCC#, SLP#, SMI#, STPCLK#, TDO,

TESTHI[12:0], THERMDA, THERMDC,

A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,

BNR#, BOOTSELECT , BPRI#, D[63:0]#, DBI[3:0]#,

1

DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,

DSTBP[3:0]#, HIT#, HITM#, LOCK#, MCERR#,

1

OPTIMIZED/COMPAT# , PROCHOT#, REQ[4:0]#,

THERMTRIP#, VID[5:0], VIDPWRGD,

GTLREF[3:0], TCK, TDI, TRST#, TMS

RS[2:0]#, RSP#, TRDY#

2

Open Drain Signals

BSEL[1:0], VID[5:0], THERMTRIP#, FERR#/PBE#,

IERR#, BPM[5:0]#, BR0#, TDO

NOTES:

1. The OPTIMIZED/COMPAT# and BOOTSELECT pins have a 500–5000 Ω pull-up to V

rather than R .

TT

CCVID

2. Signals that do not have R , nor are actively driven to their high-voltage level.

TT

Table 2-5. Signal Reference Voltages

GTLREF

V

/2

V

/2

CCVID

CC

BPM[5:0]#, LINT0/INTR, LINT1/NMI, RESET#, BINIT#,

BNR#, HIT#, HITM#, MCERR#, PROCHOT#, BR0#,

A[35:0]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BPRI#, D[63:0]#,

DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,

DSTBN[3:0]#, DSTBP[3:0]#, LOCK#, REQ[4:0]#, RS[2:0]#,

RSP#, TRDY#

A20M#, IGNNE#, INIT#,

VIDPWRGD,

1

PWRGOOD , SLP#, SMI#,

BOOTSELECT,

OPTIMIZED/

COMPAT#

1

STPCLK#, TCK , TDI ,

TMS , TRST#

1

NOTES:

1.

These signals also have hysteresis added to the reference voltage. See Table 2-12 for more information.

2.7

Asynchronous GTL+ Signals

Legacy input signals (such as A20M#, IGNNE#, INIT#, SMI#, SLP#, and STPCLK#) use CMOS

input buffers. All of these signals follow the same DC requirements as GTL+ signals; however, the

outputs are not actively driven high (during a logical 0-to-1 transition) by the processor. These

signals do not have setup or hold time specifications in relation to BCLK[1:0].

All of the Asynchronous GTL+ signals are required to be asserted/de-asserted for at least six

BCLKs for the processor to recognize the proper signal state. See Section 2.11 for the DC

specifications for the Asynchronous GTL+ signal groups. See Section 6.2 for additional timing

requirements for entering and leaving the low power states.

2.8

Test Access Port (TAP) Connection

Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is

recommended that the Celeron D processor be first in the TAP chain and followed by any other

components within the system. A translation buffer should be used to connect to the rest of the

chain unless one of the other components is capable of accepting an input of the appropriate

voltage level. Similar considerations must be made for TCK, TMS, TRST#, TDI, and TDO. Two

copies of each signal may be required, with each driving a different voltage level.

Datasheet

21

Electrical Specifications

2.9

FSB Frequency Select Signals (BSEL[1:0])

The BSEL[1:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).

Table 2-6 defines the possible combinations of the signals and the frequency associated with each

combination. The required frequency is determined by the processor, chipset, and clock

synthesizer. All agents must operate at the same frequency.

The Celeron D processor currently operates at a 533 MHz FSB frequency (selected by a 133 MHz

BCLK[1:0] frequency). Individual processors will only operate at their specified FSB frequency.

For more information about these pins, refer to Section 4.2.

Table 2-6. BSEL[1:0] Frequency Table for BCLK[1:0]

BSEL1

BSEL0

Function

L

H

133 MHz

2.10

Absolute Maximum and Minimum Ratings

Table 2-7 specifies absolute maximum and minimum ratings. Within functional operation limits,

functionality and long-term reliability can be expected.

At conditions outside functional operation condition limits, but within absolute maximum and

minimum ratings, neither functionality nor long-term reliability can be expected. If a device is

returned to conditions within functional operation limits after having been subjected to conditions

outside these limits, but within the absolute maximum and minimum ratings, the device may be

functional, but with its lifetime degraded depending on exposure to conditions exceeding the

functional operation condition limits.

At conditions exceeding absolute maximum and minimum ratings, neither functionality nor long-

term reliability can be expected. Moreover, if a device is subjected to these conditions for any

length of time then, when returned to conditions within the functional operating condition limits, it

will either not function, or its reliability will be severely degraded.

Although the processor contains protective circuitry to resist damage from static electric discharge,

precautions should always be taken to avoid high static voltages or electric fields.

Table 2-7. Processor DC Absolute Maximum Ratings

Symbol

Parameter

Min

Max

Unit

Notes

1

V

Core voltage with respect to V

- 0.3

1.55

V

CC

SS

1

FSB termination voltage with respect to V

Processor case temperature

TT

SS

See

Chapter 5

See

Chapter 5

2, 3

T

°C

C

Processor storage temperature

–40

+85

STORAGE

NOTES:

1. For functional operation, all processor electrical, signal quality, mechanical and thermal specifications must

be satisfied.

2. Storage temperature is applicable to storage conditions only. In this scenario, the processor must not receive

a clock, and no lands can be connected to a voltage bias. Storage within these limits will not affect the long-

term reliability of the device. For functional operation, refer to the processor case temperature specifications.

3. This rating applies to the processor and does not include any tray or packaging.

22

Datasheet

Electrical Specifications

2.11

Processor DC Specifications

The processor DC specifications in this section are defined at the processor core silicon and

not at the package pins unless noted otherwise. See Chapter 4 for the pin signal definitions and

signal pin assignments. Most of the signals on the processor FSB are in the GTL+ signal group. The

DC specifications for these signals are listed in Table 2-10.

Previously, legacy signals and Test Access Port (TAP) signals to the processor used low-voltage

CMOS buffer types. However, these interfaces now follow DC specifications similar to GTL+. The

DC specifications for these signal groups are listed in Table 2-11 and Table 2-12.

Table 2-8 through Table 2-15 list the DC specifications for the Celeron D processor and are valid

only while meeting specifications for case temperature, clock frequency, and input voltages. Care

should be taken to read all notes associated with each parameter.

Table 2-8. Voltage and Current Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

1

VID range

VID

1.250

—

1.400

V

See Table 2-9 and VID – I (max)

2,3,4

CC

V

CC

Figure 2-2

* 1.45 mΩ

Processor

Number

Core Frequency

for processor with

I

CC

multiple VID:

350

345

340

335

330

325

320

3.20 GHz

73

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

2.53 GHz

2.40 GHz

I

CC

5

—

A

I

Stop-Grant

3.20 GHz

3.06 GHz

2.93 GHz

2.80 GHz

2.66 GHz

2.53 GHz

2.40 GHz

CC

350

345

340

335

330

325

320

40

I

SGNT

6,7

—

A

SLP

8

9

I

TCC active

for PLL pins

—

I

CC

A

TCC

CC

60

mA

µA

CC_VCCA

CC_VCCIOPLL

CC_GTLREF

for I/O PLL pin

for GTLREF pins (all pins)

200

/

9

CC_VCCVID

I

for VCCVID/VCCVIDLB

—

150

mA

CC

VCCVIDLB

NOTES:

1. Individual processor VID values may be calibrated during manufacturing such that two devices at the same

speed may have different VID settings.

2.

These voltages are targets only. A variable voltage source should exist on systems in the event that a differ-

ent voltage is required. See Section 2.4 and Table 2-2 for more information.

Datasheet

23

Electrical Specifications

3. The voltage specification requirements are measured across VCC_SENSE and VSS_SENSE pins at the

socket with a 100 MHz bandwidth oscilloscope, 1.5 pF maximum probe capacitance, and 1 MΩ minimum im-

pedance. The maximum length of ground wire on the probe should be less than 5 mm. Ensure external noise

from the system is not coupled into the oscilloscope probe.

4.

Refer to Table 2-9 and Figure 2-2 for the minimum, typical, and maximum V allowed for a given current. The

CC

processor should not be subjected to any V and I combination wherein V exceeds V for a giv-

CC_MAX

CC

en current. Moreover, V should never exceed the VID voltage. Failure to adhere to this specification can

CC

shorten the processor lifetime.

5.

I

is specified at V

CC_MAX CC_MAX .

6. The current specified is also for AutoHALT state.

7. Stop-Grant and I Sleep are specified at V

8. The maximum instantaneous current the processor will draw while the thermal control circuit is active as in-

I

CC

CC_MAX .

dicated by the assertion of PROCHOT# is the same as the maximum I for the processor.

CC

9. These parameters are based on design characterization and are not tested.

Table 2-9. V_CCStatic and Transient Tolerance

1,2,3

Voltage Deviation from VID Setting (V)

Icc (A)

Maximum Voltage

Typical Voltage

Minimum Voltage

0

5

0.000

-0.007

-0.015

-0.022

-0.029

-0.036

-0.044

-0.051

-0.058

-0.065

-0.073

-0.080

-0.087

-0.094

-0.102

-0.106

-0.025

-0.034

-0.042

-0.051

-0.060

-0.068

-0.077

-0.085

-0.094

-0.103

-0.111

-0.120

-0.129

-0.137

-0.146

-0.151

-0.050

-0.060

-0.070

-0.080

-0.090

-0.100

-0.110

-0.120

-0.130

-0.140

-0.150

-0.160

-0.170

-0.180

-0.190

-0.196

10

15

20

25

30

35

40

45

50

55

60

65

70

73

NOTES:

1.

The loadline specification includes both static and transient limits except for overshoot allowed as

shown in Section 2.12.

2.

This table is intended to aid in reading discrete points on Figure 2-3.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE

pins. Voltage regulation feedback for voltage regulator circuits must be taken from processor VCC

and VSS pins. Refer to the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop

Socket 478 for socket loadline guidelines and VR implementation details.

24

Datasheet

Electrical Specifications

Figure 2-2. V_CCStatic and Transient Tolerance

Icc [A]

0

5

10

15

20

25

30

35

40

45

50

55

60

65

70

VID - 0.000

VID - 0.050

VID - 0.100

VID - 0.150

VID - 0.200

VID - 0.250

VID - 0.300

Vcc

Maximum

Vcc

Typical

Vcc

Minimum

NOTES:

1. The loadline specification includes both static and transient limits except for overshoot allowed as shown in

Section 2.12.

2. This loadline specification shows the deviation from the VID set point.

3. The loadlines specify voltage limits at the die measured at the VCC_SENSE and VSS_SENSE pins. Voltage

regulation feedback for voltage regulator circuits must be taken from processor VCC and VSS pins. Refer to

the Voltage Regulator-Down (VRD) 10.0 Design Guidelines for Desktop Socket 478 for socket loadline

guidelines and VR implementation details.

Datasheet

25

Electrical Specifications

Table 2-10. GTL+ Signal Group DC Specifications

1

Symbol

Parameter

Min

Max

Unit Notes

2,3

V

Input Low Voltage

Input High Voltage

Output High Voltage

0.0

GTLREF – (0.10 * V

)

CC

V

IL

3,4,5

V

GTLREF + (0.10 * V

)

V

IH

CC

3,5

V

0.90*V

N/A

V

OH

CC

V

/

CC

I

Output Low Current

A

OL

[0.50*RR

+R

]

ON_MIN

TT_MIN

6

I

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

6.33

8

± 200

10.33

12

µA

LI

7

I

µA

LO

8

R

Ω

on_compatible

8

R

Ω

on_optimized

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. The V referred to in these specifications is the instantaneous V

V

IL

.

CC

4.

5.

V

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

IH

and V may experience excursions above V

.

CC

IH

OH

6. Leakage to V with pin held at V

.

SS

CC

7. Leakage to V with pin held at 300 mV.

CC

8. These specifications are different depending on whether the platform is forward compatible to the Celeron D proces-

sor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous gen-

eration processor but has some level of compatibility with the Celeron D processor. An optimized platform is one

designed specifically for the Celeron D processor; however, it may have some level of compatibility with previous

generation processors.

Table 2-11. Asynchronous GTL+ Signal Group DC Specifications

1

Symbol

Parameter

Min

Max

Unit

Notes

2,3

V

Input Low Voltage

0.0

V

/2 – (0.10 * V )

CC

V

IL

CC

3,4,5,6

5,6,7

8

V

Input High Voltage

V

/2 + (0.10 * V

)

V

IH

CC

V

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

Buffer On Resistance

0.90*V

—

V

OH

OL

CC

I

V

/[0.50*R

+R ]

ON_MIN

A

CC

TT_MIN

9

I

N/A

6.33

8

± 200

10.33

12

µA

W

IL

10

I

LO

11

R

on_compatible

11

R

on_optimized

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.

3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals

V

IL

V

= GTLREF + (0.10 * V ) and V = GTLREF – (0.10 * V ).

IH

CC IL CC

4.

5.

is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.

and V may experience excursions above V

.

CC

OH

6. The V referred to in these specifications refers to instantaneous V

.

CC

7. All outputs are open drain.

8. The maximum output current is based on maximum current handling capability of the buffer and is not specified into

the test load.

9. Leakage to V with pin held at V

.

SS

CC

10. Leakage to V with pin held at 300 mV.

CC

26

Datasheet

Electrical Specifications

11. These specifications are different depending on whether the platform is forward compatible to the Celeron D pro-

cessor or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous

generation processor but has some level of compatibility with the Celeron D processor. An optimized platform is one

designed specifically for the Celeron D processor; however, it may have some level of compatibility with previous

generation processors.

.

Table 2-12. PWRGOOD and TAP Signal Group DC Specifications

1,2

Symbol

Parameter

Input Hysteresis

Min

Max

Unit Notes

3

V

200

350

mV

HYS

Input low to high threshold

voltage

4

V

0.5 * (V + V

)

0.5 * (V + V )

HYS_MAX

V

T+

CC

HYS_MIN

CC

Input high to low threshold

voltage

4

V

0.5 * (V – V

)

0.5 * (V – V )

HYS_MIN

V

T-

CC

HYS_MAX

CC

4

V

Output High Voltage

Output Low Current

Input Leakage Current

Output Leakage Current

Buffer On Resistance

N/A

—

7

V

OH

CC

5

I

45

mA

OL

6

I

± 200

12

µA

LI

7

I

µA

LO

8

Ron

Ω

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. All outputs are open drain.

3.

V

represents the amount of hysteresis, nominally centered about 0.5 * V for all TAP inputs.

HYS CC

4. The V referred to in these specifications refers to instantaneous V

.

CC

5. The maximum output current is based on maximum current handling capability of the buffer and is not specified into

the test load.

6. Leakage to V with pin held at V

.

SS

CC

7. Leakage to V with Pin held at 300 mV.

CC

8. These values work for compatible and optimized platforms. A compatible platform is one that is designed for a pre-

vious generation processor but has some level of compatibility with the Celeron D processor. An optimized platform

is one designed specifically for the Celeron D processor; however, it may have some level of compatibility with pre-

vious generation processors.

Table 2-13. VCCVID DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

VCCVID

Voltage

1.14

1.2

1.26

V

VCCVIDLB Voltage

Table 2-14. VIDPWRGD DC Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V

Input Low Voltage

Input High Voltage

—

0.3

—

V

IL

V

0.9

IH

Datasheet

27

Electrical Specifications

Table 2-15. BSEL [1:0] and VID[5:0] DC Specifications

1

Symbol

(BSEL) Buffer On Resistance

Parameter

Max

Unit

Notes

2

R

60

Ω

on

2

3

R

(VID)

Buffer On Resistance

Max Pin Current

on

I

8

mA

µA

V

OL

I

Output Leakage Current

Voltage Tolerance

200

LO

V

3.3 + 5%

TOL

NOTES:

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. These parameters are not tested and are based on design simulations.

3. Leakage to V with pin held at 2.5 V.

SS

Table 2-16. BOOTSELECT DC Specifications

1

Symbol

Parameter

Min

Typ

Max

Unit

Notes

V

Input Low Voltage

Input High Voltage

—

0.2 * VCCVID

—

V

IL

V

0.8 * VCCVID

IH

NOTES:

1. These parameters are not tested and are based on design simulations.

2.12

V_CCOvershoot Specification

The Celeron D processor can tolerate short transient overshoot events where V_CCexceeds the VID

voltage when transitioning from a high to low current load condition. This overshoot cannot exceed

VID + V_{OS_MAX}(V_{OS_MAX}is the maximum allowable overshoot voltage). The time duration of

the overshoot event must not exceed T_{OS_MAX}(T_{OS_MAX}is the maximum allowable time duration

above VID). These specifications apply to the processor die voltage as measured across the

VCC_SENSE and VSS_SENSE pins.

Table 2-17. V_CCOvershoot Specifications

Symbol

Parameter

Min

Typ

Max

Unit

Figure

Notes

Magnitude of V overshoot

above VID

CC

V

—

0.050

V

2-3

OS_MAX

Time duration of V

overshoot above VID

CC

T

—

25

µs

2-3

OS_MAX

28

Datasheet

Electrical Specifications

Figure 2-3. V_CCOvershoot Example Waveform

Example Overshoot Waveform

VID + 0.050

VID

V_OS

T_OS

Time

T_OS: Overshoot time above VID

V_OS: Overshoot above VID

NOTES:

1. V is measured overshoot voltage.

OS

2. T is measured time duration above VID.

OS

2.12.1

Die Voltage Validation

Overshoot events from application testing on real processors must meet the specifications in

Table 2-17 when measured across the VCC_SENSE and VSS_SENSE pins. Overshoot events that

are < 10 ns in duration may be ignored. These measurements of processor die level overshoot

should be taken with a 100 MHz bandwidth limited oscilloscope.

Datasheet

29

Electrical Specifications

2.13

GTL+ FSB Specifications

Termination resistors are not required for most GTL+ signals; they are integrated into the processor

silicon.

Valid high and low levels are determined by the input buffers that compare a signal’s voltage with a

reference voltage called GTLREF. Table 2-18 lists the GTLREF specifications. The GTL+

reference voltage (GTLREF) should be generated on the system board using high precision voltage

divider circuits.

Table 2-18. GTL+ Bus Voltage Definitions

1

Symbol

Parameter

Min

Typ

2/3 V

Max

Units Notes

2,3,4,5

GTLREF

Bus Reference Voltage

0.98 * (2/3 V

)

1.02 * (2/3 V

CC

)

V

_compatible

CC

2,3,4,5

5,6

GTLREF

Bus Reference Voltage (0.98 * 0.63) * V

0.63 * V

(1.02 * 0.63) * V

V

_optimized

CC

On die pull-up for

BOOTSELECT and

500

R

—

5000

Ω

_pullup

OPTIMIZED/

COMPAT# pins

Termination

45

5,7

5

R_{TT_compatible}

R_{TT_optimized}

50

60

55

66

Ω

Resistance

Termination

54

Resistance

5,8

COMP[1:0]

NOTES:

COMP Resistance

49.4

61.3

49.9

61.9

50.4

62.5

Ω

_compatible

_optimized

1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2. The tolerances for this specification have been stated generically to enable the system designer to calculate the mini-

mum and maximum values across the range of V

.

CC

3. GTLREF should be generated from V by a voltage divider of 1% resistors or 1% matched resistors.

CC

4. The V referred to in these specifications is the instantaneous V

.

CC

5. These specifications are different depending on whether the platform is forward compatible to the Celeron D processor

or if it is optimized for the Celeron D processor. A compatible platform is one that is designed for a previous generation

processor but has some level of compatibility with the Celeron D processor. An optimized platform is one designed spe-

cifically for the Celeron D processor; however, it may have some level of compatibility with previous generation proces-

sors.

6. These pull-ups are to the internal V

supply.

CCVID

7.

R

is the on-die termination resistance measured at V /2 of the GTL+ output driver.

TT CC

8. COMP resistance must be provided on the system board with 1% resistors.

§

30

Datasheet

Package Mechanical Specifications

3 Package Mechanical

Specifications

The Celeron D processor is packaged in a Flip-Chip Pin Grid Array (FC-mPGA4) package that

interfaces with the motherboard via a mPGA478B socket. The package consists of a processor core

mounted on a substrate pin-carrier. An integrated heat spreader (IHS) is attached to the package

substrate and core and serves as the mating surface for processor component thermal solutions

(such as a heatsink). Figure 3-1 shows a sketch of the processor package components and how they

are assembled together. Refer to the mPGA479, mPGA478A, mPGA478B, mPGA478C, and

mPGA476 Socket Design Guidelines for complete details on the mPGA478B socket.

The package components shown in Figure 3-1 include the following:

• Integrated Heat Spreader (IHS)

• Thermal Interface Material (TIM)

• Processor core (die)

• Package substrate

• Capacitors

Figure 3-1. Processor Package Assembly Sketch

CORE (DIE)

IHS

TIM

SUBSTRATE

CAPACITORS

SOCKET

MOTHERBOARD

NOTE:

1. Socket and motherboard are included for reference and are not part of processor package.

3.1

Package Mechanical Drawing

The package mechanical drawings are shown in Figure 3-2 and Figure 3-3. The drawings include

dimensions necessary to design a thermal solution for the processor. These dimensions include:

• Package reference with tolerances (total height, length, width, etc.)

• IHS parallelism and tilt

• Pin dimensions

• Top-side and back-side component keep-out dimensions

• Reference datums

All drawing dimensions are in mm [in].

Datasheet

31

Package Mechanical Specifications

Figure 3-2. Processor Package Drawing (Sheet 1 of 2)

32

Datasheet

Package Mechanical Specifications

Figure 3-3. Processor Package Drawing (Sheet 2 of 2)

Datasheet

33

Package Mechanical Specifications

3.2

Processor Component Keep-Out Zones

The processor may contain components on the substrate that define component keep-out zone

requirements. A thermal and mechanical solution design must not intrude into the required keep-

out zones. Decoupling capacitors are typically mounted to either the topside or pin-side of the

package substrate. See Figure 3-2 and Figure 3-3 for keep-out zones.

The location and quantity of package capacitors may change due to manufacturing efficiencies but

will remain within the component keep-in.

3.3

Package Loading Specifications

Table 3-1 provides dynamic and static load specifications for the processor package. These

mechanical maximum load limits should not be exceeded during heatsink assembly, shipping

conditions, or standard use condition. Also, any mechanical system or component testing should

not exceed the maximum limits. The processor package substrate should not be used as a

mechanical reference or load-bearing surface for thermal and mechanical solution. The minimum

loading specification must be maintained by any thermal and mechanical solutions.

.

Table 3-1. Processor Loading Specifications

Parameter

Minimum

Maximum

Notes

1,2,3

Static

44 N [10 lbf]

445 N [100 lbf]

890 N [200 lbf]

667 N [150 lbf]

1,3,4

1,3,5

Dynamic

Transient

—

NOTES:

1. These specifications apply to uniform compressive loading in a direction normal to the processor IHS.

2. This is the maximum force that can be applied by a heatsink retention clip. The clip must also provide the

minimum specified load on the processor package.

3. These specifications are based on limited testing for design characterization. Loading limits are for the

package only and does not include the limits of the processor socket.

4. Dynamic loading is defined as an 11 ms duration average load superimposed on the static load require-

ment.

5. Transient loading is defined as a 2 second duration peak load superimposed on the static load requirement,

representative of loads experienced by the package during heatsink installation.

34

Datasheet

Package Mechanical Specifications

3.4

Package Handling Guidelines

Table 3-2 includes a list of guidelines on package handling in terms of recommended maximum

loading on the processor IHS relative to a fixed substrate. These package handling loads may be

experienced during heatsink removal.

Table 3-2. Package Handling Guidelines

Parameter

Maximum Recommended

Notes

1 2

Shear

Tensile

356 N [80 lbf]

156 N [35 lbf]

8 N-m [70 lbf-in]

,

2,3

2,4

Torque

NOTES:

1. A shear load is defined as a load applied to the IHS in a direction parallel to the IHS top surface.

2. These guidelines are based on limited testing for design characterization.

3. A tensile load is defined as a pulling load applied to the IHS in a direction normal to the IHS surface.

4. A torque load is defined as a twisting load applied to the IHS in an axis of rotation normal to the IHS top sur-

face.

3.5

Package Insertion Specifications

The Celeron D processor can be inserted into and removed from a mPGA478B socket 15 times.

The socket should meet the mPGA478B requirements detailed in the mPGA479, mPGA478A,

mPGA478B, mPGA478C, and mPGA476 Socket Design Guidelines.

3.6

3.7

Processor Mass Specification

The typical mass of the Celeron D processor is 19 g [0.67 oz]. This mass [weight] includes all the

components that are included in the package.

Processor Materials

Table 3-3 lists some of the package components and associated materials.

Table 3-3. Processor Materials

Component

Material

Integrated Heat Spreader (IHS)

Substrate

Nickel Plated Copper

Fiber Reinforced Resin

Gold Plated Copper

Substrate Pins

Datasheet

35

Package Mechanical Specifications

3.8

Processor Markings

Figure 3-5 and Figure 3-5 show the topside markings on the processor. These diagrams are to aid in

the identification of the Celeron D processor.

Figure 3-4. Processor Top-Side Marking Example (with Processor Number)

m

I

‘04

©

Celeron® D

Processor

Number

345 SL7NX XXXXX

3.06GHz/256/533

FFFFFFFF-NNNN

2D Matrix

Figure 3-5. Processor Top-Side Marking Example

GROUP1 LINE1

GROUP1 LINE2

GROUP1 LINE3

GROUP1 LINE4

GROUP1 LINE5

Grp1line1: INTEL m © ‘03

Grp1line2: CELERON® D

Grp1line3: 2.53GHZ/256/533

Grp1line4: SLxxx PHILLIPINES

Grp1line5: 7407A234

ATPO #

SERIAL #

ATPO #

SER #

2D Matrix

36

Datasheet

Package Mechanical Specifications

3.9

Processor Pinout Coordinates

Figure 3-6 shows the top view of the processor pin coordinates. The coordinates are referred to

throughout the document to identify processor pins

.

Figure 3-6. Processor Pinout Coordinates (Top View)

Clocks

Async/TAP

VCC/VSS

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

AF

AE

AD

AC

AB

AA

Y

AF

AE

AD

AC

AB

AA

Y

W

V

W

V

U

T

R

Address

Data

Processor

Top View

P

N

M

L

M

L

K

J

H

G

F

G

F

E

D

C

B

A

26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

VCC/VSS

Common

Clock

= VCC

= VSS

= GTLREF

= Signal/Other

§

Datasheet

37

Package Mechanical Specifications

38

Datasheet

Pin Listing and Signal Descriptions

4 Pin Listing and Signal

Descriptions

This chapter provides the Celeron D processor pinout and signal description.

4.1

Processor Pin Assignments

The pinout footprint is shown in Figure 4-1 and Figure 4-2. These figures represent the pinout

arranged by pin number. Table 4-1 provides the pinout arranged alphabetically by signal name and

Table 4-2 provides the pinout arranged numerically by pin number.

Datasheet

39

Pin Listing and Signal Descriptions

Figure 4-1. Pinout Diagram (Top View—Left Side)

26

25

24

23

22

21

20

19

18

17

16

15

14

AF

AE

SKTOCC# Reserved Reserved

OPTIMIZED/

BCLK1

BCLK0

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

AF

AE

DBR#

VSS

VCCA

VSS

Reserved

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

COMPAT#

AD

AC

ITP_CLK1 TESTHI12 TESTHI0

VSSA

VSS

VCCIOPLL

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AD

AC

ITP_CLK0

SLP#

VSS

TESTHI4 TESTHI5

TESTHI2 TESTHI3

PWR

VSS

AB

RESET#

TESTHI7

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

AB

GOOD

AA

Y

VSS

D56#

D55#

VSS

D61#

VSS

D63#

D59#

VSS

D62#

VSS

GTLREF TESTHI6

AA

Y

D58#

D60#

VSS

W

V

D57#

D51#

VSS

DSTBP3# DSTBN3#

W

V

D54#

D49#

VSS

D50#

D47#

VSS

D53#

VSS

DBI3#

D52#

U

T

D48#

D44#

VSS

U

T

D45#

D42#

VSS

D46#

DSTBN2#

VSS

R

P

D43#

D41#

VSS

D40#

R

P

DBI2#

D38#

D37#

VSS

DSTBP2#

D36#

D32#

VSS

D34#

N

M

L

D39#

VSS

D33#

VSS

N

M

L

D35#

COMP0

VSS

D27#

DP3#

DP1#

VSS

D28#

DSTBN1#

VSS

D24#

K

J

DP2#

DP0#

VSS

D30#

DSTBP1#

VSS

K

J

D29#

D26#

VSS

D14#

H

G

F

D31#

DBI1#

VSS

D16#

D10#

VSS

D11#

H

G

F

D25#

D22#

VSS

D18#

D19#

VSS

D20#

D17#

VSS

DSTBP0# GTLREF

VCC

VSS

VCC

VSS

VCC

VSS

19

VSS

VCC

VSS

VCC

VSS

VCC

18

VCC

VSS

VCC

VSS

VCC

VSS

17

VSS

VCC

VSS

VCC

VSS

VCC

16

VCC

VSS

VCC

VSS

VCC

VSS

15

VSS

VCC

VSS

VCC

VSS

VCC

14

E

D21#

D15#

VSS

DSTBN0#

D5#

DBI0#

VSS

D4#

D0#

VSS

21

VCC

VSS

VCC

VSS

VCC

20

E

D

C

B

A

D23#

D12#

VSS

D13#

D7#

D

C

B

A

D8#

VSS

D9#

D6#

VSS

D1#

VSS

D3#

VSS

D2#

Reserved

22

26

25

24

23

40

Datasheet

Pin Listing and Signal Descriptions

Figure 4-2. Pinout Diagram (Top View—Right Side)

13

12

11

10

9

8

7

6

5

4

3

2

1

AF

AE

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VID0

VCCVID

VID1

VCCVIDLB

VID2

VCC

VID3

VSS

VID4

AF

AE

BOOT

SELECT

AD

VCC

VSS

VCC

VSS

VCC

VSS

VCC

BSEL0

BSEL1

VSS

VID5

VIDPWRGD

AD

AC

AB

AA

Y

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

BPM0#

VSS

BPM1#

BPM4#

VSS

BPM2#

BPM5#

VSS

IERR#

VSS

RSP#

TESTHI1

VSS

AP0#

A35#

VSS

AC

AB

AA

Y

GTLREF

BPM3#

VSS

BINIT#

TESTHI10

VSS

STPCLK#

TESTHI9

VSS

A34#

A29#

VSS

W

V

INIT#

AP1#

VSS

A33#

A27#

VSS

W

V

MCERR#

TESTHI8

VSS

A32#

U

A31#

A25#

A23#

A17#

VSS

U

T

A30#

A26#

VSS

A22#

A18#

VSS

T

R

A28#

ADSTB1#

VSS

A21#

R

P

A24#

A20#

A19#

COMP1

A12#

A13#

VSS

P

N

VSS

A16#

A15#

VSS

A14#

VSS

N

M

L

A8#

VSS

A11#

A10#

M

L

A5#

ADSTB0#

REQ1#

VSS

A7#

A9#

K

VSS

A4#

VSS

A3#

A6#

K

J

TRDY#

BR0#

VSS

REQ2#

VSS

REQ3#

REQ4#

VSS

REQ0#

VSS

J

H

DBSY#

RS1#

VSS

DRDY#

BNR#

VSS

H

G

F

LOCK#

RS2#

VSS

ADS#

RS0#

VSS

G

F

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

TMS

VSS

VCC

VSS

GTLREF

TRST#

VSS

HIT#

E

LINT1

TDO

HITM#

VSS

DEFER#

BPRI#

VSS

E

D

TCK

LINT0

TDI

D

C

A20M#

VSS

THERMDC

PROCHOT#

C

FERR#/

PBE#

B

A

VCC

VSS

VCC

VSS

VCC

VSS

VCC

SMI#

VSS

THERMDA

IGNNE#

B

A

VSS

VCC

VSS

VCC

VSS

VCC

Reserved TESTHI11 VCC_SENSE VSS_SENSE

VSS

THERMTRIP#

13

12

11

10

9

8

7

6

5

4

3

2

1

Datasheet

41

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin Name

A3#

Pin #

K2

Direction

Pin Name

Pin #

Direction

Type

Source Synch

Asynch GTL+

Input/Output

Input

BINIT#

BNR#

AA3

G2

Common Clock Input/Output

A4#

K4

L6

A5#

BOOTSELECT AD1

Power/Other

Input

A6#

K1

BPM0#

BPM1#

BPM2#

BPM3#

BPM4#

BPM5#

BPRI#

BR0#

BSEL0

BSEL1

COMP0

COMP1

D0#

AC6

AB5

AC4

Y6

Common Clock Input/Output

Common Clock Input

A7#

L3

A8#

M6

L2

A9#

A10#

A11#

A12#

A13#

A14#

A15#

A16#

A17#

A18#

A19#

A20#

A21#

A22#

A23#

A24#

A25#

A26#

A27#

A28#

A29#

A30#

A31#

A32#

A33#

A34#

A35#

A20M#

ADS#

ADSTB0#

ADSTB1#

AP0#

AP1#

BCLK0

BCLK1

M3

M4

N1

M1

N2

N4

N5

T1

AA5

AB4

D2

H6

Common Clock Input/Output

AD6

AD5

L24

P1

Power/Other

Source Synch

Output

Input

R2

P3

B21

B22

A23

A25

C21

D22

B24

C23

C24

B25

G22

H21

C26

D23

J21

D25

H22

E24

G23

F23

F24

E25

F26

D26

L21

G26

Input/Output

D1#

P4

D2#

R3

T2

D3#

D4#

U1

P6

D5#

D6#

U3

T4

D7#

D8#

V2

D9#

R6

W1

T5

D10#

D11#

D12#

D13#

D14#

D15#

D16#

D17#

D18#

D19#

D20#

D21#

D22#

D23#

D24#

D25#

U4

V3

W2

Y1

AB1

C6

G1

L5

Common Clock Input/Output

Source Synch

Input/Output

R5

AC1

V5

Common Clock Input/Output

AF22

AF23

Bus Clock

Input

42

Datasheet

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Pin Name

D26#

Pin #

Direction

Pin Name

DBI3#

Pin #

Direction

Type

H24

M21

L22

Source Synch

Input/Output

V21

AE25

H5

Source Synch

Power/Other

Input/Output

Output

D27#

D28#

D29#

D30#

D31#

D32#

D33#

D34#

D35#

D36#

D37#

D38#

D39#

D40#

D41#

D42#

D43#

D44#

D45#

D46#

D47#

D48#

D49#

D50#

D51#

D52#

D53#

D54#

D55#

D56#

D57#

D58#

D59#

D60#

D61#

D62#

D63#

DBI0#

DBI1#

DBI2#

DBR#

DBSY#

Common Clock Input/Output

Common Clock Input

J24

DEFER#

DP0#

E2

K23

H25

M23

N22

P21

M24

N23

M26

N26

N25

R21

P24

R25

R24

T26

T25

T22

T23

U26

U24

U23

V25

U21

V22

V24

W26

Y26

W25

Y23

Y24

Y21

AA25

AA22

AA24

E21

G25

P26

J26

K25

K26

L25

H2

Common Clock Input/Output

DP1#

DP2#

DP3#

DRDY#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

FERR#/PBE#

GTLREF

HIT#

E22

K22

R22

W22

F21

J23

P23

W23

B6

Source Synch

Asynch AGL+

Power/Other

Input/Output

Output

AA21

AA6

F20

F6

Input

F3

Common Clock Input/Output

HITM#

E3

IERR#

AC3

B2

Asynch GTL+

TAP

Output

Input

IGNNE#

INIT#

W5

ITP_CLK0

ITP_CLK1

LINT0

AC26

AD26

D1

TAP

Asynch GTL+

LINT1

E5

LOCK#

G4

Common Clock Input/Output

MCERR#

V6

OPTIMIZED/

COMPAT#

AE26

Power/Other

Input

PROCHOT#

PWRGOOD

REQ0#

C3

AB23

J1

Asynch GTL+

Power/Other

Source Synch

Input/Output

Input

Input/Output

REQ1#

K5

J4

REQ2#

REQ3#

J3

REQ4#

H3

Datasheet

43

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin Name

Pin #

Direction

Pin Name

VCC

Pin #

Direction

Type

RESERVED

RESET#

RS0#

A22

A7

A20

Power/Other

VCC

A8

AE21

AF24

AF25

AB25

F1

AA10

AA12

AA14

AA16

AA18

AA8

Common Clock Input

RS1#

G5

RS2#

F4

AB11

AB13

AB15

AB17

AB19

AB7

RSP#

AB2

AF26

AB26

B5

SKTOCC#

SLP#

Power/Other

Asynch GTL+

TAP

Output

Input

Output

Input

SMI#

STPCLK#

TCK

Y4

D4

AB9

TDI

C1

TAP

AC10

AC12

AC14

AC16

AC18

AC8

TDO

D5

TAP

TESTHI0

TESTHI1

TESTHI2

TESTHI3

TESTHI4

TESTHI5

TESTHI6

TESTHI7

TESTHI8

TESTHI9

TESTHI10

TESTHI11

TESTHI12

THERMDA

THERMDC

AD24

AA2

AC21

AC20

AC24

AC23

AA20

AB22

U6

Power/Other

Asynch GTL+

TAP

AD11

AD13

AD15

AD17

AD19

AD7

W4

Y3

AD9

A6

AE10

AE12

AE14

AE16

AE18

AE20

AE6

AD25

B3

C4

THERMTRIP# A2

Output

Input

TMS

F7

TRDY#

TRST#

VCC

J6

Common Clock Input

E6

TAP

Input

AE8

A10

A12

A14

A16

A18

Power/Other

AF11

AF13

AF15

AF17

AF19

VCC

44

Datasheet

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Pin Name

VCC

Pin #

Direction

Pin Name

Pin #

Direction

Output

Type

AF2

AF21

AF5

AF7

AF9

B11

B13

B15

B17

B19

B7

Power/Other

VCC_SENSE

VCCVID

VCCVIDLB

VID0

VID1

VID2

VID3

VID4

VID5

VIDPWRGD

VSS

A5

Power/Other

VCC

VCCA

VCCIOPLL

AF4

AF3

AE5

AE4

AE3

AE2

AE1

AD3

AD2

A11

Input

Output

Input

B9

VSS

A13

C10

C12

C14

C16

C18

C20

C8

VSS

A15

VSS

A17

VSS

A19

VSS

A21

VSS

A24

VSS

A26

VSS

A3

D11

D13

D15

D17

D19

D7

VSS

A9

VSS

AA1

AA11

AA13

AA15

AA17

AA19

AA23

AA26

AA4

AA7

AA9

AB10

AB12

AB14

AB16

AB18

AB20

AB21

AB24

AB3

AB6

VSS

D9

VSS

E10

E12

E14

E16

E18

E20

E8

VSS

F11

F13

F15

F17

F19

F9

VSS

AE23

AD20

VSS

Datasheet

45

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin Name

VSS

Pin #

Direction

Pin Name

VSS

Pin #

Direction

Type

AB8

Power/Other

B14

B16

B18

B20

B23

B26

B4

Power/Other

VSS

AC11

AC13

AC15

AC17

AC19

AC2

VSS

AC22

AC25

AC5

B8

C11

C13

C15

C17

C19

C2

AC7

AC9

AD10

AD12

AD14

AD16

AD18

AD21

AD23

AD4

C22

C25

C5

C7

C9

D10

D12

D14

D16

D18

D20

D21

D24

D3

AD8

AE11

AE13

AE15

AE17

AE19

AE22

AE24

AE7

D6

AE9

D8

AF1

E1

AF10

AF12

AF14

AF16

AF18

AF20

AF6

E11

E13

E15

E17

E19

E23

E26

E4

AF8

B10

E7

B12

E9

46

Datasheet

Pin Listing and Signal Descriptions

Table 4-1. Alphabetical Pin Assignment

Signal Buffer

Pin Name

VSS

Pin #

Direction

Pin Name

VSS

Pin #

Direction

Type

F10

F12

F14

F16

F18

F2

Power/Other

P5

Power/Other

VSS

VSSA

VSS_SENSE

R1

R23

R26

R4

T21

T24

T3

F22

F25

F5

T6

F8

U2

G21

G24

G3

U22

U25

U5

G6

V1

H1

V23

V26

V4

H23

H26

H4

W21

W24

W3

W6

Y2

J2

J22

J25

J5

K21

K24

K3

Y22

Y25

Y5

K6

AD22

A4

L1

Output

L23

L26

L4

M2

M22

M25

M5

N21

N24

N3

N6

P2

P22

P25

Datasheet

47

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin #

A2

Pin Name

Direction

Pin #

B18

Pin Name

VSS

Direction

Type

THERMTRIP#

VSS

Asynch GTL+

Power/Other

Output

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

TAP

A3

B19

B20

B21

B22

B23

B24

B25

B26

C1

VCC

VSS

A4

VSS_SENSE

VCC_SENSE

TESTHI11

RESERVED

VCC

Output

Input

A5

D0#

Input/Output

A6

D1#

A7

VSS

A8

Power/Other

D6#

Input/Output

A9

VSS

D9#

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

B2

VCC

VSS

TDI

Input

VCC

C2

VSS

Power/Other

Asynch GTL+

Power/Other

Asynch GTL+

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Asynch GTL+

VSS

C3

PROCHOT#

THERMDC

VSS

Input/Output

VCC

C4

VSS

C5

VCC

C6

A20M#

VSS

Input

VSS

C7

VCC

C8

VCC

VSS

C9

VCC

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

C21

C22

C23

C24

C25

C26

D1

VCC

VSS

RESERVED

D2#

VCC

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Asynch GTL+

Power/Other

Asynch GTL+

Asynch AGL+

Power/Other

Input/Output

Input

VSS

VCC

VSS

D3#

VSS

VCC

VSS

IGNNE#

THERMDA

VSS

B3

VCC

VSS

B4

B5

SMI#

Input

VCC

D4#

B6

FERR#/PBE#

VCC

Output

Input/Output

B7

VSS

B8

VSS

D7#

Input/Output

B9

VCC

D8#

B10

B11

B12

B13

B14

B15

B16

B17

VSS

VCC

D12#

LINT0

BPRI#

VSS

Input/Output

Input

VSS

VCC

D2

Common Clock Input

Power/Other

VSS

D3

VCC

D4

TCK

TAP

Input

VSS

D5

TDO

VSS

TAP

Output

VCC

D6

Power/Other

48

Datasheet

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Pin #

D7

Pin Name

VCC

Direction

Pin #

E22

Pin Name

DSTBN0#

Direction

Type

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

D8

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

D5#

E23

E24

E25

E26

F1

VSS

D9

D17#

D21#

VSS

Input/Output

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

D21

D22

D23

D24

D25

D26

E1

RS0#

VSS

Common Clock Input

Power/Other

F2

F3

HIT#

RS2#

VSS

Common Clock Input/Output

Common Clock Input

Power/Other

F4

F5

F6

GTLREF

TMS

Power/Other

TAP

Input

F7

F8

VSS

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

F9

VCC

F10

F11

F12

F13

F14

F15

F16

F17

F18

F19

F20

F21

F22

F23

F24

F25

F26

G1

VSS

Input/Output

VCC

D13#

VSS

D15#

D23#

VSS

DEFER#

HITM#

VSS

LINT1

TRST#

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

DBI0#

VSS

VCC

Input/Output

VSS

VCC

VSS

E2

Common Clock Input

Common Clock Input/Output

Power/Other

VCC

E3

VSS

E4

VCC

E5

Asynch GTL+

TAP

Input

GTLREF

DSTBP0#

VSS

Input

E6

Input/Output

E7

Power/Other

Source Synch

E8

D19#

D20#

VSS

Input/Output

E9

E10

E11

E12

E13

E14

E15

E16

E17

E18

E19

E20

E21

D22#

ADS#

BNR#

VSS

Input/Output

Common Clock Input/Output

Power/Other

G2

G3

G4

LOCK#

RS1#

VSS

Common Clock Input/Output

Common Clock Input

Power/Other

G5

G6

G21

G22

G23

G24

VSS

Power/Other

D10#

D18#

VSS

Source Synch

Power/Other

Input/Output

Datasheet

49

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin #

Pin Name

DBI1#

Direction

Pin #

L4

Pin Name

VSS

Direction

Type

G25

G26

H1

Source Synch

Power/Other

Input/Output

Power/Other

Source Synch

Power/Other

D25#

VSS

L5

ADSTB0#

A5#

Input/Output

L6

H2

DRDY#

REQ4#

VSS

Common Clock Input/Output

L21

L22

L23

L24

L25

L26

M1

D24#

D28#

VSS

H3

Source Synch

Power/Other

Input/Output

H4

H5

DBSY#

BR0#

D11#

D16#

VSS

Common Clock Input/Output

COMP0

DP3#

VSS

Input

H6

Common Clock Input/Output

Power/Other

H21

H22

H23

H24

H25

H26

J1

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

A13#

VSS

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

M2

D26#

D31#

VSS

Input/Output

M3

A10#

A11#

VSS

Input/Output

M4

M5

REQ0#

VSS

Input/Output

M6

A8#

Input/Output

J2

M21

M22

M23

M24

M25

M26

N1

D27#

VSS

J3

REQ3#

REQ2#

VSS

Input/Output

J4

D32#

D35#

VSS

Input/Output

J5

J6

TRDY#

D14#

VSS

Common Clock Input

J21

J22

J23

J24

J25

J26

K1

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

D37#

A12#

A14#

VSS

Input/Output

DSTBP1#

D29#

VSS

Input/Output

N2

N3

N4

A15#

A16#

VSS

Input/Output

DP0#

A6#

Common Clock Input/Output

N5

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

N6

K2

A3#

N21

N22

N23

N24

N25

N26

P1

VSS

K3

VSS

D33#

D36#

VSS

Input/Output

K4

A4#

Input/Output

K5

REQ1#

VSS

K6

D39#

D38#

COMP1

VSS

Input/Output

Input

K21

K22

K23

K24

K25

K26

L1

VSS

DSTBN1#

D30#

VSS

Input/Output

P2

P3

A19#

A20#

VSS

Input/Output

DP1#

DP2#

VSS

Common Clock Input/Output

Power/Other

P4

P5

P6

A24#

D34#

VSS

Input/Output

L2

A9#

Source Synch

Input/Output

P21

P22

L3

A7#

50

Datasheet

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Pin #

P23

Pin Name

DSTBP#2

Direction

Pin #

V2

Pin Name

A27#

Direction

Type

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

Source Synch

Power/Other

Input/Output

P24

P25

P26

R1

D41#

VSS

V3

A32#

V4

VSS

DBI2#

VSS

Input/Output

V5

AP1#

Common Clock Input/Output

V6

MCERR#

DBI3#

D53#

R2

A18#

A21#

VSS

Input/Output

V21

V22

V23

V24

V25

V26

W1

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Asynch GTL+

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Asynch GTL+

Power/Other

Input/Output

R3

R4

VSS

R5

ADSTB1#

A28#

D40#

DSTBN#2

VSS

Input/Output

D54#

Input/Output

R6

D51#

R21

R22

R23

R24

R25

R26

T1

VSS

A29#

Input/Output

W2

A33#

D43#

D42#

VSS

Input/Output

W3

VSS

W4

TESTHI9

INIT#

Input

W5

A17#

A22#

VSS

Input/Output

W6

VSS

T2

W21

W22

W23

W24

W25

W26

Y1

VSS

T3

DSTBN3#

DSTBP3#

VSS

Input/Output

T4

A26#

A30#

VSS

Input/Output

T5

T6

D57#

Input/Output

T21

T22

T23

T24

T25

T26

U1

VSS

D55#

D46#

D47#

VSS

Input/Output

A34#

Y2

VSS

Y3

TESTHI10

STPCLK#

VSS

Input

D45#

D44#

A23#

VSS

Input/Output

Y4

Y5

Y6

BPM3#

D60#

Common Clock Input/Output

U2

Y21

Y22

Y23

Y24

Y25

Y26

AA1

AA2

AA3

AA4

AA5

AA6

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Input/Output

U3

A25#

A31#

VSS

Input/Output

VSS

U4

D58#

Input/Output

U5

D59#

U6

TESTHI8

D52#

VSS

Input

VSS

U21

U22

U23

U24

U25

U26

V1

Input/Output

D56#

Input/Output

Input

VSS

D50#

D49#

VSS

Input/Output

TESTHI1

BINIT#

VSS

Common Clock Input/Output

Power/Other

D48#

VSS

Input/Output

BPM4#

GTLREF

Common Clock Input/Output

Power/Other

Input

Datasheet

51

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Type

Signal Buffer

Pin #

Pin Name

VSS

Direction

Pin #

Pin Name

TESTHI7

Direction

Type

AA7

Power/Other

Source Synch

Power/Other

Source Synch

Power/Other

Source Synch

AB22

AB23

AB24

AB25

AB26

AC1

Power/Other

Input

AA8

VCC

VSS

PWRGOOD

VSS

AA9

AA10

AA11

AA12

AA13

AA14

AA15

AA16

AA17

AA18

AA19

AA20

AA21

AA22

AA23

AA24

AA25

AA26

AB1

VCC

VSS

RESET#

SLP#

Common Clock Input

Asynch GTL+ Input

VCC

VSS

AP0#

Common Clock Input/Output

Power/Other

AC2

VSS

VCC

VSS

AC3

IERR#

BPM2#

VSS

Asynch GTL+

Output

AC4

Common Clock Input/Output

Power/Other

VCC

VSS

AC5

AC6

BPM0#

VSS

Common Clock Input/Output

Power/Other

VCC

VSS

AC7

AC8

VCC

Power/Other

TESTHI6

GTLREF

D62#

VSS

Input

AC9

VSS

Power/Other

Input

AC10

AC11

AC12

AC13

AC14

AC15

AC16

AC17

AC18

AC19

AC20

AC21

AC22

AC23

AC24

AC25

AC26

AD1

VCC

Power/Other

Input/Output

VSS

Power/Other

VCC

Power/Other

D63#

D61#

VSS

Input/Output

VSS

Power/Other

VCC

Power/Other

VSS

Power/Other

A35#

RSP#

VSS

Input/Output

VCC

Power/Other

AB2

Common Clock Input

Power/Other

VSS

Power/Other

AB3

VCC

Power/Other

AB4

BPM5#

BPM1#

VSS

Common Clock Input/Output

Power/Other

VSS

Power/Other

AB5

TESTHI3

TESTHI2

VSS

Power/Other

TAP

Input

AB6

AB7

VCC

VSS

Power/Other

AB8

Power/Other

TESTHI5

TESTHI4

VSS

Input

AB9

VCC

VSS

Power/Other

AB10

AB11

AB12

AB13

AB14

AB15

AB16

AB17

AB18

AB19

AB20

AB21

Power/Other

VCC

VSS

Power/Other

ITP_CLK0

Input

Output

Power/Other

BOOTSELECT Power/Other

VCC

VSS

Power/Other

AD2

VIDPWRGD

VID5

Power/Other

AD3

VCC

VSS

Power/Other

AD4

VSS

Power/Other

AD5

BSEL1

BSEL0

VCC

Output

VCC

VSS

Power/Other

AD6

Power/Other

AD7

VCC

VSS

Power/Other

AD8

VSS

Power/Other

AD9

VCC

VSS

Power/Other

AD10

VSS

52

Datasheet

Pin Listing and Signal Descriptions

Table 4-2. Numerical Pin Assignment

Signal Buffer

Pin #

Pin Name

VCC

Direction

Pin #

Pin Name

Direction

Type

AD11

AD12

AD13

AD14

AD15

AD16

AD17

AD18

AD19

AD20

AD21

AD22

AD23

AD24

AD25

AD26

AE1

Power/Other

TAP

OPTIMIZED/

COMPAT#

AE26

Power/Other

Input

VSS

AF1

VSS

Power/Other

Bus Clock

VCC

AF2

VCC

VSS

AF3

VCCVIDLB

VCCVID

VCC

Input

VCC

AF4

VSS

AF5

VCC

AF6

VSS

AF7

VCC

AF8

VSS

VCCIOPLL

VSS

AF9

VCC

AF10

AF11

AF12

AF13

AF14

AF15

AF16

AF17

AF18

AF19

AF20

AF21

AF22

AF23

AF24

AF25

AF26

VSS

VSSA

VSS

VCC

VSS

TESTHI0

TESTHI12

ITP_CLK1

VID4

Input

VCC

Input

VSS

Input

VCC

Power/Other

Output

VSS

AE2

VID3

VCC

AE3

VID2

VSS

AE4

VID1

VCC

AE5

VID0

VSS

AE6

VCC

AE7

VSS

BCLK0

BCLK1

RESERVED

SKTOCC#

Input

AE8

VCC

Bus Clock

AE9

VSS

AE10

AE11

AE12

AE13

AE14

AE15

AE16

AE17

AE18

AE19

AE20

AE21

AE22

AE23

AE24

AE25

VCC

VSS

Power/Other

Output

VCC

VSS

VCC

VSS

VCC

VSS

VCC

VSS

VCC

RESERVED

VSS

Power/Other

VCCA

VSS

DBR#

Output

Datasheet

53

Pin Listing and Signal Descriptions

4.2

Alphabetical Signals Reference

Table 4-3. Signal Description (Sheet 1 of 8)

Name

Type

Description

36

A[35:3]# (Address) define a 2 -byte physical memory address space. In sub-

phase 1 of the address phase, these pins transmit the address of a transaction.

In sub-phase 2, these pins transmit transaction type information. These signals

®

must connect the appropriate pins of all agents on the Celeron D processor

FSB. A[35:3]# are protected by parity signals AP[1:0]#. A[35:3]# are source

synchronous signals and are latched into the receiving buffers by ADSTB[1:0]#.

Input/

Output

A[35:3]#

On the active-to-inactive transition of RESET#, the processor samples a subset

of the A[35:3]# pins to determine power-on configuration. See Section 6.1 for

more details.

If A20M# (Address-20 Mask) is asserted, the processor masks physical address

bit 20 (A20#) before looking up a line in any internal cache and before driving a

read/write transaction on the bus. Asserting A20M# emulates the 8086

processor's address wrap-around at the 1-MB boundary. Assertion of A20M# is

only supported in real mode.

A20M#

ADS#

Input

A20M# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

ADS# (Address Strobe) is asserted to indicate the validity of the transaction

address on the A[35:3]# and REQ[4:0]# pins. All bus agents observe the ADS#

activation to begin parity checking, protocol checking, address decode, internal

snoop, or deferred reply ID match operations associated with the new

transaction.

Input/

Output

Address strobes are used to latch A[35:3]# and REQ[4:0]# on their rising and

falling edges. Strobes are associated with signals as shown below.

Signals

Associated Strobe

Input/

Output

ADSTB[1:0]#

REQ[4:0]#, A[16:3]#

A[35:17]#

ADSTB0#

ADSTB1#

AP[1:0]# (Address Parity) are driven by the request initiator along with ADS#,

A[35:3]#, and the transaction type on the REQ[4:0]#. A correct parity signal is

high if an even number of covered signals are low and low if an odd number of

covered signals are low. This allows parity to be high when all the covered

signals are high. AP[1:0]# should connect the appropriate pins of all Celeron D

processor FSB agents. The following table defines the coverage model of these

signals.

Input/

AP[1:0]#

Output

Request Signals

Subphase 1

Subphase 2

A[35:24]#

A[23:3]#

AP0#

AP1#

AP0#

REQ[4:0]#

The differential pair BCLK (Bus Clock) determines the FSB frequency. All

processor FSB agents must receive these signals to drive their outputs and latch

their inputs.

BCLK[1:0]

Input

All external timing parameters are specified with respect to the rising edge of

BCLK0 crossing V

.

CROSS

54

Datasheet

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 2 of 8)

Name

Type

Description

BINIT# (Bus Initialization) may be observed and driven by all processor FSB

agents and if used, must connect the appropriate pins of all such agents. If the

BINIT# driver is enabled during power-on configuration, BINIT# is asserted to

signal any bus condition that prevents reliable future operation.

If BINIT# observation is enabled during power-on configuration, and BINIT# is

sampled asserted, symmetric agents reset their bus LOCK# activity and bus

request arbitration state machines. The bus agents do not reset their IOQ and

transaction tracking state machines upon observation of BINIT# activation. Once

the BINIT# assertion has been observed, the bus agents will re-arbitrate for the

FSB and attempt completion of their bus queue and IOQ entries.

Input/

Output

BINIT#

If BINIT# observation is disabled during power-on configuration, a central agent

may handle an assertion of BINIT# as appropriate to the error handling

architecture of the system.

BNR# (Block Next Request) is used to assert a bus stall by any bus agent who is

unable to accept new bus transactions. During a bus stall, the current bus owner

cannot issue any new transactions.

Input/

Output

BNR#

This input is required to determine whether the processor is installed in a

platform that supports the Celeron D processor. The Celeron D processor will not

operate if this pin is low. This input has a weak internal pull-up.

BOOTSELECT

Input

BPM[5:0]# (Breakpoint Monitor) are breakpoint and performance monitor

signals. They are outputs from the processor which indicate the status of

breakpoints and programmable counters used for monitoring processor

performance. BPM[5:0]# should connect the appropriate pins of all Celeron D

processor FSB agents.

BPM4# provides PRDY# (Probe Ready) functionality for the TAP port. PRDY# is

a processor output used by debug tools to determine processor debug

readiness.

Input/

Output

BPM[5:0]#

BPM5# provides PREQ# (Probe Request) functionality for the TAP port. PREQ#

is used by debug tools to request debug operation of the processor.

Refer to the applicable chipset platform design guide for more detailed

information.

These signals do not have on-die termination. Refer to Section 2.5, and the

applicable chipset platform design guide for termination requirements.

BPRI# (Bus Priority Request) is used to arbitrate for ownership of the processor

FSB. It must connect the appropriate pins of all processor FSB agents.

Observing BPRI# active (as asserted by the priority agent) causes all other

agents to stop issuing new requests, unless such requests are part of an

ongoing locked operation. The priority agent keeps BPRI# asserted until all of its

requests are completed, then releases the bus by de-asserting BPRI#.

BPRI#

BR0#

Input

BR0# (Bus Request 0) drives the BREQ0# signal in the system and is used by

the processor to request the bus. During power-on configuration this pin is

sampled to determine the agent ID = 0.

Input/

Output

This signal does not have on-die termination and must be terminated.

The BCLK[1:0] frequency select signals BSEL[1:0] are used to select the

processor input clock frequency. Table 2-6 defines the possible combinations of

the signals and the frequency associated with each combination. The required

BSEL[1:0]

Output frequency is determined by the processor, chipset and clock synthesizer. All

agents must operate at the same frequency. For more information about these

pins, including termination recommendations refer to Section 2.9 and the

appropriate platform design guidelines.

COMP[1:0] must be terminated on the system board using precision resistors.

Analog Refer to the applicable chipset platform design guide for details on

implementation.

COMP[1:0]

Datasheet

55

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 3 of 8)

Name

Type

Description

D[63:0]# (Data) are the data signals. These signals provide a 64-bit data path

between the processor FSB agents, and must connect the appropriate pins on

all such agents. The data driver asserts DRDY# to indicate a valid data transfer.

D[63:0]# are quad-pumped signals and will thus be driven four times in a

common clock period. D[63:0]# are latched off the falling edge of both

DSTBP[3:0]# and DSTBN[3:0]#. Each group of 16 data signals correspond to a

pair of one DSTBP# and one DSTBN#. The following table shows the grouping

of data signals to data strobes and DBI#.

Quad-Pumped Signal Groups

DSTBN#/

DSTBP#

Input/

Output

Data Group

DBI#

D[63:0]#

D[15:0]#

D[31:16]#

D[47:32]#

D[63:48]#

0

1

2

3

0

1

2

3

Furthermore, the DBI# pins determine the polarity of the data signals. Each

group of 16 data signals corresponds to one DBI# signal. When the DBI# signal

is active, the corresponding data group is inverted and therefore sampled active

high.

DBI[3:0]# (Data Bus Invert) are source synchronous and indicate the polarity of

the D[63:0]# signals.The DBI[3:0]# signals are activated when the data on the

data bus is inverted. If more than half the data bits, within a 16-bit group, would

have been asserted electrically low, the bus agent may invert the data bus

signals for that particular sub-phase for that 16-bit group.

DBI[3:0] Assignment To Data Bus

Input/

Output

DBI[3:0]#

Bus Signal

Data Bus Signals

DBI3#

DBI2#

DBI1#

DBI0#

D[63:48]#

D[47:32]#

D[31:16]#

D[15:0]#

DBR# (Debug Reset) is used only in processor systems where no debug port is

implemented on the system board. DBR# is used by a debug port interposer so

that an in-target probe can drive system reset. If a debug port is implemented in

the system, DBR# is a no connect in the system. DBR# is not a processor signal.

DBR#

Output

DBSY# (Data Bus Busy) is asserted by the agent responsible for driving data on

Input/ the processor FSB to indicate that the data bus is in use. The data bus is

Output released after DBSY# is de-asserted. This signal must connect the appropriate

pins on all processor FSB agents.

DBSY#

DEFER# is asserted by an agent to indicate that a transaction cannot be

guaranteed in-order completion. Assertion of DEFER# is normally the

responsibility of the addressed memory or Input/Output agent. This signal must

connect the appropriate pins of all processor FSB agents.

DEFER#

DP[3:0]#

Input

DP[3:0]# (Data Parity) provide parity protection for the D[63:0]# signals. They

are driven by the agent responsible for driving D[63:0]#, and must connect the

appropriate pins of all Celeron D processor FSB agents.

Input/

Output

56

Datasheet

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 4 of 8)

Name

Type

Description

DRDY# (Data Ready) is asserted by the data driver on each data transfer,

Input/ indicating valid data on the data bus. In a multi-common clock data transfer,

Output DRDY# may be de-asserted to insert idle clocks. This signal must connect the

appropriate pins of all processor FSB agents.

DRDY#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBN0#

DSTBN1#

DSTBN2#

DSTBN3#

Input/

Output

DSTBN[3:0]#

Data strobe used to latch in D[63:0]#.

Signals

Associated Strobe

D[15:0]#, DBI0#

D[31:16]#, DBI1#

D[47:32]#, DBI2#

D[63:48]#, DBI3#

DSTBP0#

DSTBP1#

DSTBP2#

DSTBP3#

Input/

Output

DSTBP[3:0]#

FERR#/PBE# (Floating Point Error/Pending Break Event) is a multiplexed signal

and its meaning is qualified by STPCLK#. When STPCLK# is not asserted,

FERR#/PBE# indicates a floating-point error and will be asserted when the

processor detects an unmasked floating-point error. When STPCLK# is not

asserted, FERR#/PBE# is similar to the ERROR# signal on the Intel 387

coprocessor, and is included for compatibility with systems using MS-DOS*-type

floating-point error reporting.

FERR#/PBE#

Output

When STPCLK# is asserted, an assertion of FERR#/PBE# indicates that the

processor has a pending break event waiting for service. The assertion of

FERR#/PBE# indicates that the processor should be returned to the Normal

state. For additional information on the pending break event functionality,

including the identification of support of the feature and enable/disable

information, refer to volume 3 of the Intel Architecture Software Developer's

Manual and the Intel Processor Identification and the CPUID Instruction

application note.

GTLREF determines the signal reference level for GTL+ input pins. GTLREF is

used by the GTL+ receivers to determine if a signal is a logical 0 or logical 1.

Refer to the applicable chipset platform design guide for more information.

GTLREF

Input

Input/ HIT# (Snoop Hit) and HITM# (Hit Modified) convey transaction snoop operation

Output results. Any FSB agent may assert both HIT# and HITM# together to indicate

that it requires a snoop stall, which can be continued by reasserting HIT# and

HIT#

HITM# together.

HITM#

Input/

Output

IERR# (Internal Error) is asserted by a processor as the result of an internal

error. Assertion of IERR# is usually accompanied by a SHUTDOWN transaction

on the processor FSB. This transaction may optionally be converted to an

external error signal (e.g., NMI) by system core logic. The processor will keep

IERR# asserted until the assertion of RESET#.

IERR#

Output

This signal does not have on-die termination. Refer to Section 2.5 for termination

requirements.

Datasheet

57

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 5 of 8)

Name

Type

Description

IGNNE# (Ignore Numeric Error) is asserted to force the processor to ignore a

numeric error and continue to execute noncontrol floating-point instructions. If

IGNNE# is de-asserted, the processor generates an exception on a noncontrol

floating-point instruction if a previous floating-point instruction caused an error.

IGNNE# has no effect when the NE bit in control register 0 (CR0) is set.

IGNNE#

Input

IGNNE# is an asynchronous signal. However, to ensure recognition of this signal

following an Input/Output write instruction, it must be valid along with the TRDY#

assertion of the corresponding Input/Output Write bus transaction.

INIT# (Initialization), when asserted, resets integer registers inside the processor

without affecting its internal caches or floating-point registers. The processor

then begins execution at the power-on Reset vector configured during power-on

configuration. The processor continues to handle snoop requests during INIT#

assertion. INIT# is an asynchronous signal and must connect the appropriate

pins of all processor FSB agents.

INIT#

Input

If INIT# is sampled active on the active to inactive transition of RESET#, then the

processor executes its Built-in Self-Test (BIST).

ITP_CLK[1:0] are copies of BCLK that are used only in processor systems

where no debug port is implemented on the system board. ITP_CLK[1:0] are

used as BCLK[1:0] references for a debug port implemented on an interposer. If

a debug port is implemented in the system, ITP_CLK[1:0] are no connects in the

system. These are not processor signals.

ITP_CLK[1:0]

LINT[1:0] (Local APIC Interrupt) must connect the appropriate pins of all APIC

Bus agents. When the APIC is disabled, the LINT0 signal becomes INTR, a

maskable interrupt request signal, and LINT1 becomes NMI, a nonmaskable

interrupt. INTR and NMI are backward compatible with the signals of those

names on the Pentium processor. Both signals are asynchronous.

LINT[1:0]

Input

Both of these signals must be software configured via BIOS programming of the

APIC register space to be used either as NMI/INTR or LINT[1:0]. Because the

APIC is enabled by default after Reset, operation of these pins as LINT[1:0] is

the default configuration.

LOCK# indicates to the system that a transaction must occur atomically. This

signal must connect the appropriate pins of all processor FSB agents. For a

locked sequence of transactions, LOCK# is asserted from the beginning of the

first transaction to the end of the last transaction.

Input/

Output

LOCK#

When the priority agent asserts BPRI# to arbitrate for ownership of the processor

FSB, it will wait until it observes LOCK# de-asserted. This enables symmetric

agents to retain ownership of the processor FSB throughout the bus locked

operation and ensure the atomicity of lock.

MCERR# (Machine Check Error) is asserted to indicate an unrecoverable error

without a bus protocol violation. It may be driven by all processor FSB agents.

MCERR# assertion conditions are configurable at a system level. Assertion

options are defined by the following options:

•

Enabled or disabled.

Input/

Output

MCERR#

Asserted, if configured, for internal errors along with IERR#.

Asserted, if configured, by the request initiator of a bus transaction after it

observes an error.

•

Asserted by any bus agent when it observes an error in a bus transaction.

For more details regarding machine check architecture, refer to the IA-32

Software Developer’s Manual, Volume 3: System Programming Guide.

58

Datasheet

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 6 of 8)

Name

Type

Description

This is an input to the processor to determine if the processor is in an optimized

platform or a compatible platform. This input has a weak internal pull-up.

A compatible platform is one that is designed for a previous generation

processor but has some level of compatibility with the Celeron D processor. An

optimized platform is one designed specifically for the Celeron D processor;

however, it may have some level of compatibility with previous generation

processors.

OPTIMIZED/

COMPAT#

Input

As an output, PROCHOT# (Processor Hot) goes active when the processor

temperature monitoring sensor detects that the processor has reached its

Input/ maximum safe operating temperature. This indicates that the processor Thermal

Output Control Circuit (TCC) has been activated, if enabled. As an input, assertion of

PROCHOT# by the system activates the TCC, if enabled. The TCC remains

active until the system de-asserts PROCHOT#.

PROCHOT#

PWRGOOD (Power Good) is a processor input. The processor requires this

signal to be a clean indication that the clocks and power supplies are stable and

within their specifications. ‘Clean’ implies that the signal will remain low (capable

of sinking leakage current), without glitches, from the time that the power

supplies are turned on until they come within specification. The signal must then

transition monotonically to a high state. PWRGOOD can be driven inactive at

PWRGOOD

Input

any time, but clocks and power must again be stable before a subsequent rising

edge of PWRGOOD. It must also meet the minimum pulse width specification

and be followed by a 1 ms to 10 ms RESET# pulse.

The PWRGOOD signal must be supplied to the processor; it is used to protect

internal circuits against voltage sequencing issues. It should be driven high

throughout boundary scan operation.

REQ[4:0]# (Request) must connect the appropriate pins of all processor FSB

Input/ agents. They are asserted by the current bus owner to define the currently active

Output transaction type. These signals are source synchronous to ADSTB0#. Refer to

the AP[1:0]# signal description for a details on parity checking of these signals.

REQ[4:0]#

Asserting the RESET# signal resets the processor to a known state and

invalidates its internal caches without writing back any of their contents. For a

power-on Reset, RESET# must stay active for at least 1 ms after V and BCLK

CC

have reached their proper specifications. On observing active RESET#, all FSB

agents will de-assert their outputs within two clocks. RESET# must not be kept

asserted for more than 10 ms while PWRGOOD is asserted.

RESET#

RS[2:0]#

Input

A number of bus signals are sampled at the active-to-inactive transition of

RESET# for power-on configuration. These configuration options are described

in the Section 6.1.

This signal does not have on-die termination and must be terminated on the

system board.

RS[2:0]# (Response Status) are driven by the response agent (the agent

responsible for completion of the current transaction), and must connect the

appropriate pins of all processor FSB agents.

RSP# (Response Parity) is driven by the response agent (the agent responsible

for completion of the current transaction) during assertion of RS[2:0]#, the

signals for which RSP# provides parity protection. It must connect to the

appropriate pins of all processor FSB agents.

RSP#

Input

A correct parity signal is high if an even number of covered signals are low and

low if an odd number of covered signals are low. While RS[2:0]# = 000, RSP# is

also high, since this indicates it is not being driven by any agent guaranteeing

correct parity.

SKTOCC# (Socket Occupied) will be pulled to ground by the processor. System

board designers may use this pin to determine if the processor is present.

SKTOCC#

Output

Datasheet

59

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 7 of 8)

Name

Type

Description

SLP# (Sleep), when asserted in Stop-Grant state, causes the processor to enter

the Sleep state. During Sleep state, the processor stops providing internal clock

signals to all units, leaving only the Phase-Locked Loop (PLL) still operating.

Processors in this state will not recognize snoops or interrupts. The processor

will recognize only assertion of the RESET# signal, and de-assertion of SLP#. If

SLP# is de-asserted, the processor exits Sleep state and returns to Stop-Grant

state, restarting its internal clock signals to the bus and processor core units.

SLP#

SMI#

Input

SMI# (System Management Interrupt) is asserted asynchronously by system

logic. On accepting a System Management Interrupt, the processor saves the

current state and enter System Management Mode (SMM). An SMI

Acknowledge transaction is issued, and the processor begins program execution

from the SMM handler.

Input

If SMI# is asserted during the de-assertion of RESET#, the processor will tristate

its outputs.

STPCLK# (Stop Clock), when asserted, causes the processor to enter a low

power Stop-Grant state. The processor issues a Stop-Grant Acknowledge

transaction, and stops providing internal clock signals to all processor core units

except the FSB and APIC units. The processor continues to snoop bus

transactions and service interrupts while in Stop-Grant state. When STPCLK# is

de-asserted, the processor restarts its internal clock to all units and resumes

execution. The assertion of STPCLK# has no effect on the bus clock; STPCLK#

is an asynchronous input.

STPCLK#

TCK (Test Clock) provides the clock input for the processor Test Bus (also known

as the Test Access Port).

TCK

Input

TDI (Test Data In) transfers serial test data into the processor. TDI provides the

serial input needed for JTAG specification support.

TDI

TDO (Test Data Out) transfers serial test data out of the processor. TDO

provides the serial output needed for JTAG specification support.

TDO

Output

Input

TESTHI[12:0] must be connected to a V power source through a resistor for

CC

TESTHI[12:0]

proper processor operation. See Section 2.5 for more details.

THERMDA

THERMDC

Other Thermal Diode Anode. See Section 5.2.6.

Other Thermal Diode Cathode. See Section 5.2.6.

In the event of a catastrophic cooling failure, the processor will automatically

shut down when the silicon has reached a temperature approximately 20 °C

above the maximum T . Assertion of THERMTRIP# (Thermal Trip) indicates the

C

processor junction temperature has reached a level beyond which permanent

silicon damage may occur. Upon assertion of THERMTRIP#, the processor will

shut off its internal clocks (thus halting program execution) in an attempt to

reduce the processor junction temperature. To protect the processor, its core

THERMTRIP#

Output voltage (V ) must be removed following the assertion of THERMTRIP#. Driving

CC

of the THERMTRIP# signal is enabled within 10 µs of the assertion of

PWRGOOD and is disabled on de-assertion of PWRGOOD. Once activated,

THERMTRIP# remains latched until PWRGOOD is de-asserted. While the de-

assertion of the PWRGOOD signal will de-assert THERMTRIP#, if the

processor’s junction temperature remains at or above the trip level,

THERMTRIP# will again be asserted within 10 µs of the assertion of

PWRGOOD.

TMS (Test Mode Select) is a JTAG specification support signal used by debug

TMS

Input

tools.

TRDY# (Target Ready) is asserted by the target to indicate that it is ready to

TRDY#

TRST#

Input

receive a write or implicit writeback data transfer. TRDY# must connect the

appropriate pins of all FSB agents.

TRST# (Test Reset) resets the Test Access Port (TAP) logic. TRST# must be

driven low during power on Reset.

60

Datasheet

Pin Listing and Signal Descriptions

Table 4-3. Signal Description (Sheet 8 of 8)

Name

Type

Description

VCC are the power pins for the processor. The voltage supplied to these pins is

determined by the VID[5:0] pins.

VCC

Input

VCCA provides isolated power for the internal processor core PLLs. Refer to the

applicable chipset platform design guide for complete implementation details.

VCCA

Input

VCCIOPLL provides isolated power for internal processor FSB PLLs. Follow the

guidelines for VCCA, and refer to the applicable chipset platform design guide

for complete implementation details.

VCCIOPLL

VCC_SENSE is an isolated low impedance connection to processor core power

VCC_SENSE

VCCVID

Output (V ). It can be used to sense or measure voltage near the silicon with little

CC

noise.

1.2 V is required to be supplied to the VCCVID pin if the platform is going to

Input

support the Celeron D processor. Refer to the applicable chipset platform design

guide for more information.

1.2 V is required to be supplied to the VCCVIDLB pin if the platform is going to

support the Celeron D processor. Refer to the applicable chipset platform design

guide for more information.

VCCVIDLB

VID[5:0] (Voltage ID) pins are used to support automatic selection of power

supply voltages (V ). These are open drain signals that are driven by the

CC

Celeron D processor and must be pulled up to 3.3 V with 1 kΩ 5% resistors. The

voltage supply for these pins must be valid before the VR can supply V to the

CC

VID[5:0]

Output processor. Conversely, the VR output must be disabled until the voltage supply

for the VID pins becomes valid. The VID pins are needed to support the

processor voltage specification variations. See Table 2-2 for definitions of these

pins. The VR must supply the voltage that is requested by the pins, or disable

itself.

The processor requires this input to determine that the VCCVID and VCCVIDLB

voltages are stable and within specification.

VIDPWRGD

Input

VSS are the ground pins for the processor and should be connected to the

system ground plane.

VSS

Input

VSSA

Input

VSSA is the isolated ground for internal PLLs.

VSS_SENSE is an isolated low impedance connection to processor core V . It

can be used to sense or measure ground near the silicon with little noise.

SS

VSS_SENSE

Output

§

Datasheet

61

Pin Listing and Signal Descriptions

62

Datasheet

Thermal Specifications and Design Considerations

5 Thermal Specifications and

Design Considerations

5.1

Processor Thermal Specifications

The Celeron D processor requires a thermal solution to maintain temperatures within operating

limits as set forth in Section 5.1.1. Any attempt to operate the processor outside these operating

limits may result in permanent damage to the processor and potentially other components within

the system. As processor technology changes, thermal management becomes increasingly crucial

when building computer systems. Maintaining the proper thermal environment is key to reliable,

long-term system operation.

A complete thermal solution includes both component and system level thermal management

features. Component level thermal solutions can include active or passive heatsinks attached to the

processor Integrated Heat Spreader (IHS). Typical system level thermal solutions may consist of

system fans combined with ducting and venting.

For more information on designing a component level thermal solution, refer to the applicable

thermal design guide.

Note: The boxed processor will ship with a component thermal solution. Refer to Chapter 7 for details on

the boxed processor.

5.1.1

Thermal Specifications

To allow for the optimal operation and long-term reliability of Intel processor-based systems, the

system/processor thermal solution should be designed such that the processor remains within the

minimum and maximum case temperature (T_C) specifications when operating at or below the

Thermal Design Power (TDP) value listed per frequency in Table 5-1. Thermal solutions not

designed to provide this level of thermal capability may affect the long-term reliability of the

processor and system. For more details on thermal solution design, refer to the appropriate

processor thermal design guidelines.

The Celeron D processor introduces a new methodology for managing processor temperatures

through fan speed control. Selection of the appropriate fan speed will be based on the temperature

reported by the processor’s Thermal Diode. The fan must be turned on to full speed when T_DIODE

is at or above T_CONTROLand T_Cmust be maintained at or below T_C(max) as defined by the

processor thermal specifications in Table 5-1. The fan speed may be lowered when the processor

temperature can be maintained below T_CONTROLas measured by the thermal diode. Systems

implementing fan speed control must be designed to read temperature values from the diode and

T

_CONTROLregister and take appropriate action. Systems that do not alter the fan speed (always at

full speed) only need to guarantee the case temperature meets specifications in Table 5-1.

The case temperature is defined at the geometric top center of the processor IHS. Analysis

indicates that real applications are unlikely to cause the processor to consume maximum power

dissipation for sustained periods of time. Intel recommends that complete thermal solution designs

target the Thermal Design Power (TDP) indicated in Table 5-1 instead of the maximum processor

Datasheet

63

Thermal Specifications and Design Considerations

power consumption. The Thermal Monitor feature is intended to help protect the processor in the

unlikely event that an application exceeds the TDP recommendation for a sustained period of time.

For more details on the usage of this feature, refer to Section 5.2. In all cases, the Thermal

Monitor feature must be enabled for the processor to remain within specification.

Table 5-1. Processor Thermal Specifications

Core

Frequency

(GHz)

Processor

Number

ThermalDesign Minimum T

Maximum T

(°C)

1,2

C

Notes

Power (W)

(°C)

350

345

3.20

3.06

2.93

2.80

2.66

2.53

2.40

73

5

67

—

340

335

330

325

320

NOTES:

1. Thermal Design Power (TDP) should be used for processor thermal solution design targets. The

TDP is not the maximum power that the processor can dissipate.

2. This table shows the maximum TDP for a given frequency range. Individual processors may

have a lower TDP.

5.1.2

Thermal Metrology

The maximum and minimum case temperatures (T_C) are specified in Table 5-1. These temperature

specifications are meant to help ensure proper operation of the processor. Figure 5-1 illustrates

where Intel recommends T_Cthermal measurements should be made. For detailed guidelines on

temperature measurement methodology, refer to the applicable thermal design guide.

Figure 5-1. Case Temperature (T_C) Measurement Location

Measure from edge of processor IHS

15.5 mm[0.61 in]

Measure T_Cat this point

(geometric center of IHS)

15.5 mm[0.61 in]

31 mm x 31 mm IHS[1.22 x 1.22 in]

35 mm x 35 mm substrate [1.378 in x 1.378 in]

64

Datasheet

Thermal Specifications and Design Considerations

5.2

Processor Thermal Features

5.2.1

Thermal Monitor

The Thermal Monitor feature helps control the processor temperature by activating the TCC when

the processor silicon reaches its maximum operating temperature. The TCC reduces processor

power consumption as needed by modulating (starting and stopping) the internal processor core

clocks. The Thermal Monitor feature must be enabled for the processor to be operating

within specifications. The temperature at which Thermal Monitor activates the thermal control

circuit is not user configurable and is not software visible. Bus traffic is snooped in the normal

manner, and interrupt requests are latched (and serviced during the time that the clocks are on)

while the TCC is active.

When the Thermal Monitor feature is enabled, and a high temperature situation exists (i.e., TCC is

active), the clocks will be modulated by alternately turning the clocks off and on at a duty cycle

specific to the processor (typically 30–50%). Clocks often will not be off for more than

3.0 microseconds when the TCC is active. Cycle times are processor speed dependent and will

decrease as processor core frequencies increase. A small amount of hysteresis has been included to

prevent rapid active/inactive transitions of the TCC when the processor temperature is near its

maximum operating temperature. Once the temperature has dropped below the maximum

operating temperature, and the hysteresis timer has expired, the TCC goes inactive and clock

modulation ceases.

With a properly designed and characterized thermal solution, it is anticipated that the TCC would

only be activated for very short periods of time when running the most power intensive

applications. The processor performance impact due to these brief periods of TCC activation is

expected to be so minor that it would be immeasurable. An under-designed thermal solution that is

not able to prevent excessive activation of the TCC in the anticipated ambient environment may

cause a noticeable performance loss, and in some cases may result in a T_Cthat exceeds the

specified maximum temperature and may affect the long-term reliability of the processor. In

addition, a thermal solution that is significantly under-designed may not be capable of cooling the

processor even when the TCC is active continuously. Refer to the applicable thermal design guide

for information on designing a thermal solution.

The duty cycle for the TCC, when activated by the Thermal Monitor, is factory configured and

cannot be modified. The Thermal Monitor does not require any additional hardware, software

drivers, or interrupt handling routines.

5.2.2

On-Demand Mode

The Celeron D processor provides an auxiliary mechanism that allows system software to force the

processor to reduce its power consumption. This mechanism is referred to as "On-Demand" mode

and is distinct from the Thermal Monitor feature. On-Demand mode is intended as a means to

reduce system level power consumption. Systems using the Celeron D processor must not rely on

software usage of this mechanism to limit the processor temperature.

If bit 4 of the ACPI P_CNT Control Register (located in the processor IA32_THERM_CONTROL

MSR) is written to a '1', the processor will immediately reduce its power consumption via

modulation (starting and stopping) of the internal core clock, independent of the processor

temperature. When using On-Demand mode, the duty cycle of the clock modulation is

programmable via bits 3:1 of the same ACPI P_CNT Control Register. In On-Demand mode, the

duty cycle can be programmed from 12.5% on/ 87.5% off, to 87.5% on/12.5% off in 12.5%

Datasheet

65

Thermal Specifications and Design Considerations

increments. On-Demand mode may be used in conjunction with the Thermal Monitor. If the system

tries to enable On-Demand mode at the same time the TCC is engaged, the factory configured duty

cycle of the TCC will override the duty cycle selected by the On-Demand mode.

5.2.3

PROCHOT# Signal Pin

An external signal, PROCHOT# (processor hot), is asserted when the processor die temperature

has reached its maximum operating temperature. If the Thermal Monitor is enabled (note that the

Thermal Monitor must be enabled for the processor to be operating within specification), the TCC

will be active when PROCHOT# is asserted. The processor can be configured to generate an

interrupt upon the assertion or de-assertion of PROCHOT#. Refer to the Intel Architecture

Software Developer's Manuals for specific register and programming details.

The Celeron D processor implements a bi-directional PROCHOT# capability to allow system

designs to protect various components from over-temperature situations. The PROCHOT# signal is

bi-directional in that it can either signal when the processor has reached its maximum operating

temperature or be driven from an external source to activate the TCC. The ability to activate the

TCC via PROCHOT# can provide a means for thermal protection of system components.

One application is the thermal protection of voltage regulators (VR). System designers can create a

circuit to monitor the VR temperature and activate the TCC when the temperature limit of the VR

is reached. By asserting PROCHOT# (pulled-low) and activating the TCC, the VR can cool down

as a result of reduced processor power consumption. Bi-directional PROCHOT# can allow VR

thermal designs to target maximum sustained current instead of maximum current. Systems should

still provide proper cooling for the VR, and rely on bi-directional PROCHOT# only as a backup in

case of system cooling failure. The system thermal design should allow the power delivery

circuitry to operate within its temperature specification even while the processor is operating at its

Thermal Design Power. With a properly designed and characterized thermal solution, it is

anticipated that bi-directional PROCHOT# would only be asserted for very short periods of time

when running the most power intensive applications. An under-designed thermal solution that is

not able to prevent excessive assertion of PROCHOT# in the anticipated ambient environment may

cause a noticeable performance loss. Refer to the applicable chipset platform design guide and the

applicable VRD design guide for details on implementing the bi-directional PROCHOT# feature.

5.2.4

THERMTRIP# Signal Pin

Regardless of whether or not the Thermal Monitor feature is enabled, in the event of a catastrophic

cooling failure, the processor will automatically shut down when the silicon has reached an

elevated temperature (refer to the THERMTRIP# definition in Table 4-3). At this point, the FSB

signal THERMTRIP# will go active and stay active as described in Table 4-3. THERMTRIP#

activation is independent of processor activity and does not generate any bus cycles.

66

Datasheet

Thermal Specifications and Design Considerations

5.2.5

T

and Fan Speed Reduction (Optional)

CONTROL

T_CONTROLand Fan Speed Reduction are not requirements for the Celeron D processor on 90 nm

process and in the 478-pin package, but are provided as options for platforms that can use these

features. T_CONTROLis part of the temperature specification that defines temperature for system fan

speed management. The BIOS reads the T_CONTROLvalue once and configures the fan control chip

appropriately. The value for T_CONTROLwill be set during manufacturing and is unique for each

processor. The T_CONTROLtemperature for a given processor can be obtained by reading the

IA32_TEMPERATURE_TARGET MSR in the processor and is in hexadecimal format.

The value of T_CONTROL(read from IA32_TEMPERATURE_TARGET MSR) can vary from 00 h

to 1E h (0 to 30 °C). The T_CONTROLread from the IA32_TEMPERATURE_TARGET MSR needs

to be added to a base value of 50 °C to get the final value for comparison with Thermal Diode

temperature (T_DIODE). T_CONTROLplus the base value of 50 °C is compared to the temperature

reported by T_DIODE. When the T_DIODEtemperature is below T_CONTROL, fan speed can be at

minimum. As T_DIODEapproaches T_CONTROLplus the base value of 50 °C, fan speed should be

increased in an effort to maintain T_DIODEat/below T_CONTROLplus the base value of 50 °C. For

platforms that support this feature, the processor T_C-MAXspecification must be within guidelines,

as defined by the processor thermal specifications in Table 5-1. For 845G/x chipset platforms that

were not designed to read IA32_TEMPERATURE_TARGET MSR, the processor must be kept

within the T_C-MAXspecification.

5.2.6

Thermal Diode

The processor incorporates an on-die thermal diode. A thermal sensor located on the system board

may monitor the die temperature of the processor for thermal management/long term die

temperature change purposes. Table 5-2 and Table 5-3 provide the diode parameter and interface

specifications. This thermal diode is separate from the Thermal Monitor’s thermal sensor and

cannot be used to predict the behavior of the Thermal Monitor.

Table 5-2. Thermal Diode Parameters

Symbol

Parameter

Forward Bias Current

Min

Typ

Max

Unit

Notes

1

I

11

—

187

uA

—

Ω

FW

2,3,4

2,3,5

n

Diode Ideality Factor

Series Resistance

1.0083

3.242

1.011

3.33

1.0137

3.594

R

T

NOTES:

1. Intel does not support or recommend operation of the thermal diode under reverse bias.

2. Characterized at 75 °C.

3. Not 100% tested. Specified by design characterization.

4.

The ideality factor, n, represents the deviation from ideal diode behavior as exemplified by the diode equation:

qV_D/nkT

I

= I * (e

–1)

FW

S

where I = saturation current, q = electronic charge, V = voltage across the diode, k = Boltzmann Constant,

S

D

and T = absolute temperature (Kelvin).

5.

The series resistance, R_T, is provided to allow for a more accurate measurement of the junction temperature. R_T, as defined,

includes the pins of the processor but does not include any socket resistance or board trace resistance between the socket

and the external remote diode thermal sensor. R_Tcan be used by remote diode thermal sensors with automatic series re-

sistance cancellation to calibrate out this error term. Another application is that a temperature offset can be manually calcu-

lated and programmed into an offset register in the remote diode thermal sensors as exemplified by the equation:

T

= [R * (N-1) * I

] / [nk/q * ln N]

FWmin

error

T

where T

charge.

= sensor temperature error, N = sensor current ratio, k = Boltzmann Constant, q = electronic

error

Datasheet

67

Thermal Specifications and Design Considerations

Table 5-3. Thermal Diode Interface

Pin Name

Pin Number

Pin Description

THERMDA

THERMDC

B3

C4

diode anode

diode cathode

§

68

Datasheet

Features

6 Features

This chapter contains power-on configuration options and clock control/low power state

descriptions.

6.1

Power-On Configuration Options

Several configuration options can be configured by hardware. The Celeron D processor samples

the hardware configuration at reset, on the active-to-inactive transition of RESET#. For

specifications on these options, refer to Table 6-1.

The sampled information configures the processor for subsequent operation. These configuration

options cannot be changed except by another reset. All resets reconfigure the processor; for reset

purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.

Table 6-1. Power-On Configuration Option Pins

1_,2

Configuration Option

Output tristate

SMI#

Execute BIST

INIT#

In Order Queue pipelining (set IOQ depth to 1)

Disable MCERR# observation

Disable BINIT# observation

APIC Cluster ID (0-3)

Disable bus parking

A7#

A9#

A10#

A[12:11]#

A15#

BR0#

Symmetric agent arbitration ID

RESERVED

A[6:3]#, A8#, A[14:13]#, A[16:35]#

NOTES:

1. Asserting this signal during RESET# will select the corresponding option.

2. Address pins not identified in this table as configuration options should not be asserted

during RESET#.

6.2

Clock Control and Low Power States

The processor allows the use of AutoHALT, Stop-Grant, and Sleep states to reduce power

consumption by stopping the clock to internal sections of the processor, depending on each

particular state. See Figure 6-1 for a visual representation of the processor low power states.

6.2.1

Normal State—State 1

This is the normal operating state for the processor.

Datasheet

69

Features

6.2.2

AutoHALT Powerdown State—State 2

AutoHALT is a low power state entered when the processor executes the HALT instruction. The

processor will transition to the Normal state upon the occurrence of SMI#, BINIT#, INIT#, or

LINT[1:0] (NMI, INTR). RESET# will cause the processor to immediately initialize itself.

The return from a System Management Interrupt (SMI) handler can be to either Normal Mode or

the AutoHALT Power Down state. See the Intel Architecture Software Developer's Manual,

Volume III: System Programmer's Guide for more information.

The system can generate a STPCLK# while the processor is in the AutoHALT Power Down state.

When the system de-asserts the STPCLK# interrupt, the processor will return execution to the

HALT state.

While in AutoHALT Power Down state, the processor will process FSB snoops and interrupts.

Figure 6-1. Stop Clock State Machine

HALT Instruction and

HALT Bus Cycle Generated

2. Auto HALT Power Down State

BCLK running.

Snoops and interrupts allowed.

1. Normal State

Normal execution.

INIT#, BINIT#, INTR, NMI,

SMI#, RESET#

Snoop

Event

Occurs

Snoop

Event

Serviced

STPCLK#

Asserted

STPCLK#

De-asserted

3. Stop Grant State

BCLK running.

Snoops and interrupts allowed.

4. HALT/Grant Snoop State

BCLK running.

Service snoops to caches.

Snoop Event Occurs

Snoop Event Serviced

SLP#

Asserted

De-asserted

5. Sleep State

BCLK running.

No snoops or interrupts allowed.

70

Datasheet

Features

6.2.3

Stop-Grant State—State 3

When the STPCLK# pin is asserted, the Stop-Grant state of the processor is entered 20 bus clocks

after the response phase of the processor-issued Stop Grant Acknowledge special bus cycle.

Since the GTL+ signal pins receive power from the FSB, these pins should not be driven (allowing

the level to return to V_CC) for minimum power drawn by the termination resistors in this state. In

addition, all other input pins on the FSB should be driven to the inactive state.

BINIT# will not be serviced while the processor is in the Stop-Grant state. The event is latched and

can be serviced by software upon exit from the Stop Grant state.

RESET# causes the processor to immediately initialize itself, but the processor will stay in Stop-

Grant state. A transition back to the Normal state will occur with the de-assertion of the STPCLK#

signal. When re-entering the Stop Grant state from the Sleep state, STPCLK# should only be de-

asserted one or more bus clocks after the de-assertion of SLP#.

A transition to the HALT/Grant Snoop state occurs when the processor detects a snoop on the FSB

(see Section 6.2.4). A transition to the Sleep state (see Section 6.2.5) occurs with the assertion of

the SLP# signal.

While in the Stop-Grant state, SMI#, INIT#, BINIT# and LINT[1:0] are latched by the processor,

and only serviced when the processor returns to the Normal state. Only one occurrence of each

event will be recognized upon return to the Normal state.

While in Stop-Grant state, the processor processes snoops on the FSB and latches interrupts

delivered on the FSB.

The PBE# signal can be driven when the processor is in Stop-Grant state. PBE# is asserted if there

is any pending interrupt latched within the processor. Pending interrupts that are blocked by the

EFLAGS.IF bit being clear will still cause assertion of PBE#. Assertion of PBE# indicates to

system logic that it should return the processor to the Normal state.

6.2.4

HALT/Grant Snoop State—State 4

The processor responds to snoop or interrupt transactions on the FSB while in Stop-Grant state or

in AutoHALT Power Down state. During a snoop or interrupt transaction, the processor enters the

HALT/Grant Snoop state. The processor stays in this state until the snoop on the FSB has been

serviced (whether by the processor or another agent on the FSB) or the interrupt has been latched.

After the snoop is serviced or the interrupt is latched, the processor returns to the Stop-Grant state

or AutoHALT Power Down state, as appropriate.

Datasheet

71

Features

6.2.5

Sleep State—State 5

The Sleep state is a very low power state in which the processor maintains its context, maintains

the phase-locked loop (PLL), and has stopped all internal clocks. The Sleep state can only be

entered from Stop-Grant state. Once in the Stop-Grant state, the processor will enter the Sleep state

upon the assertion of the SLP# signal. The SLP# pin should only be asserted when the processor is

in the Stop Grant state. SLP# assertions while the processor is not in the Stop Grant state is out of

specification and may result in erroneous processor operation.

Snoop events that occur while in Sleep state or during a transition into or out of Sleep state will

cause unpredictable behavior.

In the Sleep state, the processor is incapable of responding to snoop transactions or latching

interrupt signals. No transitions or assertions of signals (with the exception of SLP# or RESET#)

are allowed on the FSB while the processor is in Sleep state. Any transition on an input signal

before the processor has returned to Stop-Grant state will result in unpredictable behavior.

If RESET# is driven active while the processor is in the Sleep state, and held active as specified in

the RESET# pin specification, then the processor will reset itself, ignoring the transition through

Stop-Grant state. If RESET# is driven active while the processor is in the Sleep state, the SLP# and

STPCLK# signals should be de-asserted immediately after RESET# is asserted to ensure the

processor correctly executes the reset sequence.

Once in the Sleep state, the SLP# pin must be de-asserted if another asynchronous FSB event needs

to occur. The SLP# pin has a minimum assertion of one BCLK period.

When the processor is in the Sleep state, it does not respond to interrupts or snoop transactions.

§

72

Datasheet

Boxed Processor Specifications

7 Boxed Processor Specifications

The Celeron D processor is also offered as a boxed Intel processor. Boxed Intel processors are

intended for system integrators who build systems from baseboards and standard components. The

boxed Celeron D processor will be supplied with a cooling solution. This chapter documents

baseboard and system requirements for the cooling solution that will be supplied with the boxed

Celeron D processor. This chapter is particularly important for OEMs that manufacture baseboards

for system integrators. Unless otherwise noted, all figures in this chapter are dimensioned in

millimeters and inches [in brackets]. Figure 7-1 shows a mechanical representation of a boxed

Celeron D processor.

• Drawings in this section reflect only the specifications on the boxed Intel processor product.

These dimensions should not be used as a generic keep-out zone for all cooling solutions. It is

the system designer's responsibility to consider their proprietary cooling solution when

designing to the required keep-out zone on their system platform and chassis. Refer to the

Intel^®Pentium 4 Processor on 90 nm Process Thermal Design Guidelines for further

guidance. Contact your local Intel Sales Representative for this document.

Figure 7-1. Mechanical Representation of the Boxed Intel^®Celeron^®D Processor

NOTE: The airflow of the fan heatsink is into the center and out of the sides of the fan heatsink.

Datasheet

73

Boxed Processor Specifications

7.1

Mechanical Specifications

7.1.1

Boxed Processor Cooling Solution Dimensions

This section documents the mechanical specifications of the boxed Celeron D processor. The

boxed processor will be shipped with an unattached fan heatsink. Figure 7-1 shows a mechanical

representation of the boxed Celeron D processor.

Clearance is required around the fan heatsink to ensure unimpeded airflow for proper cooling. The

physical space requirements and dimensions for the boxed processor with assembled fan heatsink

are shown in Figure 7-2 (Side Views), and Figure 7-3 (Top View). The airspace requirements for

the boxed processor fan heatsink must also be incorporated into new baseboard and system

designs. Airspace requirements are shown in Figure 7-6 and Figure 7-7. Note that some figures

have centerlines shown (marked with alphabetic designations) to clarify relative dimensioning.

Figure 7-2. Requirements for the Boxed Processor (Side View)

Figure 7-3. Space Requirements for the Boxed Processor (Top View)

74

Datasheet

Boxed Processor Specifications

7.1.2

Boxed Processor Fan Heatsink Weight

The boxed processor fan heatsink will not weigh more than 450 grams. See Chapter 5 and the

Intel^®Pentium 4 Processor on 90 nm Process Thermal Design Guidelines for details on the

processor weight and heatsink requirements.

Note: The processor retention mechanism based on the Intel reference design should be used, to ensure

compatibility with the heatsink attach clip assembly and the boxed processor thermal solution. The

heatsink attach clip assembly is latched to the retention tab features at each corner of the retention

mechanism.

The target load applied by the clips to the processor heat spreader for Intel's reference design is

75 ±15 lbf (maximum load is constrained by the package load capability). It is normal to observe a

bow or bend in the board due to this compressive load on the processor package and the socket.

The level of bow or bend depends on the motherboard material properties and component layout.

Any additional board stiffening devices (such as plates) are not necessary and should not be used

along with the reference mechanical components and boxed processor. Using such devices

increases the compressive load on the processor package and socket, likely beyond the maximum

load that is specified for those components. See the Intel^®Pentium 4 Processor on 90 nm Process

Thermal Design Guidelines for details on the Intel reference design.

Chassis that have adequate clearance between the motherboard and chassis wall (minimum

0.250 inch) should be selected to ensure the board's underside bend does not contact the chassis.

7.1.3

Boxed Processor Retention Mechanism and Heatsink

Attach Clip Assembly

The boxed processor thermal solution requires a processor retention mechanism and a heatsink

attach clip assembly, to secure the processor and fan heatsink in the baseboard socket. The boxed

processor will not ship with retention mechanisms but will ship with the heatsink attach clip

assembly. Baseboards designed for use by system integrators should include the retention

mechanism that supports the boxed Celeron D processor. Baseboard documentation should include

appropriate retention mechanism installation instructions.

Datasheet

75

Boxed Processor Specifications

7.2

Electrical Requirements

7.2.1

Fan Heatsink Power Supply

The boxed processor's fan heatsink requires a +12 V power supply. A fan power cable will be

shipped with the boxed processor to draw power from a power header on the baseboard. The power

cable connector and pinout are shown in Figure 7-4. Baseboards must provide a matched power

header to support the boxed processor. Table 7-1 contains specifications for the input and output

signals at the fan heatsink connector. The fan heatsink outputs a SENSE signal, which is an open-

collector output that pulses at a rate of 2 pulses per fan revolution. A baseboard pull-up resistor

provides V_OHto match the system board-mounted fan speed monitor requirements, if applicable.

Use of the SENSE signal is optional. If the SENSE signal is not used, pin 3 of the connector should

be tied to GND.

Note: The motherboard must supply a constant +12 V to the processor's power header to ensure proper

operation of the variable speed fan for the boxed processor.

The power header on the baseboard must be positioned to allow the fan heatsink power cable to

reach it. The power header identification and location should be documented in the platform

documentation, or on the system board itself. Figure 7-7 shows the location of the fan power

connector relative to the processor socket. The baseboard power header should be positioned

within 4.33 inches from the center of the processor socket.

Figure 7-4. Boxed Processor Fan Heatsink Power Cable Connector Description

1

Signal

GND

Straight square pin, 3-pin terminal housing with

polarizing ribs and friction locking ramp.

2

3

+12V

0.100" pin pitch, 0.025" square pin width.

SENSE

Waldom*/Molex* P/N 22-01-3037 or equivalent.

Match with straight pin, friction lock header on motherboard

Waldom/Molex P/N 22-23-2031, AMP* P/N 640456-3,

or equivalent.

1

2

3

Table 7-1. Fan Heatsink Power and Signal Specifications

Description

Min

Typ

Max

Unit

Notes

+12 V: 12 volt fan power supply

IC: Fan current draw

10.2

—

12

—

13.8

740

V

—

mA

pulses per fan

revolution

1

SENSE: SENSE frequency

—

2

—

NOTES:

1. Baseboard should pull this pin up to 5 V with a resistor.

76

Datasheet

Boxed Processor Specifications

Figure 7-5. Baseboard Power Header Placement Relative to Processor Socket

7.3

Thermal Specifications

This section describes the cooling requirements of the fan heatsink solution used by the boxed

processor.

7.3.1

Boxed Processor Cooling Requirements

The boxed processor may be directly cooled with a fan heatsink. However, meeting the processor's

temperature specification is also a function of the thermal design of the entire system, and

ultimately the responsibility of the system integrator. The processor temperature specification is

found in Chapter 5 of this document. The boxed processor fan heatsink is able to keep the

processor temperature within the specifications (see Table 5-1) in chassis that provide good

thermal management. For the boxed processor fan heatsink to operate properly, it is critical that the

airflow provided to the fan heatsink is unimpeded. Airflow of the fan heatsink is into the center and

out of the sides of the fan heatsink. Airspace is required around the fan to ensure that the airflow

through the fan heatsink is not blocked. Blocking the airflow to the fan heatsink reduces the

cooling efficiency and decreases fan life. Figure 7-6 and Figure 7-7 illustrate an acceptable

airspace clearance for the fan heatsink. The air temperature entering the fan is required to be at or

below 38 °C. Again, meeting the processor's temperature specification is the responsibility of the

system integrator.

Datasheet

77

Boxed Processor Specifications

Figure 7-6. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 1 View)

Figure 7-7. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)

78

Datasheet

Boxed Processor Specifications

7.3.2

Variable Speed Fan

The boxed processor fan operates at different speeds over a short range of internal chassis

temperatures. This allows the processor fan to operate at a lower speed and noise level, while

internal chassis temperatures are low. If internal chassis temperature increases beyond a lower set

point, the fan speed will rise linearly with the internal temperature until the higher set point is

reached. At that point, the fan speed is at its maximum. As fan speed increases, so does fan noise

levels. Systems should be designed to provide adequate air around the boxed processor fan

heatsink that remains below the lower set point. These set points, represented in Figure 7-8 and

Table 7-2, can vary by a few degrees from fan heatsink to fan heatsink. The internal chassis

temperature should be kept below 38 ºC. Meeting the processor's temperature specification

(see Chapter 5) is the responsibility of the system integrator.

Note: The motherboard must supply a constant +12 V to the processor's power header to ensure proper

operation of the variable speed fan for the boxed processor (refer to Table 7-1 for the specific

requirements).

Figure 7-8. Boxed Processor Fan Heatsink Set Points

Higher Set Point

Highest Noise Level

Increasing Fan

Speed & Noise

Lower Set Point

Lowest Noise Level

X

Y

Z

Internal Chassis Temperature (Degrees C)

Table 7-2. Boxed Processor Fan Heatsink Set Points

Boxed Processor Fan

Heatsink Set Point (ºC)

Boxed Processor Fan Speed

Notes

When the internal chassis temperature is below or equal to this set point,

the fan operates at its lowest speed. Recommended maximum internal

chassis temperature for nominal operating environment.

1

X ≤ 30 °C

When the internal chassis temperature is at this point, the fan operates

between its lowest and highest speeds. Recommended maximum

internal chassis temperature for worst-case operating environment.

Y = 34 °C

—

When the internal chassis temperature is above or equal to this set point,

the fan operates at its highest speed.

1

Z ≥ 38 °C

NOTES:

1. Set point variance is approximately ±1°C from fan heatsink to fan heatsink.

§

Datasheet

79

Boxed Processor Specifications

80

Datasheet

Debug Tools Specifications

8 Debug Tools Specifications

Refer to the ITP700 Debug Port Design Guide for information regarding debug tools

specifications. The ITP700 Debug Port Design Guide is located on http://developer.intel.com.

8.1

Logic Analyzer Interface (LAI)

Intel is working with two logic analyzer vendors to provide logic analyzer interfaces (LAIs) for use

in debugging Celeron D processor systems. Tektronix and Agilent should be contacted to obtain

specific information about their logic analyzer interfaces. The following information is general in

nature. Specific information must be obtained from the logic analyzer vendor.

Due to the complexity of Celeron D processor systems, the LAI is critical in providing the ability to

probe and capture FSB signals. There are two sets of considerations to keep in mind when

designing a Celeron D processor system that can make use of an LAI: mechanical and electrical.

8.1.1

Mechanical Considerations

The LAI is installed between the processor socket and the Celeron D processor. The LAI pins plug

into the socket, while the Celeron D processor pins plug into a socket on the LAI. Cabling that is

part of the LAI egresses the system to allow an electrical connection between the Celeron D

processor and a logic analyzer. The maximum volume occupied by the LAI, known as the keepout

volume, as well as the cable egress restrictions, should be obtained from the logic analyzer vendor.

System designers must make sure that the keepout volume remains unobstructed inside the system.

Note that it is possible that the keepout volume reserved for the LAI may differ from the space

normally occupied by the Celeron D processor heatsink. If this is the case, the logic analyzer

vendor will provide a cooling solution as part of the LAI.

8.1.2

Electrical Considerations

The LAI will also affect the electrical performance of the FSB; therefore, it is critical to obtain

electrical load models from each of the logic analyzers to be able to run system level simulations to

prove that their tool will work in the system. Contact the logic analyzer vendor for electrical

specifications and load models for the LAI solution they provide.

§

Datasheet

81

Debug Tools Specifications

82

Datasheet


型号：	NE80546RE072256
厂家：	Rochester Electronics
描述：	64-BIT, 2800 MHz, MICROPROCESSOR, CPGA478, FLIP CHIP, MICRO PGA-478 外围集成电路
文件：	总83页 (文件大小：2443K)
中文：	中文翻译
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NE80546RE072256 [ROCHESTER]

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