NTP85N03
更新时间:2024-09-18 18:34:44
品牌:ROCHESTER
描述:15A, 60V, 0.0068ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, CASE 221A-09, 3 PIN
NTP85N03 概述
15A, 60V, 0.0068ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, CASE 221A-09, 3 PIN 功率场效应晶体管
NTP85N03 规格参数
是否无铅: | 含铅 | 是否Rohs认证: | 不符合 |
生命周期: | Active | 零件包装代码: | TO-220AB |
包装说明: | CASE 221A-09, 3 PIN | 针数: | 3 |
Reach Compliance Code: | unknown | 风险等级: | 5.21 |
Is Samacsys: | N | 雪崩能效等级(Eas): | 61 mJ |
外壳连接: | DRAIN | 配置: | SINGLE WITH BUILT-IN DIODE |
最小漏源击穿电压: | 60 V | 最大漏极电流 (ID): | 15 A |
最大漏源导通电阻: | 0.0068 Ω | FET 技术: | METAL-OXIDE SEMICONDUCTOR |
JEDEC-95代码: | TO-220AB | JESD-30 代码: | R-PSFM-T3 |
JESD-609代码: | e0 | 湿度敏感等级: | NOT SPECIFIED |
元件数量: | 1 | 端子数量: | 3 |
工作模式: | ENHANCEMENT MODE | 封装主体材料: | PLASTIC/EPOXY |
封装形状: | RECTANGULAR | 封装形式: | FLANGE MOUNT |
峰值回流温度(摄氏度): | 240 | 极性/信道类型: | N-CHANNEL |
最大脉冲漏极电流 (IDM): | 45 A | 认证状态: | COMMERCIAL |
表面贴装: | NO | 端子面层: | TIN LEAD |
端子形式: | THROUGH-HOLE | 端子位置: | SINGLE |
处于峰值回流温度下的最长时间: | 30 | 晶体管应用: | SWITCHING |
晶体管元件材料: | SILICON | Base Number Matches: | 1 |
NTP85N03 数据手册
通过下载NTP85N03数据手册来全面了解它。这个PDF文档包含了所有必要的细节,如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载NTP85N03, NTB85N03
Power MOSFET
85 Amps, 28 Volts
N−Channel TO−220 and D2PAK
Designed for low voltage, high speed switching applications in
power supplies, converters and power motor controls and bridge
circuits.
http://onsemi.com
85 AMPERES, 28 VOLTS
RDS(on) = 6.1 mW (Typ)
Features
• Pb−Free Packages are Available
N−Channel
D
Typical Applications
• Power Supplies
• Converters
• Power Motor Controls
• Bridge Circuits
G
S
MAXIMUM RATINGS (T = 25°C unless otherwise noted)
J
4
Rating
Drain−to−Source Voltage
Gate−to−Source Voltage − Continuous
Drain Current
Symbol Value
Unit
Vdc
Vdc
V
28
DSS
4
V
"20
GS
1
2
3
− Continuous @ T = 25°C
2
I
85*
Adc
Apk
C
D
TO−220AB
CASE 221A
STYLE 5
D PAK
− Single Pulse (t = 10 ms)
p
I
190
DM
CASE 418AA
STYLE 2
1
2
Total Power Dissipation @ T = 25°C
P
80
W
W/°C
C
D
3
Derate above 25°C
0.66
Operating and Storage Temperature Range
T , T
−55 to
+150
°C
J
stg
MARKING DIAGRAMS
& PIN ASSIGNMENTS
Single Pulse Drain−to−Source Avalanche
E
733
mJ
AS
4
Energy − Starting T = 25°C
J
4
Drain
(V = 28 Vdc, V = 10 Vdc, L = 5.0 mH,
DD
GS
Drain
I
= 17 A, RG = 25 W)
L(pk)
Thermal Resistance,
− Junction−to−Case
°C/W
°C
NTx
85N03G
AYWW
R
R
1.55
70
q
JC
− Junction−to−Ambient (Note 1)
q
JA
NTx85N03G
AYWW
Maximum Lead Temperature for Soldering
Purposes, 1/8 in from case for 10 seconds
T
260
L
1
Gate
3
1
2
3
Maximum ratings are those values beyond which device damage can occur.
Maximum ratings applied to the device are individual stress limit values (not
normal operating conditions) and are not valid simultaneously. If these limits are
exceeded, device functional operation is not implied, damage may occur and
reliability may be affected.
Source
Gate Drain Source
2
Drain
*Chip current capability limited by package.
1. When surface mounted to an FR4 board using 1 in pad size, (Cu Area 1.127 in ).
NTx85N03 = Device Code
2
x
= B or P
A
Y
= Assembly Location
= Year
WW
G
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 2 of this data sheet.
©
Semiconductor Components Industries, LLC, 2005
1
Publication Order Number:
August, 2005 − Rev. 2
NTP85N03/D
NTP85N03, NTB85N03
ELECTRICAL CHARACTERISTICS (T = 25°C unless otherwise noted)
J
Characteristic
Symbol
Min
Typ
Max
Unit
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage (Note 2)
V
Vdc
(BR)DSS
28
−
30.6
25
−
−
(V = 0 Vdc, I = 250 mAdc)
GS
D
mV/°C
mAdc
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
I
I
DSS
−
−
−
−
1.0
10
(V = 28 Vdc, V = 0 Vdc)
DS
GS
(V = 28 Vdc, V = 0 Vdc, T = 150°C)
DS
GS
J
Gate−Body Leakage Current (V
=
20 Vdc, V = 0 Vdc)
−
−
100
nAdc
Vdc
GS
DS
GSS
ON CHARACTERISTICS (Note 2)
Gate Threshold Voltage (Note 2)
V
GS(th)
1.0
−
1.9
−3.8
3.0
−
(V = V , I = 250 mAdc)
Threshold Temperature Coefficient (Negative)
DS
GS
D
mV/°C
mW
Static Drain−to−Source On−Resistance (Note 2)
R
DS(on)
−
−
−
6.1
9.2
7.0
6.8
−
−
(V = 10 Vdc, I = 40 Adc)
GS
D
(V = 4.5 Vdc, I = 40 Adc)
GS
D
(V = 10 Vdc, I = 10 Adc)
GS
D
Forward Transconductance (Note 2) (V = 15 Vdc, I = 10 Adc)
g
FS
−
20
−
mhos
pF
DS
D
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
C
iss
−
−
−
2150
680
−
−
−
(V = 24 Vdc, V = 0 Vdc,
DS
GS
C
oss
f = 1.0 MHz)
C
rss
260
SWITCHING CHARACTERISTICS (Note 3)
Turn−On Delay Time
Rise Time
t
−
−
−
−
−
−
−
10
22
32
30
29
8.0
18
−
−
−
−
−
−
−
ns
d(on)
t
r
(V = 15 Vdc, I = 15 Adc,
DD
GS
D
V
= 10 Vdc, R = 3.3 W)
G
Turn−Off Delay Time
Fall Time
t
d(off)
t
f
Q
T
Q
1
Q
2
Gate Charge
nC
(V = 24 Vdc, I = 40 Adc,
DS
D
V
= 4.5 Vdc) (Note 2)
GS
SOURCE−DRAIN DIODE CHARACTERISTICS
Forward On−Voltage
(I = 2.3 Adc, V = 0 Vdc)
V
SD
−
−
−
0.75
1.2
0.65
1.0
−
−
Vdc
ns
S
GS
(I = 40 Adc, V = 0 Vdc) (Note 2)
S
GS
(I = 2.3 Adc, V = 0 Vdc, T = 150°C)
S
GS
J
t
−
−
−
−
39
21
−
−
−
−
Reverse Recovery Time
rr
(I = 2.3 Adc, V = 0 Vdc,
S
GS
t
a
dI /dt = 100 A/ms) (Note 2)
S
t
18
b
Reverse Recovery Stored Charge
Q
0.043
mC
RR
2. Pulse Test: Pulse Width ≤ 300 ms, Duty Cycle ≤ 2%.
3. Switching characteristics are independent of operating junction temperatures.
ORDERING INFORMATION
†
Device
Package
Shipping
NTP85N03
TO−220AB
50 Units / Rail
50 Units / Rail
NTP85N03G
TO−220AB
(Pb−Free)
2
NTB85N03
50 Units / Rail
50 Units / Rail
D PAK
2
NTB85N03G
D PAK
(Pb−Free)
2
NTB85N03T4
800 Units / Tape & Reel
800 Units / Tape & Reel
D PAK
2
NTB85N03T4G
D PAK
(Pb−Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
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2
NTP85N03, NTB85N03
50
40
30
80
3.8 V
V
≥ 10 V
DS
T = 25°C
J
V
8 V
6 V
= 10 V
GS
70
60
50
40
30
20
10
0
3.6 V
5 V
4.5 V
T = 25°C
J
3.4 V
3.2 V
20
10
0
4 V
T = 100°C
J
3 V
2.8 V
T = −55°C
J
0
1
2
3
4
5
2
3
4
5
6
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
Figure 1. On−Region Characteristics
Figure 2. Transfer Characteristics
0.07
0.015
0.01
0.005
0
T = 25°C
J
I
= 10 A
D
0.06
0.05
T = 25°C
J
V
V
= 4.5 V
= 10 V
GS
0.04
0.03
0.02
0.01
0
GS
0
2
4
6
8
10
5
10
15
20
30
V
, GATE−TO−SOURCE VOLTAGE (VOLTS)
GS
I , DRAIN CURRENT (AMPS)
D
Figure 3. On−Resistance versus
Gate−to−Source Voltage
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
1000
100
0.01
0.0075
0.005
0.0025
0
V
= 0 V
GS
I
V
= 40 A
D
= 10 V
DS
T = 125°C
J
T = 100°C
J
10
1
−50 −25
0
25
50
75
100
125
150
4
8
12
16
20
T , JUNCTION TEMPERATURE (°C)
J
V
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
DS
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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3
NTP85N03, NTB85N03
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted
by recognizing that the power MOSFET is charge
controlled. The lengths of various switching intervals (Dt)
are determined by how fast the FET input capacitance can
be charged by current from the generator.
The capacitance (C ) is read from the capacitance curve at
iss
a voltage corresponding to the off−state condition when
calculating t
and is read at a voltage corresponding to the
d(on)
on−state when calculating t
.
d(off)
At high switching speeds, parasitic circuit elements
complicate the analysis. The inductance of the MOSFET
source lead, inside the package and in the circuit wiring
which is common to both the drain and gate current paths,
produces a voltage at the source which reduces the gate drive
current. The voltage is determined by Ldi/dt, but since di/dt
is a function of drain current, the mathematical solution is
complex. The MOSFET output capacitance also
complicates the mathematics. And finally, MOSFETs have
finite internal gate resistance which effectively adds to the
resistance of the driving source, but the internal resistance
is difficult to measure and, consequently, is not specified.
The resistive switching time variation versus gate
resistance (Figure 9) shows how typical switching
performance is affected by the parasitic circuit elements. If
the parasitics were not present, the slope of the curves would
maintain a value of unity regardless of the switching speed.
The circuit used to obtain the data is constructed to minimize
common inductance in the drain and gate circuit loops and
is believed readily achievable with board mounted
components. Most power electronic loads are inductive; the
data in the figure is taken with a resistive load, which
approximates an optimally snubbed inductive load. Power
MOSFETs may be safely operated into an inductive load;
however, snubbing reduces switching losses.
The published capacitance data is difficult to use for
calculating rise and fall because drain−gate capacitance
varies greatly with applied voltage. Accordingly, gate
charge data is used. In most cases, a satisfactory estimate of
average input current (I
) can be made from a
G(AV)
rudimentary analysis of the drive circuit so that
t = Q/I
G(AV)
During the rise and fall time interval when switching a
resistive load, V remains virtually constant at a level
GS
known as the plateau voltage, V . Therefore, rise and fall
SGP
times may be approximated by the following:
t = Q x R /(V − V )
GSP
r
2
G
GG
t = Q x R /V
f
2
G
GSP
where
= the gate drive voltage, which varies from zero to V
V
GG
GG
R = the gate drive resistance
G
and Q and V
are read from the gate charge curve.
2
GSP
During the turn−on and turn−off delay times, gate current is
not constant. The simplest calculation uses appropriate
values from the capacitance curves in a standard equation for
voltage change in an RC network. The equations are:
t
t
= R C In [V /(V − V )]
G iss GG GG GSP
d(on)
d(off)
= R C In (V /V )
GG GSP
G
iss
5000
4500
4000
3500
3000
V
= 0
GS
T = 25°C
J
2500
2000
1500
1000
500
C
C
iss
oss
C
rss
0
−15
−10
−5
0
5
10
15
20
25
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
Figure 7. Capacitance Variation
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4
NTP85N03, NTB85N03
12
10
8
36
1000
V
I
V
= 24 V
= 20 A
= 10 V
DD
GS
t
d(off)
D
Q
30
24
18
12
6
T
t
f
V
DS
t
100
10
1
r
V
GS
6
t
Q
Q
d(on)
gs
gd
4
I
= 15
T = 25°C
D
2
J
0
0
30
0
5
10
15
20
25
1
10
100
R , GATE RESISTANCE (W)
G
Q , TOTAL GATE CHARGE (nC)
g
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
15
V
= 0 V
GS
T = 25°C
J
12
9
6
3
0
0.1
0.3
0.5
0.7
0.9
V
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
SD
Figure 10. Diode Forward Voltage versus Current
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define
the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and adjusted for operating conditions
differing from those specified. Although industry practice is
to rate in terms of energy, avalanche energy capability is not
a constant. The energy rating decreases non−linearly with an
increase of peak current in avalanche and peak junction
temperature.
junction temperature and a case temperature (T ) of 25°C.
C
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
Although many E−FETs can withstand the stress of
drain−to−source avalanche at currents up to rated pulsed
Switching between the off−state and the on−state may
traverse any load line provided neither rated peak current
current (I ), the energy rating is specified at rated
DM
(I ) nor rated voltage (V ) is exceeded and the
continuous current (I ), in accordance with industry custom.
DM
DSS
D
transition time (t ,t ) do not exceed 10 ms. In addition the total
power averaged over a complete switching cycle must not
The energy rating must be derated for temperature as shown
in the accompanying graph (Figure 12). Maximum energy at
r f
currents below rated continuous I can safely be assumed to
exceed (T
− T )/(R ).
D
J(MAX)
C qJC
equal the values indicated.
A Power MOSFET designated E−FET can be safely used
in switching circuits with unclamped inductive loads. For
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5
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
D2PAK
CASE 418AA−01
ISSUE O
NOTES:
C
1. DIMENSIONING AND TOLERANCING
PER ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
E
V
−B−
W
INCHES
DIM MIN MAX
MILLIMETERS
4
MIN
MAX
A
B
C
D
E
F
0.340 0.380
0.380 0.405
0.160 0.190
0.020 0.036
0.045 0.055
8.64
9.65 10.29
4.06
0.51
1.14
7.87
9.65
4.83
0.92
1.40
−−−
A
S
1
2
3
0.310
−−−
G
J
K
M
S
V
0.100 BSC
0.018 0.025
0.090 0.110
2.54 BSC
0.46
2.29
7.11
0.64
2.79
−−−
−T−
SEATING
PLANE
K
W
0.280
−−−
0.575 0.625 14.60 15.88
0.045 0.055 1.14 1.40
J
G
STYLE 2:
PIN 1. GATE
D 3 PL
M
M
0.13 (0.005)
T B
2. DRAIN
3. SOURCE
4. DRAIN
VARIABLE
CONFIGURATION
ZONE
U
M
M
M
F
F
F
VIEW W−W
1
VIEW W−W
2
VIEW W−W
3
SOLDERING FOOTPRINT*
8.38
0.33
1.016
0.04
10.66
0.42
5.08
0.20
3.05
0.12
17.02
0.67
mm
inches
ǒ
Ǔ
SCALE 3:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
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6
NTP85N03, NTB85N03
PACKAGE DIMENSIONS
TO−220
CASE 221A−09
ISSUE AA
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
SEATING
PLANE
−T−
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION Z DEFINES A ZONE WHERE ALL
BODY AND LEAD IRREGULARITIES ARE
ALLOWED.
C
S
B
F
T
4
INCHES
DIM MIN MAX
MILLIMETERS
MIN
14.48
9.66
4.07
0.64
3.61
2.42
2.80
0.46
12.70
1.15
4.83
2.54
2.04
1.15
5.97
0.00
1.15
−−−
MAX
15.75
10.28
4.82
0.88
3.73
2.66
3.93
0.64
14.27
1.52
5.33
3.04
2.79
1.39
6.47
1.27
−−−
A
K
Q
Z
A
B
C
D
F
0.570
0.380
0.160
0.025
0.142
0.095
0.110
0.018
0.500
0.045
0.190
0.100
0.080
0.045
0.235
0.000
0.045
0.620
0.405
0.190
0.035
0.147
0.105
0.155
0.025
0.562
0.060
0.210
0.120
0.110
0.055
0.255
0.050
−−−
1
2
3
U
H
G
H
J
K
L
L
R
J
N
Q
R
S
T
V
G
D
U
V
Z
N
−−− 0.080
2.04
STYLE 5:
PIN 1. GATE
2. DRAIN
3. SOURCE
4. DRAIN
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights
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Phone: 81−3−5773−3850
For additional information, please contact your
local Sales Representative.
NTP85N03/D
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NTP8G206N | ONSEMI | Power GaN Cascode Transistor | 获取价格 | |
NTP8G206NG | ONSEMI | Power GaN Cascode Transistor | 获取价格 | |
NTP8N50 | ONSEMI | 8A, 500V, 0.75ohm, N-CHANNEL, Si, POWER, MOSFET, TO-220AB, CASE 221A-09, 3 PIN | 获取价格 | |
NTP8N50 | MOTOROLA | Power Field-Effect Transistor, 8A I(D), 500V, 0.75ohm, 1-Element, N-Channel, Silicon, Metal-oxide Semiconductor FET, TO-220AB, CASE 221A-09, 3 PIN | 获取价格 | |
NTP8N50/D | ETC | Power MOSFET 8 Amps, 500 Volts | 获取价格 |
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