PRIXP420BC [ROCHESTER]
32-BIT, 533 MHz, RISC PROCESSOR, PBGA492, LEAD FREE, PLASTIC, BGA-492;
| 型号： | PRIXP420BC |
| 厂家： | 
Rochester Electronics |
| 描述： | 32-BIT, 533 MHz, RISC PROCESSOR, PBGA492, LEAD FREE, PLASTIC, BGA-492 时钟 外围集成电路 |
| 文件： | 总131页 (文件大小：2924K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane
Processor
Datasheet
Product Features
For a complete list of product features, see “Product Features” on page 12.
The following features do
not require enabling
software:
The following features do
require enabling software:
Encryption/Authentication
Intel XScale® Processor — Up to 533
(AES,DES,3DES,SHA-1,MD5)
Two High-Speed, Serial Interfaces
Three Network Processor Engines
Up to two MII Interfaces
MHz
PCI Interface
USB v1.1 Device Controller
SDRAM Interface
High-Speed UART
Console UART
One UTOPIA Level 2 Interface
Multi-Channel HDLC
Note: Refer to the Intel® IXP400 Software
Programmer’s Guide for information on
which features are currently enabled.
Internal Bus Performance Monitoring
Unit
16 GPIOs
Four Internal Timers
Packaging
— 492-pin PBGA
Commercial/Extended Temperature
Typical Applications
High-Performance DSL Modem
High-Performance Cable Modem
Residential Gateway
SME Router
Control Plane
Integrated Access Device (IAD)
Set-Top Box
Access Points (802.11a/b/g)
Industrial Controllers
Network Printers
Document Number: 252479-006US
August 2006
Legal Lines and Disclaimers
INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL® PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR
OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN INTEL'S TERMS AND CONDITIONS
OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY, RELATING
TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE,
MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for
use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.
Intel may make changes to specifications and product descriptions at any time, without notice.
Intel Corporation may have patents or pending patent applications, trademarks, copyrights, or other intellectual property rights that relate to the
presented subject matter. The furnishing of documents and other materials and information does not provide any license, express or implied, by estoppel
or otherwise, to any such patents, trademarks, copyrights, or other intellectual property rights.
Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for
future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.
Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across different
processor families. See http://www.intel.com/products/processor_number for details.
The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor may contain design defects or errors known as errata which
may cause the product to deviate from published specifications. Current characterized errata are available on request.
Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.
Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling
1-800-548-4725 or by visiting Intel's website at http://www.intel.com.
BunnyPeople, Celeron, Chips, Dialogic, EtherExpress, ETOX, FlashFile, i386, i486, i960, iCOMP, InstantIP, Intel, Intel Centrino, Intel Centrino logo, Intel
logo, Intel386, Intel486, Intel740, IntelDX2, IntelDX4, IntelSX2, Intel Inside, Intel Inside logo, Intel NetBurst, Intel NetMerge, Intel NetStructure, Intel
SingleDriver, Intel SpeedStep, Intel StrataFlash, Intel Xeon, Intel XScale, IPLink, Itanium, MCS, MMX, MMX logo, Optimizer logo, OverDrive, Paragon,
PDCharm, Pentium, Pentium II Xeon, Pentium III Xeon, Performance at Your Command, Sound Mark, The Computer Inside., The Journey Inside, VTune,
and Xircom are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries.
*Other names and brands may be claimed as the property of others.
Copyright © 2006, Intel Corporation. All Rights Reserved.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Contents
1.0 Introduction............................................................................................................ 11
1.1
1.2
About this Document ......................................................................................... 11
Product Features............................................................................................... 12
1.2.1 Product Line Features ............................................................................. 12
1.2.2 Processor Features ................................................................................. 15
2.0 Functional Overview................................................................................................ 16
2.1
Functional Units ................................................................................................ 20
2.1.1 Network Processor Engines (NPEs)............................................................ 20
2.1.2 Internal Bus .......................................................................................... 22
2.1.2.1 North AHB ............................................................................... 22
2.1.2.2 South AHB............................................................................... 22
2.1.2.3 APB Bus .................................................................................. 22
2.1.3 MII Interfaces........................................................................................ 23
2.1.4 UTOPIA Level 2...................................................................................... 23
2.1.5 USB Interface ........................................................................................ 23
2.1.6 PCI Controller........................................................................................ 24
2.1.7 SDRAM Controller................................................................................... 24
2.1.8 Expansion Bus ....................................................................................... 24
2.1.9 High-Speed, Serial Interfaces................................................................... 25
2.1.10 High-Speed and Console UARTs ............................................................... 25
2.1.11 GPIO .................................................................................................... 25
2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..................................... 25
2.1.13 Interrupt Controller ................................................................................ 26
2.1.14 Timers.................................................................................................. 26
2.1.15 AHB Queue Manager............................................................................... 26
Intel XScale® Processor ..................................................................................... 26
2.2.1 Super Pipeline........................................................................................ 27
2.2.2 Branch Target Buffer (BTB)...................................................................... 28
2.2.3 Instruction Memory Management Unit (IMMU)............................................ 29
2.2.4 Data Memory Management Unit (DMMU) ................................................... 29
2.2.5 Instruction Cache (I-Cache)..................................................................... 29
2.2.6 Data Cache (D-Cache) ............................................................................ 30
2.2.7 Mini-Data Cache..................................................................................... 30
2.2.8 Fill Buffer (FB) and Pend Buffer (PB) ......................................................... 31
2.2.9 Write Buffer (WB)................................................................................... 31
2.2.10 Multiply-Accumulate Coprocessor (CP0)..................................................... 31
2.2.11 Performance Monitoring Unit (PMU) .......................................................... 32
2.2.12 Debug Unit............................................................................................ 32
2.2
3.0 Functional Signal Descriptions................................................................................. 32
3.1 Pin Description Tables........................................................................................ 34
4.0 Package and Pinout Information ............................................................................. 49
4.1
4.2
4.3
Package Description .......................................................................................... 49
Signal-Pin Descriptions....................................................................................... 51
Package Thermal Specifications........................................................................... 78
4.3.1 Commercial Temperature ........................................................................ 79
4.3.2 Extended Temperature............................................................................ 79
5.0 Electrical Specifications........................................................................................... 79
5.1
5.2
Absolute Maximum Ratings................................................................................. 79
VCCPLL1, VCCPLL2, VCCOSCP, VCCOSC Pin Requirements .............................................. 80
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5.2.1 VCCPLL1 Requirement...............................................................................80
5.2.2 VCCPLL2 Requirement...............................................................................80
5.2.3
VCCOSCP Requirement..............................................................................81
5.2.4 VCCOSC Requirement ...............................................................................81
RCOMP Pin Requirements....................................................................................82
DC Specifications...............................................................................................83
5.4.1 Operating Conditions...............................................................................83
5.4.2 PCI DC Parameters .................................................................................83
5.4.3 USB DC Parameters ................................................................................83
5.4.4 UTOPIA Level 2 DC Parameters.................................................................84
5.4.5 MII DC Parameters .................................................................................84
5.4.6 MDIO DC Parameters ..............................................................................84
5.4.7 SDRAM Bus DC Parameters......................................................................85
5.4.8 Expansion Bus DC Parameters..................................................................85
5.4.9 High-Speed, Serial Interface 0 DC Parameters............................................86
5.4.10 High-Speed, Serial Interface 1 DC Parameters............................................86
5.4.11 High-Speed and Console UART DC Parameters............................................86
5.4.12 GPIO DC Parameters...............................................................................87
5.4.13 JTAG AND PLL_LOCK DC Parameters .........................................................87
5.4.14 Reset DC Parameters ..............................................................................87
AC Specifications ...............................................................................................88
5.5.1 Clock Signal Timings ...............................................................................88
5.5.1.1 Processor Clock Timings.............................................................88
5.5.1.2 PCI Clock Timings .....................................................................89
5.5.1.3 MII Clock Timings......................................................................89
5.5.1.4 UTOPIA Level 2 Clock Timings.....................................................90
5.5.1.5 Expansion Bus Clock Timings ......................................................90
5.5.2 Bus Signal Timings..................................................................................90
5.5.2.1 PCI..........................................................................................90
5.5.2.2 USB Interface ...........................................................................92
5.5.2.3 UTOPIA Level 2 (33 MHz) ...........................................................92
5.5.2.4 MII..........................................................................................93
5.5.2.5 MDIO.......................................................................................94
5.5.2.6 SDRAM Bus ..............................................................................95
5.5.2.7 Expansion Bus ..........................................................................97
5.5.2.8 High-Speed, Serial Interfaces....................................................122
5.5.2.9 JTAG .....................................................................................123
5.5.3 Reset Timings ......................................................................................124
5.5.3.1 Cold Reset..............................................................................124
5.5.3.2 Hardware Warm Reset .............................................................125
5.5.3.3 Soft Reset..............................................................................125
5.5.3.4 Reset Timings.........................................................................126
Power Sequence..............................................................................................127
ICC and Total Average Power .............................................................................128
5.3
5.4
5.5
5.6
5.7
6.0 Ordering Information.............................................................................................130
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Intel® IXP42X product line and IXC1100 control plane processors
Figures
1
2
3
4
5
6
7
8
9
Intel® IXP425 Network Processor Block Diagram.......................................................... 17
Intel® IXP423 Network Processor Block Diagram.......................................................... 18
Intel® IXP422 Network Processor Block Diagram.......................................................... 19
Intel® IXP421 Network Processor Block Diagram.......................................................... 19
Intel® IXP420 Network Processor Block Diagram.......................................................... 20
Intel XScale® Technology Block Diagram..................................................................... 27
492-Pin Lead PBGA Package...................................................................................... 49
Package Markings .................................................................................................... 50
VCCPLL1 Power Filtering Diagram................................................................................. 80
10 VCCPLL2 Power Filtering Diagram................................................................................. 81
11 VCCOSCP Power Filtering Diagram................................................................................ 81
12 VCCOSC Power Filtering Diagram ................................................................................. 82
13 RCOMP Pin External Resistor Requirements ................................................................. 82
14 Typical Connection to an Oscillator ............................................................................. 89
15 PCI Output Timing.................................................................................................... 90
16 PCI Input Timing...................................................................................................... 91
17 UTOPIA Level 2 Input Timings.................................................................................... 92
18 UTOPIA Level 2 Output Timings ................................................................................. 92
19 MII Output Timings .................................................................................................. 93
20 MII Input Timings .................................................................................................... 94
21 MDIO Output Timings ............................................................................................... 94
22 MDIO Input Timings ................................................................................................. 95
23 SDRAM Input Timings............................................................................................... 95
24 SDRAM Output Timings............................................................................................. 96
25 Signal Timing With Respect to Clock Rising Edge .......................................................... 97
26 Intel® Multiplexed Read Mode.................................................................................... 98
27 Intel® Multiplexed Write Mode ................................................................................... 99
28 Intel® Simplex Read Mode ...................................................................................... 101
29 Intel® Simplex Write Mode...................................................................................... 102
30 Motorola* Multiplexed Read Mode ............................................................................ 104
31 Motorola* Multiplexed Write Mode............................................................................ 105
32 Motorola* Simplex Read Mode ................................................................................. 106
33 Motorola* Simplex Write Mode................................................................................. 107
34 HPI-8 Mode Read Accesses...................................................................................... 109
35 HPI-8 Mode Write Accesses ..................................................................................... 110
36 HPI-16 Multiplexed Write Mode ................................................................................ 113
37 HPI-16 Multiplex Read Mode.................................................................................... 115
38 HPI-16 Simplex Read Mode ..................................................................................... 117
39 HPI-16 Simplex Write Mode..................................................................................... 119
40 I/O Wait Normal Phase Timing................................................................................. 120
41 I/O Wait Extended Phase Timing.............................................................................. 121
42 High-Speed, Serial Timings ..................................................................................... 122
43 Boundary-Scan General Timings .............................................................................. 123
44 Boundary-Scan Reset Timings.................................................................................. 124
45 Reset Timings........................................................................................................ 126
46 Power-Up Sequence Timing..................................................................................... 128
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Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Tables
1
2
3
4
5
6
7
8
9
Related Documents...................................................................................................11
Terminology and Acronyms........................................................................................11
Processor Features ...................................................................................................15
Processor Functions ..................................................................................................21
Signal Type Definitions..............................................................................................33
Processors’ Signal Interface Summary Table ................................................................33
SDRAM Interface......................................................................................................34
PCI Controller ..........................................................................................................36
High-Speed, Serial Interface 0 ...................................................................................38
10 High-Speed, Serial Interface 1 ...................................................................................39
11 MII Interfaces..........................................................................................................40
12 UTOPIA Level 2 Interface...........................................................................................42
13 Expansion Bus Interface............................................................................................44
14 UART Interfaces .......................................................................................................45
15 USB Interface ..........................................................................................................45
17 GPIO Interface.........................................................................................................46
18 JTAG Interface .........................................................................................................46
16 Oscillator Interface ...................................................................................................46
19 System Interface†† ..................................................................................................47
20 Power Interface........................................................................................................48
21 Part Numbers for the Intel® IXP42X Product Line of Network Processors ..........................50
22 Ball Map Assignment for the Intel® IXP425 Network Processor........................................51
23 Ball Map Assignment for the Intel® IXP422 Network Processor........................................58
24 Ball Map Assignment for the Intel® IXP421 Network Processor........................................65
25 Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor ................................................................72
26 Operating Conditions ................................................................................................83
27 PCI DC Parameters...................................................................................................83
28 USB v1.1 DC Parameters...........................................................................................83
29 UTOPIA Level 2 DC Parameters ..................................................................................84
30 MII DC Parameters ...................................................................................................84
31 MDIO DC Parameters................................................................................................84
32 SDRAM Bus DC Parameters........................................................................................85
33 Expansion Bus DC Parameters....................................................................................85
34 High-Speed, Serial Interface 0 DC Parameters..............................................................86
35 High-Speed, Serial Interface 1 DC Parameters..............................................................86
36 UART DC Parameters ................................................................................................86
37 GPIO DC Parameters.................................................................................................87
38 JTAG AND PLL_LOCK DC Parameters @ 3.3V................................................................87
39 PWRON_RESET_N DC Parameters...............................................................................87
40 RESET_IN_N Parameters @ 3.3V................................................................................88
41 Devices’ Clock Timings (Oscillator Reference)...............................................................88
42 Processors’ Clock Timings Spread Spectrum Parameters ................................................88
43 PCI Clock Timings.....................................................................................................89
44 MII Clock Timings.....................................................................................................89
45 UTOPIA Level 2 Clock Timings....................................................................................90
46 Expansion Bus Clock Timings .....................................................................................90
47 PCI Bus Signal Timings..............................................................................................91
48 UTOPIA Level 2 Input Timings Values..........................................................................92
49 UTOPIA Level 2 Output Timings Values........................................................................93
50 MII Output Timings Values.........................................................................................93
51 MII Input Timings Values...........................................................................................94
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52 MDIO Timings Values................................................................................................ 95
53 SDRAM Input Timings Values..................................................................................... 95
54 SDRAM Output Timings Values................................................................................... 96
55 Signal Timing With Respect to Clock Rising Edge .......................................................... 97
56 Intel® Multiplexed Mode Values................................................................................ 100
57 Intel Simplex Mode Values ...................................................................................... 103
58 Motorola* Multiplexed Mode Values .......................................................................... 105
59 Motorola* Simplex Mode Values............................................................................... 107
60 HPI Timing Symbol Description ................................................................................ 111
61 HPI-8 Mode Write Access Values .............................................................................. 111
62 HPI-16 Multiplexed Write Accesses Values................................................................. 112
63 HPI-16 Multiplexed Read Accesses Values.................................................................. 114
64 HPI-16 Simplex Read Accesses Values ...................................................................... 116
65 HPI-16 Simplex Write Accesses Values...................................................................... 118
66 High-Speed, Serial Timing Values............................................................................. 123
67 Boundary-Scan Interface Timings Values................................................................... 124
68 Reset Timings Table Parameters .............................................................................. 127
69 ICC and Total Average Power – Commercial Temperature Range................................... 128
70 ICC and Total Average Power – Extended Temperature Range ...................................... 129
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Revision History
Date
Revision
Description
1.
Table 3, Table 21: Added the FWIXP423BD, 533MHz
IXP423
2.
3.
4.
Clarified GPIO functions in Section 2.1.11
Updated Pin Types in Table 11 and Table 12
Added Section 3.1 to help explain the tables outlined in
Table 6
Modified some signals in Table 8 through Table 17 to be
pulled up when unused in new designs. No change to
existing designs.
5.
6.
Updated Power on Reset or Sys Reset column values in
Table 17 and Table 19
Table 21: Removed the IXC1100
August 2006
006
7.
8.
Corrected the maximum Talepulse value in Table 55
Clarified ordering information in Section 6.0
Updated Intel® product branding. References to Intel
XScale core were updated to Intel XScale Processor.
Incorporated specification changes, specification
clarifications and document changes from the Intel®
IXP4XX Product Line of Network Processors Specification
Update (306428-004)
9.
10.
11.
1.
2.
3.
4.
5.
6.
7.
8.
Rearranged product features lists in Section 1.2, “Product
Features”
Added two new columns to Table 3 to indicate Software
Enable/Disable, and IXP423 network processor features
Replaced network processor block diagrams: Figure 1,
Figure 2, Figure 3, Figure 4, and Figure 5
Added new row for the IXP423 network processor to
Table 4, “Processor Functions”
Corrected the PCI_IDSEL definition in Table 8, “PCI
Controller”
Added pull-up resistor requirement for the ETH_MDIO pin
in Table 11, “MII Interfaces”
Added footnote to Table 19, “System Interface††”
regarding system level reset
Added part number for IXP423 on Table 21, “Part
Numbers for the Intel® IXP42X Product Line of Network
Processors”
Added note 4 to Table 27, “PCI DC Parameters”
Changed VIH “Minimum” parameter to 2.0 in Table 28,
“USB v1.1 DC Parameters” (see the Intel® IXP4XX
Product Line of Network Processors Specification Update
(306428)); added note 2
9.
10.
March 2005
005
11.
12.
Added new paragraph to Section 5.5.1.1, “Processor
Clock Timings” regarding crystal oscillators application
Added footnote regarding PLL operation at the lowest
slew rate to Table 41, “Devices’ Clock Timings (Oscillator
Reference)”
13.
14.
Added footnote to Table 51, “MII Input Timings Values”
and Table 52, “MDIO Timings Values”
Inserted new Figure 25, “Signal Timing With Respect to
Clock Rising Edge”
15.
16.
Replaced Expansion Bus figures: Figure 25–Figure 39
Updated Table 55, “Signal Timing With Respect to Clock
Rising Edge”
17.
18.
19.
Updated Trdsetup and Trdhold values in Table 56,
Table 57, Table 58 and Table 59
Added footnotes to Table 63, “HPI-16 Multiplexed Read
Accesses Values”
Replaced Table 69, “ICC and Total Average Power –
Commercial Temperature Range” , and inserted new
Table 70, “ICC and Total Average Power – Extended
Temperature Range”
Updated Intel® product branding. Change bars are retained from
the previous release of this document (-003).
June 2004
004
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Date
Revision
Description
Incorporated specification changes, specification clarifications and
document changes from the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor
Specification Update (252702-003).
April 2004
003
Incorporated specification changes, specification clarifications and
document changes from the Intel® IXP42X Product Line of
Network Processors Specification Update (252702-001).
May 2003
002
001
Incorporated information for the Intel® IXC1100 Control Plane
Processor.
Initial release of this document. Document reissued, without
“Confidential” marking.
February 2003
§ §
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Datasheet
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Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
1.0
Introduction
1.1
About this Document
This datasheet contains a functional overview of the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor, as well as mechanical data
(package signal locations and simulated thermal characteristics), targeted electrical
specifications, and some bus functional wave forms for the device. Detailed functional
descriptions — other than parametric performance — are published in the Intel®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
Other related documents are shown in Table 1.
Table 1.
Related Documents
Document Title
Document #
Intel® IXP4XX Product Line of Network Processors Specification Update
306428
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual
252480
Intel® IXP400 Software Programmer’s Guide
Intel® IXP400 Software Specification Update
Intel XScale® Core Developer’s Manual
252539
273795
273473
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Hardware Design Guidelines
252817
Intel XScale® Microarchitecture Technical Summary
PCI Local Bus Specification, Rev. 2.2
—
—
—
Universal Serial Bus Specification, Revision 1.1
Table 2.
Terminology and Acronyms
Acronym/
Description
Terminology
AAL
AES
ATM Adaptation Layers
Advanced Encryption Standard
Advanced High-Performance Bus
Advanced Peripheral Bus
AHB
APB
API
Application Program Interface
The logically active value of a signal or bit.
Asynchronous Transmission Mode
AHB Queue Manager
Assert
ATM
AQM
BTB
Branch Target Buffer
CRC
Cyclical Redundancy Check
The logically inactive value of a signal or bit.
Double Data Rate
Deassert
DDR
DES
Data-Encryption Standard
Direct Memory Access
DMA
DSP
Digital Signal Processor
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Table 2.
Terminology and Acronyms (Continued)
Acronym/
Terminology
Description
E1
FIFO
GCI
Euro 1 trunk line
First In First Out
General Circuit Interface
General-purpose input/output
High-level Data Link Control
GPIO
HDLC
HPI
(Texas Instruments*) Host Port Interfaces
High-Speed Serial (port)
HSS
LSb
Least-Significant bit
LSB
Least-Significant Byte
MAC
MDIO
MII
Media Access Controller
Management Data Input/Output
Media-Independent Interface
Memory Management Unit
Most-Significant bit
MMU
MSb
MSB
NPE
PCI
Most-Significant Byte
Network Processor Engine
Peripheral Component Interconnect
Physical Layer (Layer 1) Interface
PHY
A field that may be used by an implementation. Software should not modify reserved
fields or depend on any values in reserved fields.
Reserved
RX
SRAM
SDRAM
T1
Receive (HSS is receiving from off-chip)
Static Random Access Memory
Synchronous Dynamic Random Access Memory
Type 1 trunk line
TX
Transmit (HSS is transmitting off-chip)
Universal Asynchronous Receiver-Transmitter
Universal Serial Bus
UART
USB
UTOPIA
WAN
Universal Test and Operations PHY Interface for ATM
Wide Area Network
1.2
Product Features
1.2.1
Product Line Features
This section outlines the features that apply to the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor
Some of the features described in this document require enablement by software
delivered by Intel. Some features may not be enabled with current software releases.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
The features that require software are identified below. Please refer to the Intel®
IXP400 Software Programmer’s Guide for information on which features are enabled at
this time.
• Intel XScale® Processor (compliant with ARM* architecture)
— High-performance processor based on Intel XScale® Microarchitecture
— Seven/eight-stage Intel® Super-Pipelined RISC Technology
— Management unit
• 32-entry, data memory management unit
• 32-entry, instruction memory management unit
• 32-Kbyte, 32-way, set associative instruction cache
• 32-Kbyte, 32-way, set associative data cache
• 2-Kbyte, two-way, set associative mini-data cache
• 128-entry, branch target buffer
• Eight-entry write buffer
• Four-entry fill and pend buffers
— Clock speeds:
• 266 MHz
• 400 MHz
• 533 MHz
— ARM* Version V5TE Compliant
— Intel® Media Processing Technology
Multiply-accumulate coprocessor
— Debug unit
Accessible through JTAG port
• PCI interface
— 32-bit interface
— Selectable clock
• 33 MHz clock output derived from either GPIO14 or GPIO15
• 33 and 66 MHz clock input
— PCI Local Bus Specification, Rev. 2.2 compatible
— PCI arbiter supporting up to four external PCI devices (four REQ/GNT pairs)
— Host/option capable
— Master/target capable
— Two DMA channels
• USB v 1.1 device controller
— Full-speed capable
— Embedded transceiver
— 16 endpoints
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Intel® IXP42X product line and IXC1100 control plane processors
• SDRAM interface
— 32-bit data
— 13-bit address
— 133 MHz
— Up to eight open pages simultaneously maintained
— Programmable auto-refresh
— Programmable CAS/data delay
— Support for 8 MB, minimum, up to 256 MB maximum
• Expansion interface
— 24-bit address
— 16-bit data
— Eight programmable chip selects
— Supports Intel/Motorola* microprocessors
• Multiplexed-style bus cycles
• Simplex-style bus cycles
• DSP support for:
— Texas Instruments* DSPs supporting HPI-8 bus cycles
• Texas Instruments DSPs supporting HPI-16 bus cycles
• High-speed/Console UARTs
— 1,200 baud to 921 Kbaud
— 16550 compliant
— 64-byte Tx and Rx FIFOs
— CTS and RTS modem control signals
• Internal bus performance monitoring unit
— Seven 27-bit event counters
— Monitoring of internal bus occurrences and duration events
• 16 GPIOs
• Four internal timers
• Packaging
— 492-pin PBGA
— Commercial temperature (0° to +70° C)
— Extended temperature (-40° to +85° C)
The remaining features described in the product line features list require software in
order for these features to be functional. To determine if the feature is enabled, see the
Intel® IXP400 Software Programmer’s Guide.
• Three network processor engines (NPEs) Note 1
Used to offload typical Layer-2 networking functions such as:
— Ethernet filtering
— ATM SARing
— HDLC
Note 1
• Encryption/Authentication/Hashing
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— DES
— Triple-DES (3DES)
— AES 128-bit and 256-bit
— ARC4/WEP-CRC
— SHA-1
— MD5
Note 1
• Two MII interfaces
— 802.3 MII interfaces
— Single MDIO interface to control both MII interfaces
• UTOPIA Level 2 Interface Note 1
— Eight-bit interface
— Up to 33 MHz clock speed
— Five transmit and five receive address lines
Note 1
• Two high-speed, serial interfaces
— Six-wire
— Supports speeds up to 8.192 MHz
— Supports connection to T1/E1 framers
— Supports connection to CODEC/SLICs
— Eight HDLC Channels
Note:
This feature requires Intel supplied software. To determine if this feature is enabled by
a particular software release, see the Intel® IXP400 Software Programmer’s Guide.
1.2.2
Processor Features
Table 3 on page 15 describes the features that apply to the Intel® IXP42X Product Line
of Network Processors and IXC1100 Control Plane Processor.
Table 3.
Processor Features (Sheet 1 of 2)
Intel®
IXC1100
Control
Plane
Requires
Enabling
Software
(Note 1)
Intel®
IXP425
Network
Processor
Intel®
IXP423
Network
Processor
Intel®
IXP422
Network
Processor
Intel®
IXP421
Network
Processor
Intel®
IXP420
Network
Processor
Feature
Processor
Processor
Speed (MHz)
266/400/533
266/533
266
266
266/400/533
266/400/533
UTOPIA 2
GPIO
Yes
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
UART 0/1
HSS 0
Yes
Yes
Yes
Yes
HSS 1
MII 0
X
X
X
X
X
X
MII 1
Notes:
1.
The features marked “Yes” require enabling software. Please refer to the Intel® IXP400 Software Programmer’s Guide to
determine if the feature is enabled.
2.
Only the 266 MHz version of the Intel® IXP420 Network Processor supports extended temperature.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Table 3.
Processor Features (Sheet 2 of 2)
Intel®
IXC1100
Control
Plane
Requires
Enabling
Software
(Note 1)
Intel®
IXP425
Network
Processor
Intel®
IXP423
Network
Processor
Intel®
IXP422
Network
Processor
Intel®
IXP421
Network
Processor
Intel®
IXP420
Network
Processor
Feature
Processor
USB
PCI
X
X
X
X
X
X
X
X
X
X
X
X
Expansion
Bus
16-bit, 66 MHz 16-bit, 66 MHz 16-bit, 66 MHz 16-bit, 66 MHz 16-bit, 66 MHz 16-bit, 66 MHz
32-bit, 133
MHz
32-bit, 133
MHz
32-bit, 133
MHz
32-bit, 133
MHz
32-bit, 133
MHz
32-bit, 133
MHz
SDRAM
AES / DES /
3DES
Yes
Yes
Yes
X
8
X
Multi-
Channel
HDLC
8
X
8
X
SHA-1 /
MD-5
X
X
X
X
X
Commercial
Temperature
X
X
X
Extended
Temperature
X (Note 2)
Notes:
1.
The features marked “Yes” require enabling software. Please refer to the Intel® IXP400 Software Programmer’s Guide to
determine if the feature is enabled.
2.
Only the 266 MHz version of the Intel® IXP420 Network Processor supports extended temperature.
2.0
Functional Overview
The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor are compliant with the ARM* Version 5TE instruction-set architecture (ISA).
The Intel® IXP42X product line and IXC1100 control plane processors are designed
with Intel 0.18-micron production semiconductor process technology. This process
technology — along with the compactness of the Intel XScale® processor, the ability to
simultaneously process up to three integrated network processing engines (NPEs), and
numerous dedicated-function peripheral interfaces — enables the IXP42X product line
and IXC1100 control plane processors to operate over a wide range of low-cost
networking applications, with industry-leading performance.
As indicated in Figure 1 through Figure 5, the Intel® IXP42X product line and IXC1100
control plane processors combine many features with the Intel XScale® Processor to
create a highly integrated processor applicable to LAN/WAN-based networking
applications in addition to other embedded networking applications.
This section briefly describes the main features of the product. For detailed functional
descriptions, see the Intel® IXP42X Product Line of Network Processors and IXC1100
Control Plane Processor Developer’s Manual.
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 1.
Intel® IXP425 Network Processor Block Diagram
HSS-0
UTOPIA 2
WAN/Voice NPE
UTOPIA
(Max 24 xDSL PHYs)
AAL, HSS, HDLC
MII-0
MII-1
Ethernet
NPE A
Ethernet MAC
133.32 MHz x 32 bits North Advance High-Performance Bus
Ethernet
NPE B
Queue Status Bus
Ethernet MAC
SHA-1/MD5,
DES/3DES, AES
North AHB
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
North/South
AHB Bridge
South AHB
Arbiter
UART
921Kbaud Controller
Interrupt
Timers
AHB/APB
Bridge
66.66 MHz Advanced Peripheral Bus
133.32 MHz x 32 bits South Advance High-Performance Bus
USB
Device
V1.1
UART
921Kbaud
PMU
(AHB)
GPIO
Controller
Intel XScalefi Processor
266/400/533 MHz
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Expansion
Bus
Controller
PCI
Controller
Test Logic
Unit
B1563-04
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 2.
Intel® IXP423 Network Processor Block Diagram
HSS-0
UTOPIA-2
WAN/Voice NPE
UTOPIA
(Max 24 xDSL PHYs)
AAL, HSS, HDLC
MII-0
MII-1
Ethernet
NPE A
Ethernet MAC
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet
NPE B
Ethernet MAC
North AHB
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
North/South
AHB Bridge
South AHB
Arbiter
UART
921Kbaud Controller
Interrupt
Timers
AHB/APB
Bridge
66.66 MHz Advanced Peripheral Bus
133.32 MHz x 32 bits South Advance High-Performance Bus
USB
Device
V1.1
UART
921Kbaud
PMU
(AHB)
GPIO
Controller
Intel XScalefi Processor
266/533 MHz
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Expansion
Bus
Controller
PCI
Controller
Test Logic
Unit
B4285-02
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 3.
Intel® IXP422 Network Processor Block Diagram
MII-0
MII-1
Ethernet
NPE A
Ethernet MAC
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet
NPE B
Ethernet MAC
SHA-1/MD5,
DES, 3DES, AES
North AHB
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
North/South
AHB Bridge
South AHB
Arbiter
UART
921Kbaud Controller
Interrupt
Timers
AHB/APB
Bridge
66.66 MHz Advanced Peripheral Bus
133.32 MHz x 32 bits South Advance High-Performance Bus
USB
Device
V1.1
UART
921Kbaud
PMU
(AHB)
GPIO
Controller
fi
Intel XScale Processor
266/533 MHz
Expansion
Bus
Controller
PCI
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Test Logic
Unit
B1566-04
Figure 4.
Intel® IXP421 Network Processor Block Diagram
HSS-0
UTOPIA 2
WAN/Voice NPE
UTOPIA
(Max 4 xDSL PHYs)
AAL, HSS
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet
NPE A
Ethernet MAC
MII-0
North AHB
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
North/South
AHB Bridge
South AHB
Arbiter
UART
921Kbaud Controller
Interrupt
Timers
AHB/APB
Bridge
66.66 MHz Advanced Peripheral Bus
133.32 MHz x 32 bits South Advance High-Performance Bus
USB
Device
V1.1
UART
921Kbaud
PMU
(AHB)
GPIO
Controller
266 MHz
fi
Intel XScale Processor
Expansion
Bus
Controller
PCI
Controller
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Test Logic
Unit
B1565-04
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Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 5.
Intel® IXP420 Network Processor Block Diagram
MII-0
MII-1
Ethernet
NPE A
Ethernet MAC
133.32 MHz x 32 bits North Advance High-Performance Bus
Queue Status Bus
Ethernet
NPE B
Ethernet MAC
North AHB
Arbiter
Queue
Manager
8 KB SRAM
SDRAM
Controller
8 - 256 MB
32-Bit
North/South
AHB Bridge
South AHB
Arbiter
UART
921Kbaud Controller
Interrupt
Timers
AHB/APB
Bridge
66.66 MHz Advanced Peripheral Bus
133.32 MHz x 32 bits South Advance High-Performance Bus
USB
Device
V1.1
UART
921Kbaud
PMU
(AHB)
GPIO
Controller
fi
Intel XScale Processor
266/400/533 MHz
32 KB Data Cache
32 KB Instruction Cache
2 KB Mini-Data Cache
Expansion
Bus
Controller
PCI
Controller
Test Logic
Unit
B1564-04
2.1
Functional Units
The following sections briefly the functional units and their interaction in the system.
For more detailed information, refer to the Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane Processor Developer’s Manual.
Unless otherwise specified, the functional descriptions apply to all processors in the
IXP42X product line and IXC1100 control plane processors. Refer to Table 3 on page 15
and Figure 1 on page 17 through Figure 5 for specific information on supported
interfaces.
2.1.1
Network Processor Engines (NPEs)
The network processor engines (NPEs) are dedicated-function processors containing
hardware coprocessors integrated into the IXP42X product line and IXC1100 control
plane processors. The NPEs are used to off-load processing functions required by the
Intel XScale® processor.
These NPEs are high-performance, hardware-multi-threaded processors with additional
local-hardware-assist functionality used to off-load highly processor-intensive functions
such as MII (MAC), CRC checking/generation, AAL segmentation and re-assembly, AES,
DES, 3DES, SHA-1, and MD5. All instruction code for the NPEs are stored locally with a
dedicated instruction memory bus and dedicated data memory bus.
These NPEs support processing of the dedicated peripherals that can include:
• A Universal Test and Operation PHY Interface for ATM (UTOPIA) 2 interface
• Two High-Speed Serial (HSS) interfaces
• Two Media-Independent Interfaces (MII)
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Table 4 specifies which devices, in the IXP42X product line and IXC1100 control plane
processors, have which of these capabilities.
Table 4.
Processor Functions
Multi-
Channel
HDLC
AES / DES
/ 3DES
SHA-1 /
MD-5
Device
UTOPIA HSS MII 0 MII 1
Intel® IXP425 Network
Processor
X
X
X
X
X
X
X
X
X
X
X
X
X
8
8
X
Intel® IXP423 Network
Processor
Intel® IXP422 Network
Processor
X
X
Intel® IXP421 Network
Processor
X
X
8
Intel® IXP420 Network
Processor
X
X
Intel® IXC1100
Control Plane
Processor
X
The NPE is a hardware-multi-threaded processor engine that is used to accelerate
functions that are difficult to achieve high performance in a standard RISC processor.
Each NPE is a 133.32 MHz (which is 4 * OSC_IN input pin) processor core that has self-
contained instruction memory and self-contained data memory that operate in parallel.
In addition to having separate instruction/data memory and local-code store, the NPE
supports hardware multi-threading with support for multiple contexts. The support of
hardware multi-threading creates an efficient processor engine with minimal processor
stalls due to the ability of the processor to switch contexts in a single clock cycle, based
on a prioritized/preemptive basis. The prioritized/preemptive nature of the context
switching allows time-critical applications to be implemented in a low-latency fashion —
which is required when processing multi-media applications.
The NPE also connects several hardware-based coprocessors that are used to
implement functions that are difficult for a processor to implement. These functions
include:
• Serialization/De-
serialization
• CRC checking/generation
• DES/3DES/AES
• MD5
• SHA-1
• HDLC bit stuffing/de-
stuffing
These coprocessors are implemented in hardware, enabling the coprocessors and the
NPE processor core to operate in parallel.
The combined forces of the hardware multi-threading, local-code store, independent
instruction memory, independent data memory, and parallel processing allows the Intel
XScale® processor to be utilized for application purposes. The multi-processing
capability of the peripheral interface functions allows unparalleled performance to be
achieved by the application running on the Intel XScale® processor.
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Intel® IXP42X product line and IXC1100 control plane processors
2.1.2
Internal Bus
The internal bus architecture of the IXP42X product line and IXC1100 control plane
processors is designed to allow parallel processing to occur and to isolate bus
utilization, based on particular traffic patterns. The bus is segmented into three major
buses: the North AHB, South AHB, and APB.
2.1.2.1
North AHB
The North AHB is a 133.32 MHz, 32-bit bus that can be mastered by the NPEs. The
targets of the North AHB can be the SDRAM or the AHB/AHB bridge. The AHB/AHB
bridge allows the NPEs to access the peripherals and internal targets on the South AHB.
Data transfers by the NPEs on the North AHB to the South AHB are targeted
predominately to the queue manager. Transfers to the AHB/AHB bridge may be
“posted,” when writing, or “split,” when reading.
When a transaction is “posted,” a master on the North AHB requests a write to a
peripheral on the South AHB. If the AHB/AHB Bridge has a free FIFO location, the write
request will be transferred from the master on the North AHB to the AHB/AHB bridge.
The AHB/AHB bridge will complete the write on the South AHB, when it can obtain
access to the peripheral on the South AHB. The North AHB is released to complete
another transaction.
When a transaction is “split,” a master on the North AHB requests a read of a peripheral
on the South AHB. If the AHB/AHB bridge has a free FIFO location, the read request will
be transferred from the master on the North AHB to the AHB/AHB bridge. The AHB/AHB
bridge will complete the read on the South AHB, when it can obtain access to the
peripheral on the South AHB.
Once the AHB/AHB bridge has obtained the read information from the peripheral on the
South AHB, the AHB/AHB bridge notifies the arbiter, on the North AHB, that the AHB/
AHB bridge has the data for the master that requested the “split” transfer. The master
on the North AHB — that requested the split transfer — will arbitrate for the North AHB
and transfer the read data from the AHB/AHB bridge. The North AHB is released to
complete another transaction while the North AHB master — that requested the “split”
transfer — waits for the data to arrive.
These “posting” and “splitting” transfers allow control of the North AHB to be given to
another master on the North AHB — enabling the North AHB to achieve maximum
efficiency. Transfers to the AHB/AHB bridge are considered to be small and infrequent,
relative to the traffic passed between the NPEs on the North AHB and the SDRAM.
2.1.2.2
2.1.2.3
South AHB
The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale®
processor, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus
can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB
bridge.
Accessing across the APB/AHB bridge allows interfacing to peripherals attached to the
APB.
APB Bus
The APB Bus is a 66.66 MHz (which is 2 * OSC_IN input pin.), 32-bit bus that can be
mastered by the AHB/APB bridge only. The targets of the APB bus can be:
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• High-speed UART interface
• USB v1.1 interface
• Console UART interface
• All NPEs
• Internal bus performance monitoring
unit (IBPMU)
• Interrupt controller
• GPIO
• Timers
The APB interface is also used as an alternate-path interface to the NPEs and is used
for NPE code download and configuration.
2.1.3
2.1.4
2.1.5
MII Interfaces
Two industry-standard, media-independent interface (MII) interfaces are integrated
into most of the IXP42X product line and IXC1100 control plane processors with
separate media-access controllers and independent network processing engines. (See
Table 4 on page 21.)
The independent NPEs and MACs allow parallel processing of data traffic on the MII
interfaces and off-loading of processing required by the Intel XScale® processor. The
IXP42X product line and IXC1100 control plane processors are compliant with the IEEE,
802.3 specification.
In addition to two MII interfaces, the IXP42X product line and IXC1100 control plane
processors include a single management data interface that is used to configure and
control PHY devices that are connected to the MII interface.
UTOPIA Level 2
The integrated, UTOPIA Level 2 interface works with a network processing engine, for
several of the IXP42X product line and IXC1100 control plane processors. (See Table 4
on page 21.)
The UTOPIA Level 2 interface supports a single- or a multiple-physical-interface
configuration with cell-level or octet-level handshaking. The network processing engine
handles segmentation and reassembly of ATM cells, CRC checking/generation, and
transfer of data to/from memory. This allows parallel processing of data traffic on the
UTOPIA Level 2 interface, off-loading processor overhead required by the Intel XScale®
processor.
The IXP42X product line and IXC1100 control plane processors are compliant with the
ATM Forum, UTOPIA Level-2 Specification, Revision 1.0.
USB Interface
The integrated USB 1.1 interface is a device-only controller. The interface supports full-
speed operation and 16 endpoints and includes an integrated transceiver.
There are:
• Six isochronous endpoints (three input and three output)
• One control endpoints
• Three interrupt endpoints
• Six bulk endpoints (three input and three output)
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Intel® IXP42X product line and IXC1100 control plane processors
2.1.6
2.1.7
PCI Controller
The IXP42X product line and IXC1100 control plane processors’ PCI controller is
compatible with the PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit
compatible bus and capable of operating as either a host or an option (i.e., not the
Host) For more information on PCI Controller support and configuration see the Intel®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Developer’s Manual.
SDRAM Controller
The memory controller manages the interface to external SDRAM memory chips. The
interface:
• Operates at 133.32 MHz (which is 4 * OSC_IN input pin.)
• Supports eight open pages simultaneously
• Has two banks to support memory configurations from 8 Mbyte to 256 Mbyte
The memory controller only supports 32-bit memory. If a x16 memory chip is used, a
minimum of two memory chips would be required to facilitate the 32-bit interface
required by the IXP42X product line and IXC1100 control plane processors. A maximum
of four SDRAM memory chips may be attached to the processors. For more information
on SDRAM support and configuration see the Intel® IXP42X Product Line of Network
Processors and IXC1100 Control Plane Processor Developer’s Manual.
The memory controller internally interfaces to the North AHB and South AHB with
independent interfaces. This architecture allows SDRAM transfers to be interleaved and
pipelined to achieve maximum possible efficiency.
The maximum burst size supported to the SDRAM interface is eight 32-bit words. This
burst size allows the best efficiency/fairness performance between accesses from the
North AHB and the South AHB.
2.1.8
Expansion Bus
The expansion interface allows easy and — in most cases — glue-less connection to
peripheral devices. It also provides input information for device configuration after
reset. Some of the peripheral device types are flash, ATM control interfaces, and DSPs
used for voice applications. (Some voice configurations can be supported by the HSS
interfaces and the Intel XScale® processor, implementing voice-compression
algorithms.)
The expansion bus interface is a 16-bit interface that allows an address range of
512 bytes to 16 Mbytes, using 24 address lines for each of the eight independent chip
selects.
Accesses to the expansion bus interface consists of five phases. Each of the five phases
can be lengthened or shortened by setting various configuration registers on a per-
chip-select basis. This feature allows the IXP42X product line and IXC1100 control
plane processors to connect to a wide variety of peripheral devices with varying speeds.
The expansion bus interface supports Intel or Motorola* microprocessor-style bus
cycles. The bus cycles can be configured to be multiplexed address/data cycles or
separate address/data cycles for each of the eight chip-selects.
Additionally, Chip Selects 4 through 7 can be configured to support Texas Instruments
HPI-8 or HPI-16 style accesses for DSPs.
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The expansion bus interface is an asynchronous interface to externally connected
chips. However, a clock must be supplied to the IXP42X product line and IXC1100
control plane processors’ expansion bus interface for the interface to operate. This
clock can be driven from GPIO 15 or an external source. The maximum clock rate that
the expansion bus interface can accept is 66.66 MHz.
At the de-assertion of reset, the 24-bit address bus is used to capture configuration
information from the levels that are applied to the pins at this time. External pull-up/
pull-down resistors are used to tie the signals to particular logic levels. For additional
details, refer to Section 8 (Expansion Bus Controller) of the Intel® IXP42X Product Line
of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.)
2.1.9
High-Speed, Serial Interfaces
The high-speed, serial interfaces are six-signal interfaces that support serial transfer
speeds from 512 KHz to 8.192 MHz, for some models of the IXP42X product line and
IXC1100 control plane processors. (See Table 4 on page 21.)
Each interface allows direct connection of up to four T1/E1 framers and CODEC/SLICs
to the IXP42X product line and IXC1100 control plane processors. The high-speed,
serial interfaces are capable of supporting various protocols, based on the
implementation of the code developed for the network processor engine. For a list of
supported protocols, see the Intel® IXP400 Software Programmer’s Guide.
2.1.10
High-Speed and Console UARTs
The UART interfaces are 16550-compliant UARTs with the exception of transmit and
receive buffers. Transmit and receive buffers are 64 bytes-deep versus the 16 bytes
required by the 16550 UART specification.
The interface can be configured to support speeds from 1,200 baud to 921 Kbaud. The
interface support configurations of:
• Five, six, seven, or eight data-bit transfers
• One or two stop bits
• Even, odd, or no parity
The request-to-send (RTS_N) and clear-to-send (CTS_N) modem control signals also
are available with the interface for hardware flow control.
2.1.11
GPIO
16 GPIO pins are supported by the IXP42X product line and IXC1100 control plane
processors. GPIO pins 0 through 15 can be configured to be general-purpose input or
general-purpose output. Additionally, GPIO pins 0 through 12 can be configured to be
an interrupt input.
GPIO Pin 14 and GPIO 15 can also be configured as a clock output. The output-clock
configuration can be set at various speeds, up to 33.33 MHz, with various duty cycles.
GPIO Pin 14 is configured as an input, upon reset. GPIO Pin 15 is configured as an
output, upon reset. GPIO Pin 15 can be used to clock the expansion interface, after
reset.
2.1.12
Internal Bus Performance Monitoring Unit (IBPMU)
The IXP42X product line and IXC1100 control plane processors consists of seven 27-bit
counters that may be used to capture predefined durations or occurrence events on the
North AHB, South AHB, or SDRAM controller page hits/misses.
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2.1.13
Interrupt Controller
The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt
sources to allow an extension of the Intel XScale® processor FIQ and IRQ interrupt
sources. These sources can originate from some external GPIO pins or internal
peripheral interfaces.
The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled.
The interrupt sources tied to Interrupt 0 to 7 can be prioritized. The remaining
interrupts are prioritized in ascending order. For example, Interrupt 8 has a higher
priority than 9, 9 has a higher priority than 10, and 30 has a higher priority that 31.
2.1.14
2.1.15
Timers
The IXP42X product line and IXC1100 control plane processors consists of four internal
timers operating at 66.66 MHz (which is 2 * OSC_IN input pin.) to allow task
scheduling and prevent software lock-ups. The device has four 32-bit counters:
• Watch-Dog Timer
• Timestamp Timer
• Two general-purpose
timers
AHB Queue Manager
The AHB Queue Manager (AQM) provides queue functionality for various internal
blocks. It maintains the queues as circular buffers in an embedded 8KB SRAM. It also
implements the status flags and pointers required for each queue.
The AQM manages 64 independent queues. Each queue is configurable for buffer and
entry size. Additionally status flags are maintained for each queue.
The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the
NPEs and Intel XScale® processor (or any other AHB bus master), a Flag Bus interface,
an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale®
processor. The AHB interface is used for configuration of the AQM and provides access
to queues, queue status and SRAM. Individual queue status for queues 0-31 is
communicated to the NPEs via the flag bus. Combined queue status for queues 32-63
are communicated to the NPEs via the event bus. The two interrupts, one for queues 0-
31 and one for queues 32-63, provide status interrupts to the Intel XScale® processor.
2.2
Intel XScale® Processor
The Intel XScale technology is compliant with the ARM* Version 5TE instruction-set
architecture (ISA). The Intel XScale® processor, shown in Figure 6, is designed with
Intel 0.18-micron production semiconductor process technology. This process
technology enables the Intel XScale® processor to operate over a wide speed and
power range, producing industry-leading mW/MIPS performance.
Intel XScale® processor features include:
• Seven/eight-stage super-pipeline promotes high-speed, efficient processor
performance
• 128-entry branch target buffer keeps pipeline filled with statistically correct branch
choices
• 32-entry instruction memory-management unit for logical-to-physical address
translation, access permissions, I-cache attributes
• 32-entry data-memory management unit for logical-to-physical address
translation, access permissions, D-cache attributes
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• 32-Kbyte instruction cache can hold entire programs, preventing processor stalls
caused by multi-cycle memory accesses
• 32-Kbyte data cache reduces processor stalls caused by multi-cycle memory
accesses
• 2-Kbyte mini-data cache for frequently changing data streams avoids “thrashing”
of the D-cache
• Four-entry fill-and-pend buffers to promote processor efficiency by allowing “hit-
under-miss” operation with data caches
• Eight-entry write buffer allows the processor to continue execution while data is
written to memory
• Multiple-accumulate coprocessor that can do two simultaneous, 16-bit, SIMD
multiplies with 40-bit accumulation for efficient, high-quality media and signal
processing
• Performance monitoring unit (PMU) furnishing two 32-bit event counters and one
32-bit cycle counter for analysis of hit rates, etc.
This PMU is for the Intel XScale® processor only. An additional PMU is supplied for
monitoring of internal bus performance.
• JTAG debug unit that uses hardware break points and 256-entry trace history
buffer (for flow-change messages) to debug programs
Figure 6.
Intel XScale® Technology Block Diagram
Branch Target Cache
FIQ
Interrupt
Request
IRQ
M
M
U
Instruction Cache
32 KB
Instruction
South
AHB
Bus
Execution
Core
Data Cache
32 KB
Data
Address
M
M
U
Coprocessor Interface
Mini-Data Cache
2 KB
Data
Multiply
Accumulate
System
Management
Debug/
PMU
JTAG
A9568-02
2.2.1
Super Pipeline
The super pipeline is composed of integer, multiply-accumulate (MAC), and memory
pipes.
The integer pipe has seven stages:
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• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
• Integer Writeback
The memory pipe has eight stages:
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
. . . then finish with the following memory stages:
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
The MAC pipe has six to nine stages:
• The first four stages of the Integer pipe (BTB/Fetch 1 through Register File/ Shift)
. . . then finish with the following MAC stages:
• MAC 1
• MAC 2
• MAC 3
• MAC 4
• Data Cache Writeback
The MAC pipe supports a data-dependent early terminate where stages MAC 2, MAC 3,
and/or MAC 4 are bypassed.
Deep pipes promote high instruction execution rates only when a means exists to
successfully predict the outcome of branch instructions. The branch target buffer
provides such a means.
2.2.2
Branch Target Buffer (BTB)
Each entry of the 128-entry BTB contains the address of a branch instruction, the
target address associated with the branch instruction, and a previous history of the
branch being taken or not taken. The history is recorded as one of four states:
• Strongly
taken
• Weakly taken
• Weakly not
taken
• Strongly not taken
The BTB can be enabled or disabled via Coprocessor 15, Register 1.
When the address of the branch instruction hits in the BTB and its history is strongly or
weakly taken, the instruction at the branch target address is fetched. When its history
is strongly or weakly not-taken, the next sequential instruction is fetched. In either
case the history is updated.
Data associated with a branch instruction enters the BTB the first time the branch is
taken. This data enters the BTB in a slot with a history of strongly not-taken
(overwriting previous data when present).
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Successfully predicted branches avoid any branch-latency penalties in the super
pipeline. Unsuccessfully predicted branches result in a four to five cycle branch-latency
penalty in the super pipeline.
2.2.3
Instruction Memory Management Unit (IMMU)
For instruction pre-fetches, the IMMU controls logical-to-physical address translation,
memory access permissions, memory-domain identifications, and attributes (governing
operation of the instruction cache). The IMMU contains a 32-entry, fully associative
instruction-translation, look-aside buffer (ITLB) that has a round-robin replacement
policy. ITLB entries zero through 30 can be locked.
When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic
table-walk mechanism that fetches an associated descriptor from memory and loads it
into the ITLB. The descriptor contains information for logical-to-physical address
translation, memory-access permissions, memory-domain identifications, and
attributes governing operation of the I-cache. The IMMU then continues the instruction
pre-fetch by using the address translation just entered into the ITLB. When an
instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch using the
address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When
an instruction pre-fetch is attempted to an area of memory in violation of access
permissions, the attempt is aborted and a pre-fetch abort is sent to the Intel XScale®
processor for exception processing. The IMMU and DMMU can be enabled or disabled
together.
2.2.4
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory-
access permissions, memory-domain identifications, and attributes (governing
operation of the data cache or mini-data cache and write buffer). The DMMU contains a
32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-
robin replacement policy. DTLB entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the
DTLB. The descriptor contains information for logical-to-physical address translation,
memory-access permissions, memory-domain identifications, and attributes (governing
operation of the D-cache or mini-data cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into
the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the
address translation already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a
data fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a data abort is sent to the Intel XScale® processor for exception
processing.
The IMMU and DMMU can be enabled or disabled together.
2.2.5
Instruction Cache (I-Cache)
The I-cache can contain high-use, multiple-code segments or entire programs, allowing
the Intel XScale® processor access to instructions at core frequencies. This prevents
processor stalls caused by multi-cycle accesses to external memory.
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The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways
and each way contains a tag address, a cache line of instructions (eight 32-bit words
and one parity bit per word), and a line-valid bit. For each of the 32 sets, 0 through
28 ways can be locked. Unlocked ways are replaceable via a round-robin policy.
The I-cache can be enabled or disabled. Attribute bits within the descriptors —
contained in the ITLB of the IMMU — provide some control over an enabled I-cache.
When a needed line (eight 32-bit words) is not present in the I-cache, the line is
fetched (critical word first) from memory via a two-level, deep-fetch queue. The fetch
queue allows the next instruction to be accessed from the I-cache, but only when its
data operands do not depend on the execution results of the instruction being fetched
via the queue.
2.2.6
Data Cache (D-Cache)
The D-cache can contain high-use data such as lookup tables and filter coefficients,
allowing the Intel XScale® processor access to data at core frequencies. This prevents
processor stalls caused by multi-cycle accesses to external memory.
The 32-Kbyte D-cache is 32-set/32-way associative, where each set contains 32 ways
and each way contains a tag address, a cache line (32 bytes with one parity bit per
byte) of data, two dirty bits (one for each of two eight-byte groupings in a line), and
one valid bit. For each of the 32 sets, zero through 28 ways can be locked, unlocked,
or used as local SRAM. Unlocked ways are replaceable via a round-robin policy.
The D-cache (together with the mini-data cache) can be enabled or disabled. Attribute
bits within the descriptors, contained in the DTLB of the DMMU, provide significant
control over an enabled D-cache. These bits specify cache operating modes such as
read and write allocate, write-back, write-through, and D-cache versus mini-data cache
targeting.
The D-cache (and mini-data cache) work with the load buffer and pend buffer to
provide “hit-under-miss” capability that allows the Intel XScale® processor to access
other data in the cache after a “miss” is encountered. The D-cache (and mini-data
cache) works in conjunction with the write buffer for data that is to be stored to
memory.
2.2.7
Mini-Data Cache
The mini-data cache can contain frequently changing data streams such as MPEG
video, allowing the Intel XScale® processor access to data streams at core frequencies.
This prevents processor stalls caused by multi-cycle accesses to external memory. The
mini-data cache relieves the D-cache of data “thrashing” caused by frequently
changing data streams.
The 2-Kbyte, mini-data cache is 32-set/two-way associative, where each set contains
two ways and each way contains a tag address, a cache line (32 bytes with one parity
bit per byte) of data, two dirty bits (one for each of two eight-byte groupings in a line),
and a valid bit. The mini-data cache uses a round-robin replacement policy, and cannot
be locked.
The mini-data cache (together with the D-cache) can be enabled or disabled. Attribute
bits contained within a coprocessor register specify operating modes write and/or read
allocate, write-back, and write-through.
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The mini-data cache (and D-cache) work with the load buffer and pend buffer to
provide “hit-under-miss” capability that allows the Intel XScale® processor to access
other data in the cache after a “miss” is encountered. The mini-data cache (and D-
cache) works in conjunction with the write buffer for data that is to be stored to
memory.
2.2.8
Fill Buffer (FB) and Pend Buffer (PB)
The four-entry fill buffer (FB) works with the Intel XScale® processor to hold non-
cacheable loads until the bus controller can act on them. The FB and the four-entry
pend buffer (PB) work with the D-cache and mini-data cache to provide “hit-under-
miss” capability, allowing the Intel XScale® processor to seek other data in the caches
while “miss” data is being fetched from memory.
The FB can contain up to four unique “miss” addresses (logical), allowing four “misses”
before the processor is stalled. The PB holds up to four addresses (logical) for
additional “misses” to those addresses that are already in the FB. A coprocessor
register can specify draining of the fill and pend (write) buffers.
2.2.9
Write Buffer (WB)
The write buffer (WB) holds data for storage to memory until the bus controller can act
on it. The WB is eight entries deep, where each entry holds 16 bytes. The WB is
constantly enabled and accepts data from the Intel XScale® processor, D-cache, or
mini-data cache.
Coprocessor 15, Register 1 specifies whether WB coalescing is enabled or disabled.
When coalescing is disabled, stores to memory occur in program order regardless of
the attribute bits within the descriptors located in the DTLB. When coalescing is
enabled, the attribute bits within the descriptors located in the DTLB are examined to
determine when coalescing is enabled for the destination region of memory. When
coalescing is enabled in both CP15, R1 and the DTLB, data entering the WB can
coalesce with any of the eight entries (16 bytes) and be stored to the destination
memory region, but possibly out of program order.
Stores to a memory region specified to be non-cacheable and non-bufferable by the
attribute bits within the descriptors located in the DTLB causes the processor to stall
until the store completes. A coprocessor register can specify draining of the write
buffer.
2.2.10
Multiply-Accumulate Coprocessor (CP0)
For efficient processing of high-quality, media-and-signal-processing algorithms, CP0
provides 40-bit accumulation of 16 x 16, dual-16 x 16 (SIMD), and 32 x 32 signed
multiplies. Special MAR and MRA instructions are implemented to move the 40-bit
accumulator to two Intel XScale® processor general registers (MAR) and move two
Intel XScale® processor general registers to the 40-bit accumulator (MRA). The 40-bit
accumulator can be stored or loaded to or from D-cache, mini-data cache, or memory
using two STC or LDC instructions.
The 16 x 16 signed multiply-accumulates (MIAxy) multiply either the high/high, low/
low, high/low, or low/high 16 bits of a 32-bit Intel XScale® processor general register
(multiplier) and another 32-bit Intel XScale® processor general register (multiplicand)
to produce a full, 32-bit product that is sign-extended to 40 bits and added to the 40-
bit accumulator.
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Dual-signed, 16 x 16 (SIMD) multiply-accumulates (MIAPH) multiply the high/high and
low/low 16-bits of a packed 32-bit, Intel XScale® processor general register (multiplier)
and another packed 32-bit, Intel XScale® processor general register (multiplicand) to
produce two 16-bits products that are both sign-extended to 40 bits and added to the
40-bit accumulator.
The 32 x 32 signed multiply-accumulates (MIA) multiply a 32-bit, Intel XScale®
processor general register (multiplier) and another 32-bit, Intel XScale® processor
general register (multiplicand) to produce a 64-bit product where the 40 LSBs are
added to the 40-bit accumulator. The 16 x 32 versions of the 32 x 32 multiply-
accumulate instructions complete in a single cycle.
2.2.11
2.2.12
Performance Monitoring Unit (PMU)
The performance monitoring unit contains two 32-bit, event counters and one 32-bit,
clock counter. The event counters can be programmed to monitor I-cache hit rate, data
caches hit rate, ITLB hit rate, DTLB hit rate, pipeline stalls, BTB prediction hit rate, and
instruction execution count.
Debug Unit
The debug unit is accessed through the JTAG port. The industry-standard, IEEE 1149.1
JTAG port consists of a test access port (TAP) controller, boundary-scan register,
instruction and data registers, and dedicated signals TDI, TDO, TCK, TMS, and TRST#.
The debug unit — when used with debugger application code running on a host system
outside of the Intel XScale® processor — allows a program, running on the Intel
XScale® processor, to be debugged. It allows the debugger application code or a debug
exception to stop program execution and redirect execution to a debug-handling
routine.
Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint,
external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once
execution has stopped, the debugger application code can examine or modify the Intel
XScale® processor’s state, coprocessor state, or memory. The debugger application
code can then restart program execution.
The debug unit has two hardware-instruction, break point registers; two hardware,
data-breakpoint registers; and a hardware, data-breakpoint control register. The
second data-breakpoint register can be alternatively used as a mask register for the
first data-breakpoint register.
A 256-entry trace buffer provides the ability to capture control flow messages or
addresses. A JTAG instruction (LDIC) can be used to download a debug handler via the
JTAG port to the mini-instruction cache (the I-cache has a 2-Kbyte, mini-instruction
cache to hold a debug handler).
3.0
Functional Signal Descriptions
Listed in the signal definition tables — starting at Table 7, “SDRAM Interface” on
page 34 — are pull-up an pull-down resistor recommendations that are required when
the particular enabled interface is not being used in the application. These external
resistor requirements are only needed if the particular model of Intel® IXP42X product
line and IXC1100 control plane processors has the particular interface enabled and the
interface is not required in the application.
Warning:
All IXP42X product line and IXC1100 control plane processors I/O pins are not 5-V
tolerant.
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Disabled features, within the IXP42X product line and IXC1100 control plane
processors, do not require external resistors as the processor will have internal pull-up
or pull-down resistors enabled as part of the disabled interface.
Table 5 presents the legend for interpreting the Type field in the other tables in this
section of the document.
To determine which interfaces are not enabled within the IXP42X product line and
IXC1100 control plane processors, see Table 3 on page 15.
Table 5.
Signal Type Definitions
Symbol
Description
I
O
Input pin only
Output pin only
I/O
OD
PWR
GND
1
Pin can be either an input or output
Open Drain pin
Power pin
Ground pin
Driven to Vcc
0
Driven to Vss
X
Driven to unknown state
Input is disabled
ID
H
Pulled up to Vcc
L
Pulled to Vss
PD
Z
Pull-up Disabled
Output Disabled
VO
VI
PE
Tri
N/C
-
A valid output level is driven, allowed states - 1, 0, H, Z
Need to drive a valid input level, allowed states - 1, 0, H, Z
Pull-up Enabled, equivalent to H
Output Only/Tristatable
No Connect
Pin must be connected as described
Table 6.
Processors’ Signal Interface Summary Table
Reference
Table 7, “SDRAM Interface” on page 34
Table 8, “PCI Controller” on page 36
Table 9, “High-Speed, Serial Interface 0” on page 38
Table 10, “High-Speed, Serial Interface 1” on page 39
Table 11, “MII Interfaces” on page 40
Table 12, “UTOPIA Level 2 Interface” on page 42
Table 13, “Expansion Bus Interface” on page 44
Table 14, “UART Interfaces” on page 45
Table 15, “USB Interface” on page 45
Table 16, “Oscillator Interface” on page 46
Table 17, “GPIO Interface” on page 46
Table 18, “JTAG Interface” on page 46
Table 19, “System Interface††” on page 47
Table 20, “Power Interface” on page 48
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3.1
Pin Description Tables
This section identifies all the signal pins by symbol name, type and description. Names
should follow the following convention, all capital letters with a trailing “_N” indicate a
signal is asserted when driven to a logic low (digital 0). The description includes the full
name of the pin along with a functional description. This section does not specify the
number of power and ground pins required, but does include the number of different
types of power pins required.
A signal called active high specifies that the interface is active when driven to a logic 1
and inactive when driven to a logic 0.
A signal called active low specifies that the interface is active when driven to a logic 0
and inactive when driven to a logic 1.
The following information attempts to explain how to interpret the tables. There are
five vertical columns:
• The Power Reset or Sys Reset column indicates signal state for the following
conditions:
— Power Reset is defined as follows:
PWRON_RESET_N = 0 and RESET_IN_N = X
— Sys Reset is defined as follows:
PWRON_RESET_N = 1 and RESET_IN_N = 0
• The Post Reset column indicates signal state for the following condition:
— Post Reset is defined as follows:
PWRON_RESET_N = 1, RESET_IN_N = 1 and PLL_LOCK = 1
Table 7.
SDRAM Interface (Sheet 1 of 2)
Power
Reset
orSys
Reset
Post
Reset
Name
Type†
Description
SDRAM Address: A0-A12 signals are output during the READ/
WRITE commands and ACTIVE commands to select a location
in memory to act upon.
SDM_ADDR[12:0]
SDM_DATA[31:0]
SDM_CLKOUT
SDM_BA[1:0]
Z
Z
Z
Z
Z
0
1
0
0
1
O
I/O
O
SDRAM Data: Bidirectional data bus used to transfer data to
and from the SDRAM
SDRAM Clock: All SDRAM input signals are sampled on the
rising edge of SDM_CLKOUT. All output signals are driven
with respect to the rising edge of SDM_CLKOUT.
SDRAM Bank Address: SDM_BA0 and SDM_BA1 define the
bank the current command is attempting to access.
O
SDRAM Row Address strobe/select (active low): Along with
SDM_CAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDM_RAS_N
O
SDRAM Column Address strobe/select (active low): Along
with SDM_RAS_N, SDM_WE_N, and SDM_CS_N signals
determines the current command to be executed.
SDM_CAS_N
SDM_CS_N[1:0]
SDM_WE_N
Z
Z
Z
1
1
1
O
O
O
SDRAM Chip select (active low): CS# enables the command
decoder in the external SDRAM when logic low and disables
the command decoder in the external SDRAM when logic
high.
SDRAM Write enable (active low): Along with SDM_CAS_N,
SDM_RAS_N, and SDM_CS_N signals determines the current
command to be executed.
†
For a legend of the Type codes, see Table 5 on page 33.
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Table 7.
SDRAM Interface (Sheet 2 of 2)
Power
Reset
orSys
Reset
Post
Reset
Name
Type†
Description
SDRAM Clock Enable: CKE is driving high to activate the
clock to an external SDRAM and driven low to de-activate the
CLK to an external SDRAM.
SDM_CKE
Z
Z
1
0
O
O
SDRAM Data bus mask: DQM is used to byte select data
during read/write access to an external SDRAM.
SDM_DQM[3:0]
†
For a legend of the Type codes, see Table 5 on page 33.
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Table 8.
PCI Controller (Sheet 1 of 2)
Power
Reset
Post
Name
PCI_AD[31:0]
PCI_CBE_N[3:0]
PCI_PAR
Type†
Description
or Sys Reset
Reset
PCI Address/Data bus used to transfer address and bidirectional
data to and from multiple PCI devices.
Should be pulled high†† with a 10-KΩ resistor when not being
Z
Z
Z
Z
Z
Z
I/O
utilized in the system.
PCI Command/Byte Enables is used as a command word during
PCI address cycles and as byte enables for data cycles.
Should be pulled high with a 10-KΩ resistor when not being
I/O
utilized in the system.
PCI Parity used to check parity across the 32 bits of PCI_AD and
the four bits of PCI_CBE_N.
Should be pulled high†† with a 10-KΩ resistor when not being
I/O
utilized in the system.
PCI Cycle Frame used to signify the beginning and duration of a
transaction. The signal will be inactive prior to or during the final
data phase of a given transaction.
PCI_FRAME_N
Z
Z
I/O
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Target Ready informs that the target of the PCI bus is ready
to complete the current data phase of a given transaction.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI_TRDY_N
PCI_IRDY_N
PCI_STOP_N
Z
Z
Z
Z
Z
Z
I/O
I/O
I/O
PCI Initiator Ready informs the PCI bus that the initiator is ready
to complete the transaction.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Stop indicates that the current target is requesting the
current initiator to stop the current transaction.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Parity Error asserted when a PCI parity error is detected —
between the PCI_PAR and associated information on the PCI_AD
bus and PCI_CBE_N — during all PCI transactions, except for
Special Cycles. The agent receiving data will drive this signal.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI_PERR_N
PCI_SERR_N
Z
Z
Z
Z
I/O
PCI System Error asserted when a parity error occurs on special
cycles or any other error that will cause the PCI bus not to
function properly. This signal can function as an input or an open
drain output.
I/OD
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Device Select:
•
When used as an output, PCI_DEVSEL_N indicates that
device has decoded that address as the target of the
requested transaction.
PCI_DEVSEL_N
Z
Z
I/O
•
When used as an input, PCI_DEVSEL_N indicates if any
device on the PCI bus exists with the given address.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Initialization Device Select is a chip select during
configuration reads and writes.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI_IDSEL
Z
Z
Z
Z
I
I
PCI arbitration request: Used by the internal PCI arbiter to allow
an agent to request the PCI bus.
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI_REQ_N[3:1]
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
36
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 8.
PCI Controller (Sheet 2 of 2)
Power
Reset
Post
Name
Type†
Description
or Sys Reset
Reset
PCI arbitration request:
•
When configured as an input (PCI arbiter enabled), the
internal PCI arbiter will allow an agent to request the PCI
bus.
PCI_REQ_N[0]
PCI_GNT_N[3:1]
PCI_GNT_N[0]
Z
Z
Z
Z
Z
Z
I/O
O
•
When configured as an output (PCI arbiter disabled), the pin
will be used to request access to the PCI bus from an
external arbiter.
Should be pulled high with a 10-KΩ resistor, when the PCI bus is
not being utilized in the system.
PCI arbitration grant: Generated by the internal PCI arbiter to
allow an agent to claim control of the PCI bus.
PCI arbitration grant:
•
When configured as an output (PCI arbiter enabled), the
internal PCI arbiter to allow an agent to claim control of the
PCI bus.
When configured as an input (PCI arbiter disabled), the pin
will be used to claim access of the PCI bus from an external
arbiter.
I/O
•
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI interrupt: Used to request an interrupt.
PCI_INTA_N
PCI_CLKIN
Z
Z
Z
O/D
Should be pulled high with a 10-KΩ resistor when not being
utilized in the system.
PCI Clock: provides timing for all transactions on PCI. All PCI
signals — except INTA#, INTB#, INTC#, and INTD# — are
sampled on the rising edge of CLK and timing parameters are
defined with respect to this edge. The PCI clock rate can operate
at up to 66 MHz.
Should be pulled high†† with a 10-KΩ resistor when not being
utilized in the system.
VI
I
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Document Number: 252479-006US
37
Intel® IXP42X product line and IXC1100 control plane processors
Table 9.
High-Speed, Serial Interface 0
Power
Reset
orSys
Reset
Post
Reset
Name
Type†
Description
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source become synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
HSS_TXFRAME0
HSS_TXDATA0
Z
Z
Z
Z
I/O
Should be pulled high†† with a 10-KΩ resistor when not being
utilized in the system.
Transmit data out. Open Drain output.
O/D
Must be pulled high with a 10-KΩ resistor to V
.
CCP
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to clock
out the transmitted data. Configured as an input upon reset.
Frame sync and data can be selected to be generated on the
rising or falling edge of the transmit clock.
HSS_TXCLK0
Z
Z
Z
Z
I/O
I/O
Should be pulled high†† with a 10-KΩ resistor when not being
utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to become synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high†† with a 10-KΩ resistor when not being
utilized in the system.
HSS_RXFRAME0
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
HSS_RXDATA0
HSS_RXCLK0
Z
Z
VI
Z
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
Should be pulled high†† with a 10-KΩ resistor when not being
utilized in the system.
I/O
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 10.
High-Speed, Serial Interface 1
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
HSS_TXFRAME1
HSS_TXDATA1
Z
Z
Z
Z
I/O
Should be pulled high†† with a 10-KΩ resistor when not
being utilized in the system.
Transmit data out. Open Drain output.
O/D
Must be pulled high with a 10-KΩ resistor to V
.
CCP
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to
clock out the transmitted data. Configured as an input upon
reset. Frame sync and Data can be selected to be generated
on the rising or falling edge of the transmit clock.
HSS_TXCLK1
Z
Z
Z
Z
I/O
I/O
Should be pulled high†† with a 10-KΩ resistor when not
being utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to be synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high†† with a 10-KΩ resistor when not
being utilized in the system.
HSS_RXFRAME1
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
HSS_RXDATA1
HSS_RXCLK1
Z
Z
VI
Z
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
Should be pulled high†† with a 10-KΩ resistor when not
being utilized in the system.
I/O
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Table 11.
MII Interfaces (Sheet 1 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
Externally supplied transmit clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_TXCLK0
Z
VI
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK0.
ETH_TXDATA0[3:0]
ETH_TXEN0
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK0, at the first nibble of the preamble and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_RXCLK0
Z
Z
VI
VI
I
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Receive data bus from PHY, data sampled synchronously
with respect to ETH_RXCLK0
•
ETH_RXDATA0[3:0]
Should be pulled high†† through a 10-KΩ resistor when
not being utilized in the system.
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data. Should be pulled high††
through a 10-KΩ resistor when not being utilized in the
system.
ETH_RXDV0
ETH_COL0
Z
Z
VI
VI
I
I
Asserted by the PHY when a collision is detected by the
PHY. Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium is active. De-asserted when both the transmit and
receive medium are idle. Remains asserted throughout the
duration of a collision condition. PHY asserts CRS
ETH_CRS0
Z
VI
I
asynchronously and de-asserts synchronously, with respect
to ETH_RXCLK0. Should be pulled high†† through a 10-KΩ
resistor when not being utilized in the system.
Management data output. Provides the write data to both
PHY devices connected to each MII interface.
An external 1.5-KΩ pull-up resistor is required.
Note: If interfacing with a single Intel® LXT972 Fast
Ethernet Transceiver, and a 1.5K pull-up resistor is
not used, the NPE will ‘see’ 32 PHYs on the MII
interface.
ETH_MDIO
ETH_MDC
Z
Z
Z
Z
I/O
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Management data clock. Management data interface clock
is used to clock the MDIO signal as an output and sample
the MDIO as an input. The ETH_MDC is an input on power
up and can be configured to be an output through an Intel
API as documented in the Intel® IXP400 Software
Programmer’s Guide.
IO
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
40
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 11.
MII Interfaces (Sheet 2 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
Externally supplied transmit clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_TXCLK1
Z
VI
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Transmit data bus to PHY, asserted synchronously with
respect to ETH_TXCLK1.
ETH_TXDATA1[3:0]
ETH_TXEN1
Z
Z
0
0
O
O
Indicates that the PHY is being presented with nibbles on
the MII interface. Asserted synchronously, with respect to
ETH_TXCLK1, at the first nibble of the preamble, and
remains asserted until all the nibbles of a frame are
presented.
Externally supplied receive clock.
•
•
25 MHz for 100 Mbps operation
2.5 MHz for 10 Mbps
ETH_RXCLK1
Z
VI
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Receive data bus from PHY, data sampled synchronously,
with respect to ETH_RXCLK1.
ETH_RXDATA1[3:0]
ETH_RXDV1
Z
Z
Z
VI
VI
VI
I
I
I
•
Should be pulled high†† through a 10-KΩ resistor when
not being utilized in the system.
Receive data valid, used to inform the MII interface that the
Ethernet PHY is sending data.
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
Asserted by the PHY when a collision is detected by the
PHY.
ETH_COL1
•
Should be pulled low through a 10-KΩ resistor when
not being utilized in the system.
Asserted by the PHY when the transmit medium or receive
medium are active. De-asserted when both the transmit
and receive medium are idle. Remains asserted throughout
the duration of collision condition. PHY asserts CRS
asynchronously and de-asserts synchronously with respect
to ETH_RXCLK1.
ETH_CRS1
Z
VI
I
Should be pulled high†† through a 10-KΩ resistor when not
being utilized in the system.
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Table 12.
UTOPIA Level 2 Interface (Sheet 1 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
UTOPIA Transmit clock input. Also known as UTP_TX_CLK.
This signal is used to synchronize all UTOPIA-transmit
outputs to the rising edge of the UTP_OP_CLK.
UTP_OP_CLK
Z
Z
VI
I
This signal should be pulled high†† through a 10-KΩ
resistor when not being utilized in the system.
UTOPIA flow control output signal. Also known as the
TXENB_N signal.
Used to inform the selected PHY that data is being
transmitted to the PHY. Placing the PHY’s address on the
UTP_OP_ADDR — and bringing UTP_OP_FCO to logic 1,
during the current clock — followed by the UTP_OP_FCO
going to a logic 0, on the next clock cycle, selects which
PHY is active in MPHY mode.
UTP_OP_FCO
Z
O
In SPHY configurations, UTP_OP_FCO is used to inform
the PHY that the processor is ready to send data.
Start of Cell. Also known as TX_SOC.
UTP_OP_SOC
Z
Z
Z
Z
Z
O
O
Active high signal is asserted when UTP_OP_DATA
contains the first valid byte of a transmitted cell.
UTOPIA output data. Also known as UTP_TX_DATA. Used
to send data from the processor to an ATM UTOPIA-Level-
2-compliant PHY.
UTP_OP_DATA[7:0]
UTP_OP_ADDR[4:0]
Transmit PHY address bus. Used by the processor when
operating in MPHY mode to poll and select a single PHY at
any given time.
VI
I/O
UTOPIA Output data flow control input: Also known as the
TXFULL/CLAV signal.
Used to inform the processor of the ability of each polled
PHY to receive a complete cell. For cell-level flow control
in an MPHY environment, TxClav is an active high tri-
stateable signal from the MPHY to ATM layer. The
UTP_OP_FCI, which is connected to multiple MPHY
devices, will see logic high generated by the PHY, one
clock after the given PHY address is asserted — when a
full cell can be received by the PHY. The UTP_OP_FCI will
see a logic low generated by the PHY one clock cycle, after
the PHY address is asserted — if a full cell cannot be
received by the PHY.
UTP_OP_FCI
Z
VI
I
This signal should be pulled high†† through a 10-KΩ
resistor if not being used.
UTOPIA Receive clock input. Also known as UTP_RX_CLK.
This signal is used to synchronize all UTOPIA-received
inputs to the rising edge of the UTP_IP_CLK.
UTP_IP_CLK
Z
VI
I
This signal should be pulled high†† through a 10-KΩ
resistor when not being utilized in the system.
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 12.
UTOPIA Level 2 Interface (Sheet 2 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
UTOPIA Input Data flow control input signal. Also known
as RXEMPTY/CLAV.
Used to inform the processor of the ability of each polled
PHY to send a complete cell. For cell-level flow control in
an MPHY environment, RxClav is an active high tri-
stateable signal from the MPHY to ATM layer. The
UTP_IP_FCI, which is connected to multiple MPHY devices,
will see logic high generated by the PHY, one clock after
the given PHY address is asserted, when a full cell can be
received by the PHY. The UTP_IP_FCI will see a logic low
generated by the PHY, one clock cycle after the PHY
address is asserted if a full cell cannot be received by the
PHY.
UTP_IP_FCI
Z
VI
I
In SPHY mode, this signal is used to indicate to the
processor that the PHY has an octet or cell available to be
transferred to the processor.
Should be pulled high†† through a 10-KΩ resistor when
not being utilized in the system.
Start of Cell. RX_SOC
Active-high signal that is asserted when UTP_IP_DATA
contains the first valid byte of a transmitted cell.
UTP_IP_SOC
Z
VI
I
Should be pulled high†† through a 10-KΩ resistor when
not being utilized in the system.
UTOPIA input data. Also known as RX_DATA.
Used by to the processor to receive data from an ATM
UTOPIA-Level-2-compliant PHY.
UTP_IP_DATA[7:0]
UTP_IP_ADDR[4:0]
Z
Z
VI
VI
I
Should be pulled high†† through a 10-KΩ resistor when
not being utilized in the system.
Receive PHY address bus.
Used by the processor when operating in MPHY mode to
poll and select a single PHY at any one given time.
I/O
UTOPIA Input Data Flow Control Output signal: Also
known as the RX_ENB_N.
In SPHY configurations, UTP_IP_FCO is used to inform the
PHY that the processor is ready to accept data.
In MPHY configurations, UTP_IP_FCO is used to select
which PHY will drive the UTP_RX_DATA and UTP_RX_SOC
signals. The PHY is selected by placing the PHY’s address
on the UTP_IP_ADDR and bringing UTP_OP_FCO to logic 1
during the current clock, followed by the UTP_OP_FCO
going to a logic 0 on the next clock cycle.
UTP_IP_FCO
Z
Z
O
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
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Intel® IXP42X product line and IXC1100 control plane processors
Table 13.
Expansion Bus Interface
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
Input clock signal used to sample all expansion interface
inputs and clock all expansion interface outputs.
EX_CLK
Z
Z
Z
0
I
Address-latch enable used for multiplexed address/data bus
accesses. Used in Intel and Motorola* multiplexed modes of
operation.
EX_ALE
O
Expansion-bus address used as an output for data accesses
over the expansion bus. Also, used as an input during reset to
capture device configuration. These signals have a weak pull-
up resistor attached internally. Based on the desired
EX_ADDR[23:0]
H
H
I/O
configuration, various address signals must be pulled low in
order for the device to operate in the desired mode.
Intel-mode write strobe / Motorola-mode data strobe
(EXP_MOT_DS_N) / TI*-mode data strobe (TI_HDS1_N).
EX_WR_N
EX_RD_N
Z
Z
1
1
O
O
Intel-mode read strobe / Motorola-mode read-not-write
(EXPB_MOT_RNW) / TI mode read-not-write (TI_HR_W_N).
External chip selects for expansion bus.
•
Chip selects 0 through 7 can be configured to support
Intel or Motorola bus cycles.
Chip selects 4 through 7 can be configured to support TI
HPI bus cycles.
EX_CS_N[7:0]
EX_DATA[15:0]
Z
Z
1
0
O
•
I/O
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices.
Expansion-bus access is halted when an external device sets
EX_IOWAIT_N to logic 0 and resume from the halted location
once the external device sets EX_IOWAIT_N to logic 1. This
signal affects accesses that use EX_CS_N[7:0] when the chip
select is configured in Intel- or Motorola-mode of operation.
EX_IOWAIT_N
EX_RDY[3:0]
H
H
H
H
I
I
Should be pulled high through a 10-KΩ resistor when not
being utilized in the system.
HPI interface ready signals. Can be configured to be active
high or active low. These signals are used to halt accesses
using Chip Selects 7 through 4 when the chip selects are
configured to operate in HPI mode. There is one RDY signal
per chip select. This signal only affects accesses that use
EX_CS_N[7:4].
Should be pulled high†† though a 10-KΩ resistor when not
being utilized in the system.
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 14.
UART Interfaces
Power
Reset
Post
Name
Type†
Description
or Sys
Reset
Reset
UART serial data input to High-Speed UART Pins.
Should be pulled high†† through a 10-KΩ resistor when not being
RXDATA0
TXDATA0
Z
Z
VI
I
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a reset operation. High-Speed Serial UART Pins.
VO
O
UART CLEAR-TO-SEND input to High-Speed UART Pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
CTS0_N
RTS0_N
H
H
VI/PE
I
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1).
High-Speed UART Pins.
UART serial data input.
Should be pulled high†† through a 10-KΩ resistor when not being
RXDATA1
TXDATA1
Z
Z
VI
I
utilized in the system.
UART serial data output. The TXD signal is set to the MARKING
(logic 1) state upon a Reset operation. Console UART Pins.
VO
O
UART CLEAR-TO-SEND input to Console UART pins.
When logic 0, this pin indicates that the modem or data set
connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose
condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being
utilized in the system.
CTS1_N
RTS1_N
H
H
VI/PE
I
UART REQUEST-TO-SEND output:
When logic 0, this informs the modem or the data set connected to
the UART interface of the processor that the UART is ready to
exchange data. A reset sets the request to send signal to logic 1.
VO/PE
O
LOOP-mode operation holds this signal in its inactive state (logic 1).
Console UART Pins.
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Table 15.
USB Interface
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
USB_DPOS
USB_DNEG
Z
Z
Z
Z
I/O
I/O
Positive signal of the differential USB receiver/driver.
Negative signal of the differential USB receiver/driver.
†
For a legend of the Type codes, see Table 5 on page 33.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Table 16.
Oscillator Interface
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
OSC_IN
VI
VI
I
33.33 MHz, sinusoidal input signal. Can be driven by an oscillator.
33.33 MHz, sinusoidal output signal. Left disconnected when being
driven by an oscillator.
OSC_OUT
VO
VO
O
†
For a legend of the Type codes, see Table 5 on page 33.
Table 17.
GPIO Interface
Power
Reset
Post
Name
Type†
Description
or Sys
Reset
Reset
General purpose Input/Output pins. May be configured as an input
or an output. As an input, each signal may be configured a
processor interrupt. Default after reset is to be configured as
inputs.
GPIO[12:0]
GPIO[13]
GPIO[14]
Z
Z
Z
Z
Z
Z
I/O
Should be pulled high†† using a 10-KΩ resistor when not being
utilized in the system.
General purpose input/output pins. May be configured as an input
or an output. Default after reset is to be configured as inputs.
I/O
Should be pulled high†† using a 10-KΩ resistor when not being
utilized in the system.
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an input,
upon reset.
Should be pulled high†† though a 10-KΩ resistor when not being
utilized in the system.
I/O
Can be configured similar to GPIO Pin 13 or as a clock output.
Configuration as an output clock can be set at various speeds of up
to 33.33 MHz with various duty cycles. Configured as an output,
upon reset. Can be used to clock the expansion interface, after
reset.
CLKOUT
/VO
GPIO[15]
0
I/O
Should be pulled high†† though a 10-KΩ resistor when not being
utilized in the system.
†
††
For a legend of the Type codes, see Table 5 on page 33.
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Table 18.
JTAG Interface (Sheet 1 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
JTG_TMS
JTG_TDI
H
H
VI/PE
VI/PE
I
I
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
†
For a legend of the Type codes, see Table 5 on page 33.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
46
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 18.
JTAG Interface (Sheet 2 of 2)
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
JTG_TDO
Z
H
Z
VO
VI/PE
VI
O
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
The JTG_TRST_N signal must be asserted (driven low) during
power-up, otherwise the TAP controller may not be initialized
properly, and the processor may be locked.
JTG_TRST_N
I
When the JTAG interface is not being used, the signal must be
pulled low using a 10-KΩ resistor.
JTG_TCK
I
Used as the clock for the IEEE 1149.1 JTAG interface.
†
For a legend of the Type codes, see Table 5 on page 33.
Table 19.
System Interface††
Power
Reset
or Sys
Reset
Post
Reset
Name
Type†
Description
Used for test purposes only.
Must be pulled high for normal operation.
BYPASS_CLK
Z
H
VI
I
I
Used for test purposes only.
Must be pulled high for normal operation.
SCANTESTMODE_N
VI/PE
Used as a reset input to the device when
PWRON_RESET_N is in an inactive state and once power
up conditions are met. Power up conditions include the
following:
RESET_IN_N
0
VI
I
— Power supplies reaching a safe stable
condition and
— The PLL achieving a locked state
Signal used at power up to reset all internal logic to a
known state after the PLL has achieved a locked state.
The PWRON_RESET_N input is a 1.3-V tolerant only.
PWRON_RESET_N
0
VI
I
Used for test purposes only.
Must be pulled high for normal operation.
HIGHZ_N
PLL_LOCK
H
0
VI/PE
VO
I
Signal used to inform external reset logic that the
internal PLL has achieved a locked state.
O
Signal used to control PCI drive strength characteristics.
Drive strength is varied on PCI address, data and control
signals.
Pin requires a 34-Ω +/- 1% tolerance resistor to ground.
Refer to Figure 13 on page 82.
Tied off Tiedoff
to a to a
resistor resistor
RCOMP
O
†
††
For a legend of the Type codes, see Table 5 on page 33.
IMPORTANT NOTE: When a system-level reset is asserted to the Intel® IXP42X Product Line of
Network Processors and IXC1100 Control Plane Processor — either via a power-on reset, a system
reset, or a Watchdog-Timer reset — and any interface is in an active transaction (particularly the PCI
bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior
of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a
reset of other attached devices may be required.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
47
Intel® IXP42X product line and IXC1100 control plane processors
Table 20.
Power Interface
Name
VCC
Type†
Description
I
I
1.3-V power supply input pins used for the internal logic.
VCCP
VSS
3.3-V power supply input pins used for the peripheral (I/O) logic.
Ground power supply input pins used for both the 3.3-V and the 1.3-V power
supplies.
3.3-V power supply input pins used for the peripheral (I/O) logic of the analog
oscillator circuitry.
Require special power filtering circuitry. Refer to Figure 11 on page 81
VCCOSCP
VSSOSCP
VCCOSC
VSSOSC
VCCPLL1
VCCPLL2
I
I
I
I
I
I
Ground input pins used for the peripheral (I/O) logic of the analog oscillator circuitry.
Used in conjunction with the VCCOSCP pins.
Requires special power filtering circuitry. Refer to Figure 11 on page 81
1.3-V power supply input pins used for the internal logic of the analog oscillator
circuitry.
Requires special power filtering circuitry. Refer to Figure 12 on page 82
Ground power supply input pins used for the internal logic of the analog oscillator
circuitry. Used in conjunction with the VCCOSC pins.
Requires special power filtering circuitry. Refer to Figure 12 on page 82
1.3-V power supply input pins used for the internal logic of the analog phase lock-loop
circuitry.
Requires special power filtering circuitry. Refer to Figure 9 on page 80
1.3-V power supply input pins used for the internal logic of the analog phase lock-loop
circuitry.
Requires special power filtering circuitry. Refer to Figure 10 on page 81
†
For a legend of the Type codes, see Table 5 on page 33.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
48
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
4.0
Package and Pinout Information
The Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial-
temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array
with a drop-in heat spreader (H) for extended-temperature applications.
4.1
Package Description
Figure 7.
492-Pin Lead PBGA Package
-A-
0.127
A
35.00 ± 0.20
30.00 ± 0.25
(1)
0.90
0.60
Pin #1
Corner
ø
26 24 22
25 23 21
20 18
19
16 14 12 10
15 13
8
6
4
2
3 1
17
11
9
7
5
2
C
-B-
ø 0.30
S
A
S
S
B
A
B
C
D
E
F
G
H
J
Pin 1 ID
K
L
M
35.00 ± 0.20
22.00 REF
N
P
R
T
U
(2)
1.27
30.00 ± 0.25
V
W
+
+
Y
AA
AB
AC
AD
AE
AF
+
+ +
1.63 REF
ø1.0
45º Chamfer
4 Places
1.27
1.63 REF
22.00 REF
3 Places
TOP VIEW
2.38 ± 0.21
1.17 ± 0.05
30º
0.15
0.20
C
-C-
0.61 ± 0.06
3
0.60 ± 0.10
Seating Plane
SIDE VIEW
B1268-03
1.
2.
3.
All measurements are in millimeters (mm).
The size of the land pad at the interposer side (1) is 0.81 mm.
The size of the solder resist at the interposer side (2) is 0.66 mm.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
49
Intel® IXP42X product line and IXC1100 control plane processors
Figure 8.
Package Markings
Pin #1
(Not a mark)
*
Level 1 Name
FWIXP42 XBX
<FPO>
INTEL M C 2002
i
<ATPO>
YWW KOREA
BSMC marking zone:
0.380” max.
BSMC
(ATPO#, Date
Code and COO)
Note: See Table 21 for specific on “Level 1 Name.”
Table 21.
Part Numbers for the Intel® IXP42X Product Line of Network Processors
(Sheet 1 of 2)
Speed
(MHz)
Extended
Temp.
Lead
Free
Device
Stepping
Part #
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP425
Intel® IXP423
Intel® IXP423
Intel® IXP423
Intel® IXP423
Intel® IXP422
Intel® IXP422
Intel® IXP421
Intel® IXP421
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
533
266
533
400
266
533
400
266
533
400
266
533
533
266
266
266
266
266
266
Yes
Yes
Yes
Yes
Yes
Yes
Yes
EWIXP425BDT
EWIXP425BBT
PRIXP425BD
PRIXP425BC
PRIXP425BB
GWIXP425BDT
GWIXP425BCT
GWIXP425BBT
FWIXP425BD
FWIXP425BC
FWIXP425BB
PRIXP423BD
FWIXP423BD
PRIXP423BB
FWIXP423BB
PRIXP422BB
FWIXP422BB
PRIXP421BB
FWIXP421BB
Yes
Yes
Yes
Yes
Yes
Yes
Yes
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
50
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 21.
Part Numbers for the Intel® IXP42X Product Line of Network Processors
(Sheet 2 of 2)
Speed
(MHz)
Extended
Temp.
Lead
Free
Device
Stepping
Part #
Intel® IXP420
Intel® IXP420
Intel® IXP420
Intel® IXP420
Intel® IXP420
Intel® IXP420
Intel® IXP420
Intel® IXP420
B-0
B-0
B-0
B-0
B-0
B-0
B-0
B-0
266
266
533
400
266
533
400
266
Yes
Yes
Yes
EWIXP420BBT
GWIXP420BBT
PRIXP420BD
PRIXP420BC
PRIXP420BB
FWIXP420BD
FWIXP420BC
FWIXP420BB
Yes
Yes
Yes
4.2
Signal-Pin Descriptions
In this section, separate ball-map-assignment tables are given for each model of the
IXP42X product line and IXC1100 control plane processors. These tables include:
Device
Table #
Starting Page
Intel® IXP425 Network Processor
Intel® IXP423 Network Processor
Intel® IXP422 Network Processor
Intel® IXP421 Network Processor
22
22
23
24
51
51
58
65
Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane
Processor
25
72
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
B10
B11
B12
B13
B14
B15
B16
B17
B18
C10
C11
C12
C13
C14
C15
C16
C17
C18
D10
D11
D12
D13
D14
D15
D16
D17
D18
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
51
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A19
A20
A21
A22
A23
A24
A25
A26
E1
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
B19
B20
B21
B22
B23
B24
B25
B26
F1
SDM_ADDR[10]
VSS
C19
C20
C21
C22
C23
C24
C25
C26
G1
VSS
D19
D20
D21
D22
D23
D24
D25
D26
H1
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
PCI_AD[21]
VCCP
VCC
EX_ADDR[1]
EX_ADDR[3]
EX_ADDR[5]
PCI_AD[23]
VCCP
EX_ADDR[6]
RCOMP
VCCP
EX_ADDR[9]
PCI_AD[20]
PCI_IDSEL
VCC
EX_ADDR[17]
PCI_AD[16]
PCI_AD[18]
VCC
E2
F2
G2
H2
E3
PCI_REQ_N[2]
VSS
F3
G3
PCI_AD[24]
VSS
H3
E4
F4
PCI_REQ_N[0]
VCCP
G4
H4
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
F5
G5
PCI_REQ_N[1]
VSS
H5
E6
F6
VCC
G6
H6
PCI_REQ_N[3]
E7
F7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
F8
E9
F9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
F10
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
52
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
VCC
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
53
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
54
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
Y1
Y2
Y3
Y4
Y5
Y6
HSS_TXCLK0
HSS_RXCLK0
HSS_TXFRAME1
VCC
PCI_AD[0]
PCI_AD[7]
HSS_TXDATA0
VCC
PCI_AD[3]
VCC
HSS_RXFRAME0
VSS
HSS_TXFRAME0
VSS
HSS_TXCLK1
HSS_RXFRAME1
VCCP
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
VCC
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
55
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
HSS_RXDATA0
VCCP
AB1
AB2
HSS_TXDATA1
HSS_RXDATA1
ETH_TXDATA0[3]
ETH_TXDATA0[1]
VSS
AC1
AC2
VSS
ETH_TXDATA0[0]
VCCP
AD1
AD2
ETH_TXCLK0
ETH_RXDV0
VSS
VSS
AB3
AC3
AD3
HSS_RXCLK1
ETH_TXDATA0[2]
VCC
AB4
AC4
VCC
AD4
ETH_CRS0
ETH_MDC
AB5
AC5
ETH_RXDATA0[0]
VSS
AD5
AB6
ETH_RXCLK0
VCCP
AC6
AD6
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
ETH_RXDATA0[1]
VSS
AB7
AC7
VCC
AD7
AB8
ETH_TXDATA1[2]
ETH_RXDATA1[1]
VCCP
AC8
ETH_RXDATA1[2]
VCC
AD8
ETH_TXDATA1[1]
VCC
AB9
AC9
AD9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AC10
AC11
AC12
AC13
AC14
VCC
AD10
AD11
AD12
AD13
AD14
VSSOSCP
VCCP
VCCOSCP
VCC
VCCP
VSS
PLL_LOCK
UTP_OP_DATA[7]
VCCP
RESET_IN_N
VCC
PWRON_RESET_N
UTP_OP_DATA[4]
UTP_OP_DATA[2]
VSS
UTP_OP_SOC
VSS
AC15 UTP_OP_DATA[1] AD15
AC16 UTP_OP_FCI AD16
AC17 UTP_OP_ADDR[1] AD17
AC18 VCC AD18
AC19 UTP_IP_DATA[2] AD19
AA17
AA18
VCC
UTP_IP_DATA[6]
VCCP
UTP_OP_ADDR[3]
UTP_IP_DATA[7]
VCCP
UTP_IP_FCI
AA19 UTP_IP_ADDR[0] AB19
UTP_IP_CLK
UTP_IP_ADDR[1]
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VSS
VCC
AB20
AC20
UTP_IP_SOC
VCC
AD20
AD21
AD22
AD23
AD24
AD25
AD26
UTP_IP_DATA[1]
UTP_IP_ADDR[4]
VSS
AB21 SCANTESTMODE_N AC21
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
JTG_TDO
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
VSS
TXDATA0
GPIO[7]
GPIO[4]
RTS0_N
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
56
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 22.
Ball Map Assignment for the Intel® IXP425 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1
AE2
ETH_RXDATA0[3]
VCCP
AF1
AF2
ETH_RXDATA0[2]
ETH_MDIO
AE3
ETH_COL0
ETH_TXEN1
VCCP
AF3
(Reserved)
AE4
AF4
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
VSSOSC
AE9
AF9
OSC_IN
AE10
AE11
AE12
AE13
VCCPLL1
VSS
AF10
AF11
AF12
AF13
VSSOSCP
OSC_OUT
VCCPLL2
VCCP
VCCOSC
BYPASS_CLK
UTP_OP_DATA[6]
UTP_OP_DATA[3]
UTP_OP_DATA[0]
UTP_OP_CLK
UTP_OP_ADDR[4]
UTP_OP_ADDR[0]
UTP_IP_DATA[5]
UTP_IP_DATA[3]
UTP_IP_DATA[0]
UTP_IP_ADDR[3]
UTP_IP_ADDR[2]
JTG_TMS
AE14 UTP_OP_DATA[5] AF14
AE15
AE16
AE17
VSS
UTP_OP_FCO
VCCP
AF15
AF16
AF17
AE18 UTP_OP_ADDR[2] AF18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VSS
UTP_IP_DATA[4]
VCCP
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
UTP_IP_FCO
VCCP
JTG_TDI
VCCP
HIGHZ_N
JTG_TCK
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
57
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
58
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
59
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
VCC
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
60
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
61
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
N/C
Y1
Y2
Y3
Y4
Y5
Y6
N/C
N/C
PCI_AD[0]
PCI_AD[7]
N/C
PCI_AD[3]
VCC
N/C
VSS
VCC
N/C
N/C
VCCP
VCC
VSS
N/C
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
VCC
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
62
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
N/C
AB1
AB2
N/C
AC1
AC2
VSS
ETH_TXDATA0[0]
VCCP
AD1
AD2
ETH_TXCLK0
ETH_RXDV0
VSS
VCCP
N/C
VSS
N/C
AB3
ETH_TXDATA0[3]
AC3
AD3
AB4
ETH_TXDATA0[1]
AC4
VCC
AD4
ETH_CRS0
ETH_MDC
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
ETH_TXDATA0[2]
VCC
AB5
VSS
AC5
ETH_RXDATA0[0]
VSS
AD5
AB6
ETH_RXCLK0
AC6
AD6
ETH_RXDATA0[1]
VSS
AB7
VCCP
AC7
VCC
AD7
AB8
ETH_TXDATA1[2]
AC8
ETH_RXDATA1[2]
VCC
AD8
ETH_TXDATA1[1]
VCC
AB9
ETH_RXDATA1[1]
AC9
AD9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
VCCP
VCCP
VSS
N/C
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
VCC
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
VSSOSCP
VCCP
VCCOSCP
VCC
PLL_LOCK
PWRON_RESET_N
N/C
RESET_IN_N
VCC
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
VSS
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VCC
N/C
N/C
N/C
VCCP
N/C
VCC
N/C
N/C
N/C
VCCP
VSS
N/C
N/C
N/C
VCC
AB21 SCANTESTMODE_N AC21
VCC
N/C
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
VSS
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
63
Intel® IXP42X product line and IXC1100 control plane processors
Table 23.
Ball Map Assignment for the Intel® IXP422 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1
AE2
ETH_RXDATA0[3]
VCCP
AF1
AF2
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
OSC_IN
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
N/C
AE3
ETH_COL0
ETH_TXEN1
VCCP
AF3
AE4
AF4
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VCCPLL1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
VCCPLL2
VCCP
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VCCP
N/C
JTG_TDI
VCCP
N/C
JTG_TMS
JTG_TCK
HIGHZ_N
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
64
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
65
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
66
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
VCC
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
67
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
68
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
Y1
Y2
Y3
Y4
Y5
Y6
HSS_TXCLK0
HSS_RXCLK0
HSS_TXFRAME1
VCC
PCI_AD[0]
PCI_AD[7]
HSS_TXDATA0
VCC
PCI_AD[3]
VCC
HSS_RXFRAME0
VSS
HSS_TXFRAME0
VSS
HSS_TXCLK1
HSS_RXFRAME1
VCCP
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
VCC
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
69
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
HSS_RXDATA0
AB1
AB2
HSS_TXDATA1
HSS_RXDATA1
ETH_TXDATA0[3]
ETH_TXDATA0[1]
VSS
AC1
AC2
VSS
AD1
AD2
ETH_TXCLK0
ETH_RXDV0
VSS
VCCP
VSS
ETH_TXDATA0[0]
AB3
AC3
VCCP
VCC
AD3
HSS_RXCLK1
ETH_TXDATA0[2]
VCC
AB4
AC4
AD4
ETH_CRS0
ETH_MDC
N/C
AB5
AC5
ETH_RXDATA0[0]
VSS
AD5
AB6
ETH_RXCLK0
VCCP
AC6
AD6
ETH_RXDATA0[1]
VSS
AB7
AC7
VCC
AD7
N/C
AB8
N/C
AC8
N/C
AD8
N/C
N/C
AB9
N/C
AC9
VCC
AD9
VSS
VCC
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
VCCP
AC10
AC11
AC12
AC13
AC14
VCC
AD10
AD11
AD12
AD13
AD14
VSSOSCP
VCCP
VCCP
VCCOSCP
VCC
VSS
PLL_LOCK
PWRON_RESET_N
UTP_OP_DATA[4]
UTP_OP_DATA[2]
VSS
UTP_OP_DATA[7]
VCCP
RESET_IN_N
VCC
UTP_OP_SOC
VSS
AC15 UTP_OP_DATA[1] AD15
AC16 UTP_OP_FCI AD16
AC17 UTP_OP_ADDR[1] AD17
AC18 VCC AD18
AC19 UTP_IP_DATA[2] AD19
AA17
AA18
VCC
UTP_IP_DATA[6]
VCCP
UTP_OP_ADDR[3]
UTP_IP_DATA[7]
VCCP
UTP_IP_FCI
AA19 UTP_IP_ADDR[0] AB19
UTP_IP_CLK
UTP_IP_ADDR[1]
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VSS
VCC
AB20
AC20
UTP_IP_SOC
VCC
AD20
AD21
AD22
AD23
AD24
AD25
AD26
UTP_IP_DATA[1]
UTP_IP_ADDR[4]
VSS
AB21 SCANTESTMODE_N AC21
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
70
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 24.
Ball Map Assignment for the Intel® IXP421 Network Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1
AE2
ETH_RXDATA0[3]
VCCP
AF1
AF2
ETH_RXDATA0[2]
ETH_MDIO
AE3
ETH_COL0
N/C
AF3
(Reserved)
AE4
AF4
N/C
AE5
VCCP
AF5
N/C
AE6
N/C
AF6
N/C
AE7
VSS
AF7
N/C
AE8
N/C
AF8
VSSOSC
AE9
VCCP
AF9
OSC_IN
AE10
AE11
AE12
AE13
VCCPLL1
VSS
AF10
AF11
AF12
AF13
VSSOSCP
OSC_OUT
VCCPLL2
VCCP
VCCOSC
BYPASS_CLK
UTP_OP_DATA[6]
UTP_OP_DATA[3]
UTP_OP_DATA[0]
UTP_OP_CLK
UTP_OP_ADDR[4]
UTP_OP_ADDR[0]
UTP_IP_DATA[5]
UTP_IP_DATA[3]
UTP_IP_DATA[0]
UTP_IP_ADDR[3]
UTP_IP_ADDR[2]
JTG_TMS
AE14 UTP_OP_DATA[5] AF14
AE15
AE16
AE17
VSS
UTP_OP_FCO
VCCP
AF15
AF16
AF17
AE18 UTP_OP_ADDR[2] AF18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VSS
UTP_IP_DATA[4]
VCCP
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
UTP_IP_FCO
VCCP
JTG_TDI
VCCP
HIGHZ_N
JTG_TCK
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
71
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 1 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
A1
A2
PCI_AD[27]
PCI_GNT_N[1]
PCI_GNT_N[3]
SDM_DATA[19]
SDM_DATA[27]
SDM_DATA[26]
SDM_DATA[25]
SDM_DATA[23]
SDM_DATA[14]
SDM_DATA[13]
SDM_DATA[11]
SDM_DATA[10]
SDM_DATA[6]
SDM_DATA[8]
SDM_DQM[1]
SDM_CS_N[0]
SDM_CLKOUT
SDM_RAS_N
B1
B2
PCI_AD[28]
VCCP
C1
C2
PCI_AD[26]
PCI_AD[30]
VSS
D1
D2
PCI_AD[25]
VSS
A3
B3
PCI_GNT_N[2]
VCCP
C3
D3
PCI_AD[31]
VCC
A4
B4
C4
PCI_INTA_N
VSS
D4
A5
B5
SDM_DATA[28]
VCCP
C5
D5
PCI_SERR_N
VCC
A6
B6
C6
SDM_DATA[18]
VSS
D6
A7
B7
SDM_DATA[21]
VSS
C7
D7
SDM_DATA[29]
SDM_DATA[20]
VCC
A8
B8
C8
VCCP
D8
A9
B9
SDM_DATA[0]
VCCP
C9
SDM_DATA[24]
VSS
D9
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
B10
B11
B12
B13
B14
B15
B16
B17
B18
B19
B20
B21
B22
B23
B24
B25
B26
C10
C11
C12
C13
C14
C15
C16
C17
C18
C19
C20
C21
C22
C23
C24
C25
C26
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
D21
D22
D23
D24
D25
D26
SDM_DATA[15]
SDM_DATA[1]
VCC
SDM_DATA[12]
VSS
SDM_DATA[2]
SDM_DATA[4]
VSS
SDM_DATA[9]
VCCP
SDM_DATA[5]
VCC
SDM_DATA[7]
SDM_DQM[3]
VCCP
SDM_DQM[2]
VSS
SDM_WE_N
SDM_CS_N[1]
SDM_BA[1]
VCC
SDM_CKE
VCCP
SDM_CAS_N
SDM_ADDR[11]
VSS
SDM_ADDR[12]
SDM_ADDR[9]
SDM_ADDR[8]
SDM_ADDR[5]
EX_RD_N
SDM_ADDR[10]
VSS
SDM_ADDR[0]
VSS
SDM_ADDR[6]
SDM_ADDR[2]
VSS
SDM_ADDR[1]
VCCP
VCC
EX_ALE
EX_IOWAIT_N
VSS
EX_ADDR[0]
EX_ADDR[4]
EX_ADDR[7]
EX_ADDR[13]
VCC
EX_ADDR[1]
EX_ADDR[6]
RCOMP
EX_ADDR[3]
VCCP
EX_ADDR[5]
EX_ADDR[9]
EX_ADDR[17]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
72
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 2 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
E1
E2
PCI_AD[23]
VCCP
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
PCI_AD[20]
PCI_IDSEL
VCC
G1
G2
G3
G4
G5
G6
PCI_AD[21]
VCCP
H1
H2
H3
H4
H5
H6
PCI_AD[16]
PCI_AD[18]
VCC
E3
PCI_REQ_N[2]
VSS
PCI_AD[24]
VSS
E4
PCI_REQ_N[0]
VCCP
PCI_CBE_N[3]
VCC
E5
PCI_GNT_N[0]
SDM_DATA[16]
VCCP
PCI_REQ_N[1]
VSS
E6
VCC
PCI_REQ_N[3]
E7
SDM_DATA[31]
VSS
E8
SDM_DATA[30]
VSS
E9
SDM_DATA[17]
VCC
E10
E11
E12
E13
E14
E15
E16
E17
E18
E19
E20
E21
E22
E23
E24
E25
E26
SDM_DATA[22]
VCCP
SDM_DATA[3]
VSS
SDM_DQM[0]
VCCP
SDM_BA[0]
VSS
F17
F18
F19
F20
F21
F22
F23
F24
F25
F26
VCC
SDM_ADDR[4]
VSS
SDM_ADDR[7]
VCCP
SDM_ADDR[3]
USB_DNEG
VCCP
USB_DPOS
VCC
G21
G22
G23
G24
G25
G26
EX_ADDR[2]
VSS
H21
H22
H23
H24
H25
H26
VSS
EX_ADDR[11]
EX_ADDR[18]
VCCP
EX_WR_N
VCC
VSS
EX_ADDR[12]
VSS
EX_ADDR[10]
EX_ADDR[15]
EX_ADDR[19]
EX_ADDR[14]
VCCP
EX_ADDR[20]
EX_ADDR[22]
VSS
EX_ADDR[21]
EX_CS_N[1]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
73
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 3 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
J1
J2
J3
J4
J5
J6
PCI_CLKIN
VCCP
K1
K2
K3
K4
K5
K6
PCI_CBE_N[2]
VSS
L1
L2
L3
L4
L5
PCI_DEVSEL_N
VCCP
M1
M2
M3
M4
M5
PCI_CBE_N[1]
PCI_PAR
VSS
VSS
PCI_AD[17]
VCCP
PCI_STOP_N
VCC
PCI_AD[22]
VSS
PCI_IRDY_N
VCCP
PCI_AD[19]
VCC
PCI_FRAME_N
PCI_AD[29]
L11
L12
L13
L14
L15
L16
VSS
VSS
VSS
VSS
VSS
VSS
M11
M12
M13
M14
M15
M16
VSS
VSS
VSS
VSS
VSS
VSS
J21
J22
J23
J24
J25
J26
EX_ADDR[8]
EX_ADDR[16]
VCC
K21
K22
K23
K24
K25
K26
VCC
VSS
L22
L23
L24
L25
L26
VCCP
M22
M23
M24
M25
M26
EX_CS_N[5]
EX_CLK
EX_CS_N[0]
EX_CS_N[3]
VCCP
VCC
EX_ADDR[23]
EX_CS_N[2]
EX_CS_N[4]
EX_CS_N[6]
EX_DATA[0]
EX_DATA[1]
EX_DATA[2]
VSS
EX_CS_N[7]
EX_DATA[3]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
74
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 4 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
N1
N2
N3
N4
N5
PCI_AD[11]
VCCP
P1
P2
P3
P4
P5
PCI_CBE_N[0]
PCI_AD[14]
PCI_AD[13]
VSS
R1
R2
R3
R4
R5
PCI_AD[10]
VSS
T1
T2
T3
T4
T5
PCI_AD[6]
PCI_TRDY_N
VSS
VCC
PCI_AD[9]
VCC
PCI_PERR_N
PCI_AD[15]
PCI_AD[2]
VCCP
PCI_AD[12]
PCI_AD[4]
N11
N12
N13
N14
N15
N16
VSS
VSS
VSS
VSS
VSS
VSS
P11
P12
P13
P14
P15
P16
VSS
VSS
VSS
VSS
VSS
VSS
R11
R12
R13
R14
R15
R16
VSS
VSS
VSS
VSS
VSS
VSS
T11
T12
T13
T14
T15
T16
VSS
VSS
VSS
VSS
VSS
VSS
N22
N23
N24
N25
N26
VCC
VSS
P22
P23
P24
P25
P26
EX_DATA[6]
EX_DATA[7]
EX_DATA[8]
VCCP
R22
R23
R24
R25
R26
VCCP
T22
T23
T24
T25
T26
EX_RDY_N[0]
VSS
VCC
VCC
EX_DATA[12]
EX_DATA[11]
EX_DATA[10]
EX_DATA[14]
VSS
EX_DATA[4]
EX_DATA[5]
EX_DATA[9]
EX_DATA[13]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
75
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 5 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
U1
U2
U3
U4
U5
U6
PCI_AD[8]
VCCP
V1
V2
V3
V4
V5
V6
PCI_AD[5]
VSS
W1
W2
W3
W4
W5
W6
PCI_AD[1]
VCCP
N/C
Y1
Y2
Y3
Y4
Y5
Y6
N/C
N/C
PCI_AD[0]
PCI_AD[7]
N/C
PCI_AD[3]
VCC
N/C
VSS
VCC
N/C
N/C
VCCP
VCC
VSS
N/C
ETH_TXEN0
U21
U22
U23
U24
U25
U26
VCC
V21
V22
V23
V24
V25
V26
GPIO[6]
GPIO[9]
VCC
W21
W22
W23
W24
W25
W26
GPIO[1]
VCCP
Y21
Y22
Y23
Y24
Y25
Y26
RXDATA1
GPIO[0]
VCC
GPIO[14]
EX_RDY_N[1]
EX_RDY_N[2]
GPIO[15]
GPIO[8]
VSS
GPIO[13]
VCCP
GPIO[5]
VCCP
GPIO[11]
GPIO[12]
EX_DATA[15]
EX_RDY_N[3]
GPIO[10]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
76
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 6 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AA1
AA2
AA3
AA4
AA5
AA6
AA7
AA8
AA9
AA10
N/C
AB1
AB2
N/C
AC1
AC2
VSS
ETH_TXDATA0[0]
VCCP
AD1
AD2
ETH_TXCLK0
ETH_RXDV0
VSS
VCCP
N/C
VSS
N/C
AB3
ETH_TXDATA0[3]
AC3
AD3
AB4
ETH_TXDATA0[1]
AC4
VCC
AD4
ETH_CRS0
ETH_MDC
ETH_TXDATA1[0]
ETH_RXDATA1[3]
ETH_RXCLK1
VSS
ETH_TXDATA0[2]
VCC
AB5
VSS
AC5
ETH_RXDATA0[0]
VSS
AD5
AB6
ETH_RXCLK0
AC6
AD6
ETH_RXDATA0[1]
VSS
AB7
VCCP
AC7
VCC
AD7
AB8
ETH_TXDATA1[2]
AC8
ETH_RXDATA1[2]
VCC
AD8
ETH_TXDATA1[1]
VCC
AB9
ETH_RXDATA1[1]
AC9
AD9
AB10
AB11
AB12
AB13
AB14
AB15
AB16
AB17
AB18
AB19
AB20
VCCP
VCCP
VSS
N/C
AC10
AC11
AC12
AC13
AC14
AC15
AC16
AC17
AC18
AC19
AC20
VCC
AD10
AD11
AD12
AD13
AD14
AD15
AD16
AD17
AD18
AD19
AD20
AD21
AD22
AD23
AD24
AD25
AD26
VSSOSCP
VCCP
VCCOSCP
VCC
PLL_LOCK
PWRON_RESET_N
N/C
RESET_IN_N
VCC
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
VSS
AA17
AA18
AA19
AA20
AA21
AA22
AA23
AA24
AA25
AA26
VCC
N/C
N/C
N/C
VCCP
N/C
VCC
N/C
N/C
N/C
VCCP
VSS
N/C
N/C
N/C
VCC
AB21 SCANTESTMODE_N AC21
VCC
N/C
TXDATA1
VSS
AB22
AB23
AB24
AB25
AB26
VCCP
CTS0_N
CTS1_N
VCCP
AC22
AC23
AC24
AC25
AC26
JTG_TRST_N
VCC
VSS
JTG_TDO
VSS
GPIO[3]
VSS
RXDATA0
RTS1_N
GPIO[2]
TXDATA0
RTS0_N
GPIO[7]
GPIO[4]
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
77
Intel® IXP42X product line and IXC1100 control plane processors
Table 25.
Ball Map Assignment for the Intel® IXP420 Network Processor
and Intel® IXC1100 Control Plane Processor (Sheet 7 of 7)
Ball
Signal
Ball
Signal
Ball
Signal
Ball
Signal
AE1
AE2
ETH_RXDATA0[3]
VCCP
AF1
AF2
ETH_RXDATA0[2]
ETH_MDIO
(Reserved)
ETH_TXDATA1[3]
ETH_TXCLK1
ETH_RXDATA1[0]
ETH_CRS1
VSSOSC
OSC_IN
VSSOSCP
OSC_OUT
VCCOSC
BYPASS_CLK
N/C
AE3
ETH_COL0
ETH_TXEN1
VCCP
AF3
AE4
AF4
AE5
AF5
AE6
ETH_RXDV1
VSS
AF6
AE7
AF7
AE8
ETH_COL1
VCCP
AF8
AE9
AF9
AE10
AE11
AE12
AE13
AE14
AE15
AE16
AE17
AE18
AE19
AE20
AE21
AE22
AE23
AE24
AE25
AE26
VCCPLL1
VSS
AF10
AF11
AF12
AF13
AF14
AF15
AF16
AF17
AF18
AF19
AF20
AF21
AF22
AF23
AF24
AF25
AF26
VCCPLL2
VCCP
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VSS
N/C
N/C
N/C
VCCP
N/C
N/C
N/C
VCCP
N/C
JTG_TDI
VCCP
N/C
JTG_TMS
JTG_TCK
HIGHZ_N
Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and
requirements, see Section 3.0, “Functional Signal Descriptions” on page 32.
4.3
Package Thermal Specifications
The thermal characterization parameter “ΨJT” is proportional to the temperature
difference between the top, center of the package and the junction temperature.
This can be a useful value for verifying device temperatures in an actual environment.
By measuring the package of the device, the junction temperature can be estimated, if
the thermal characterization parameter has been measured under similar conditions.
The use of ΨJT should not be confused with Θjc, which is the thermal resistance from
the device junction to the external surface of the package or case nearest the die
attachment — as the case is held at a constant temperature.
Case temperature = Junction Temperature - (ΨJT * Power
Dissipation)
T
JC = TJ - (ΨJT * Power Dissipation)
The case temperature can then be monitored to make sure that the maximum junction
temperature is not violated. Examples are given in the following sections.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
78
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
4.3.1
Commercial Temperature
“Commercial” temperature range is defined in terms of the ambient temperature range,
which is specified as 0° C to 70° C. The maximum power (P) is 2.4 W and the maximum
junction temperature (Tj) is 115 ° C.
ΨJT for commercial temperature is 0.89° C/W.
Using the preceding junction-temperature formula, the commercial temperature for a
266 MHz device — assuming a maximum power of 2 W — would be:
T
JC = 115° C - (0.89 * 2.0)
JC = 113.22° C
T
4.3.2
Extended Temperature
“Extended” temperature range is defined in terms of the ambient temperature range,
which is specified as -40° C to 85° C. The maximum power (P) is 2.4 W and the
maximum junction temperature (Tj) is 115° C.
ΨJT for extended temperature is 0.32° C/W.
Using the preceding junction-temperature formula, the extended temperature for a 533
MHz device — assuming a maximum power of 2.4 W — would be:
TJC = 115° C - (0.32 * 2.4)
TJC = 114.23° C
5.0
Electrical Specifications
5.1
Absolute Maximum Ratings
Parameter
Maximum Rating
Ambient Air Temperature (Extended)
Ambient Air Temperature (Commercial)
Supply Voltage (Intel XScale® processor)
Supply Voltage I/O
-40º C to 85º C
0º C to 70º C
-0.3 V to 2.1V
-0.3 V to 3.6V
-0.3 V to 2.1V
-0.3 V to 3.6V
-0.3 V to 2.1V
-0.3 V to 2.1V
-0.3 V to 3.6V
-55o C to 125o C
Supply Voltage Oscillator (V
Supply Voltage Oscillator (V
)
CCOSC
)
CCOSCP
Supply Voltage PLL (V
)
CCPLL1
Supply Voltage PLL (V
)
CCPLL2
Voltage On Any I/O Ball
Storage Temperature
Warning:
Stressing the device beyond the “absolute maximum ratings” may cause permanent
damage. These are stress ratings only. Operation beyond the “operating conditions” is
not recommended and extended exposure beyond the “operating conditions” may
affect device reliability.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
79
Intel® IXP42X product line and IXC1100 control plane processors
5.2
V
, V
, V
, V
Pin Requirements
CCOSC
CCPLL1
CCPLL2
CCOSCP
To reduce voltage-supply noise on the analog sections of the Intel® IXP42X Product
Line of Network Processors and IXC1100 Control Plane Processor, the phase-lock loop
circuits (VCCPLL1, VCCPLL2) and oscillator circuit (VCCOSCP, VCCOSC) require isolated
voltage supplies.
The filter circuits for each supply are shown in the following sections.
5.2.1
VCCPLL1 Requirement
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor —
for a first-order filter with a cut-off frequency below 30 MHz — must be connected to
the VCCPLL1 pin of the Intel® IXP42X product line and IXC1100 control plane
processors.
The ground of both capacitors should be connected to the nearest VSS supply pin. Both
capacitors should be located less than 0.5 inch away from the VCCPLL1 pin and the
associated VSS pin. In order to achieve the 200-nF capacitance, a parallel combination
of two 100-nF capacitors may be used as long as the capacitors are placed directly
beside each other.
Figure 9.
VCCPLL1 Power Filtering Diagram
1.3 V
VCCPLL1
Intel® IXP42X
Product Line /
Intel® IXC1100
Control Plane
Processor
10 nF
100 nF
100 nF
VSS
VSS
B1680-03
5.2.2
VCCPLL2 Requirement
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor —
for a first-order filter with a cut-off frequency below 30 MHz — must be connected to
the VCCPLL2 pin of the IXP42X product line and IXC1100 control plane processors.
The ground of both capacitors should be connected to the nearest VSS supply pin. Both
capacitors should be located less than 0.5 inch away from the VCCPLL2 pin and the
associated VSS pin. In order to achieve the 200-nF capacitance, a parallel combination
of two 100-nF capacitors may be used as long as the capacitors are placed directly
beside each other.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
80
August 2006
Document Number: 252479-006US
Intel® IXP42X product line and IXC1100 control plane processors
Figure 10.
VCCPLL2 Power Filtering Diagram
1.3 V
VCCPLL2
100 nF
Intel® IXP42X
Product Line /
Intel® IXC1100
Control Plane
Processor
10 nF
100 nF
VSS
VSS
B1681-03
5.2.3
VCCOSCP Requirement
A single 170-nF capacitor must be connected between the VCCP_OSC pin and VSSP_OSC
pin of the IXP42X product line and IXC1100 control plane processors. This capacitor
value provides both bypass and filtering.
When 170 nF is an inconvenient size, capacitor values between 150 nF to 200 nF could
be used with little adverse effects, assuming that the effective series resistance of the
200-nF capacitor is under 50 mΩ.
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF
capacitors may be used as long as the capacitors are placed directly beside each other.
V
SSP_OSC consists of two pins, AD10 and AF10. Ensure that both pins are connected as
shown in Figure 11.
Figure 11.
VCCOSCP Power Filtering Diagram
3.3 V
VCCOSCP
Intel® IXP42X
Product Line /
Intel® IXC1100
Control Plane
Processor
170 nF
VSSOSCP
VSSOSCP
VSS
B1675-04
5.2.4
VCCOSC Requirement
A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor —
for a first-order filter with a cut-off frequency below 33 MHz — must be connected to
both of the VCCOSC pins of the IXP42X product line and IXC1100 control plane
processors.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
August 2006
Document Number: 252479-006US
81
Intel® IXP42X product line and IXC1100 control plane processors
The grounds of both capacitors should be connected to the VSSOSC supply pin. Both
capacitors should be located less than 0.5 inch away from the VCCOSC pin and the
associated VSSOSC pin.
In order to achieve a 200-nF capacitance, a parallel combination of two 100-nF
capacitors may be used as long as the capacitors are placed directly beside each other.
Figure 12.
VCCOSC Power Filtering Diagram
1.3 V
Intel® IXP42X
Product Line /
Intel® IXC1100
Control Plane
Processor
10 nF
100 nF
100 nF
VSS
B1676-03
5.3
RCOMP Pin Requirements
Figure 13 shows the requirements for the RCOMP pin.
Figure 13.
RCOMP Pin External Resistor Requirements
RCOMP
Intel® IXP42X Product Line /
Intel® IXC1100 Control Plane
Processor
34 Ω,
+ 1%
VSS
VSS
B1672-02
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
5.4
DC Specifications
5.4.1
Operating Conditions
Table 26.
Operating Conditions
Symbol
Parameter
Min.
Typ.
Max.
Units
Notes
V
Voltage supplied to the I/O.
3.135
1.235
3.3
1.3
3.465
1.365
V
V
CCP
V
Voltage supplied to the internal logic.
CC
Voltage supplied to the internal oscillator
logic.
V
1.235
3.135
1.235
1.3
3.3
1.3
1.365
3.465
1.365
V
V
V
CCOSC
V
Voltage supplied to the oscillator I/O.
CCOSCP
Voltage supplied to the analog phase-lock
loop.
V
V
CCPLL1
CCPLL2
Voltage supplied to the analog phase-lock
loop.
1.235
1.3
1.365
V
5.4.2
PCI DC Parameters
Table 27.
PCI DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
0.5 V
V
V
4
3
IH
CCP
V
0.3 V
0.1 V
IL
CCP
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -500 µA
= 1500 µA
0.9 V
V
3
OH
OUT
OUT
CCP
V
I
V
3
OL
CCP
0 < V < V
-10
10
µA
pF
1, 3
2, 3
IL
IN
CCP
C
5
5
IN
I/O or output pin
capacitance
C
pF
2, 3
OUT
C
IDSEL-pin capacitance
Pin inductance
5
pF
2, 3
2, 3
IDSEL
L
20
nH
PIN
Notes:
1.
2.
3.
4.
Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
These values are typical values seen by the manufacturing process and are not tested.
For additional information, see the PCI Local Bus Specification, Rev. 2.2.
Please refer to the product specification update.
5.4.3
USB DC Parameters
Table 28.
USB v1.1 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
1
IH
V
0.8
IL
I
=
OUT
V
Output-high voltage
Output-low voltage
2.8
-10
V
V
OH
-6.1 * V mA
OH
IOUT =
6.1 * V mA
V
I
0.3
10
OL
OH
Input-leakage current
Input-pin capacitance
0 < V < V
µA
pF
IL
IN
CCP
C
5
2
IN
Notes:
1.
2.
Please refer to the product specification update.
These values are typical values seen by the manufacturing process and are not tested
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
5.4.4
UTOPIA Level 2 DC Parameters
Table 29.
UTOPIA Level 2 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
V
V
IH
V
0.8
0.5
IL
V
I
I
= -8 mA
= 8 mA
2.4
-8
OH
OUT
OUT
V
OL
Output current at high
voltage
I
V
V
> 2.4 V
< 0.5 V
mA
mA
OH
OH
OL
Output current at low
voltage
I
8
OL
I
Input-leakage current
Input-pin capacitance
0 < V < V
CCP
-10
10
µA
pF
1
2
IL
IN
C
5
5
IN
I/O or output pin
capacitance
C
pF
2
OUT
Notes:
1.
2.
Input leakage currents include hi-Z output leakage for all bidirectional buffers with tri-state outputs.
These values are typical values seen by the manufacturing process and are not tested.
5.4.5
MII DC Parameters
Table 30.
MII DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
V
V
IH
V
0.8
0.4
IL
V
I
I
= -4 mA
= 4mA
2.4
-8
OH
OUT
OUT
V
OL
Output current at high
voltage
I
V
V
> 2.4 V
< 0.4 V
mA
mA
OH
OH
OL
Output current at low
voltage
I
8
OL
I
Input-leakage current
Input-pin capacitance
0 < V < V
CCP
-10
10
µA
pF
IL
IN
C
5
1
IN
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
5.4.6
MDIO DC Parameters
Table 31.
MDIO DC Parameters (Sheet 1 of 2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
Output-high voltage
Output-low voltage
2.0
V
V
V
V
IH
V
0.8
0.4
IL
V
I
I
= -4 mA
= 4 mA
2.4
OH
OUT
OUT
V
OL
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
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Table 31.
MDIO DC Parameters (Sheet 2 of 2)
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
I
Input-leakage current 0 < V < V
IN
-10
10
µA
pF
pF
IL
CCP
C
Input-pin capacitance
Input-pin capacitance
5
5
1
1
IN
INMDIO
C
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
5.4.7
SDRAM Bus DC Parameters
Table 32.
SDRAM Bus DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
1
2
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
I
I
= -4 mA
= 4 mA
2.4
V
OH
OUT
V
0.4
5
V
OL
IL
OUT
I
0 < V < V
-5
-5
µA
IN
CCP
CCP
Output-leakage
current
I
0 < V < V
5
µA
OL
IN
C
Input-pin capacitance
I/O-pin capacitance
4
5
pF
pF
3
3
INCLK
C
IO
Notes:
1.
V
overshoot: V
= V
+ 2 V for a pulse width < 3 ns, and the pulse width cannot be greater
CCP
IH
IH (MAX)
than one third of the cycle rate.
undershoot: V = -2 V for a pulse width < 3 ns cannot be exceeded.
These values are typical values seen by the manufacturing process and are not tested.
2.
3.
V
IL
IL (MIN)
5.4.8
Expansion Bus DC Parameters
Table 33.
Expansion Bus DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -4 mA
= 4mA
2.4
-10
V
1
1
OH
OUT
V
I
0.4
10
V
OL
OUT
0 < V < V
µA
pF
IL
IN
CCP
C
5
2
IN
Notes:
1.
2.
Test conditions were a 70 pF load to ground.
These values are typical values seen by the manufacturing process and are not tested.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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5.4.9
High-Speed, Serial Interface 0 DC Parameters
Table 34.
High-Speed, Serial Interface 0 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -8 mA
= 8 mA
2.4
-10
V
OH
OUT
OUT
V
I
0.4
10
V
OL
IL
0 < V < V
µA
pF
IN
CCP
C
5
1
Notes
1
IN
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
5.4.10
High-Speed, Serial Interface 1 DC Parameters
Table 35.
High-Speed, Serial Interface 1 DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -8 mA
= 8 mA
2.4
-10
V
OH
OUT
OUT
V
I
0.4
10
V
OL
IL
0 < V < V
µA
pF
IN
CCP
C
5
IN
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
5.4.11
High-Speed and Console UART DC Parameters
Table 36.
UART DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -4 mA
= 4 mA
2.4
-10
V
OH
OUT
V
I
0.4
10
V
OL
OUT
0 < V < V
µA
pF
IL
IN
CCP
C
5
1
IN
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
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5.4.12
GPIO DC Parameters
Table 37.
GPIO DC Parameters
Note
s
Symbol
Parameter
Conditions
Min.
Typ.
Max. Units
V
Input-high voltage
2.0
V
IH
V
Input-low voltage
0.8
0.4
V
V
IL
Output-high voltage for GPIO 0 to
GPIO 13
V
I
OUT = -16 mA
2.4
OH
Output-low voltage for GPIO 0 to
GPIO 13
V
I
= 16 mA
= -4 mA
= 4 mA
V
V
V
OL
OUT
Output-high voltage for GPIO 14 and
GPIO 15
V
I
2.4
-10
OH
OUT
Output-low voltage for GPIO 14 and
GPIO 15
V
I
I
0.4
10
OL
OUT
Input-leakage current
Input-pin capacitance
0 < V < V
µA
pF
IL
IN
CCP
C
5
IN
5.4.13
JTAG AND PLL_LOCK DC Parameters
Table 38.
JTAG AND PLL_LOCK DC Parameters @ 3.3V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
V
Output-high voltage
Output-low voltage
Input-leakage current
Input-pin capacitance
I
I
= -4 mA
= 4 mA
2.4
-10
V
OH
OUT
OUT
V
I
0.4
10
V
OL
IL
0 < V < V
µA
pF
IN
CCP
C
5
1
IN
Note:
1.
These values are typical values seen by the manufacturing process and are not tested.
5.4.14
Reset DC Parameters
Table 39.
PWRON_RESET_N DC Parameters
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
The input voltage
must not exceed
1.3V or long-term
reliability may be
adversely affected.
V
Input-high voltage
1.0
1.3
V
IH
V
Input-low voltage
Input leakage current
Input Capacitance
0.3
10
1
V
IL
0 < V
1.3V
<
IN
I
-500
µA
pF
IL
C
Simulated results.
IN
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Table 40.
RESET_IN_N Parameters @ 3.3V
Symbol
Parameter
Conditions
Min.
Typ.
Max.
Units
Notes
V
Input-high voltage
Input-low voltage
2.0
V
V
IH
V
0.8
IL
5.5
AC Specifications
5.5.1
Clock Signal Timings
Processor Clock Timings
5.5.1.1
Table 41.
Devices’ Clock Timings (Oscillator Reference)
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
V
Input-high voltage
2.0
V
V
IH
V
Input-low voltage
0.8
IL
Clock frequency for IXP42X product line
and IXC1100 control plane processors
oscillator.
T
33.33
MHz
1, 3
FREQUENCY
U
Clock tolerance over -40º C to 85º C.
-50
35
50
65
ppm
pF
FREQUENCY
Pin capacitance of IXP42X product line and
IXC1100 control plane processors’ inputs.
C
5
IN
T
Duty cycle
50
%
2
DC
Notes:
1.
This value is an oscillator input. Use as an oscillator input, tie to the crystal input pin and leave the
crystal output pin disconnected.
2.
3.
This parameter applies when driving the clock input with an oscillator.
Where the IXP42X product line or IXC1100 control plane processor is configured with an input
reference-clock, the slew rate should never be faster than 2.5 V/nS to ensure proper PLL operation.
To help ensure proper PLL operation at the slower slew rate, the VIH and VIL voltage levels need to be
within the specified range at an input clock frequency of 33.33 MHz.
Table 42. Processors’ Clock Timings Spread Spectrum Parameters
Spread-Spectrum
Min
Max
Notes
Conditions
Characterized and guaranteed by design, but not
tested. Do not over-clock the PLL input. The A.C.
timings will not be guaranteed if the device exceeds
33.33 MHz.
Frequency deviation from
33.33 MHz as a percentage
-2.0%
+0.0%
50 KHz
Characterized and guaranteed by design, but not
tested
Modulation Frequency
Notes:
1.
It is important to note that when using spread spectrum clocking, other clocks in the system will
change frequency over a specific range. This change in other clocks can present some system level
limitations. Please refer to the application note titled Spread Spectrum Clocking to Reduce EMI
Application Note, when designing a product that utilizes spread spectrum clocking.
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Figure 14.
Typical Connection to an Oscillator
Intel® IXP42X Product Line /
Intel® IXC1100 Control Plane
Processor
OSC_IN
Oscillator
OSC_OUT
B1678-03
5.5.1.2
PCI Clock Timings
PCI Clock Timings
Table 43.
33 MHz
66 MHz
Symbol
Parameter
Units
Notes
Min.
Max.
Min.
Max.
T
Clock period for PCI Clock
PCI Clock high time
PCI Clock low time
30
11
11
15
6
ns
ns
ns
PERIODPCICLK
T
CLKHIGH
T
6
CLKLOW
Slew Rate requirements for
PCI Clock
T
1
4
1.5
4
V/ns
SLEW RATE
5.5.1.3
MII Clock Timings
Table 44.
MII Clock Timings (Sheet 1 of 2)
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Clock period for Tx and Rx Ethernet
clocks
T
40
40
ns
period100Mbit
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Table 44.
MII Clock Timings (Sheet 2 of 2)
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Clock period for Tx and Rx Ethernet
clocks
T
400
400
ns
period10Mbit
Duty cycle for Tx and Rx Ethernet
clocks
T
35
50
65
%
duty
Frequency
Tolerance
Frequency tolerance requirement
for Tx and Rx Ethernet clocks
+/- 50
+/- 100
ppm
5.5.1.4
UTOPIA Level 2 Clock Timings
UTOPIA Level 2 Clock Timings
Table 45.
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
Clock period for Tx and Rx UTOPIA Level 2
clocks
T
30.303
ns
1
period
Duty cycle for Tx and Rx UTOPIA Level 2
clocks
T
40
50
60
2
%
ns
1
1
duty
Rise and fall time requirements for Tx and
Rx UTOPIA Level 2 clocks
T
rise/fall
Note:
1.
The UTOPIA interface can operate at a minimum frequency greater than 0 Hz.
5.5.1.5
Expansion Bus Clock Timings
Expansion Bus Clock Timings
Table 46.
Symbol
Parameter
Min.
Nom.
Max.
Units
Notes
T
Clock period for expansion-bus clock
Duty cycle for expansion-bus clock
15.15
40
333.33
60
ns
%
period
T
50
duty
Rise and fall time requirements for
expansion-bus clock
T
2
ns
rise/fall
5.5.2
Bus Signal Timings
The AC timing waveforms are shown in the following sections.
5.5.2.1
PCI
Figure 15.
PCI Output Timing
V
V
hi
CLK
low
T
clk2out(b)
Output
Delay
A9572-01
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Note:
V
= 0.6 V and V
= 0.2 V
LOW CC
HI
CC
Figure 16.
PCI Input Timing
CLK
T
setup(b)
T
hold
Inputs
Valid
Input
A9573-01
Table 47.
PCI Bus Signal Timings
33 MHz
66 MHz
Symbol
Parameter
Units
ns
Notes
Min.
Max.
Min.
Max.
Clock to output for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
1, 2, 5,
7, 8
T
2
11
1
6
clk2outb
Clock to output for all point-to-
point signals. This is the
PCI_GNT_N and PCI_REQ_N(0)
only.
1, 2, 5,
7, 8
T
2
7
12
1
3
6
ns
clk2out
Input setup time for all bused
signals. This is the PCI_AD[31:0],
PCI_CBE_N [3:0], PCI_PAR,
PCI_FRAME_N, PCI_IRDY_N,
PCI_TRDY_N, PCI_STOP_N,
PCI_DEVSEL_N, PCI_PERR_N,
PCI_SERR_N
4, 6, 7,
8
T
ns
setupb
Input setup time for all point-to-
point signals. This is the
PCI_REQ_N and PCI_GNT_N(0)
only.
T
10, 12
0
5
0
ns
4, 7, 8
4, 7, 8
setup
T
Input hold time from clock.
ns
ns
hold
5, 6, 7,
8
T
Reset active-to-output float delay
40
40
rst-off
Notes:
1.
2.
3.
See the timing measurement conditions.
Parts compliant to the 3.3 V signaling environment.
REQ# and GNT# are point-to-point signals and have different output valid delay and input setup
times than do bused signals. GNT# has a setup of 10 ns for 33 MHz and 5 ns for 66 MHz; REQ# has
a setup of 12 ns for 33 MHz and 5 ns for 66 MHz.
4.
5.
6.
RST# is asserted and de-asserted asynchronously with respect to CLK.
All PCI outputs must be asynchronously driven to a tri-state value when RST# is active.
Setup time applies only when the device is not driving the pin. Devices cannot drive and receive
signals at the same time.
7.
8.
Timing was tested with a 70-pF capacitor to ground.
For additional information, see the PCI Local Bus Specification, Rev. 2.2.
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5.5.2.2
USB Interface
For timing parameters, see the USB 1.1 specification. The IXP42X product line and
IXC1100 control plane processors’ USB 1.1 interface is a device or function controller
only. The IXP42X product line and IXC1100 control plane processors’ USB v 1.1
interface cannot be line-powered.
5.5.2.3
UTOPIA Level 2 (33 MHz)
UTOPIA Level 2 Input Timings
Figure 17.
Clock
Signals
Tsetup
Thold
A9578-01
Table 48.
UTOPIA Level 2 Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are UTP_IP_DATA[7:0],
UTP_IP_SOC, AND UTP_IP_FCI, and
UTP_OP_FCI.
T
8
ns
ns
setup
Input hold time after the rising edge of the
clock. Inputs included in this timing are
UTP_IP_DATA[7:0], UTP_IP_SOC, and
UTP_IP_FCI, and UTP_OP_FCI.
T
1
hold
Figure 18.
UTOPIA Level 2 Output Timings
Clock
Signals
Tclk2out
Tholdout
A9579-01
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Table 49.
UTOPIA Level 2 Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Rising edge of clock to signal output. Outputs
included in this timing are UTP_IP_DATA[3:0],
UTP_OP_SOC, UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
T
17
ns
1
clk2out
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
UTP_IP_DATA[3:0], UTP_OP_SOC,
T
1
ns
1
holdout
UTP_OP_FCO, UTP_IP_FCO,
UTP_OP_DATA[7:0], and UTP_OP_ADDR[3:0].
Note:
1.
Timing was tested with a 70-pF capacitor to ground.
5.5.2.4
MII
Figure 19.
MII Output Timings
T
T
2
1
eth_tx_clk
eth_tx_data[7:0]
eth_tx_en
eth_crs
A9580-01
Table 50.
MII Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Clock to output delay for ETH_TXDATA and
ETH_TXEN.
T
T
17
ns
1
1
2
ETH_TXDATA and ETH_TXEN hold time after
ETH_TXCLK.
2
ns
Note:
1.
These values satisfy the MII specification requirement of 0 ns to 25 ns clock to output delay.
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Figure 20.
MII Input Timings
T
T
4
3
eth_rx_clk
eth_rx_data[7:0]
eth_rx_dv
eth_crs
A9581-01
Table 51.
MII Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
ETH_RXDATA and ETH_RXDV setup time prior to
rising edge of ETH_RXCLK
T
T
5.5
ns
1, 2
3
4
ETH_RXDATA and ETH_RXDV hold time after the
rising edge of ETH_RXCLK
0
ns
1, 2, 3
Notes:
1.
2.
3.
These values satisfy the MII specification requirement of 10-ns setup and hold time.
Timing tests were performed with a 70-pF capacitor to ground.
This parameter has been simulated but has not been fully tested.
5.5.2.5
MDIO
Figure 21.
MDIO Output Timings
ETH_MDC
ETH_MDIO
T
T
1
2
A9582-02
Note: NPE is sourcing MDIO.
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Figure 22.
MDIO Input Timings
T
5
ETH_MDC
ETH_MDIO
T
T
4
3
A9583-02
Note: PHY is sourcing MDIO.
MDIO Timings Values
Symbol
Table 52.
Parameter
Min.
Max.
Units
Notes
ETH_MDIO, clock to output timing with respect to
rising edge of ETH_MDC clock
ETH_MDC/2
+ 10 ns
T1
T2
T3
ns
ETH_MDIO output hold timing after the rising
edge of ETH_MDC clock
10
2
ns
ns
ETH_MDIO input setup prior to rising edge of
ETH_MDC clock
ETH_MDIO hold time after the rising edge of
ETH_MDC clock
T4
T5
0
ns
ns
1
ETH_MDC clock period
125
500
Note:
1.
This parameter is guaranteed by design but has not been 100% tested.
5.5.2.6
SDRAM Bus
Figure 23.
SDRAM Input Timings
Table 53.
SDRAM Input Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Input setup prior to rising edge of clock. Inputs
included in this timing are SDM_DQ[31:0]
(during a read operation).
T
1.4
ns
setup
Input hold time after the rising edge of the clock.
Inputs included in this timing are SDM_DQ[31:0]
(during a read operation).
T
1.5
ns
hold
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Figure 24.
SDRAM Output Timings
Clock
Signals
Data Valid
T
T
clk2out
holdout
A9584-01
Table 54.
SDRAM Output Timings Values
Symbol
Parameter
Min.
Max.
Units
Notes
Rising edge of clock-to-signal output. Outputs
included in this timing are SDM_ADDR[12:0],
SDM_BA[1:0], SDM_DQM[3:0], SDM_CKE,
SDM_WE_N, SDM_CS_N[1:0], SDM_CAS_N,
SDM_RAS_N, SDM_DQ[31:0] (during a write
operation).
T
5.5
ns
1
clk2out
Signal output hold time after the rising edge of
the clock. Outputs included in this timing are
SDM_DQ[31:0] (during a write operation).
T
1.5
ns
1
holdout
Note:
1.
Timing test were performed with a 70-pF load to ground.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
5.5.2.7
Expansion Bus
Figure 25.
Signal Timing With Respect to Clock Rising Edge
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
EX_CLK
TOV
EX_CS_N[0]
EX_ADDR[23:0]
EX_IOWAIT_N
Valid Address
TOV
EX_RD_N
Thold
Tsetup
EX_DATA[15:0]
EX_WR_N
Data In
TOV
EX_DATA[15:0]
Data Out
B4870-002
Table 55.
Signal Timing With Respect to Clock Rising Edge
Symbol
Description
Min.
Max. Units
Notes
Control signal and data output valid after clock rising
edge
T
15
ns
ov
Tsetup
Thold
Input Setup time with respect to clock rising edge.
Input Hold time with respect to clock rising edge.
3
2
ns
ns
1
1
Note:
1.
The Setup and Hold Timing Values are for all modes.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 26.
Intel® Multiplexed Read Mode
Intel® Multiplexed
Read Mode
T1
T2
T3
T4
T5
1-4 Cycles 1-16 Cycles 1-4 Cycles 1-16 Cycles
2-5 Cycles
ALE Extended
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
EX_ALE
Valid Address
EX_IOWAIT_N
Trdsetup
EX_RD_N
Trdhold
EX_DATA[15:0]
Valid Address
Valid Data
B3747-001
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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August 2006
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 27.
Intel® Multiplexed Write Mode
Intel® Multiplexed
Write Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-16 Cycles 1-4 Cycles
1-16 Cycles
2-5 Cycles
ALE Extended
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
EX_ALE
Valid Address
EX_IOWAIT_N
EX_WR_N
Tdhold2afterwr
Twrpulse
Tdval2valwrt
Tale2addrhold
Valid Address
EX_DATA[15:0]
Valid Data
B3748-001
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Table 56.
Intel® Multiplexed Mode Values
Symbol
Talepulse
Parameter
Min. Max. Units Notes
Pulse width of EX_ALE (ADDR is valid at the rising edge of
EX_ALE)
1
4
Cycles
1, 7
Tale2addrhold Valid address hold time after from falling edge of EX_ALE
1
1
1
4
Cycles 1, 2, 7
Tdval2valwrt
Twrpulse
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
Cycles
Cycles
Cycles
Cycles
ns
3, 7
4, 7
5, 7
7
1
16
4
Tdholdafterwr Valid data after the rising edge of EX_WR_N
1
Tale2valcs
Trdsetup
Trdhold
Valid chip select after the falling edge of EX_ALE
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
1
4
15
0
ns
Time needed between successive accesses on expansion
interface.
Trecov
1
16
Cycles
6
Notes:
1.
2.
3.
4.
5.
6.
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears (read
or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
7.
8.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
9.
Timing tests were performed with a 70-pF capacitor to ground.
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 28.
Intel® Simplex Read Mode
Intel® Simplex Read Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles 1-16 Cycles
1-4 Cycles 1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
EX_ADDR[23:0]
EX_IOWAIT_N
EX_RD_N
Valid Address
Trdsetup
Trdhold
EX_DATA[15:0]
Valid Data
B3749-002
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
101
Intel® IXP42X product line and IXC1100 control plane processors
Figure 29.
Intel® Simplex Write Mode
Intel® Simplex Write Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles 1-16 Cycles
1-4 Cycles 1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
EX_ADDR[23:0]
EX_IOWAIT_N
EX_WR_N
Valid Address
Tdhold2afterwr
Twrpulse
Tdval2valwrt
Taddr2valcs
EX_DATA[15:0]
Valid Data
B3750-002
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Table 57.
Intel Simplex Mode Values
Symbol
Parameter
Min. Max. Units
Notes
T
Valid address to valid chip select
1
1
4
4
Cycles
Cycles
Cycles
Cycles
ns
1, 2, 7
3, 7
addr2valcs
T
Write data valid prior to EX_WR_N falling edge
Pulse width of the EX_WR_N
dval2valwrt
T
1
16
4
4, 7
wrpulse
dholdafterwr
T
Valid data after the rising edge of EX_WR_N
Data valid required before the rising edge of EX_RD_N
Data hold required after the rising edge of EX_RD_N
1
5, 7
T
15
0
rdsetup
T
ns
rdhold
Time required between successive accesses on the
expansion interface.
T
1
16
Cycles
6
recov
Notes:
1.
2.
EX_ALE is not valid in simplex mode of operation.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
3.
4.
5.
6.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
One cycle is the period of the Expansion Bus clock.
7.
8.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
9.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 30.
Motorola* Multiplexed Read Mode
Motorola* Multiplexed
Read Mode
T1
T2
T3
T4
T5
2-5 Cycles
ALE Extended
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
Valid Address
EX_ALE
EX_IOWAIT_N
EX_RD_N
(exp_mot_rnw)
Trdsetup
EX_WR_N
(exp_mot_ds_n)
Trdhold
EX_DATA[15:0]
Valid Address
Valid Data
B3751-001
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 31.
Motorola* Multiplexed Write Mode
Motorola* Multiplexed
Write Mode
T1
T2
T3
T4
T5
2-5 Cycles
1-4 Cycles
1-16 Cycles
1-4 Cycles
1-16 Cycles
ALE Extended
EX_CLK
Trecov
EX_CS_N[0]
Talepulse
Tale2valcs
EX_ADDR[23:0]
EX_ALE
Valid Address
EX_IOWAIT_N
EX_RD_N
(exp_mot_rnw)
Tdspulse
EX_WR_N
(exp_mot_ds_n)
Tdval2valds
Tale2addrhold
Valid Address
EX_DATA[15:0]
Valid Data
B3752-001
Table 58.
Motorola* Multiplexed Mode Values (Sheet 1 of 2)
Symbol
Parameter
Min. Max. Units
Notes
Pulse width of EX_ALE (ADDR is valid at the rising edge of
EX_ALE)
T
1
4
Cycles
1, 7
alepulse
T
Valid address hold time after from falling edge of EX_ALE
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
1
1
1
1
4
Cycles 1, 2, 7
ale2addrhold
T
Cycles
Cycles
3, 7
4, 7
dval2valds
T
16
dspulse
Notes:
1.
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
2.
3.
4.
5.
6.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
7.
8.
9.
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Intel® IXP42X product line and IXC1100 control plane processors
Table 58.
Motorola* Multiplexed Mode Values (Sheet 2 of 2)
Symbol
Parameter
Min. Max. Units
Notes
T
Valid data after the rising edge of EXP_MOT_DS_N
Valid chip select after the falling edge of EX_ALE
1
1
4
4
Cycles
Cycles
ns
5, 7
7
dholdafterds
T
ale2valcs
T
Data valid required before the rising edge of EXP_MOT_DS_N
Data hold required after the rising edge of EXP_MOT_DS_N
15
0
rdsetup
T
ns
rdhold
Time needed between successive accesses on expansion
interface.
T
1
16
Cycles
6
recov
Notes:
1.
The EX_ALE signal is extended from 1 to 4 cycles based on the programming of the T1 timing
parameter. The parameter Tale2addrhold is fixed at 1 cycle.
2.
3.
4.
5.
6.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on the
expansion interface.
One cycle is the period of the Expansion Bus clock.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
7.
8.
9.
Figure 32.
Motorola* Simplex Read Mode
Motorola* Simplex
Read Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles 1-16 Cycles
1-4 Cycles 1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Tad2valcs
EX_ADDR[23:0]
EX_ALE
Valid Address
EX_IOWAIT_N
EX_RD_N
(exp_mot_rnw)
Trdsetup
EX_WR_N
(exp_mot_ds_n)
Trdhold
EX_DATA[15:0]
Valid Data
B3753-001
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 33.
Motorola* Simplex Write Mode
Motorola* Simplex
Write Mode
T1
T2
T3
T4
T5
1-4 Cycles
1-4 Cycles 1-16 Cycles
1-4 Cycles 1-16 Cycles
EX_CLK
Trecov
EX_CS_N[0]
Tad2valcs
EX_ADDR[23:0]
EX_ALE
Valid Address
EX_IOWAIT_N
Tdhold2afterds
EX_RD_N
(exp_mot_rnw)
Tdspulse
EX_WR_N
(exp_mot_ds_n)
Tdval2valds
EX_DATA[15:0]
Valid Data
B3754-001
Table 59.
Motorola* Simplex Mode Values (Sheet 1 of 2)
Symbol
Parameter
Min. Max.
Units
Notes
T
Valid address to valid chip select
1
1
1
1
4
4
Cycles 1, 2, 7
Cycles 3, 7
Cycles 4, 7
Cycles 5, 7
ad2valcs
T
Write data valid prior to EXP_MOT_DS_N falling edge
Pulse width of the EXP_MOT_DS_N
dval2valds
T
16
4
dspulse
dholdafterds
T
Valid data after the rising edge of EXP_MOT_DS_N
Notes:
1.
2.
EX_ALE is not valid in simplex mode of operation.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
3.
4.
5.
6.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
One cycle is the period of the Expansion Bus clock.
7.
8.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
9.
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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Intel® IXP42X product line and IXC1100 control plane processors
Table 59.
Motorola* Simplex Mode Values (Sheet 2 of 2)
Symbol
Parameter
Min. Max.
Units
Notes
Data valid required before the rising edge of
EXP_MOT_DS_N
T
15
ns
rdsetup
Data hold required after the rising edge of
EXP_MOT_DS_N
T
0
ns
rdhold
Time required between successive accesses on the
expansion interface.
T
1
16
Cycles
6
recov
Notes:
1.
2.
EX_ALE is not valid in simplex mode of operation.
Setting the address phase parameter (T1) will adjust the duration that the address appears to the
external device.
3.
4.
5.
6.
Setting the data setup phase parameter (T2) will adjust the duration that the data appears prior to a
data strobe (read or write) to an external device.
Setting the data strobe phase parameter (T3) will adjust the duration that the data strobe appears
(read or write) to an external device. Data will be available during this time as well.
Setting the data hold strobe phase parameter (T4) will adjust the duration that the chip selects,
address, and data (during a write) will be held.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the expansion interface.
One cycle is the period of the Expansion Bus clock.
7.
8.
Clock to output delay for all signals will be a maximum of 15 ns for devices requiring operation in
synchronous mode.
Timing tests were performed with a 70-pF capacitor to ground.
9.
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 34.
HPI-8 Mode Read Accesses
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
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Datasheet
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 35.
HPI-8 Mode Write Accesses
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Intel® IXP42X product line and IXC1100 control plane processors
Table 60.
HPI Timing Symbol Description
State
Description
Min.
Max.
Unit
Notes
T1
T2
T3
T4
T5
Address Timing
Setup/Chip Select Timing
Strobe Timing
3
3
2
3
2
4
4
Cycles
Cycles
Cycles
Cycles
Cycles
1, 5, 6
2, 6
3, 5, 6
6
16
4
Hold Timing
Recovery Phase
17
6
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
6.
7.
Table 61.
HPI-8 Mode Write Access Values
Symbol
Parameter
Min.
Max. Units
Notes
Valid time that address is asserted on the line. The
address is asserted at the same time as chip select.
T
11
45
Cycles
1, 5, 6
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
3
4
4
4
2
4
5
Cycles
Cycles
Cycles
Cycles
Cycles
5, 6
2, 4, 5
3, 5, 6
3, 6
cs2hds1val
hds1_pulse
data_setup
T
T
Pulse width of the HDS1 data strobe
Data valid prior to the rising edge of the HDS1 data
strobe.
5
T
Data valid after the rising edge of the HDS1 data strobe.
36
17
data_hold
Time required between successive accesses on the
expansion interface.
T
4, 6
recov
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
7.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
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Table 62.
HPI-16 Multiplexed Write Accesses Values
Symbol
Parameter
Min. Max.
Units
Cycles 1, 5, 6
Cycles 5, 6
Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
T
11
3
45
4
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
cs2hds1val
T
T
Pulse width of the HDS1 data strobe.
4
4
4
5
5
Cycles 2, 4, 5
Cycles 3, 5, 6
hds1_pulse
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
data_setup
T
36
Cycles
Cycles
3, 6
4, 6
data_hold
Time required between successive accesses on the
expansion interface.
T
2
17
recov
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
6.
7.
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Figure 36.
HPI-16 Multiplexed Write Mode
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Table 63.
HPI-16 Multiplexed Read Accesses Values
Symbol
Parameter
Min. Max.
Units Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
T
11
45
Cycles 1, 5, 6
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
3
4
4
4
5
5
Cycles
5, 6
cs2hds1val
hds1_pulse
data_setup
T
T
Pulse width of the HDS1 data strobe.
Cycles 2, 4, 5
Cycles 3, 5, 6
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
Time required between successive accesses on the
expansion interface.
T
2
17
Cycles
4, 6
recov
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three
T clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
7.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
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Figure 37.
HPI-16 Multiplex Read Mode
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Table 64.
HPI-16 Simplex Read Accesses Values
Min
.
Symbol
Parameter
Max.
Units
Notes
Valid time that address is asserted on the line. The address is
asserted at the same time as chip select.
T
11
45
Cycles 1, 5, 6
Cycles 5, 6
add_setup
Delay from chip select being active and the HDS1 data strobe
being active.
T
3
4
4
4
5
5
cs2hds1val
hds1_pulse
data_setup
T
T
Pulse width of the HDS1 data strobe.
Cycles 2, 4, 5
Cycles 3, 5, 6
Data is valid from the time from of the falling edge of
HDS1_N to when the data is read.
Time required between successive accesses on the expansion
interface.
T
2
17
Cycles
4, 6
recov
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-
active.
4.
5.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
6.
7.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
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Figure 38.
HPI-16 Simplex Read Mode
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Table 65.
HPI-16 Simplex Write Accesses Values
Symbol
Parameter
Min. Max.
Units
Notes
Valid time that address is asserted on the line. The address
is asserted at the same time as chip select.
T
11
3
45
4
Cycles
1, 5, 6
add_setup
Delay from chip select being active and the HDS1 data
strobe being active.
T
Cycles
5, 6
cs2hds1val
T
T
Pulse width of the HDS1 data strobe.
4
4
4
5
5
Cycles
Cycles
Cycles
2, 4, 5
3, 5, 6
3, 6
hds1_pulse
Data valid prior to the rising edge of the HDS1 data strobe.
Data valid after the rising edge of the HDS1 data strobe.
data_setup
T
36
data_hold
Time required between successive accesses on the
expansion interface.
T
2
17
Cycles
4, 6
recov
Notes:
1.
The address phase parameter (T1) must be set to a minimum value of 2. This value allows three T
clocks for the address phase. This setting is required to ensure that in the event of an HRDY, the
Intel® IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to
recognize the HRDY and hold the address phase for at least one clock pulse after the HRDY is de-
active.
2.
3.
The data setup phase parameter (T2) must be set to a minimum value of 2. This value allows three T
clocks for setup phase.
The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T
clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel®
IXP42X Product Line and Intel® IXC1100 Control Plane processors has had sufficient time to recognize
the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de-active.
Setting the recovery phase parameter (T5) will adjust the duration between successive accesses on
the Expansion Bus interface.
HRDY can be asserted by the DSP at any point in the access. The interface will not leave states T1 or
T3 until HRDY is de-active.
One cycle is the period of the Expansion Bus clock.
Timing tests were performed with a 70-pF capacitor to ground.
4.
5.
6.
7.
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 39.
HPI-16 Simplex Write Mode
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
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5.5.2.7.1
EX_IOWAIT_N
The EX_IOWAIT_N signal is available to be shared by devices attached to chip selects 0
through 7, when configured in Intel or Motorola modes of operation. The main purpose
of this signal is to properly communicate with slower devices requiring more time to
respond during data access. During idle cycles, the board is responsible for ensuring
that EX_IOWAIT_N is pulled-up. The Expansion bus controller will always ignore
EX_IOWAIT_N for synchronous Intel mode writes.
Refer to the Using I/O Wait sub-section in the Expansion Bus Controller chapter of the
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane
Processor Developer’s Manual for detailed information.
Figure 40.
I/O Wait Normal Phase Timing
T1=0 h T2=0 h
T3=2h or 1h or 0h
3 Cycles
T4=0 h T5=0 h
1 Cycle
1 Cycle
1 Cycle
1 Cycle
EX_CLK
2 Cycles
EX_CS_N[0]
EX_ADDR[23:0]
Valid Address
EX_IOWAIT_N
EX_RD_N
Valid Data
EX_DATA[15:0]
B5242-01
Note: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last
three clock cycles. The data is returned from the peripheral device prior to the three clocks and the
peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though
the strobe phase was configured to pulse for three clocks.
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Figure 41.
I/O Wait Extended Phase Timing
T1=3 h T2=3 h
4 Cycles 4 Cycles
T3=F h
T4=3 h
4 Cycles
T5=F h
16 Cycles
16 Cycles
....
....
EX_CLK
2 Cycles
EX_CS_N[0]
EX_ADDR[23:0]
Valid Address
EX_IOWAIT_N
EX_RD_N
Valid Data
EX_DATA[15:0]
B5243-01
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5.5.2.8
High-Speed, Serial Interfaces
Figure 42.
High-Speed, Serial Timings
T2
T4
T9
T1
T3
As Inputs:
hss_txclk/
hss_rxclk1
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ rxdata
(Positive edge)
Valid Data
hss_ rxdata
(Negative edge)
Valid Data
T5
T6
T7
T8
As Outputs:
hss_(tx or rx)frame
(Positive edge)
hss_(tx or rx)frame
(Negative edge)
hss_ txdata
(Positive edge)
Valid Data
hss_ txdata
(Negative edge)
Valid Data
A9594-01
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Table 66.
High-Speed, Serial Timing Values
Symbol
Parameter
Min.
Max.
Units Notes
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the rising edge of clock
T1
5
ns
ns
ns
ns
ns
ns
ns
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 4
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the rising edge of clock
T2
T3
T4
T5
T6
T7
0
5
0
Setup time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA prior to the falling edge of clock
Hold time of HSS_TXFRAME, HSS_RXFRAME, and
HSS_RXDATA after the falling edge of clock
Rising edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
15
15
Falling edge of clock to output delay for HSS_TXFRAME,
HSS_RXFRAME, and HSS_TXDATA
1, 3, 4
1, 3, 4
Output Hold Delay after rising edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
0
0
Output Hold Delay after falling edge of final clock for
HSS_TXFRAME, HSS_RXFRAME, and HSS_TXDATA
T8
T9
ns
ns
1, 3, 4
5
HSS_TXCLK period and HSS_RXCLK period
1/8.192 MHz 1/512 KHz
Notes:
1.
HSS_TXCLK and HSS_RXCLK may be coming from external independent sources or being driven by the
IXP42X product line and IXC1100 control plane processors. The signals are shown to be synchronous
for illustrative purposes and are not required to be synchronous.
2.
3.
4.
5.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by an external source
as inputs into the IXP42X product line and IXC1100 control plane processors. Always applicable to
HSS_RXDATA.
The HSS_RXFRAME and HSS_TXFRAME can be configured to accept data on the rising or falling edge of
the given reference clock. HSS_RXFRAME and HSS_RXDATA signals are synchronous to HSS_RXCLK
and HSS_TXFRAME and HSS_TXDATA signals are synchronous to the HSS_TXCLK.
Applicable when the HSS_RXFRAME and HSS_TXFRAME signals are being driven by the IXP42X
product line and IXC1100 control plane processors to an external source. Always applicable to
HSS_TXDATA.
The HSS_TXCLK can be configured to be driven by an external source or be driven by the IXP42X
product line and IXC1100 control plane processors. The slowest clock speed that can be accepted or
driven is 512 KHz. The maximum clock speed that can be accepted or driven is 8.192 MHz. The clock
duty cycle accepted will be 50/50 + 20%.
6.
Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor.
For more information on the HSS Jitter Specifications see the Intel® IXP42X Product
Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.
5.5.2.9
JTAG
Figure 43.
Boundary-Scan General Timings
T
T
bsch
bsel
JTG_TCK
JTG_TMS, JTG_TDI
T
bsis
T
bsih
JTG_TDO
T
bsoh
T
bsod
B0416-01
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Figure 44.
Boundary-Scan Reset Timings
JTG_TRST_N
JTG_TMS
T
bsr
T
T
bsrs bsrh
A9597-01
Table 67.
Boundary-Scan Interface Timings Values
Symbol
Parameter
JTAG_TCK low time
Conditions
Min.
Typ.
Max.
Units Notes
T
50
50
ns
ns
2
2
bscl
T
JTAG_TCK high time
bsch
JTAG_TDI, JTAG_TMS setup time
to rising edge of JTAG_TCK
T
10
10
ns
ns
ns
bsis
bsih
bsoh
bsod
JTAG_TDI, JTAG_TMS hold time
from rising edge of JTAG_TCK
T
JTAG_TDO hold time after falling
edge of JTAG_TCK
T
T
1.5
1
1
JTAG_TDO clock to output from
falling edge of JTAG_TCK
40
ns
ns
ns
T
JTAG_TRST_N reset period
30
10
bsr
JTAG_TMS setup time to rising
edge of JTAG_TRST_N
T
bsrs
JTAG_TMS hold time from rising
edge of JTAG_TRST_N
T
10
ns
bsrh
Notes:
1.
2.
Tests completed with a TBD pF load to ground on JTAG_TDO.
JTAG_TCK may be stopped indefinitely in either the low or high phase.
5.5.3
Reset Timings
The IXP42X product line and IXC1100 control plane processors’ can be reset in any of
the following three modes:
• Cold Reset
• Warm Reset
• Soft Reset.
Normally, a Cold Reset is executed each time power is initially applied to the board, a
Warm Reset is executed when it is only intended to reset the IXP42X product line and
IXC1100 control plane processors, and a Soft Reset is executed by the watchdog timer.
5.5.3.1
Cold Reset
A Cold Reset condition is when the network processor is initially powered-up and has
successfully come out of the Reset. During this state all internal modules and registers
are set to the initial default state. To successfully come out of reset, two things must
occur:
• Proper power sequence as described in Section 5.6, “Power Sequence” on page 127
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• Followed by proper resetting of PWRON_RST_N and RESET_IN_N signals as
described in Section 5.5.3.4, “Reset Timings” on page 126
The following procedural sequence must be followed to achieve a successful cold reset:
1. VCC and VCC33 power supplies must reach steady state
2. Hold PWRON_RST_N and RESET_IN_N asserted for 2000nSec
3. De-assert PWRON_RST_N (signal goes high with the help of a pull-up resistor)
4. Continue to hold RESET_IN_N asserted for at least 10nSec more after releasing
PWRON_RST_N
5. De-assert RESET_IN_N (signal goes high with the help of a pull-up resistor)
6. The network processor asserts PLL_LOCK indicating that the processor has
successfully come out of Reset
5.5.3.2
Hardware Warm Reset
A Hardware Warm Reset can only be asserted when PWRON_RST_N is de-asserted and
the network processor is in a normal operating mode. A Hardware Warm Reset is
initiated by the assertion of RESET_IN_N. During this state, all internal registers and
modules are set to their initial default state except for the PLL internal modules. Since
the PLL modules are not reset, the Reset sequence is executed much faster by the
processor.
The following procedural sequence must be followed to achieve a successful Warm
Reset:
1. The system must have previously completed a Cold Reset successfully.
2. PWRON_RST_N must be de-asserted (held high for the entire process).
3. Hold RESET_IN_N asserted for 500nSec.
4. De-assert RESET_IN_N (signal goes high with the help of a pull-up resistor)
5. The network processor asserts PLL_LOCK indicating that the processor has
successfully come out of reset.
5.5.3.3
Soft Reset
A Soft Reset condition is accomplished by the usage of the hardware Watch-Dog Timer
module, and software to manage and perform counter updates. For a complete
description of Watch-Dog Timer functionality, refer to Watchdog Timer sub-section in
the Timers Chapter of the Intel® IXP42X Product Line of Network Processors and
IXC1100 Control Plane Processor Developer’s Manual.
The Soft Reset is similar to what is described in Section 5.5.3.2. The main difference is
that there is no hardware requirement; everything is done within the network
processor and software support. That is why it is also referred to as a Soft Warm Reset.
Since Hardware Warm Reset and Soft Reset are very similar, there must be a way to
determine which reset was last executed after recovering. This is done by reading the
Timer Status Register bit 4 (Warm Reset). If this bit was last set to 1, it will indicate
that a Soft Reset was executed, and if the bit was last reset to 0, then it will indicate
that the processor has just come out of either a Hardware Warm Reset or a Cold Reset.
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5.5.3.4
Reset Timings
Reset Timings
Figure 45.
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Table 68.
Reset Timings Table Parameters
Symbol
Parameter
Min.
Typ.
Max.
Units
Note
Minimum time required to hold the
PWRON_RST_N at logic 0 state after
stable power has been applied to the
IXP42X product line and IXC1100 control
plane processors.
T
T
2000
ns
1
RELEASE_PWRON_RST_N
Minimum time required to hold the
RESET_IN_N at logic 0 state after
PWRON_RST_N has been released to a
logic 1 state. The RESET_IN_N signal
must be held low when the
10
ns
RELEASE_RESET_IN_N
PWRON_RST_N signal is held low.
Maximum time for PLL_LOCK signal to
drive to logic 1 after RESET_IN_N is
driven to logic 1 state. The boot
sequence does not occur until this period
is complete.
T
T
T
10
µs
ns
ns
PLL_LOCK
Minimum time for the EX_ADDR signals
to drive the inputs prior to RESET_IN_N
being driven to logic 1 state. This is used
for sampling configuration information.
50
0
2
2
EX_ADDR_SETUP
EX_ADDR_HOLD
Minimum/maximum time for the
EX_ADDR signals to drive the inputs prior
to PLL_LOCK being driven to logic 1
state. This is used for sampling
configuration information.
20
Minimum time required to drive
RESET_IN_N signal to logic 0 in order to
cause a Warm Reset in the IXP42X
product line and IXC1100 control plane
processors. During this period, the power
supply must not be disturbed and
PWRON_RST_N signal must remain at
logic high during the entire process.
T
500
ns
WARM_RESET
Notes:
1.
2.
T
is the time required for the internal oscillator to reach stability.
RELEASE_PWRON_RST_N
The expansion bus address is captured as a derivative of the RESET_IN_N signal going high. When a
programmable-logic device is used to drive the EX_ADDR signals instead of pull-downs, the signals
must be active until PLL_LOCK goes high.
3.
PLL_LOCK is deasserted immediately when watchdog timer event occurs, or when RESET_IN_N is
asserted, or when PWRON_RST_N is asserted. PLL_LOCK remains deasserted for ~24 ref_clocks after
the watchdog reset is deasserted (internal to the chip). A ref clock time period is 1/CLKIN.
5.6
Power Sequence
The 3.3-V I/O voltage (VCCP) must be powered up 1 µs before the Intel XScale®
processor voltage (VCC). The IXP42X product line and IXC1100 control plane
processors’ voltage (VCC) must never become stable prior to the 3.3-V I/O voltage
(VCCP). The VCCOSC, VCCPLL1, and VCCPLL2 voltages follow the VCC power-up pattern. The
VCCOSCP follows the VCCP power-up pattern. The value for TPOWER_UP must be at least
1 µs. The TPOWER_UP timing parameter is measured from VCCP at 3.3 V and VCC at 1.3 V.
There are no power-down requirements for the IXP42X product line and IXC1100
control plane processors.
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Intel® IXP42X product line and IXC1100 control plane processors
Figure 46.
Power-Up Sequence Timing
VCCP
VCC
TPOWER _UP
4
3
2
1
TIME
B2263-02
5.7
I and Total Average Power
CC
Table 69.
I
CC and Total Average Power – Commercial Temperature Range (Sheet 1 of 2)
Typical
Average Max
Speed
Symbol
Description
Current and
Max Current2
Power2
Power1
Intel XScale®
processor
I
0.70A
0.17A
1.5W
0.725A
0.26A
1.0W
0.9W
1.9W
CC_TOTAL
supply current
I/O supply
current
266 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
TOTAL
Intel XScale®
processor
I
0.75A
0.17A
1.57W
0.800A
0.26A
1.09W
0.9W
2.0W
CC_TOTAL
supply current
I/O supply
current
400 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
TOTAL
Notes:
1.
Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel®
IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon
samples. A SmartBits* tester was used in a router application running Linux* on the
KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this
router application. Typical case power supply voltages VCC =1.327V, VCCP = 3.363 V. Typical
operating temperature is room temperature.
Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V,
VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and
ICCP are steady state currents at maximum operating temperature.
2.
3.
4.
I
I
includes total current for V , V
, V
, and V
CC_TOTAL
CC
CCOSC
CCPLL1 CCPLL2
includes total current for V , V
CCP_TOTAL
CCP CCOSCP
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Table 69.
ICC and Total Average Power – Commercial Temperature Range (Sheet 2 of 2)
Typical
Current and
Power1
Average Max
Power2
Speed
Symbol
Description
Max Current2
Intel XScale®
processor
supply current
I
0.82A
0.17A
1.66W
1.00A
0.26A
1.4W
0.9W
2.3W
CC
I/O supply
current
533 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
TOTAL
Notes:
1.
Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel®
IXDP425 / IXCDP1100 Development Platform at room temperature using typical SKU silicon
samples. A SmartBits* tester was used in a router application running Linux* on the
KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this
router application. Typical case power supply voltages VCC =1.327V, VCCP = 3.363 V. Typical
operating temperature is room temperature.
Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V,
VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and
ICCP are steady state currents at maximum operating temperature.
2.
3.
4.
I
I
includes total current for V , V
, V
, and V
CC_TOTAL
CC
CCOSC
CCPLL1 CCPLL2
includes total current for V , V
CCP_TOTAL
CCP CCOSCP
Table 70.
ICC and Total Average Power – Extended Temperature Range (Sheet 1 of 2)
Typical
Average Max.
Power2
Speed
Symbol
Description
Current and
Max. Current2
Power1
Intel XScale®
processor
I
0.70A
0.17A
1.5W
0.95A
0.26A
1.3W
0.9W
2.2W
CC_TOTAL
supply current
I/O supply
current
266 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
TOTAL
Intel XScale®
processor
I
0.75A
0.17A
1.57W
1.05A
0.26A
1.43W
0.9W
CC_TOTAL
supply current
I/O supply
current
400 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
2.33W
TOTAL
Notes:
1.
Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel® IXDP425 /
IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A
SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet
NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power
supply voltages VCC = 1.327 V, VCCP = 3.363 V. Typical operating temperature is room temperature.
Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V,
VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and ICCP are
steady state currents at maximum operating temperature.
2.
3.
4.
I
I
includes total current for V , V
, V
, and V
CC_TOTAL
CCP_TOTAL
CC
CCOSC
CCPLL1 CCPLL2
includes total current for V , V
CCP CCOSCP
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
August 2006
Document Number: 252479-006US
Datasheet
129
Intel® IXP42X product line and IXC1100 control plane processors
Table 70.
ICC and Total Average Power – Extended Temperature Range (Sheet 2 of 2)
Typical
Average Max.
Speed
Symbol
Description
Current and
Max. Current2
Power2
Power1
Intel XScale®
processor
supply current
I
0.82A
0.17A
1.66W
1.15A
0.26A
1.57W
0.9W
CC_TOTAL
I/O supply
current
533 MHz
I
CCP_TOTAL
Total average
power both
supplies
P
2.47W
TOTAL
Notes:
1.
Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel® IXDP425 /
IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A
SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet
NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power
supply voltages VCC = 1.327 V, VCCP = 3.363 V. Typical operating temperature is room temperature.
Maximum voltages: VCC = 1.365 V, VCCP = 3.465 V, VCCosc= 1.365 V, VCCPLL1= 1.365 V,
VCCPLL2= 1.365 V, maximum capacitive loading on all I/O pins of 50 pF. Maximum ICC and ICCP are
steady state currents at maximum operating temperature.
2.
3.
4.
I
I
includes total current for V , V
, V
, and V
CC_TOTAL
CCP_TOTAL
CC
CCOSC
CCPLL1 CCPLL2
includes total current for V , V
CCP CCOSCP
6.0
Ordering Information
For ordering information, please contact your local Intel sales representative.
Please refer to Table 21 on page 50 for the part numbers of the Intel® IXP42X Product
Line of Network Processors.
§ §
Intel® IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Datasheet
130
August 2006
Document Number: 252479-006US
相关型号：
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