SN74ABT3611-15PQ [ROCHESTER]
64X36 OTHER FIFO, 10ns, PQFP132, PLASTIC, BQFP-132;
| 型号： | SN74ABT3611-15PQ |
| 厂家： | 
Rochester Electronics |
| 描述： | 64X36 OTHER FIFO, 10ns, PQFP132, PLASTIC, BQFP-132 先进先出芯片 信息通信管理 |
| 文件： | 总30页 (文件大小：1135K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
Empty Flag and Almost-Empty Flag
Synchronized by CLKB
64 × 36 Clocked FIFO Buffering Data From
Passive Parity Checking on Each Port
Port A to Port B
Parity Generation Can Be Selected for Each
Port
Mailbox-Bypass Register In Each Direction
Programmable Almost-Full and
Almost-Empty Flags
Low-Power Advanced BiCMOS Technology
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 10 ns
Microprocessor Interface Control Logic
Full Flag and Almost-Full Flag
Synchronized by CLKA
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Plastic Quad
Flat (PQ) Packages
description
The SN74ABT3611 is a high-speed, low-power BiCMOS clocked FIFO memory. It supports clock frequencies
up to 67 MHz and has read access times as fast as 10 ns. A 64 × 36 dual-port SRAM FIFO buffers data from
port A to port B. The FIFO has flags to indicate empty and full conditions and two programmable flags (almost
full and almost empty) to indicate when a selected number of words is stored in memory. Communication
between each port takes place through two 36-bit mailbox registers. Each mailbox register has a flag to signal
when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired.
Paritygenerationcanbeselectedfordatareadfromeachport. Twoormoredevicesareusedinparalleltocreate
wider datapaths.
The SN74ABT3611 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port
are arranged to provide a simple bidirectional interface between microprocessors and/or buses with
synchronous control.
The full flag (FF) and almost-full (AF) flag of the FIFO are two-stage synchronized to the port clock that writes
data to its array (CLKA). The empty flag (EF) and almost-empty (AE) flag of the FIFO are two-stage
synchronized to the port clock that reads data from its array.
The SN74ABT3611 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the following application reports:
•
•
•
FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature
number SCAA007)
Parity-Generate and Parity-Check Features for High-Bandwidth-Computing FIFO Applications
(literature number SCAA015)
Metastability Performance of Clocked FIFOs (literature number SCZA004)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
PCB PACKAGE
(TOP VIEW)
A23
A22
A21
GND
A20
A19
A18
A17
A16
A15
A14
A13
A12
A11
A10
GND
A9
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
B22
B21
GND
B20
B19
B18
B17
B16
B15
B14
B13
B12
B11
B10
GND
B9
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B8
B7
A8
A7
V
B6
CC
V
CC
A6
B5
B4
B3
GND
B2
B1
B0
EFB
AEB
NC
A5
A4
A3
GND
A2
A1
A0
NC
NC
NC – No internal connection
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
†
PQ PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 132 130 128
131
129
126 124
122 120 118
121 119
127
125 123
117
116
GND
NC
NC
A0
A1
A2
GND
A3
A4
A5
A6
GND
AEB
EFB
B0
B1
B2
GND
B3
B4
B5
B6
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
V
CC
CC
A7
A8
A9
GND
A10
A11
B7
B8
B9
GND
B10
B11
V
98
V
CC
CC
A12
A13
A14
GND
A15
A16
A17
A18
A19
A20
GND
A21
A22
A23
97
B12
B13
B14
GND
B15
B16
B17
B18
B19
B20
GND
B21
B22
B23
96
95
94
93
92
91
90
89
88
87
86
85
84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
functional block diagram
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBF1
PEFB
Parity
Gen/Check
MBA
Mail1
Register
RST
PGB
Device
ODD/
EVEN
Control
64 × 36
SRAM
36
36
Write
Pointer
Read
Pointer
A0–A35
B0–B35
Status-Flag
FF
AF
EF
AE
Logic
FIFO
Programmable-
Flag
Offset Register
FS0
FS1
PGA
Mail2
Register
Parity
Gen/Check
PEFA
MBF2
CLKB
CSB
W/RB
ENB
MBB
Port-B
Control
Logic
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
I/O
I/O
O
DESCRIPTION
A0–A35
Port-A data. The 36-bit bidirectional data port for side A.
Almost-empty flag. Programmable flag synchronized to CLKB. AE is low when the number of words in the FIFO is less
than or equal to the value in the offset register, X.
AE
Almost-full flag. Programmable flag synchronized to CLKA. AF is low when the number of empty locations in the FIFO
is less than or equal to the value in the offset register, X.
AF
O
I/O
I
B0–B35
CLKA
Port-B data. The 36-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. FF and AF are synchronized to the low-to-high transition of CLKA.
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. EF and AE are synchronized to the low-to-high transition of CLKB.
CLKB
CSA
CSB
I
I
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A35 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0–B35 outputs are in the high-impedance state when CSB is high.
Empty flag. EF is synchronized to the low-to-high transition of CLKB. When EF is low, the FIFO is empty and reads from
its memory are disabled. Data can be read from the FIFO to its output register when EF is high. EF is forced low when
the device is reset and is set high by the second low-to-high transition of CLKB after data is loaded into empty FIFO
memory.
EF
O
ENA
ENB
I
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Full flag. FF is synchronized to the low-to-high transition of CLKA. When FF is low, the FIFO is full and writes to its
memory are disabled. FF is forced low when the device is reset and is set high by the second low-to-high transition of
CLKA after reset.
FF
O
Flag-offset selects. The low-to-high transition of RST latches the values of FS0 and FS1, which loads one of four preset
values into the almost-full and almost-empty offset register, X.
FS1, FS0
MBA
I
I
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation.
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B35 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
the FIFO output register data for output.
MBB
MBF1
MBF2
I
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
to the mail1 register are inhibited while MBF1 is low. MBF1 is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1 is set high when the device is reset.
O
O
I
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
to the mail2 register are inhibited while MBF2 is low. MBF2 is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when the device is reset.
Odd/even parity select. Odd parity is checked on each port when ODD/EVEN is high and even parity is checked when
ODD/EVEN is low. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled
for a read operation.
ODD/
EVEN
Port-A parity error flag. When any byte applied to A0–A35 fails parity, PEFA is low. Bytes are organized as A0–A8,
A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte serving as the parity bit. The type of parity
checked is determined by the state of ODD/EVEN.
O
PEFA
(port A)
The parity trees used to check the A0–A35 inputs are shared by the mail2 register to generate parity if parity generation
is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA low, ENA high, W/RA low,
MBA high, and PGA high, PEFA is forced high, regardless of the state of the A0 –A35 inputs.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
Terminal Functions (continued)
TERMINAL
NAME
I/O
DESCRIPTION
Port-B parity error flag. When any byte applied to terminals B0–B35 fails parity, PEFB is low. Bytes are organized as
B0–B8, B9–B17, B18–B26, andB27–B35, withthemost-significantbitofeachbyteservingastheparitybit. Thetype
of parity checked is determined by the state of ODD/EVEN.
O
PEFB
(port B)
TheparitytreesusedtochecktheB0–B35inputsaresharedbythemail1registertogenerateparityifparitygeneration
is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB low, ENB high, W/RB
low, MBB high, and PGB high, PEFB is forced high regardless of the state of the B0–B35 inputs.
Port-A parity generation. Parity is generated for mail2 register reads from port A when PGA is high. The type of parity
generatedis selected by the state of ODD/EVEN. Bytes are organized as A0–A8, A9–A17, A18–A26, and A27–A35.
The generated parity bits are output in the most-significant bit of each byte.
PGA
PGB
RST
I
I
I
Port-B parity generation. Parity is generated for data reads from port B when PGB is high. The type of parity generated
is selected by the state of ODD/EVEN. Bytes are organized as B0–B8, B9–B17, B18–B26, and B27–B35. The
generated parity bits are output in the most significant bit of each byte.
Reset. To reset the device, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
whileRSTislow. ThissetsAF, MBF1, andMBF2highandEF, AE, andFFlow. Thelow-to-hightransitionofRSTlatches
the status of FS1 and FS0 to select AF and AE flag offset.
Port-A write/read select. W/RA high selects a write operation and a low selects a read operation on port A for a
low-to-high transition of CLKA. The A0–A35 outputs are in the high-impedance state when W/RA is high.
W/RA
W/RB
I
I
Port-B write/read select. W/RB high selects a write operation and a low selects a read operation on port B for a
low-to-high transition of CLKB. The B0–B35 outputs are in the high-impedance state when W/RB is high.
detailed description
reset
The SN74ABT3611 is reset by taking the reset (RST) input low for at least four port-A clock (CLKA) and four
port-B clock (CLKB) low-to-high transitions. RST can switch asynchronously to the clocks. A device reset
initializes the internal read and write pointers of the FIFO and forces the full flag (FF) low, the empty flag (EF)
low, the almost-empty flag (AE) low, and the almost-full flag (AF) high. A reset also forces the mailbox flags
(MBF1, MBF2) high. After a reset, FF is set high after two low-to-high transitions of CLKA. The device must be
reset after power up before data is written to its memory.
A low-to-high transition on RSTloads the almost-full and almost-empty offset register (X) with the value selected
by the flag-select (FS0, FS1) inputs. The values that can be loaded into the register are shown in Table 1.
Table 1. Flag Programming
ALMOST-FULL AND
FS1
FS0
RST
ALMOST-EMPTY FLAG
OFFSET REGISTER (X)
H
H
L
H
L
↑
↑
↑
↑
16
12
8
H
L
L
4
FIFO write/read operation
The state of the port-A data (A0–A35) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A35 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A35 outputs are active when both CSA and W/RA are low. Data is loaded into the FIFO from the
A0–A35 inputs on a low-to-high transition of CLKA when CSA is low, W/RA is high, ENA is high, MBA is low,
and FF is high (see Table 2).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
FIFO write/read operation (continued)
Table 2. Port-A Enable Function Table
CSA W/RA ENA
MBA CLKA
A0–A35 OUTPUTS
PORT FUNCTION
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, mail2 register
Active, mail2 register
Active, mail2 register
Active, mail2 register
None
None
FIFO write
Mail1 write
None
H
H
L
H
L
↑
X
↑
L
H
L
L
None
L
H
H
X
↑
None
L
H
Mail2 read (set MBF2 high)
The port-B control signals are identical to those of port A. The state of the port-B data (B0–B35) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B35 outputs are
in the high-impedance state when either CSB or W/RB is high. The B0–B35 outputs are active when both CSB
and W/RB are low. Data is read from the FIFO to the B0–B35 outputs by a low-to-high transition of CLKB when
CSB is low, W/RB is low, ENB is high, MBB is high, and EF is high (see Table 3).
Table 3. Port-B Enable Function Table
CSB W/RB ENB
MBB CLKB
B0–B35 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO output register
Active, FIFO output register
Active, mail1 register
PORT FUNCTION
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
None
None
None
H
H
L
H
L
↑
Mail2 write
None
X
↑
L
H
L
L
FIFO read
L
H
H
X
↑
None
L
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects (CSA, CSB) and write/read
selects (W/RA, W/RB) are only for enabling write and read operations and are not related to high-impedance
control of the data outputs. If a port enable is low during a clock cycle, the port-chip select and write/read select
can change states during the setup- and hold-time window of the cycle.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
synchronized FIFO flags
EachFIFOflagissynchronizedtoitsportclockthroughtwoflip-flopstages. Thisisdonetoimproveflagreliability
by reducing the probability of metastable events on their outputs when CLKA and CLKB operate
asynchronously to one another. FF and AF are synchronized to CLKA. EF and AE are synchronized to CLKB.
Table 4 shows the relationship of the flags to the FIFO.
Table 4. FIFO Flag Operation
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
NUMBER OF WORDS
IN THE FIFO
EF
L
AE
L
AF
H
H
H
L
FF
H
H
H
H
L
0
1 to X
H
H
H
H
L
(X + 1) to [64 – (X + 1)]
(64 – X) to 63
64
H
H
H
L
†
Xisthevalueinthealmost-emptyflagandalmost-fullflagoffsetregister.
empty flag (EF)
The FIFO empty flag is synchronized to the port clock that reads data from its array (CLKB). When EF is high,
new data can be read to the FIFO output register. When EF is low, the FIFO is empty and attempted FIFO reads
are ignored.
The FIFO read pointer is incremented each time a new word is clocked to its output register. A word written to
the FIFO can be read to the FIFO output register in a minimum of three port-B clock (CLKB) cycles; therefore,
EF is low if a word in memory is the next data to be sent to the FIFO output register and two CLKB cycles have
not elapsed since the time the word was written. The empty flag of the FIFO is set high by the second low-to-high
transition of CLKB, and the new data word can be read to the FIFO output register in the following cycle.
A low-to-high transition on CLKB begins the first synchronization cycle of a write if the clock transition occurs
at time t , or greater, after the write. Otherwise, the subsequent CLKB cycle can be the first synchronization
sk1
cycle (see Figure 4).
full flag (FF)
The FIFO full flag is synchronized to the port clock that writes data to its array (CLKA). When FF is high, an
SRAM location is free to receive new data. No memory locations are free when FF is low and attempted writes
to the FIFO are ignored.
Each time a word is written to the FIFO, its write pointer is incremented. From the time a word is read from the
FIFO, its previous memory location is ready to be written in a minimum of three port-A clock cycles. FF is low
if less than two CLKA cycles have elapsed since the next memory write location has been read. The second
low-to-high transition on CLKA after the read sets FF high and data can be written in the following clock cycle.
A low-to-high transition on CLKA begins the first synchronization cycle of a read if the clock transition occurs
at time t , or greater, after the read. Otherwise, the subsequent clock cycle can be the first synchronization
sk1
cycle (see Figure 5).
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
almost-empty flag (AE)
The FIFO almost-empty flag is synchronized to the port clock that reads data from its array (CLKB). The
almost-empty state is defined by the value of the almost-full and almost-empty offset register (X). This register
is loaded with one of four preset values during a device reset (see reset). AE is low when the FIFO contains
X or fewer words in memory and is high when the FIFO contains (X + 1) or more words.
Two low-to-high transitions on the port-B clock (CLKB) are required after a FIFO write for the almost-empty flag
to reflect the new level of fill. The almost-empty flag (AE) of a FIFO containing (X + 1) or more words remains
low if two CLKB cycles have not elapsed since the write that filled the memory to the (X + 1) level. AE is set high
by the second CLKB low-to-high transition after the FIFO write that fills memory to the (X + 1) level. A low-to-high
transition on CLKB begins the first synchronization cycle if it occurs at time t , or greater, after the write that
sk2
fills the FIFO to (X + 1) words. Otherwise, the subsequent CLKB cycle can be the first synchronization cycle
(see Figure 6).
almost-full flag (AF)
The FIFO almost-full flag is synchronized to the port clock that writes data to its array (CLKA). The almost-full
state is defined by the value of the almost-full and almost-empty offset register (X). This register is loaded with
one of four preset values during a device reset (see reset). AF is low when the FIFO contains (64 – X) or more
words in memory and is high when the FIFO contains [64 – (X + 1)] or fewer words.
Two low-to-high transitions on the port-A clock (CLKA) are required after a FIFO read for AF to reflect the new
level of fill. The almost-full flag of a FIFO containing [64 – (X + 1)] or fewer words remains low if two CLKA cycles
have not elapsed since the read that reduced the number of words in memory to [64 – (X + 1)]. AF is set high
by the second CLKA low-to-high transition after the FIFO read that reduces the number of words in memory
to [64 – (X + 1)]. A low-to-high transition on CLKA begins the first synchronization cycle if it occurs at time t
,
sk2
or greater, after the read that reduces the number of words in memory to [64 – (X + 1)]. Otherwise, the
subsequent CLKA cycle can be the first synchronization cycle (see Figure 7).
mailbox registers
Two 36-bit bypass registers are on the SN74ABT3611 to pass command and control information between port
A and port B. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO for a
port-data-transfer operation. A low-to-high transition on CLKA writes A0–A35 data to the mail1 register when
a port-A write is selected by(CSA, W/RA, and ENA) with MBA high. A low-to-high transition on CLKB writes
B0–B35 data to the mail2 register when a port-B write is selected by (CSB, W/RB, and ENB) with MBB high.
Writingdatatoamailregistersetsitscorrespondingflag(MBF1orMBF2)low. Attemptedwritestoamailregister
are ignored while its mail flag is low.
When the port-B data (B0–B35) outputs are active, the data on the bus comes from the FIFO output register
whenMBBislowandfromthemail1registerwhenMBBishigh. Mail2dataisalwayspresentonA0–A35outputs
when they are active. The mail1 register flag (MBF1) is set high by a low-to-high transition on CLKB when a
port-B read is selected by CSB, W/RB, and ENB with MBB high. The mail2 register flag (MBF2) is set high by
a low-to-high transition on CLKA when a port-A read is selected by CSA, W/RA, and ENA with MBA high. The
data in a mail register remains intact after it is read and changes only when new data is written to the register.
parity checking
The port-A (A0–A35) inputs and port-B (B0–B35) inputs each have four parity trees to check the parity of
incoming (or outgoing) data. A parity failure on one or more bytes of the input bus is reported by a low level on
the port-parity-error flag (PEFA, PEFB). Odd or even parity checking can be selected and the parity-error flags
can be ignored if this feature is not desired.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
parity checking (continued)
Parity status is checked on each input bus according to the level of the odd/even parity (ODD/EVEN) select
input. A parity error on one or more bytes of a port is reported by a low level on the corresponding port parity
error flag (PEFA, PEFB) output. Port-A bytes are arranged as A0–A8, A9–A17, A18–A26, and A27–A35, and
port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35. When odd/even parity is selected,
PEFA, PEFB is low if any byte on the port has an odd/even number of low levels applied to its bits.
The four parity trees used to check the A0–A35 inputs are shared by the mail2 register when parity generation
is selected for port-A reads (PGA = high). When a port-A read from the mail2 register with parity generation is
selected with CSA low, ENA high, W/RA low, MBA high, and PGA high, PEFA is held high, regardless of the
levels applied to the A0–A35 inputs. Likewise, the parity trees used to check the B0–B35 inputs are shared
by the mail1 register when parity generation is selected for port-B reads (PGB = high). When a port-B read from
the mail1 register with parity generation is selected with CSB low, ENB high, W/RB low, MBB high, and PGB
high, PEFB is held high, regardless of the levels applied to the B0–B35 inputs.
parity generation
A high level on the port-A parity-generate select (PGA) or port-B parity-generate select (PGB) enables the
SN74ABT3611 to generate parity bits for port reads from a FIFO or mailbox register. Port-A bytes are arranged
as A0–A8, A9–A17, A18–A26, and A27–A35, with the most-significant bit of each byte used as the parity bit.
Port-B bytes are arranged as B0–B8, B9–B17, B18–B26, and B27–B35, with the most-significant bit of each
byte used as the parity bit. A write to a FIFO or mail register stores the levels applied to all 36 inputs, regardless
of the state of the parity-generate select (PGA, PGB) inputs. When data is read from a port with parity generation
selected, the lower eight bits of each byte are used to generate a parity bit according to the level on the
ODD/EVEN select. The generated parity bits are substituted for the levels originally written to the
most-significant bits of each byte as the word is read to the data outputs.
Parity bits for FIFO data are generated after the data is read from SRAM and before the data is written to the
output register. Therefore, the port-B parity generate select (PGB) and ODD/EVEN have setup- and hold-time
constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read a new word to the FIFO output
register.
The circuit used to generate parity for the mail1 data is shared by the port-B bus (B0–B35) to check parity and
the circuit used to generate parity for the mail2 data is shared by the port-A bus (A0–A35) to check parity. The
shared parity trees of a port are used to generate parity bits for the data in a mail register when W/RA, W/RB
is low, MBA, MBB is high, CSA, CSB is low, ENA, ENB is high, and PGA, PGB is high. Generating parity for
mail-register data does not change the contents of the register.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
CLKB
t
h(RS)
t
h(FS)
t
su(RS)
t
su(FS)
RST
FS1, FS0
FF
0,1
t
t
pd(C-FF)
pd(C-FF)
t
pd(C-EF)
EF
AE
AF
t
pd(C-AE)
t
pd(C-AF)
t
pd(R-F)
MBF1,
MBF2
Figure 1. Device Reset Loading the X Register With the Value of Eight
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
FF
High
t
t
t
su(EN1)
h(EN1)
CSA
t
t
su(EN1)
h(EN1)
W/RA
MBA
ENA
t
t
su(EN3)
h(EN3)
t
h(EN2)
t
h(EN2)
t
t
t
t
su(EN2)
h(EN2)
su(EN2)
su(EN2)
t
su(D)
h(D)
No Operation
W1
W2
A0–A35
ODD/
EVEN
t
t
pd(D-PE)
pd(D-PE)
PEFA
Valid
Valid
Figure 2. FIFO1 Write-Cycle Timing
12
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
EF High
CSB
W/RB
MBB
t
t
t
su(EN2)
su(EN2)
h(EN2)
su(EN2)
t
t
t
h(EN2)
h(EN2)
ENB
No
Operation
t
pd(M-DV)
t
dis
t
en
t
a
t
a
B0–B35
Previous Data
Word 1
Word 2
t
t
h(PG)
h(PG)
t
t
su(PG)
su(PG)
PGB,
ODD/
EVEN
Figure 3. FIFO Read-Cycle Timing
13
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
CSA
High
W/RA
t
su(EN3)
t
h(EN3)
MBA
ENA
t
su(EN2)
t
h(EN2)
High
FFA
t
su(D)
t
h(D)
A0–A35
W1
t
t
c
†
t
sk1
w(CLKL)
t
w(CLKH)
1
2
CLKB
EF
t
t
pd(C-EF)
pd(C-EF)
Empty FIFO
CSB Low
W/RB
MBB
Low
Low
t
h(EN2)
t
su(EN2)
ENB
t
a
B0–B35
W1
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for EF to transition high in the next CLKB cycle. If the time
sk1
between the rising CLKA edge and rising CLKB edge is less than t
, the transition of EF high may occur one CLKB cycle later than shown.
sk1
Figure 4. EF-Flag Timing and First Data Read When the FIFO Is Empty
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
Low
Low
CSB
W/RB
MBB
ENB
t
t
h(EN2)
su(EN2)
EFB
High
t
a
B0–B35 Previous Word in FIFO Output Register
Next Word From FIFO
†
t
sk1
t
c
t
t
w(CLKL)
w(CLKH)
1
2
CLKA
FF
t
t
pd(C-FF)
pd(C-FF)
Full FIFO
CSA
W/RA
MBA
Low
High
t
t
t
h(EN3)
su(EN3)
t
t
su(EN2)
h(EN2)
ENA
t
su(D)
h(D)
A0–A35
To FIFO
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for FF to transition high in the next CLKA cycle. If the time
sk1
between the rising CLKB edge and rising CLKA edge is less t
, FF may transition high one CLKA cycle later than shown.
sk1
Figure 5. FF-Flag Timing and First Available Write When the FIFO Is Full
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
t
h(EN2)
t
su(EN2)
ENA
†
t
sk2
CLKB
AE
1
2
t
t
pd(C-AE)
pd(C-AE)
X Words in FIFO
(X + 1) Words in FIFO
t
h(EN2)
t
su(EN2)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AE to transition high in the next CLKB cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, AE may transition high one CLKB cycle later than shown.
sk2
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 6. Timing for AE When the FIFO Is Almost Empty
‡
t
sk2
CLKA
ENA
1
2
t
h(EN2)
t
su(EN2)
t
t
pd(C-AF)
pd(C-AF)
(64 – X) Words in FIFO
AF
[64 – (X + 1)] Words in FIFO
CLKB
ENB
t
h(EN2)
t
su(EN2)
‡
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AF to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, AF may transition high one CLKB cycle later than shown.
sk2
NOTE A: FIFO write (CSA = L, W/RA = H, MBA = L), FIFO read (CSB = L, W/RB = L, MBB = L).
Figure 7. Timing for AF When the FIFO Is Almost Full
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKA
t
h(EN1)
t
su(EN1)
CSA
W/RA
MBA
ENA
t
h(D)
t
su(D)
A0–A35
W1
CLKB
MBF1
t
t
pd(C-MF)
pd(C-MF)
CSB
W/RB
MBB
ENB
t
h(EN2)
t
su(EN2)
t
pd(M-DV)
t
dis
t
en
t
pd(C-MR)
B0–B35
W1 (remains valid in mail1 register after read)
FIFO Output Register
NOTE A: Port-B parity generation off (PGB = L)
Figure 8. Timing for Mail1 Register and MBF1 Flag
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
CLKB
t
h(EN1)
t
su(EN1)
CSB
W/RB
MBB
ENB
t
h(D)
t
su(D)
B0–B35
W1
CLKA
MBF2
t
t
pd(C-MF)
pd(C-MF)
CSA
W/RA
MBA
ENA
t
h(EN2)
t
su(EN2)
t
t
en
t
dis
pd(C-MR)
A0–A35
W1 (remains valid in mail2 register after read)
NOTE A: Port-A parity generation off (PGA = L)
Figure 9. Timing for Mail2 Register and MBF2 Flag
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
ODD/
EVEN
W/RA
MBA
PGA
t
t
t
t
pd(E-PE)
pd(O-PE)
pd(O-PE)
pd(E-PE)
PEFA
Valid
Valid
Valid
Valid
NOTE A: CSA = L and ENA = H
Figure 10. ODD/EVEN, W/RA, MBA, and PGA to PEFA Timing
ODD/
EVEN
W/RB
MBB
PGB
t
t
t
t
pd(E-PE)
pd(O-PE)
pd(O-PE)
pd(E-PE)
PEFB
Valid
Valid
Valid
Valid
NOTE A: CSB = L and ENB = H
Figure 11. ODD/EVEN, W/RB, MBB, and PGB to PEFB Timing
19
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SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
ODD/
EVEN
Low
CSA
W/RA
MBA
PGA
t
en
t
t
t
pd(E-PB)
pd(O-PB)
pd(E-PB)
A8, A17,
A26, A35
Mail2 Data
Generated Parity
Generated Parity
Mail2 Data
NOTE A: ENA = H
Figure 12. Parity-Generation Timing When Reading From the Mail2 Register
ODD/
EVEN
CSB
Low
W/RB
MBB
PGB
t
pd(E-PB)
pd(M-DV)
t
t
pd(O-PB)
pd(E-PB)
t
t
en
B8, B17,
B26, B35
Generated Parity
Generated Parity
Mail1 Data
Mail1
Data
NOTE A: ENB = H
Figure 13. Parity-Generation Timing When Reading From the Mail1 Register
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 50 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 500 mA
JA
PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–4
8
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
‡
PARAMETER
TEST CONDITIONS
= –4 mA
MIN TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
I
I
2.4
OH
CC
CC
CC
CC
OH
= 8 mA
or 0
0.5
± 50
± 50
60
V
OL
OL
I
I
V = V
µA
µA
I
CC
= V or 0
CC
I
V
OZ
O
Outputs high
or GND Outputs low
Outputs disabled
I
V
CC
= 5.5 V,
I
O
= 0 mA,
V = V
I CC
130
60
mA
CC
C
C
V = 0,
f = 1 MHz
f = 1 MHz
4
8
pF
pF
i
I
V
O
= 0,
o
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
21
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 14)
’ABT3611-15
’ABT3611-20
’ABT3611-30
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
t
Clock frequency, CLKA or CLKB
66.7
50
33.4
MHz
MHz
ns
clock
Clock cycle time, CLKA or CLKB
15
6
20
8
30
12
12
6
c
Pulse duration, CLKA and CLKB high
Pulse duration, CLKA and CLKB low
w(CLKH)
w(CLKL)
su(D)
6
8
ns
Setup time, A0–A35 before CLKA↑ and B0–B35 before CLKB↑
4
5
ns
Setup time, CSA, W/RA before CLKA↑; CSB, W/RB,
before CLKB↑
t
6
6
7
ns
su(EN1)
t
t
t
t
t
t
t
t
t
t
t
t
Setup time, ENA before CLKA↑; ENB before CLKB↑
Setup time, MBA before CLKA↑; ENB before CLKB↑
4
4
4
5
5
1
1
1
1
0
6
4
5
5
5
6
6
1
1
1
1
0
6
4
6
6
6
7
7
1
1
1
1
0
7
4
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
su(EN2)
su(EN3)
su(PG)
su(RS)
su(FS)
h(D)
†
Setup time, ODD/EVEN and PGB before CLKB↑
‡
Setup time, RST low before CLKA↑ or CLKB↑
Setup time, FS0 and FS1 before RST high
Hold time, A0–A35 after CLKA↑ and B0–B35 after CLKB↑
Hold time, CSA, W/RA after CLKA↑; CSB, W/RB after CLKB↑
Hold time, ENA after CLKA↑; ENB after CLKB↑
h(EN1)
h(EN2)
h(EN3)
h(PG)
Hold time, MBA after CLKA↑; MBB after CLKB↑
†
Hold time, ODD/EVEN and PGB after CLKB↑
‡
Hold time, RST low after CLKA↑ or CLKB↑
h(RS)
Hold time, FS0 and FS1 after RST high
h(FS)
Skew time between CLKA↑ and CLKB↑ for EFA, EFB,
FFA, and FFB
§
8
9
8
10
20
ns
ns
t
sk1
Skew time between CLKA↑ and CLKB↑ for AEA, AEB,
AFA, and AFB
§
16
t
sk2
†
‡
§
Applies only for a rising edge of CLKB that does a FIFO read
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
22
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Figures 1 through 13)
L
’ABT3611-15
’ABT3611-20
’ABT3611-30
PARAMETER
UNIT
MIN
MAX
66.7
10
MIN
MAX
50
MIN
MAX
33
f
t
t
t
t
t
ns
ns
ns
ns
ns
ns
max
Access time, CLKB↑ to B0–B35
2
2
2
2
2
2
2
2
2
2
12
2
2
2
2
2
15
a
Propagation delay time, CLKA↑ to FF
Propagation delay time, CLKB↑ to EF
Propagation delay time, CLKB↑ to AE
Propagation delay time, CLKA↑ to AF
10
12
15
pd(C-FF)
pd(C-EF)
pd(C-AE)
pd(C-AF)
10
12
15
10
12
15
10
12
15
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
t
1
9
1
12
1
15
ns
pd(C-MF)
†
Propagation delay time, CLKA↑ to B0–B35 and CLKB↑ to
A0–A35
t
t
t
t
t
3
1
3
3
2
12
11
12
11
12
3
1
3
3
2
14
11.5
13
3
1
3
3
2
16
12
14
14
15
ns
ns
ns
ns
ns
pd(C-MR)
pd(M-DV)
pd(D-PE)
pd(O-PE)
‡
Propagation delay time, MBB to B0–B35 valid
Propagation delay time, A0–A35 valid to PEFA valid; B0–B35
valid to PEFB valid
Propagation delay time, ODD/EVEN to PEFA and PEFB
12
Propagation delay time, ODD/EVEN to parity bits (A8, A17, A26,
A35) and (B8, B17, B26, B35)
§
13
pd(O-PB)
pd(E-PE)
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
PEFA; CSB, ENB, W/RB, MBB, or PGB to PEFB
t
1
3
12
14
1
3
13
15
1
3
15
16
ns
ns
Propagation delay time, CSA, ENA, W/RA, MBA, or PGA to
parity bits (A8, A17, A26, A35); CSB, ENB, W/RB, MBB, or PGB
to parity bits (B8, B17, B26, B35)
§
t
pd(E-PB)
Propagation delay time, RST to AE low and (AF, MBF1, MBF2)
high
t
t
t
1
2
1
15
10
9
1
2
1
20
12
10
1
2
1
30
14
11
ns
ns
ns
pd(R-F)
Enable time, CSA and W/RA low to A0–A35 active and CSB low
and W/RB high to B0–B35 active
en
Disable time, CSA or W/RA high to A0–A35 at high impedance
and CSB high or W/RB low to B0–B35 at high impedance
dis
†
‡
§
Writing data to the mail1 register when the B0–B35 outputs are active and MBB is high.
Writing data to the mail2 register when the A0–A35 outputs are active and MBA is high.
Applies only when reading data from a mail register
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 kΩ
From Output
Under Test
30 pF
(see Note A)
680 Ω
LOAD CIRCUIT
3 V
3 V
Timing
Input
High-Level
Input
1.5 V
t
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
h
w
t
su
Data,
Enable
Input
3 V
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
PLZ
t
PZL
≈ 3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
V
V
OL
GND
t
PZH
t
t
pd
pd
OH
High-Level
Output
V
V
OH
1.5 V
In-Phase
Output
1.5 V
1.5 V
≈ 0 V
OL
t
PHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTES: A. Includes probe and jig capacitance
B.
C.
t
t
and t
and t
are the same as t
are the same as t
.
en
.
en
PZL
PLZ
PZH
PHZ
Figure 14. Load Circuit and Voltage Waveforms
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ABT3611
64 × 36
CLOCKED FIRST-IN, FIRST-OUT MEMORY
SCBS127E – JULY 1992 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
400
350
300
250
200
150
100
50
f
T
C
= 1/2 f
clock
V
= 5.5 V
data
A
L
CC
= 25°C
= 0 pF
V
CC
= 5 V
V
= 4.5 V
CC
0
0
10
20
30
40
50
60
70
80
f
– Clock Frequency – MHz
clock
Figure 15
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
OBSOLETE HLQFP
OBSOLETE BQFP
OBSOLETE HLQFP
OBSOLETE BQFP
OBSOLETE HLQFP
OBSOLETE BQFP
Drawing
PCB
PQ
SN74ABT3611-15PCB
SN74ABT3611-15PQ
SN74ABT3611-20PCB
SN74ABT3611-20PQ
SN74ABT3611-30PCB
SN74ABT3611-30PQ
120
132
120
132
120
132
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
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Call TI
Call TI
Call TI
Call TI
Call TI
PCB
PQ
PCB
PQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15)
M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
Seating Plane
”D2” SQ
0°–8°
0.046 (1,17)
0.036 (0,91)
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
DIM
MAX
MIN
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
”D”
MAX
MIN
”D1”
MAX
MIN
”D2”
”D3”
NOM
4040045/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998
PCB (S-PQFP-G120)
PLASTIC QUAD FLATPACK (DIE DOWN)
0,23
0,13
M
0,07
0,40
90
61
Heat Slug
60
91
31
120
0,13 NOM
1
30
11,60 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040202/C 12/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced molded plastic package with a heat slug (HSL)
D. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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