SN74ABT573DBLE [ROCHESTER]
Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, PLASTIC, SSOP-20;
| 型号： | SN74ABT573DBLE |
| 厂家： | 
Rochester Electronics |
| 描述： | Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, PLASTIC, SSOP-20 驱动 信息通信管理 光电二极管 逻辑集成电路 |
| 文件： | 总7页 (文件大小：104K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABT573, SN74ABT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190A – JANUARY 1991 – REVISED JULY 1994
SN54ABT573 . . . J PACKAGE
SN74ABT573 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
• State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
• ESD Protection Exceeds 2000 V Per
MIL-STD-883C, Method 3015; Exceeds
200 V Using Machine Model (C = 200 pF,
R = 0)
OE
1D
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
1Q
2Q
3Q
4Q
5Q
6Q
2D
3D
• Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
4D
5D
6D
• Typical V
(Output Ground Bounce)
OLP
CC
< 1 V at V
= 5 V, T = 25°C
A
7D
8D
13 7Q
12 8Q
• High-Drive Outputs (–32-mA I
,
OH
64-mA I
)
OL
11
GND
LE
• Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
SN54ABT573 . . . FK PACKAGE
(TOP VIEW)
description
3
2
1
20 19
18
4
5
6
7
8
3D
4D
5D
6D
7D
2Q
3Q
4Q
5Q
6Q
These 8-bit latches feature 3-state outputs
designed specifically for driving highly capacitive
or relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
17
16
15
14
9 10 11 12 13
The eight latches of the ′ABT573 are transparent
D-type latches. While the latch-enable (LE) input
is high, the Q outputs follow the data (D) inputs.
When the latch enable is taken low, the Q outputs
are latched at the logic levels set up at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT573 is available in TI’s shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT573 is characterized for operation over the full military temperature range of –55°C to 125°C. The
SN74ABT573 is characterized for operation from –40°C to 85°C.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190A – JANUARY 1991 – REVISED JULY 1994
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
H
L
L
L
X
X
Q
0
H
X
Z
†
logic symbol
logic diagram (positive logic)
1
OE
1
EN
C1
OE
11
LE
11
LE
2
1D
3
19
18
17
16
15
14
13
12
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
C1
19
2D
4
1Q
2
1D
1D
3D
5
4D
6
5D
7
6D
8
7D
9
To Seven Other Channels
8D
†
This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high state or power-off state, V
. . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABT573 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . 0.6 W
A
DW package . . . . . . . . . . . . . . . . . . . 1.6 W
N package . . . . . . . . . . . . . . . . . . . . . 1.3 W
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils,
except for the N package, which has a trace length of zero. For more information, refer to the Package Thermal Considerations
application note in the 1994 ABT Advanced BiCMOS Technology Data Book, literature number SCBD002B.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190A – JANUARY 1991 – REVISED JULY 1994
recommended operating conditions (see Note 3)
SN54ABT573 SN74ABT573
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
High-level input voltage
Low-level input voltage
Input voltage
IH
0.8
0.8
V
IL
0
V
CC
0
V
CC
V
I
I
I
High-level output current
Low-level output current
Input transition rise or fall rate
Operating free-air temperature
–24
48
–32
64
5
mA
mA
ns/V
°C
OH
OL
∆t/∆v
Outputs enabled
5
T
–55
125
–40
85
A
NOTE 3: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54ABT573 SN74ABT573
A
PARAMETER
TEST CONDITIONS
UNIT
†
MIN TYP
MAX
MIN
MAX
MIN
MAX
V
V
V
V
= 4.5 V,
= 4.5 V,
= 5 V,
I = –18 mA
–1.2
–1.2
–1.2
V
IK
CC
CC
CC
I
I
= –3 mA
2.5
3
2.5
3
2.5
3
OH
IOH = –3 mA
V
OH
V
I
I
I
I
= –24 mA
= –32 mA
= 48 mA
2
2
OH
OH
OL
OL
V
= 4.5 V
= 4.5 V
CC
CC
2*
2
0.55
0.55*
±1
0.55
V
OL
V
V
= 64 mA
0.55
±1
I
I
I
I
I
I
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 0,
V = V or GND
I CC
±1
10
µA
µA
µA
µA
µA
mA
µA
mA
µA
I
V
V
= 2.7 V
= 0.5 V
50
50
OZH
OZL
off
O
–50
±100
50
–10
–50
±100
50
O
V or V ≤ 4.5 V
I
O
= 5.5 V,
= 5.5 V,
V
= 5.5 V
Outputs high
50
–180
250
30
CEX
O
O
‡
V
= 2.5 V
–50
–100
1
–180
250
30
–50
–50
–180
250
30
O
Outputs high
Outputs low
V
= 5.5 V,
or GND
CC
I
O
= 0,
CC
I
24
CC
V = V
I
Outputs disabled
0.5
250
250
250
V
= 5.5 V,
One input at 3.4 V,
CC
§
1.5
1.5
1.5
mA
∆I
CC
Other inputs at V or GND
CC
V = 2.5 V or 0.5 V
C
C
3
6
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
o
* On products compliant to MIL-STD-883, Class B, this parameter does not apply.
†
‡
§
All typical values are at V
= 5 V.
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
or GND.
CC
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190A – JANUARY 1991 – REVISED JULY 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABT573 SN74ABT573
UNIT
MIN
3.3
1.9
1.5
1
MAX
MIN
3.3
2.5
2.5
2.5
MAX
MIN
3.3
1.9
1.5
1
MAX
t
w
t
su
t
h
Pulse duration, LE high
ns
ns
ns
High
Low
Setup time, data before LE↓
Hold time, data after LE↓
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABT573 SN74ABT573
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
1.9
2.2
2.2
3.2
1.2
2.7
2.5
2
TYP
3.2
4.2
4
MAX
5.4
5.7
6.1
6.7
4.7
6.2
6.4
6
MIN
1.4
1.6
2
MAX
6.4
6.7
7.1
7.5
6.2
7.2
7.7
7
MIN
1.9
2.2
2.2
3.2
1.2
2.7
2.5
2
MAX
5.9
6.2
6.6
7.2
5.2
6.7
6.9
6.5
t
t
t
t
t
t
t
t
PLH
PHL
PLH
PHL
PZH
PZL
PHZ
PLZ
D
Q
Q
Q
Q
ns
ns
ns
ns
LE
OE
OE
5.2
3.2
4.7
4.9
4.2
2.8
0.8
2
2.2
1.4
2–4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABT573, SN74ABT573
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS190A – JANUARY 1991 – REVISED JULY 1994
PARAMETER MEASUREMENT INFORMATION
7 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
7 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
Open
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
3 V
0 V
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
t
PHL
PLH
t
PLZ
Output
Waveform 1
S1 at 7 V
V
V
3.5 V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
t
PZH
PHL
Output
Waveform 2
S1 at Open
(see Note C)
V
OH
V
V
OH
OH
1.5 V
1.5 V
Output
0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
2–5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
2–6
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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Bus Driver, ABT Series, 1-Func, 8-Bit, True Output, BICMOS, PDSO20, PLASTIC, SOP-20
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