SN74ABTH162460DLR [ROCHESTER]
ABT SERIES, 4-BIT EXCHANGER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56;
| 型号： | SN74ABTH162460DLR |
| 厂家： | 
Rochester Electronics |
| 描述： | ABT SERIES, 4-BIT EXCHANGER, TRUE OUTPUT, PDSO56, 0.300 INCH, GREEN, PLASTIC, SSOP-56 信息通信管理 光电二极管 输出元件 逻辑集成电路 |
| 文件： | 总16页 (文件大小：1099K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
SN54ABTH162460 . . . WD PACKAGE
SN74ABTH162460 . . . DL PACKAGE
(TOP VIEW)
Members of the Texas Instruments
Widebus Family
B-Port Outputs Have Equivalent 25-Ω
Series Resistors, So No External Resistors
Are Required
LEAB1
LEAB2
LEBA
GND
LEB1
LEB2
OEB1
OEB2
SEL0
GND
1B1
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
State-of-the-Art EPIC-ΙΙB BiCMOS Design
Significantly Reduces Power Dissipation
3
4
5
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
1B2
6
V
V
7
CC
CC
Typical V
(Output Ground Bounce) < 1 V
OLP
CLKBA
1B3
1B4
2B1
GND
2B2
2B3
2B4
3B1
3B2
3B3
GND
3B4
4B1
4B2
8
at V
= 5 V, T = 25°C
CC
A
OEB
CLKAB
GND
1A
2A
CE_SEL0
CE_SEL1
3A
4A
GND
CLKENAB
CLKENB
CLKENBA
9
High-Impedance State During Power Up
and Power Down
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
Distributed V
Minimizes High-Speed Switching Noise
and GND Pin Configuration
CC
Flow-Through Architecture Optimizes PCB
Layout
Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Package and
380-mil Fine-Pitch Ceramic Flat (WD)
Package Using 25-mil Center-to-Center
Spacings
V
V
CC
CC
LEB3
LEB4
GND
OEA
LEAB3
LEAB4
4B3
4B4
GND
SEL1
OEB3
OEB4
description
The ’ABTH162460 are 4-bit to 1-bit multiplexed
registered transceivers used in applications
where four separate data paths must be
multiplexed onto or demultiplexed from a single
data path. Typical applications include
multiplexing and/or demultiplexing of address and
data
information
in
microprocessor
or
bus-interface applications. This device also is
useful in memory-interleaving applications.
Five 4-bit I/O ports (1A–4A, 1B1–4, 2B1–4, 3B1–4, and 4B1–4) are available for address and/or data transfer.
The output-enable (OEB, OEB1–OEB4, and OEA) inputs control the bus-transceiver functions. These control
signals also allow 4-bit or 16-bit control, depending on the OEB level.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-ΙΙB are trademarks of Texas Instruments Incorporated.
Copyright 1997, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
description (continued)
Address and/or data information can be stored using the internal storage latches/flip-flops. The latch-enable
(LEB1–LEB4,LEBA, andLEAB1–LEAB4)andclock/clock-enable(CLK/CLKEN) inputs are used to control data
storage. When either one of the latch-enable inputs is high, the latch is transparent (clock is a don’t care as long
as the latch enable is high). When the latch-enable input goes low (providing that the clock does not transit from
low to high), the data present at the inputs is latched and remains latched until the latch-enable input is returned
high. When the clock enable is low and the corresponding latch enable is low, data can be clocked on the
low-to-high transition of the clock. When either the clock enable or the corresponding latch enable is high, the
clock is a don’t care.
Four select (SEL0, SEL1, CE_SEL0, and CE_SEL1) pins are provided to multiplex data (A port), or to select
one of four clock enables (B port). This allows the user the flexibility of controlling one bit at a time.
The B-port outputs, which are designed to sink up to 12 mA, include equivalent 25-Ω series resistors to reduce
overshoot and undershoot.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
When V
is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.
CC
However, to ensure the high-impedance state above 2.1 V, OE should be tied to V
the minimum value of the resistor is determined by the current-sinking capability of the driver.
through a pullup resistor;
CC
The SN54ABTH162460 is characterized for operation over the full military temperature range of –55°C to
125°C. The SN74ABTH162460 is characterized for operation from –40°C to 85°C.
Function Tables
†
A-TO-B OUTPUT ENABLE
INPUTS
OUTPUT
Bn
OEB
OEBn
H
H
L
H
L
Z
Z
H
L
Z
L
Active
†
n = 1, 2, 3, 4
A-TO-B STORAGE
(assuming OEB = L, OEBn = L)
‡
INPUTS
CLKENAB CE_SEL1 CE_SEL0 CLKAB LEAB1 LEAB2 LEAB3 LEAB4
OUTPUTS
B2 B3
B1
A
B4
X
X
L
L
L
L
L
H
X
X
X
L
X
X
X
L
H or L
H
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
A
0
A
0
A
0
A
0
A
0
A
0
A
0
A
0
H or L
A
A
A
L
↑
↑
↑
↑
↑
A
A
A
0
A
0
A
0
0
0
0
A
A
L
H
L
A
0
A
0
A
0
A
0
A
H
H
X
A
0
A
0
A
0
A
H
X
A
A
A
0
A
0
0
‡
This table does not cover all the latch-enable cases since they have similar results.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
Function Tables (Continued)
B-TO-A STORAGE
(before point P)
INPUTS
CLKBA LEB1 LEB2 LEB3 LEB4 SEL1 SEL0
P
CLKENB
X
X
X
X
X
X
X
X
H
L
L
L
L
H
L
L
L
L
L
L
L
L
H
L
B1
B2
B3
B4
B1
B2
B3
B4
H
L
L
H
H
L
L
H
H
L
L
H
L
L
L
↑
L
L
L
L
L
L
L
L
H
H
L
H
L
†
†
†
†
B1
0
0
0
0
L
H
L
B2
B3
B4
L
H
H
H
†
Output level before the indicated steady-state input conditions were established
B-TO-A STORAGE
(after point P)
INPUTS
OUTPUT
A
CLKBA LEBA
B
X
L
CLKENBA
OEA
X
X
X
H
L
X
X
X
X
↑
X
H
H
L
H
L
L
L
L
L
L
Z
L
H
X
L
H
†
A
0
L
L
L
↑
L
H
X
H
†
A
0
L
L
L
†
Output level before the indicated steady-state input conditions
were established
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
logic diagram (positive logic)
24
28
27
2
LEB4
LEAB4
LEAB3
LEAB2
23
LEB3
6
LEB2
5
1
56
55
LEB1
LEAB1
OEB1
OEB2
30
20
OEB3
CLKENB
29
9
OEB4
OEB
31
SEL1
14
15
CE_SEL0
CE_SEL1
54
SEL0
3
LEBA
19
CLKENAB
8
CLKBA
CLKENAB Selector
21
CLKENBA
One of Four
Channels
LE
D
52
1B1
CLK
CE
LE
D
CLK
CE
51
1B2
CE
CLK
D
LE
M
U
X
P
CLK
CE
D
49
48
1B3
1B4
LE
CLK
CE
D
LE
LE
10
CLKAB
CLK
CE
D
LE
CLK
CE
D
26
12
OEA
1A
LE
CLK
CE
D
LE
CLK
CE
D
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (except I/O ports) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Voltage range applied to any output in the high or power-off state, V
. . . . . . . . . . . . . . . . . . . –0.5 V to 5.5 V
O
Current into any output in the low state, I : SN54ABTH162460 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 96 mA
O
SN74ABTH162460 (A port) . . . . . . . . . . . . . . . . . . . . . . . . 128 mA
B port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –18 mA
IK
OK
I
Output clamp current, I
(V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
O
Package thermal impedance, θ (see Note 2): DL package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 °C/W
Storage temperature range, T
JA
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The package thermal impedance is calculated in accordance with EIA/JEDEC Std JESD51.
recommended operating conditions (see Note 3)
SN54ABTH162460
MIN NOM MAX
SN74ABTH162460
MIN NOM MAX
UNIT
V
CC
V
IH
V
IL
V
I
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
V
V
High-level input voltage
Low-level input voltage
Input voltage
0.8
CC
0.8
CC
0
V
0
V
A port
–24
–12
48
–32
–12
64
I
High-level output current
Low-level output current
mA
mA
OH
OL
B port
A port
I
B port
12
12
∆t/∆v
∆t/∆V
Input transition rise or fall rate
Power-up ramp rate
Outputs enabled
10
10
ns/V
µs/V
°C
200
–55
200
–40
CC
T
A
Operating free-air temperature
125
85
NOTE 3: Unused control pins must be held high or low to prevent them from floating.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54ABTH162460
SN74ABTH162460
PARAMETER
A port
TEST CONDITIONS
UNIT
†
†
MIN TYP
MAX
MIN TYP
MAX
V
IK
V
V
= 4.5 V,
= 5 V,
I = –18 mA
I
–1.2
–1.2
V
CC
I
I
I
I
I
I
I
I
I
I
I
= –3 mA
= –3 mA
= –32 mA
= –1 mA
= –1 mA
= –3 mA
= –12 mA
= 24 mA
= 64 mA
= 8 mA
3
3.4
3
3
3.4
2.7
CC
OH
OH
OH
OH
OH
OH
OH
OL
OL
OL
OL
2.5
V
= 4.5 V
= 5 V,
CC
CC
2
3.85
3.35
3.1
V
OH
V
3.8
3.3
3
4.2
3.7
3.6
V
V
B port
V
CC
= 4.5 V
2.6
0.25
0.4
0.55
0.8
A port
B port
V
V
= 4.5 V
= 4.5 V
CC
0.3
0.4
0.5
100
0.55
0.65
0.8
V
V
OL
CC
= 12 mA
100
mV
hys
Control inputs
A or B ports
V
V
V
V
V
= 0 to 5.5 V,
= 2.1 V to 5.5 V,
= 5.5 V,
V = V
or GND
or GND
±1
±20
500
–500
–180
–90
–180
50
±1
±20
500
–500
–180
–90
–180
50
CC
CC
CC
CC
CC
I
CC
CC
I
µA
I
V = V
I
V = 0.8 V
I
75
–75
–50
–25
–50
75
–75
–50
–25
–50
I
A or B ports
A port
µA
I(hold)
= 4.5 V,
V = 2 V
I
= 5.5 V,
V
O
V
O
V
O
V
O
= 2.5 V
–110
–55
‡
= 2.5 V
= 0
mA
I
O
B port
V
CC
= 5.5 V
–110
I
I
I
I
Outputs high
V
CC
V
CC
V
CC
V
CC
= 5.5 V,
= 0,
= 5.5 V
µA
µA
µA
µA
CEX
V or V ≤ 4.5 V
I
±100
±50
±50
1.5
±100
±50
±50
1.5
off
O
§
= 0 to 2.1 V, V = 0.5 V to 2.7 V, OE = X
OZPU
OZPD
O
§
= 2.1 V to 0, V = 0.5 V to 2.7 V, OE = X
O
Outputs high
A port low
0.7
6
10
10
I
V
CC
= 5.5 V, Outputs open
mA
CC
B port low
32
18
0.7
32
Outputs disabled
1.5
1.5
V
= 5.5 V, One input at 3.4 V,
CC
¶
1
1
mA
∆I
CC
Other inputs at V
or GND
CC
V = 2.5 V or 0.5 V
C
C
Control inputs
A or B ports
3.5
8
3.5
8
pF
pF
i
I
V
O
= 2.5 V or 0.5 V
io
†
‡
§
¶
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be tested at a time, and the duration of the test should not exceed one second.
This parameter is characterized but not production tested.
This is the increase in supply current for each input that is at the specified TTL voltage level rather than V
CC
or GND.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)(see Figure 1)
V
T
= 5 V,
= 25°C
CC
A
SN54ABTH162460 SN74ABTH162460
UNIT
MIN
0
MAX
MIN
0
MAX
MIN
0
MAX
f
t
Clock frequency
CLKAB high or low
160
160
160
MHz
clock
3.8
4.5
2.8
2.8
3
3.8
4.5
2.8
2.8
3
3.8
4.5
2.8
2.8
3
CLKBA high or low
LEAB1, 2, 3, or 4 high
LEBA high
Pulse
duration
ns
w
LEB1, 2, 3, or 4 high
A bus
2.5
3.2
3.2
3.6
3.8
2.3
2.5
4.3
4.5
3.2
4
2.5
3.2
3.2
3.6
3.8
2.3
2.5
4.3
4.5
3.2
4
2.5
3.2
3.2
3.6
3.8
2.3
2.5
4.3
4.5
3.2
4
Before CLKAB↑
CE_SEL0/1
CLKENAB
A bus
Before LEAB1, 2, 3, or 4↓
B bus
CLKENB
CLKENBA
LEB1, 2, 3, or 4
SEL0/1
t
su
Setup time Before CLKBA↑
ns
Before LEB1, 2, 3, or 4↓
B bus
B bus
Before LEBA↓
LEB1, 2, 3, or 4
SEL0/1
4.4
4.3
0.5
1.1
0.5
1.2
1.3
1
4.4
4.3
0.5
1.1
0.5
1.2
1.3
1
4.4
4.3
0.5
1.1
0.5
1.2
1.3
1
A bus
After CLKAB↑
CE_SEL0/1
CLKENAB
A bus
After LEAB1, 2, 3, or 4↓
B bus
t
h
Hold time
CLKENB
CLKENBA
SEL0/1
ns
After CLKBA↑
1
1
1
0
0
0
After LEB1, 2, 3, or 4↓
After LEBA↓
B bus
1.5
0.4
0.1
1.5
0.4
0.1
1.5
0.4
0.1
B bus
SEL0/1
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 50 pF (unless otherwise noted) (see Figure 1)
L
V
T
= 5 V,
= 25°C
CC
A
SN54ABTH162460 SN74ABTH162460
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
UNIT
MIN
160
2
TYP
MAX
MIN
160
2
MAX
MIN
160
2
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
MHz
ns
max
PLH
PHL
PZH
PZL
PHZ
PLZ
PLH
PHL
PZH
PZL
PHZ
PLZ
PZH
PZL
PHZ
PLZ
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
PLH
PHL
3.6
3.5
2.8
2.6
3.8
4
5.9
5.8
4.8
4.8
5.3
6.1
5.5
5.8
5.8
5.6
5.6
5.2
5.8
5.4
4.8
4.4
6.7
6.9
5.8
6
7.1
6.8
5.9
5.7
6
6.5
6.5
5.6
5.5
5.9
6.5
6.2
6.5
6.8
6.3
6.2
5.8
6.6
6.2
5.3
4.9
7.4
7.7
6.5
6.5
5.8
5.8
6.2
6.2
7.2
6.8
7.5
6.9
B
A
A
A
B
B
B
B
B
A
B
A
B
A
A
2
2
2
1.5
1.5
2
1.5
1.5
2
1.5
1.5
2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
OEA
OEA
A
1.5
2
1.5
2
7
1.5
2
3.3
3.7
3.9
3.7
4
6.5
6.8
7.1
6.6
6.4
6.1
6.8
6.4
5.4
5.1
8.1
8.4
6.9
7
2
2
2
2
2
2
OEB
OEB
2
2
1.5
2
2
2
2
3.7
3.7
3.5
3.3
3.1
4.2
4.4
3.5
3.7
3
2
2
2
2
2
OEB1, 2, 3, 4
OEB1, 2, 3, 4
CLKBA
2
2
2
1.5
1.5
1.5
1.5
2
1.5
1.5
1.5
1.5
2
1.5
1.5
1.5
1.5
2
CLKAB
2
2
2
1.5
1.5
2
5.2
5
1.5
1.5
2
6.3
6.3
6.5
6.3
7.8
7.5
8.1
7.3
1.5
1.5
2
LEBA
3
3.4
3.6
4
5.4
5.7
6.5
6.1
6.7
6.2
LEAB1, 2, 3, 4
LEBA1, 2, 3, 4
SEL
2
2
2
2
2
2
2
4
2
2
2
4.1
3.8
2
2
2
2
2
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54ABTH162460, SN74ABTH162460
4-TO-1 MULTIPLEXED/DEMULTIPLEXED REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS241E – FEBRUARY 1993 – REVISED MAY 1997
PARAMETER MEASUREMENT INFORMATION
7 V
TEST
/t
S1
Open
S1
500 Ω
From Output
Under Test
t
Open
7 V
PLH PHL
GND
t
/t
PLZ PZL
C
= 50 pF
t
/t
Open
L
PHZ PZH
500 Ω
(see Note A)
3 V
0 V
LOAD CIRCUIT
Timing Input
Data Input
1.5 V
t
w
t
t
h
su
3 V
0 V
3 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
Input
t
PZL
t
t
t
PHL
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 7 V
3.5 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
V
+ 0.3 V
OL
V
OL
OL
(see Note B)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at Open
(see Note B)
V
OH
V
V
OH
– 0.3 V
OH
1.5 V
1.5 V
Output
≈ 0 V
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
74ABTH162460DGGRE4
74ABTH162460DGGRG4
74ABTH162460DLG4
74ABTH162460DLRG4
SN74ABTH162460DGGR
SN74ABTH162460DL
SN74ABTH162460DLR
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
TSSOP
DGG
56
56
56
56
56
56
56
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
TSSOP
SSOP
SSOP
TSSOP
SSOP
SSOP
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DGG
DL
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
DL
1000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0 (mm)
B0 (mm)
K0 (mm)
P1
W
Pin1
Diameter Width
(mm) W1 (mm)
(mm) (mm) Quadrant
SN74ABTH162460DGGR TSSOP
SN74ABTH162460DLR SSOP
DGG
DL
56
56
2000
1000
330.0
330.0
24.4
32.4
8.6
15.6
1.8
3.1
12.0
16.0
24.0
32.0
Q1
Q1
11.35
18.67
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
11-Mar-2008
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74ABTH162460DGGR
SN74ABTH162460DLR
TSSOP
SSOP
DGG
DL
56
56
2000
1000
346.0
346.0
346.0
346.0
41.0
49.0
Pack Materials-Page 2
MECHANICAL DATA
MTSS003D – JANUARY 1995 – REVISED JANUARY 1998
DGG (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0,27
0,17
M
0,08
0,50
48
25
6,20
6,00
8,30
7,90
0,15 NOM
Gage Plane
0,25
1
24
0°–8°
A
0,75
0,50
Seating Plane
0,10
0,15
0,05
1,20 MAX
PINS **
48
56
64
DIM
A MAX
12,60
12,40
14,10
13,90
17,10
16,90
A MIN
4040078/F 12/97
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MSSO001C – JANUARY 1995 – REVISED DECEMBER 2001
DL (R-PDSO-G**)
PLASTIC SMALL-OUTLINE PACKAGE
48 PINS SHOWN
0.025 (0,635)
48
0.0135 (0,343)
0.008 (0,203)
0.005 (0,13)
M
25
0.010 (0,25)
0.005 (0,13)
0.299 (7,59)
0.291 (7,39)
0.420 (10,67)
0.395 (10,03)
Gage Plane
0.010 (0,25)
0°–ā8°
1
24
0.040 (1,02)
0.020 (0,51)
A
Seating Plane
0.004 (0,10)
0.008 (0,20) MIN
PINS **
0.110 (2,79) MAX
28
48
0.630
56
DIM
0.380
(9,65)
0.730
A MAX
A MIN
(16,00) (18,54)
0.370
(9,40)
0.620
0.720
(15,75) (18,29)
4040048/E 12/01
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0.006 (0,15).
D. Falls within JEDEC MO-118
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should
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