SN74ACT3638-30PQR [ROCHESTER]
512X32 BI-DIRECTIONAL FIFO, 15ns, PQFP132, PLASTIC, BQFP-132;
| 型号： | SN74ACT3638-30PQR |
| 厂家： | 
Rochester Electronics |
| 描述： | 512X32 BI-DIRECTIONAL FIFO, 15ns, PQFP132, PLASTIC, BQFP-132 先进先出芯片 |
| 文件： | 总34页 (文件大小：1229K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
Free-Running CLKA and CLKB Can Be
Asynchronous or Coincident
IRA, ORA, AEA, and AFA Flags
Synchronized by CLKA
Two Independent 512 × 32 Clocked FIFOs
Buffering Data in Opposite Directions
IRB, ORB, AEB, and AFB Flags
Synchronized by CLKB
Read Retransmit Capability From FIFO on
Port B
Low-Power 0.8-µm Advanced CMOS
Technology
Mailbox-Bypass Register for Each FIFO
Supports Clock Frequencies up to 67 MHz
Fast Access Times of 11 ns
Programmable Almost-Full and
Almost-Empty Flags
Package Options Include 120-Pin Thin
Quad Flat (PCB) and 132-Pin Quad Flat
(PQ) Packages
Microprocessor Interface Control Logic
PCB PACKAGE
(TOP VIEW)
CSA
W/RA
ENA
1
2
3
4
5
6
7
8
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
CSB
W/RB
ENB
CLKB
GND
B31
B30
B29
B28
B27
CLKA
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
V
CC
B15
B14
B13
B12
GND
V
A12
CC
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
†
PQ PACKAGE
(TOP VIEW)
17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1 132 130 128
131
129
126 124 122 120 118
127 125 123
121 119
117
116
NC
CSB
W/RB
ENB
CLKB
GND
B31
B30
B29
B28
B27
NC
NC
CSA
W/RA
ENA
CLKA
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
V
CC
A31
A30
GND
A29
A28
A27
A26
A25
A24
A23
GND
A22
B26
V
CC
B25
B24
GND
B23
B22
B21
B20
B19
B18
GND
B17
B16
98
97
V
CC
A21
A20
A19
A18
GND
A17
A16
A15
A14
A13
96
95
94
93
92
V
91
CC
B15
B14
B13
B12
GND
NC
90
89
88
87
V
86
CC
A12
NC
85
NC
84
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
NC – No internal connection
†
Uses Yamaichi socket IC51-1324-828
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
description
The SN74ACT3638 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock
frequencies up to 67 MHz and has read access times as fast as 11 ns. Two independent 512 × 32 dual-port
SRAM FIFOs on the chip buffer data in opposite directions. The FIFO memory buffering data from port A to port
B has retransmit capability, which allows previously read data to be accessed again. Each FIFO has flags to
indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when
a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via
two 32-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two
or more devices can be used in parallel to create wider datapaths.
The SN74ACT3638 is a clocked FIFO, which means each port employs a synchronous interface. All data
transfersthroughaportaregatedtothelow-to-hightransitionofacontinuous(free-running)portclockbyenable
signals. The continuous clocks for each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple bidirectional interface between
microprocessors and/or buses with synchronous control.
The input-ready (IRA, IRB) flags and almost-full (AFA, AFB) flags of the SN74ACT3638 are two-stage
synchronizedtotheportclockthatwritesdatatoitsarray. Theoutput-ready(ORA, ORB)flagsandalmost-empty
(AEA, AEB) flags of the SN74ACT3638 are two-stage synchronized to the port clock that reads data from its
array. Offsets for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.
The SN74ACT3638 is characterized for operation from 0°C to 70°C.
For more information on this device family, see the application reports FIFO Mailbox-Bypass Registers: Using
Bypass Registers to Initialize DMA Control (literature number SCAA007) and Metastability Performance of
Clocked FIFOs (literature number SCZA004).
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
functional block diagram
MBF1
Mail1
Register
CLKA
CSA
W/RA
ENA
Port-A
Control
Logic
MBA
512 × 32
SRAM
FIFO1,
Mail1
Reset
Logic
32
RST1
RTM
RFM
Write
Pointer
Read
Pointer
Status-Flag
IRA
AFA
ORB
AEB
Logic
FIFO1
Programmable-
Flag
Offset Registers
FS0
FS1
A0–A31
RDYB
9
B0–B31
RDYA
FIFO2
Status-Flag
Logic
ORA
AEA
IRB
AFB
Read
Write
32
Pointer
Pointer
FIFO2,
Mail2
Reset
Logic
RST2
CLKB
512 × 32
SRAM
Port-B
Control
Logic
CSB
W/RB
ENB
MBB
Mail2
Register
MBF2
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
A0–A31
AEA
I/O
O
Port-A data. The 32-bit bidirectional data port for side A.
Port-A almost-empty flag. Programmable flag synchronized to CLKA. AEA is low when the number of words in FIFO2
(port A) is less than or equal to the value in the almost-empty A offset register, X2.
Port-B almost-empty flag. Programmable flag synchronized to CLKB. AEB is low when the number of words in FIFO1
(port B) is less than or equal to the value in the almost-empty B offset register, X1.
Port-A almost-full flag. Programmable flag synchronized to CLKA. AFA is low when the number of empty locations in
(port A) FIFO1 is less than or equal to the value in the almost-full A offset register, Y1.
Port-B almost-full flag. Programmable flag synchronized to CLKB. AFB is low when the number of empty locations
(port B) in FIFO2 is less than or equal to the value in the almost full B offset register, Y2.
O
AEB
AFA
O
O
AFB
B0–B31
CLKA
I/O
Port-B data. The 32-bit bidirectional data port for side B.
Port-A clock. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous
or coincident to CLKB. IRA, ORA, AFA, and AEA are synchronous to the low-to-high transition of CLKA.
I
Port-B clock. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous
or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronous to the low-to-high transition of CLKB.
CLKB
CSA
CSB
I
I
I
Port-A chip select. CSA must be low to enable a low-to-high transition of CLKA to read or write data on port A. The
A0–A31 outputs are in the high-impedance state when CSA is high.
Port-B chip select. CSB must be low to enable a low-to-high transition of CLKB to read or write data on port B. The
B0 –B31 outputs are in the high-impedance state when CSB is high.
ENA
ENB
I
I
Port-A enable. ENA must be high to enable a low-to-high transition of CLKA to read or write data on port A.
Port-B enable. ENB must be high to enable a low-to-high transition of CLKB to read or write data on port B.
Flag-offset selects. The low-to-high transition of a FIFO reset input latches the values of FS0 and FS1. If either FS0
or FS1 is high when a reset input goes high, one of three preset values is selected as the offset for the FIFO almost-full
and almost-empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are low when RST1 and RST2
go high, the first four writes to FIFO1 program the almost-full and almost-empty offsets for both FIFOs.
FS1, FS0
IRA
I
Port-A input-ready flag. IRA is synchronized to the low-to-high transition of CLKA. When IRA is low, FIFO1 is full and
writes to its array are disabled. When FIFO1 is in retransmit mode, IRA indicates when the memory has been filled
to the point of the retransmit data and prevents further writes. IRA is set low when FIFO1 is reset and is set high on
the second low-to-high transition of CLKA after reset.
O
(port A)
Port-B input-ready flag. IRB is synchronized to the low-to-high transition of CLKB. When IRB is low, FIFO2 is full and
writes to its array are disabled. IRB is set low when FIFO2 is reset and is set high on the second low-to-high transition
of CLKB after reset.
O
IRB
MBA
MBB
MBF1
MBF2
(port B)
Port-A mailbox select. A high level on MBA chooses a mailbox register for a port-A read or write operation. When the
A0–A31 outputs are active, a high level on MBA selects data from the mail2 register for output and a low level selects
FIFO2 output-register data for output.
I
Port-B mailbox select. A high level on MBB chooses a mailbox register for a port-B read or write operation. When the
B0–B31 outputs are active, a high level on MBB selects data from the mail1 register for output and a low level selects
FIFO1 output-register data for output.
I
Mail1 register flag. MBF1 is set low by the low-to-high transition of CLKA that writes data to the mail1 register. Writes
tothemail1registerareinhibitedwhileMBF1is low. MBF1is set high by a low-to-high transition of CLKB when a port-B
read is selected and MBB is high. MBF1 is set high when FIFO1 is reset.
O
O
Mail2 register flag. MBF2 is set low by the low-to-high transition of CLKB that writes data to the mail2 register. Writes
tothemail2registerareinhibitedwhileMBF2is low. MBF2is set high by a low-to-high transition of CLKA when a port-A
read is selected and MBA is high. MBF2 is set high when FIFO2 is reset.
Port-Aoutput-readyflag. ORAissynchronizedtothelow-to-hightransitionofCLKA. WhenORAislow, FIFO2isempty
and reads from its memory are disabled. Ready data is present on the output register of FIFO2 when ORA is high.
ORA is forced low when FIFO2 is reset and goes high on the third low-to-high transition of CLKA after a word is loaded
to empty memory.
O
ORA
(port A)
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
Terminal Functions (Continued)
TERMINAL
NAME
I/O
DESCRIPTION
Port-Boutput-readyflag. ORBissynchronizedtothelow-to-hightransitionofCLKB. WhenORBislow, FIFO1isempty
and reads from its memory are disabled. Ready data is present on the output register of FIFO1 when ORB is high.
ORB is forced low when FIFO1 is reset and goes high on the third low-to-high transition of CLKB after a word is loaded
to empty memory.
O
ORB
(port B)
O
Port-A ready. A high on W/RA selects the inverted state of IRA for output on RDYA, and a low on W/RA selects the
RDYA
RDYB
RFM
(port A) inverted state of ORA for output on RDYA.
O
Port-B ready. A low on W/RB selects the inverted state of IRB for output on RDYB, and a high on W/RB selects the
(port B) inverted state of ORB for output on RDYB.
FIFO1 read from mark. When FIFO1 is in retransmit mode, a high on RFM enables a low-to-high transition of CLKB
to reset the FIFO1 read pointer to the retransmit location and output the first retransmit data.
I
FIFO1 reset. To reset FIFO1, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST1 is low. The low-to-high transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset
selection. FIFO1 must be reset upon power up before data is written to its RAM.
RST1
RST2
RTM
I
I
I
FIFO2 reset. To reset FIFO2, four low-to-high transitions of CLKA and four low-to-high transitions of CLKB must occur
while RST2 is low. The low-to-high transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset
selection. FIFO2 must be reset upon power up before data is written to its RAM.
FIFO1 retransmit mode. When RTM is high and valid data is present on the output of FIFO1, a low-to-high transition
of CLKB selects the data for the beginning of a FIFO1 retransmit. The selected position remains the initial retransmit
point until a low-to-high transition of CLKB occurs while RTM is low, which takes FIFO out of retransmit mode.
Port-A write/read select. A high on W/RA selects a write operation and a low selects a read operation on port A for
a low-to-high transition of CLKA. The A0–A31 outputs are in the high-impedance state when W/RA is high.
W/RA
W/RB
I
I
Port-B write/read select. A low on W/RB selects a write operation and a high selects a read operation on port B for
a low-to-high transition of CLKB. The B0–B31 outputs are in the high-impedance state when W/RB is low.
detailed description
reset
The FIFO memories of the SN74ACT3638 are reset separately by taking their reset (RST1, RST2) inputs low
for at least four port-A clock (CLKA) and four port-B clock (CLKB) low-to-high transitions. The reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read and write pointers and forces the
input-ready flag (IRA, IRB) low, the output-ready flag (ORA, ORB) low, the almost-empty flag (AEA, AEB) low,
and the almost-full flag (AFA, AFB) high. Resetting a FIFO also forces the mailbox flag (MBF1, MBF2) of the
parallel mailbox register high. After a FIFO is reset, its input-ready flag is set high after two clock cycles to begin
normal operation. A FIFO must be reset after power up before data is written to its memory.
A low-to-high transition on a FIFO reset (RST1, RST2) input latches the value of the flag-select (FS0, FS1)
inputs for choosing the almost-full and almost-empty offset programming method (see almost-empty and
almost-full flag offset programming).
almost-empty flag and almost-full flag offset programming
FourregistersintheSN74ACT3638areusedtoholdtheoffsetvaluesforthealmost-emptyandalmost-fullflags.
The port-B almost-empty flag (AEB) offset register is labeled X1, and the port-A almost-empty flag (AEA) offset
register is labeled X2. The port-A almost-full flag (AFA) offset register is labeled Y1, and the port-B almost-full
flag (AFB) offset register is labeled Y2. The index of each register name corresponds to its FIFO number. The
offset registers can be loaded with preset values during the reset of a FIFO or they can be programmed from
port A (see Table 1).
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
almost-empty flag and almost-full flag offset programming (continued)
Table 1. Flag Programming
†
‡
FS1
H
FS0
H
RST1 RST2
X1 AND Y1 REGISTERS
X2 AND Y2 REGISTERS
↑
X
↑
X
↑
64
X
X
64
X
H
H
H
L
X
↑
16
X
H
L
X
↑
16
X
L
H
X
↑
8
L
H
X
↑
X
8
L
L
↑
Programmed from port A
Programmed from port A
†
‡
X1 register holds the offset for AEB; Y1 register holds the offset for AFA.
X2 register holds the offset for AEA; Y2 register holds the offset for AFB.
To load the almost-empty flag and almost-full flag offset registers of a FIFO with one of the three preset values
listed in Table 1, at least one of the flag-select inputs must be high during the low-to-high transition of its reset
input. For example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be high when FIFO1 reset
(RST1) returns high. Flag-offset registers associated with FIFO2 are loaded with one of the preset values in the
same way with FIFO2 reset (RST2). When using one of the preset values for the flag offsets, the FIFOs can
be reset simultaneously or at different times.
To program the X1, X2, Y1, and Y2 registers from port A, both FIFOs should be reset simultaneously with FS0
and FS1 low during the low-to-high transition of the reset inputs. After this reset is complete, the first four writes
to FIFO1 do not store data in RAM but load the offset registers in the order Y1, X1, Y2, X2. Each offset register
uses port-A (A8–A0) inputs, with A8 as the most-significant bit. Each register value can be programmed from
1 to 508. After all the offset registers are programmed from port A, the port-B input-ready flag (IRB) is set high,
and both FIFOs begin normal operation.
FIFO write/read operation
The state of the port-A data (A0–A31) outputs is controlled by the port-A chip select (CSA) and the port-A
write/read select (W/RA). The A0–A31 outputs are in the high-impedance state when either CSA or W/RA is
high. The A0–A31 outputs are active when both CSA and W/RA are low.
Data is loaded into FIFO1 from the A0–A31 inputs on a low-to-high transition of CLKA when CSA is low, W/RA
ishigh, ENAishigh, MBAislow, andIRAishigh. DataisreadfromFIFO2totheA0–A31outputsbyalow-to-high
transition of CLKA when CSA is low, W/RA is low, ENA is high, MBA is low, and ORA is high (see Table 2). FIFO
reads and writes on port A are independent of any concurrent port-B operation.
Table 2. Port-A Enable Function Table
CSA W/RA ENA
MBA CLKA
A0–A31 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO2 output register
Active, FIFO2 output register
Active, mail2 register
PORT FUNCTION
None
H
L
L
L
L
L
L
L
X
H
H
H
L
X
L
X
X
L
X
X
↑
None
H
H
L
FIFO1 write
Mail1 write
None
H
L
↑
X
↑
L
H
L
L
FIFO2 read
None
L
H
H
X
↑
L
H
Active, mail2 register
Mail2 read (set MBF2 high)
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
FIFO write/read operation (continued)
The port-B control signals are identical to those of port A with the exception that the port-B write/read select
(W/RB) is the inverse of the port-A write/read select (W/RA). The state of the port-B data (B0–B31) outputs is
controlled by the port-B chip select (CSB) and the port-B write/read select (W/RB). The B0–B31 outputs are
in the high-impedance state when either CSB is high or W/RB is low. The B0–B31 outputs are active when CSB
is low and W/RB is high.
Data is loaded into FIFO2 from the B0–B31 inputs on a low-to-high transition of CLKB when CSB is low, W/RB
is low, ENB is high, MBB is low, and IRB is high. Data is read from FIFO1 to the B0–B31 outputs by a low-to-high
transition of CLKB when CSB is low, W/RB is high, ENB is high, MBB is low, and ORB is high (see Table 3). FIFO
reads and writes on port B are independent of any concurrent port-A operation.
Table 3. Port-B Enable Function Table
CSB W/RB ENB
MBB CLKB
B0–B31 OUTPUTS
In high-impedance state
In high-impedance state
In high-impedance state
In high-impedance state
Active, FIFO1 output register
Active, FIFO1 output register
Active, mail1 register
PORT FUNCTION
None
H
L
L
L
L
L
L
L
X
L
X
L
X
X
L
X
X
↑
None
L
H
H
L
FIFO2 write
Mail2 write
None
L
H
L
↑
H
H
H
H
X
↑
H
L
L
FIFO1 read
None
H
H
X
↑
H
Active, mail1 register
Mail1 read (set MBF1 high)
The setup- and hold-time constraints to the port clocks for the port-chip selects and write/read selects are only
for enabling write and read operations and are not related to high-impedance control of the data outputs. If a
port enable is low during a clock cycle, the port-chip select and write/read select can change states during the
setup- and hold-time window of the cycle.
When a FIFO output-ready flag is low, the next data word is sent to the FIFO output register automatically by
the low-to-high transition of the port clock that sets the output-ready flag high. When the output-ready flag is
high, an available data word is clocked to the FIFO output register only when a FIFO read is selected by the
port-chip select, write/read select, enable, and mailbox select.
synchronized FIFO flags
Each FIFO is synchronized to its port clock through at least two flip-flop stages. This is done to improve
flag-signal reliability by reducing the probability of metastable events when CLKA and CLKB operate
asynchronously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA. ORB, AEB, IRB, and AFB
are synchronized to CLKB. Tables 4 and 5 show the relationship of each port flag to FIFO1 and FIFO2.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
synchronized FIFO flags (continued)
Table 4. FIFO1 Flag Operation
SYNCHRONIZED
TO CLKB
SYNCHRONIZED
TO CLKA
NUMBER OF WORDS
†‡
IN FIFO1
ORB
L
AEB
L
AFA
H
IRA
H
0
1 to X1
(X1 + 1) to [512 – (Y1 + 1)]
(512 – Y1) to 511
512
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
†
‡
X1 is the almost-empty offset for FIFO1 used by AEB. Y1 is the almost-full
offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of
FIFO1 or programmed from port A.
When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.
Table 5. FIFO2 Flag Operation
SYNCHRONIZED
TO CLKA
SYNCHRONIZED
TO CLKB
NUMBER OF WORDS
‡§
IN FIFO2
ORA
L
AEA
L
AFB
H
IRB
H
0
1 to X2
(X2 + 1) to [512 – (Y2 +1)]
(512 – Y2) to 511
512
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
‡
§
When a word loaded to an empty FIFO is shifted to the output register, its
previous FIFO memory location is free.
X2 is the almost-empty offset for FIFO2 used by AEA. Y2 is the almost-full
offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset
of FIFO2 or programmed from port A.
output-ready flags (ORA, ORB)
The output-ready flag of a FIFO is synchronized to the port clock that reads data from its array. When the
output-ready flag is high, new data is present in the FIFO output register. When the output-ready flag is low, the
previous data word is present in the FIFO output register and attempted FIFO reads are ignored.
A FIFO read pointer is incremented each time a new word is clocked to its output register. From the time a word
is written to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles of the output-ready
flag synchronizing clock; therefore, an output-ready flag is low if a word in memory is the next data to be sent
to the FIFO output register and three cycles of the port clock that reads data from the FIFO have not elapsed
since the time the word was written. The output-ready flag of the FIFO remains low until the third low-to-high
transition of the synchronizing clock occurs, simultaneously forcing the output-ready flag high and shifting the
word to the FIFO output register.
A low-to-high transition on an output-ready flag synchronizing clock begins the first synchronization cycle of a
write if the clock transition occurs at time t , or greater, after the write. Otherwise, the subsequent clock cycle
sk1
can be the first synchronization cycle (see Figures 7 and 8).
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
input-ready flags (IRA, IRB)
The input-ready flag of a FIFO is synchronized to the port clock that writes data to its array. When the input-ready
flag is high, a memory location is free in the SRAM to receive new data. No memory locations are free when
the input-ready flag is low and attempted writes to the FIFO are ignored.
Each time a word is written to a FIFO, its write pointer is incremented. From the time a word is read from a FIFO,
its previous memory location is ready to be written in a minimum of two cycles of the input-ready flag
synchronizing clock; therefore, an input-ready flag is low if less than two cycles of the input-ready flag
synchronizing clock have elapsed since the next memory write location has been read. The second low-to-high
transition on the input-ready flag synchronizing clock after the read sets the input-ready flag high.
A low-to-high transition on an input-ready flag synchronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time t , or greater, after the read. Otherwise, the subsequent clock cycle
sk1
can be the first synchronization cycle (see Figures 9 and 10).
ready flags (RDYA, RDYB)
A ready flag is provided on each port to show if the transmitting or receiving FIFO chosen by the port write/read
select is available for data transfer. The port-A ready flag (RDYA) outputs the complement of the IRA flag when
W/RA is high and the complement of the ORA flag when W/RA is low. The port-B ready flag (RDYB) outputs
the complement of the IRB flag when W/RB is low and the complement of the ORB flag when W/RB is high (see
Figures 11 and 12).
almost-empty flags (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the port clock that reads data from its array. The
almost-empty state is defined by the contents of register X1 for AEB and register X2 for AEA. These registers
are loaded with preset values during a FIFO reset or programmed from port A (see almost-empty flag and
almost-full flag offset programming). A FIFO is almost empty when it contains X or fewer words in memory and
is no longer almost empty when it contains (X + 1) or more words. Note that a data word present in the FIFO
output register has been read from memory.
Two low-to-high transitions of the almost-empty flag synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill; therefore, the almost-empty flag of a FIFO containing (X + 1)
or more words remains low if two cycles of its synchronizing clock have not elapsed since the write that filled
the memory to the (X + 1) level. An almost-empty flag is set high by the second low-to-high transition of its
synchronizing clock after the FIFO write that fills memory to the (X + 1) level. A low-to-high transition of an
almost-empty flag synchronizing clock begins the first synchronization cycle if it occurs at time t , or greater,
sk2
after the write that fills the FIFO to (X + 1) words. Otherwise, the subsequent synchronizing clock cycle can be
the first synchronization cycle (see Figures 13 and 14).
almost-full flags (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port clock that writes data to its array. The almost-full state
is defined by the contents of register Y1 for AFA and register Y2 for AFB. These registers are loaded with preset
values during a FIFO reset or programmed from port A (see almost-empty flag and almost-full flag offset
programming). A FIFO is almost full when it contains (512 – Y) or more words in memory and is not almost full
when it contains [512 – (Y + 1)] or fewer words. A data word present in the FIFO output register has been read
from memory.
almost-full flags (AFA, AFB) (continued)
Two low-to-high transitions of the almost-full flag synchronizing clock are required after a FIFO read for its
almost-full flag to reflect the new level of fill; therefore, the almost-full flag of a FIFO containing [512 – (Y + 1)]
or fewer words remains low if two cycles of its synchronizing clock have not elapsed since the read that reduced
the number of words in memory to [512 – (Y + 1)]. An almost-full flag is set high by the second low-to-high
transition of its synchronizing clock after the FIFO read that reduces the number of words in memory to
[512 – (Y + 1)]. Alow-to-hightransitionofanalmost-fullflagsynchronizingclockbeginsthefirstsynchronization
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
cycle if it occurs at time t , or greater, after the read that reduces the number of words in memory to
sk2
[512 – (Y + 1)]. Otherwise, the subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figures 15 and 16).
synchronous retransmit
The synchronous retransmit feature of the SN74ACT3638 allows FIFO1 data to be read repeatedly, starting at
a user-selected position. FIFO1 is first put into retransmit mode to select a beginning word and prevent ongoing
FIFO write operations from destroying retransmit data. Data vectors with a minimum length of three words can
retransmit repeatedly, starting at the selected word. FIFO1 can be taken out of retransmit mode at any time and
allow normal operation.
FIFO1 is put in retransmit mode by a low-to-high transition on CLKB when the retransmit-mode (RTM) input is
high and ORB is high. This rising CLKB edge marks the data present in the FIFO1 output register as the first
retransmit data. FIFO1 remains in retransmit mode until a low-to-high transition on CLKB occurs while RTM is
low.
When two or more reads have been completed past the initial retransmit word, a retransmit is initiated by a
low-to-high transition on CLKB when the read-from-mark (RFM) input is high. This rising CLKB edge shifts the
first retransmit word to the FIFO1 output register and subsequent reads can begin immediately. Retransmit
loops can be done endlessly while FIFO1 is in retransmit mode. RFM should not be high during the CLKB rising
edge that takes the FIFO1 out of retransmit mode.
When FIFO1 is put into retransmit mode, it operates with two read pointers. The current read pointer operates
normally, incrementing each time a new word is shifted to the FIFO1 output register and used by the ORB and
AEB flags. The shadow read pointer stores the SRAM location at the time FIFO1 is put into retransmit mode
and does not change until FIFO1 is taken out of retransmit mode. The shadow read pointer is used by the IRA
and AFA flags. Data writes can proceed while FIFO1 is in retransmit mode, AFA is set low by the write that stores
(512 – Y1) words after the first retransmit word, and IR is set low by the 512th write after the first retransmit word.
When FIFO1 is in retransmit mode and RFM is high, a rising CLKB edge loads the current read pointer with the
shadow read-pointer value and the ORB flag reflects the new level of fill immediately. If the retransmit changes
the FIFO1 status out of the almost-empty range, up to two CLKB rising edges after the retransmit cycle are
neededtoswitchAEBhigh(seeFigure18). TherisingCLKBedgethattakesFIFO1outofretransmitmodeshifts
the read pointer used by the IRA and AFA flags from the shadow to the current read pointer. If the change of
read pointer used by IRA and AFA should cause one or both flags to transition high, at least two CLKA
synchronizing cycles are needed before the flags reflect the change. A rising CLKA edge after FIFO1 is taken
out of retransmit mode is the first synchronizing cycle of IRA if it occurs at time t
or greater after the rising
sk1
CLKB edge (see Figure 19). A rising CLKA edge after FIFO1 is taken out of retransmit mode is the first
synchronizing cycle of AFA if it occurs at time t , or greater, after the rising CLKB edge (see Figure 20).
sk2
mailbox registers
Each FIFO has a 32-bit bypass register to pass command and control information between port A and port B
without putting it in queue. The mailbox-select (MBA, MBB) inputs choose between a mail register and a FIFO
for a port data-transfer operation. A low-to-high transition on CLKA writes A0–A31 data to the mail1 register
when a port-A write is selected by CSA, W/RA, and ENA and with MBA high. A low-to-high transition on CLKB
writes B0–B31 data to the mail2 register when a port-B write is selected by CSB, W/RB, and ENB and with MBB
high. Writing data to a mail register sets its corresponding flag (MBF1 or MBF2) low. Attempted writes to a mail
register are ignored while the mail flag is low.
mailbox registers (continued)
When data outputs of a port are active, the data on the bus comes from the FIFO output register when the port
mailbox-select input is low and from the mail register when the port mailbox-select input is high. The mail1
register flag (MBF1) is set high by a low-to-high transition on CLKB when a port-B read is selected by CSB,
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
W/RB, and ENB and with MBB high. The mail2 register flag (MBF2) is set high by a low-to-high transition on
CLKA when a port-A read is selected by CSA, W/RA, and ENA and with MBA high. The data in a mail register
remains intact after it is read and changes only when new data is written to the register.
CLKA
t
h(RS)
CLKB
t
h(FS)
t
su(RS)
t
su(FS)
RST1
FS1, FS0
0,1
t
t
pd(C-IR)
pd(C-IR)
IRA
ORB
AEB
t
pd(C-OR)
t
t
t
pd(R-F)
pd(R-F)
pd(R-F)
AFA
MBF1
†
Figure 1. FIFO1 Reset Loading X1 and Y1 With a Preset Value of Eight
†
FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
CLKA
4
t
su(FS)
RST1,
RST2
t
h(FS)
FS1, FS0
0,0
t
pd(C-IR)
IRA
ENA
t
su(EN)
‡
t
sk1
t
h(EN)
t
t
h(D)
su(D)
A0–31
AFA Offset AEB Offset AFB Offset AEA Offset
(Y1) (X1) (Y2) (X2)
First Word to FIFO1
CLKB
IRB
1
2
t
pd(C-IR)
‡
t
is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition high in the next cycle. If the time between
sk1
the rising edge of CLKA and rising edge of CLKB is less than t
, then IRB may transition high one cycle later than shown.
sk1
NOTE A: CSA = L, W/RA = H, MBA = L. It is not necessary to program offset register on consecutive clock cycles.
Figure 2. Programming the Almost-Full Flag and Almost-Empty Flag Offset Values After Reset
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
t
w(CLKL)
h(EN)
w(CLKH)
t
su(EN)
CLKA
IRA
t
t
t
t
t
su(EN)
h(EN)
h(EN)
CSA
t
t
su(EN)
h(EN)
h(EN)
W/RA
MBA
t
t
t
t
su(EN)
h(EN)
h(EN)
t
h(EN)
h(EN)
t
t
t
t
su(EN)
su(EN)
h(EN)
su(EN)
ENA
t
su(D)
h(D)
†
W1
†
W2
A0–A31
No Operation
†
Written to FIFO1
Figure 3. Port-A Write-Cycle Timing for FIFO1
t
c
t
t
w(CLKL)
t
w(CLKH)
h(EN)
t
su(EN)
CLKB
IRB
t
t
t
t
su(EN)
h(EN)
h(EN)
CSB
t
t
t
su(EN)
h(EN)
h(EN)
W/RB
MBB
ENB
t
t
t
t
su(EN)
h(EN)
h(EN)
t
h(EN)
h(EN)
t
t
t
t
su(EN)
su(EN)
h(EN)
su(EN)
t
su(D)
h(D)
‡
W1
‡
W2
B0–B31
No Operation
‡
Written to FIFO2
Figure 4. Port-B Write-Cycle Timing for FIFO2
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
ORB
CSB
t
h(EN)
W/RB
MBB
ENB
t
su(EN)
t
t
t
t
t
h(EN)
h(EN) su(EN)
h(EN)
su(EN)
t
pd(M-DV)
No
Operation
t
dis
t
a
t
a
t
en
†
W1
†
W2
†
W3
B0–B31
†
Read from FIFO1
Figure 5. Port-B Read-Cycle Timing for FIFO1
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
ORA
CSA
t
h(EN)
W/RA
MBA
ENA
t
su(EN)
t
t
t
t
t
h(EN)
h(EN) su(EN)
h(EN)
su(EN)
t
pd(M-DV)
No
Operation
t
dis
t
a
t
a
t
en
‡
W1
‡
W2
‡
W3
A0–A31
‡
Read from FIFO2
Figure 6. Port-A Read-Cycle Timing for FIFO2
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
CSA
Low
W/RA
High
t
su(EN)
t
t
h(EN)
MBA
ENA
t
su(EN)
h(EN)
High
IRA
t
su(D)
t
h(D)
A0–A31
W1
t
t
t
c
†
t
sk1
w(CLKL)
w(CLKH)
1
2
3
CLKB
ORB
t
t
pd(C-OR)
pd(C-OR)
Old Data in FIFO1 Output Register
t
t
pd(C-R)
pd(C-R)
RDYB
CSB Low
High
W/RB
MBB Low
ENB
t
h(EN)
t
su(EN)
t
a
B0–B31
W1
Old Data in FIFO1 Output Register
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition high and to clock the next word to the FIFO1
sk1
output register in three CLKB cycles. If the time between the rising CLKA edge and rising CLKB edge is less than t
ORB high and load of the first word to the output register may occur one CLKB cycle later than shown.
, then the transition of
sk1
Figure 7. ORB-Flag Timing and First Data-Word Fall-Through When FIFO1 Is Empty
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
Low
CSB
W/RB
t
su(EN)
t
h(EN)
MBB
ENB
IRB
t
su(EN)
t
h(EN)
High
t
su(D)
t
h(D)
B0–B31
W1
t
c
†
t
sk1
t
w(CLKL)
t
w(CLKH)
1
2
3
CLKA
ORA
t
t
pd(C-OR)
pd(C-OR)
Old Data in FIFO2 Output Register
t
t
pd(C-R)
pd(C-R)
RDYA
CSA Low
W/RA
Low
MBA Low
ENA
t
h(EN)
t
su(EN)
t
a
A0–A31
Old Data in FIFO2 Output Register
W1
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition high and to clock the next word to the FIFO2
sk1
output register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than t
ORA high and load of the first word to the output register may occur one CLKA cycle later than shown.
, then the transition of
sk1
Figure 8. ORA-Flag Timing and First Data-Word Fall-Through When FIFO2 Is Empty
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKB
Low
CSB
W/RB
MBB
High
Low
t
t
h(EN)
su(EN)
ENB
ORB
High
t
a
B0–B31 Previous Word in FIFO1 Output Register
Next Word From FIFO1
†
t
sk1
t
c
t
t
w(CLKL)
w(CLKH)
1
2
CLKA
IRA
t
t
t
pd(C-IR)
pd(C-IR)
FIFO1 Full
t
pd(C-R)
pd(C-R)
RDYA
CSA
Low
W/RA
High
t
t
t
h(EN)
su(EN)
MBA
ENA
t
su(EN)
h(EN)
h(D)
t
t
su(D)
A0–A31
To FIFO1
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time
sk1
between the rising CLKB edge and rising CLKA edge is less than t
, then IRA may transition high one CLKA cycle later than shown.
sk1
Figure 9. IRA-Flag Timing and First Available Write When FIFO1 Is Full
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
t
c
t
t
w(CLKL)
w(CLKH)
CLKA
Low
Low
Low
CSA
W/RA
MBA
ENA
ORA
t
t
h(EN)
su(EN)
High
t
a
A0–A31 Previous Word in FIFO2 Output Register
Next Word From FIFO2
†
t
sk1
t
c
t
t
w(CLKH)
w(CLKL)
1
2
CLKB
IRB
t
t
t
pd(C-IR)
pd(C-IR)
FIFO2 Full
t
pd(C-R)
pd(C-R)
RDYB
CSB
Low
Low
W/RB
t
t
t
h(EN)
su(EN)
MBB
ENB
t
su(EN)
h(EN)
t
t
su(D)
h(D)
B0–B31
To FIFO2
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition high in the next CLKB cycle. If the time
sk1
between the rising CLKA edge and rising CLKB edge is less than t
, then IRB may transition high one CLKB cycle later than shown.
sk1
Figure 10. IRB-Flag Timing and First Available Write When FIFO2 Is Full
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
W/RA
RDYA
t
t
pd(W-R)
pd(W-R)
Inverse of IRA
Inverse of ORA
Figure 11. W/RA to RDYA Timing
W/RB
RDYB
t
t
pd(W-R)
pd(W-R)
Inverse of IRB
Inverse of ORB
Figure 12. W/RB to RDYB Timing
CLKA
ENA
t
h(EN)
t
su(EN)
†
t
sk2
CLKB
AEB
1
2
t
t
pd(C-AE)
pd(C-AE)
X1 Words in FIFO1
(X1 + 1) Words in FIFO1
t
h(EN)
t
su(EN)
ENB
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AEB to transition high in the next CLKB cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, then AEB may transition high one CLKB cycle later than shown.
sk2
NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been
read from the FIFO.
Figure 13. Timing for AEB When FIFO1 Is Almost Empty
CLKB
t
h(EN)
t
su(EN)
ENB
‡
t
sk2
CLKA
AEA
1
2
t
t
pd(C-AE)
pd(C-AE)
X2 Words in FIFO2
(X2 + 1) Words in FIFO2
t
h(EN)
t
su(EN)
ENA
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKB edge and rising CLKA edge is less than t
, then AEA may transition high one CLKA cycle later than shown.
sk2
NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been
read from the FIFO.
Figure 14. Timing for AEA When FIFO2 Is Almost Empty
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CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
†
t
sk2
CLKA
ENA
1
2
t
h(EN)
t
su(EN)
t
t
pd(C-AF)
pd(C-AF)
(512 – Y1) Words in FIFO1
AFA
[512 – (Y1 + 1)] Words in FIFO1
CLKB
ENB
t
h(EN)
t
su(EN)
†
t
is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKA edge and rising CLKB edge is less than t
, then AFA may transition high one CLKB cycle later than shown.
sk2
NOTE A: FIFO1 write (CSA = L, W/RA = H, MBA = L), FIFO1 read (CSB = L, W/RB = H, MBB = L). Data in the FIFO1 output register has been
read from the FIFO.
Figure 15. Timing for AFA When FIFO1 Is Almost Full
‡
t
sk2
CLKB
ENB
1
2
t
h(EN)
t
su(EN)
t
t
pd(C-AF)
pd(C-AF)
(512 – Y2) Words in FIFO2
AFB
[512 – (Y2 + 1)] Words in FIFO2
CLKA
ENA
t
h(EN)
t
su(EN)
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition high in the next CLKB cycle. If the time
sk2
between the rising CLKB edge and rising CLKA edge is less than t
, then AFB may transition high one CLKA cycle later than shown.
sk2
NOTE A: FIFO2 write (CSB = L, W/RB = L, MBB = L), FIFO2 read (CSA = L, W/RA = L, MBA = L). Data in the FIFO2 output register has been
read from the FIFO.
Figure 16. Timing for AFB When FIFO2 Is Almost Full
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
CLKB
ENB
t
t
t
t
t
su(EN)
h(EN)
su(EN)
h(EN)
t
t
t
su(RM)
h(RM)
su(RM)
h(RM)
RTM
RFM
t
t
su(RM)
h(RM)
ORB
High
t
a
t
a
t
a
t
a
B0–B31
W0
W1
W2
W0
W1
Initiate Retransmit Mode
With W0 as First Word
Retransmit From
Selected Position
End Retransmit
Mode
NOTE A: CSB = L, W/RB = H, MBB = L. No input enables other than RTM and RFM are needed to control retransmit mode or begin a retransmit.
Other enables are shown only to relate retransmit operations to the FIFO1 output register.
Figure 17. FIFO1 Retransmit Timing Showing Minimum Retransmit Length
CLKB
RTM
1
2
High
t
h(RM)
t
su(RM)
RFM
AEB
t
pd(C-AE)
X1 or Fewer Words From Empty
(X1 + 1) or More Words From Empty
NOTE A: X1 is the value loaded in the almost-full flag offset register.
Figure 18. AEB Maximum Latency When Retransmit Increases the Number of Stored Words Above X1
21
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SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
†
t
sk1
CLKA
IRA
1
2
t
pd(C-IR)
FIFO1 Filled to First Retransmit Word
One or More FIFO1 Write Locations
Available
CLKB
t
t
h(RM)
su(RM)
RTM
†
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition high in the next CLKA cycle. If the time
sk1
between the rising CLKB edge and rising CLKA edge is less than t
, then IRA may transition high one CLKA cycle later than shown.
sk1
Figure 19. IRA Timing From the End of Retransmit Mode When One or More
FIFO1 Write Locations Are Available
‡
t
sk2
CLKA
AFA
1
2
t
pd(C-AE)
(512 – Y1) or More Words Past First Retransmit Word
(Y1+ 1) or More Write Locations Available
CLKB
t
t
su(RM)
h(RM)
RTM
‡
t
is the minimum time between a rising CLKB edge and a rising CLKA edge for AFA to transition high in the next CLKA cycle. If the time
sk2
between the rising CLKB edge and rising CLKA edge is less than t
, then AFA may transition high one CLKA cycle later than shown.
sk2
NOTE A: Y is the value loaded in the almost-full flag offset register.
Figure 20. AFA Timing From the End of Retransmit Mode When (Y1 + 1) or More
FIFO1 Write Locations Are Available
22
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SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
CLKA
t
h(EN)
t
su(EN)
CSA
W/RA
MBA
ENA
t
h(D)
t
su(D)
A0–A31
W1
CLKB
MBF1
t
t
pd(C-MF)
pd(C-MF)
CSB
W/RB
MBB
ENB
t
h(EN)
t
su(EN)
t
pd(M-DV)
t
dis
t
en
t
pd(C-MR)
B0–B31
W1 (remains valid in mail1 register after read)
FIFO1 Output Register
Figure 21. Timing for Mail1 Register and MBF1 Flag
23
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
CLKB
t
h(EN)
t
su(EN)
CSB
W/RB
MBB
ENB
t
h(D)
t
su(D)
B0–B31
W1
CLKA
MBF2
t
t
pd(C-MF)
pd(C-MF)
CSA
W/RA
MBA
ENA
t
h(EN)
t
su(EN)
t
pd(M-DV)
t
dis
t
en
t
pd(C-MR)
A0–A31
W1 (remains valid in mail2 register after read)
FIFO2 Output Register
Figure 22. Timing for Mail2 Register and MBF2 Flag
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
+ 0.5 V
I
CC
CC
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
O
Input clamp current, I (V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
I
CC
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Package thermal impedance,
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±400 mA
(see Note 2): PCB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28°C/W
PQ package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46°C/W
JA
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
24
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
recommended operating conditions
MIN
4.5
2
MAX
UNIT
V
V
V
V
Supply voltage
5.5
CC
High-level input voltage
Low-level input voltage
High-level output current
Low-level output current
Operating free-air temperature
V
IH
0.8
–4
8
V
IL
I
I
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
PARAMETER
TEST CONDITIONS
= –4 mA
MIN TYP
MAX
UNIT
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I
I
2.4
OH
OH
= 8 mA
0.5
±5
V
OL
OL
I
I
I
V = V
or 0
µA
µA
µA
I
I
CC
V
= V
or 0
±5
OZ
CC
O
CC
V = V
– 0.2 V or 0
400
I
CC
CSA = V
CSB = V
CSA = V
CSB = V
A0–A31
B0–B31
A0–A31
B0–B31
0
0
IH
IH
IL
IL
V
= 5.5 V, One input at 3.4 V,
CC
‡
∆I
CC
1
1
1
mA
Other inputs at V
or GND
CC
All other inputs
C
C
V = 0,
f = 1 MHz
f = 1 MHz
4
8
pF
pF
i
I
V
O
= 0,
o
†
‡
All typical values are at V
= 5 V, T = 25°C.
A
CC
This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or V
.
CC
25
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (see Figures 1 through 23)
’ACT3638-15 ’ACT3638-20 ’ACT3638-30
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
t
Clock frequency, CLKA or CLKB
66.7
50
33.4
MHz
ns
clock
Clock cycle time, CLKA or CLKB
15
6
20
8
30
10
10
6
c
Pulse duration, CLKA and CLKB high
Pulse duration, CLKA and CLKB low
ns
w(CLKH)
w(CLKL)
su(D)
6
8
ns
Setup time, A0–A31 before CLKA↑ and B0–B31 before CLKB↑
4.5
5
ns
Setup time, CSA, W/RA, ENA, and MBA before CLKA↑; CSB,
W/RB, ENB, and MBB before CLKB↑
t
5
6
7
ns
su(EN)
t
t
t
t
Setup time, RTM and RFM before CLKB↑
6
5
7
0
6.5
6
7
7
9
0
ns
ns
ns
ns
su(RM)
su(RS)
su(FS)
h(D)
†
Setup time, RST1 or RST2 low before CLKA↑ or CLKB↑
Setup time, FS0 and FS1 before RST1 and RST2 high
8
Hold time, A0–A31 after CLKA↑ and B0–B31 after CLKB↑
0
Hold time, CSA, W/RA, ENA, and MBA after CLKA↑; CSB, W/
RB, ENB, and MBB after CLKB↑
t
0
0
0
ns
h(EN)
t
t
t
Hold time, RTM and RFM after CLKB↑
0
4
2
0
4
3
0
5
3
ns
ns
ns
h(RM)
h(RS)
h(FS)
†
Hold time, RST1 or RST2 low after CLKA↑ or CLKB↑
Hold time, FS0 and FS1 after RST1 and RST2 high
Skew time between CLKA↑ and CLKB↑ for ORA, ORB, IRA, and
IRB
‡
t
8
9
11
20
ns
ns
sk1
Skew time between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and
AFB
‡
t
12
16
sk2
†
‡
Requirement to count the clock edge as one of at least four needed to reset a FIFO
Skew time is not a timing constraint for proper device operation and is included only to illustrate the timing relationship between CLKA cycle and
CLKB cycle.
26
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C = 30 pF (see Figures 1 through 23)
L
’ACT3638-15 ’ACT3638-20 ’ACT3638-30
PARAMETER
UNIT
MIN
MAX
MIN
50
3
MAX
MIN
MAX
f
t
t
t
t
t
t
t
66.7
3
33.4
3
MHz
ns
max
Access time, CLKA↑ to A0–A31 and CLKB↑ to B0–B31
Propagation delay time, CLKA↑ to IRA and CLKB↑ to IRB
Propagation delay time, CLKA↑ to ORA and CLKB↑ to ORB
Propagation delay time, CLKA↑ to RDYA and CLKB↑ to RDYB
Propagation delay time, W/RA to RDYA and W/RB to RDYB
Propagation delay time, CLKA↑ to AEA and CLKB↑ to AEB
Propagation delay time, CLKA↑ to AFA and CLKB↑ to AFB
11
8
13
10
10
10
10
10
10
15
12
12
12
12
12
12
a
1
1
1
ns
pd(C-IR)
pd(C-OR)
pd(C-R)
pd(W-R)
pd(C-AE)
pd(C-AF)
1
8
1
1
ns
1
8
1
1
ns
1
8
1
1
ns
1
8
1
1
ns
1
8
1
1
ns
Propagation delay time, CLKA↑ to MBF1 low or MBF2 high and
CLKB↑ to MBF2 low or MBF1 high
t
t
t
0
3
3
8
13.5
13
0
3
3
10
15
15
0
3
3
12
17
17
ns
ns
ns
pd(C-MF)
pd(C-MR)
pd(M-DV)
†
Propagation delay time, CLKA↑ to B0–B31 and CLKB↑ to
‡
A0–A31
Propagation delay time, MBA to A0–A31 valid and MBB to
B0–B31 valid
Propagation delay time, RST1 low to AEB low, AFA high, and
MBF1 high, and RST2 low to AEA low, AFB high, and MBF2
high
t
1
15
1
20
1
30
ns
pd(R-F)
Enable time, CSA and W/RA low to A0–A31 active and CSB
low and W/RB high to B0–B31 active
t
t
2
1
12
13
2
1
13
14
2
1
14
15
ns
ns
en
Disable time, CSA or W/RA high to A0–A31 at high impedance
and CSB high or W/RB low to B0–B31 at high impedance
dis
†
‡
Writing data to the mail1 register when the B0–B31 outputs are active and MBB is high
Writing data to the mail2 register when the A0–A31 outputs are active and MBA is high
27
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
PARAMETER MEASUREMENT INFORMATION
5 V
1.1 kΩ
From Output
Under Test
30 pF
(see Note A)
680 Ω
LOAD CIRCUIT
3 V
3 V
Timing
Input
High-Level
Input
1.5 V
t
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
h
w
t
su
Data,
Enable
Input
3 V
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
PLZ
t
PZL
≈ 3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
V
V
OL
GND
t
PZH
t
t
pd
pd
OH
High-Level
Output
V
V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
≈ 0 V
OL
t
PHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTE A: Includes probe and jig capacitance
Figure 23. Load Circuit and Voltage Waveforms
28
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT3638
512 × 32 × 2
CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
SCAS228D – JUNE 1992 – REVISED APRIL 1998
TYPICAL CHARACTERISTICS
SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
250
200
150
100
50
f
T
C
= 1/2 f
clock
data
= 75°C
A
= 0 pF
L
V
CC
= 5.5 V
V
CC
= 5 V
V
CC
= 4.5 V
0
0
10
20
30
40
50
60
70
f
– Clock Frequency – MHz
clock
Figure 24
29
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
19-Sep-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
OBSOLETE HLQFP
OBSOLETE BQFP
OBSOLETE HLQFP
OBSOLETE BQFP
OBSOLETE HLQFP
OBSOLETE BQFP
Drawing
PCB
PQ
SN74ACT3638-15PCB
SN74ACT3638-15PQ
SN74ACT3638-20PCB
SN74ACT3638-20PQ
SN74ACT3638-30PCB
SN74ACT3638-30PQ
120
132
120
132
120
132
TBD
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
PCB
PQ
PCB
PQ
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
MECHANICAL DATA
MBQF001A – NOVEMBER 1995
PQ (S-PQFP-G***)
PLASTIC QUAD FLATPACK
100 LEAD SHOWN
13
1 100
89
14
88
0.012 (0,30)
0.008 (0,20)
0.006 (0,15)
M
”D3” SQ
0.025 (0,635)
0.006 (0,16) NOM
64
38
0.150 (3,81)
0.130 (3,30)
39
63
Gage Plane
”D1” SQ
”D” SQ
0.010 (0,25)
0.020 (0,51) MIN
Seating Plane
”D2” SQ
0°–8°
0.046 (1,17)
0.036 (0,91)
0.004 (0,10)
0.180 (4,57) MAX
LEADS ***
100
132
DIM
MAX
MIN
0.890 (22,61)
0.870 (22,10)
0.766 (19,46)
0.734 (18,64)
0.912 (23,16)
0.888 (22,56)
0.600 (15,24)
1.090 (27,69)
1.070 (27,18)
0.966 (24,54)
0.934 (23,72)
1.112 (28,25)
1.088 (27,64)
0.800 (20,32)
”D”
MAX
MIN
”D1”
MAX
MIN
”D2”
”D3”
NOM
4040045/C 11/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-069
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL DATA
MHTQ004A – JANUARY 1995 – REVISED JANUARY 1998
PCB (S-PQFP-G120)
PLASTIC QUAD FLATPACK (DIE DOWN)
0,23
0,13
M
0,07
0,40
90
61
Heat Slug
60
91
31
120
0,13 NOM
1
30
11,60 TYP
Gage Plane
14,20
SQ
13,80
0,25
16,20
SQ
0,05 MIN
0°–7°
15,80
1,45
1,35
0,75
0,45
Seating Plane
0,08
1,60 MAX
4040202/C 12/96
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Thermally enhanced molded plastic package with a heat slug (HSL)
D. Falls within JEDEC MS-026
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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相关型号：
SN74ACT3641-20PCB
FIFO, 1KX36, 13ns, Synchronous, CMOS, PQFP120, GREEN, PLASTIC, HLQFP-120
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