SN74ACT7200L15RJ [ROCHESTER]
256X9 OTHER FIFO, 15ns, PQCC32, PLASTIC, LCC-32;
| 型号： | SN74ACT7200L15RJ |
| 厂家： | 
Rochester Electronics |
| 描述： | 256X9 OTHER FIFO, 15ns, PQCC32, PLASTIC, LCC-32 先进先出芯片 |
| 文件： | 总24页 (文件大小：989K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
DV OR NP PACKAGE
(TOP VIEW)
Reads and Writes Can Be Asynchronous
or Coincident
Organization:
W
D8
D3
D2
D1
D0
XI
V
CC
D4
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
– SN74ACT7200L – 256 × 9
– SN74ACT7201LA – 512 × 9
– SN74ACT7202LA – 1024 × 9
D5
D6
D7
FL/RT
RS
Fast Data Access Times of 15 ns
Read and Write Frequencies up to 40 MHz
Bit-Width and Word-Depth Expansion
FF
Q0
EF
XO/HF
Fully Compatible With the
IDT7200/7201/7202
Q1 10
19 Q7
Retransmit Capability
Q2
Q3
Q6
Q5
11
12
18
17
Empty, Full, and Half-Full Flags
TTL-Compatible Inputs
Q8 13
16 Q4
15
GND 14
R
Available in 28-Pin Plastic DIP (NP),
Small-Outline (DV), and 32-Pin Plastic
J-Leaded Chip-Carrier (RJ) Packages
RJ PACKAGE
(TOP VIEW)
description
The SN74ACT7200L, SN74ACT7201LA, and
SN74ACT7202LA are constructed with dual-port
SRAM and have internal write and read address
counters to provide data throughput on a first-in,
first-out (FIFO) basis. Write and read operations
are independent and can be asynchronous or
coincident. Empty and full status flags prevent
underflow and overflow of memory, and
depth-expansion logic allows combining the
storage cells of two or more devices into one
FIFO. Word-width expansion is also possible.
4
3
2
1
32 31 30
29
5
6
7
8
9
D2
D1
D0
XI
D6
D7
NC
FL/RT
RS
28
27
26
25
FF
Q0 10
24 EF
Q1
NC
Q2
XO/HF
Q7
Q6
11
12
13
23
22
21
14 15 16 17 18 19 20
Data is loaded into memory by the write-enable
(W) input and unloaded by the read-enable (R)
input. Read and write cycle times of 25 ns
(40 MHz) are possible with data access times of
15 ns.
NC – No internal connection
These devices are particularly suited for providing a data channel between two buses operating at
asynchronous rates. Applications include use as rate buffers from analog-to-digital converters in data-
acquisition systems, temporary storage elements between buses and magnetic or optical memories, and
queues for communication systems. A 9-bit-wide data path is provided for the transmission of byte data plus
a parity bit or packet-framing information. The read pointer can be reset independently of the write pointer for
retransmitting previously read data when a device is not used in depth expansion.
The SN74ACT7200L, SN74ACT7201LA, and SN74ACT7202LA are characterized for operation from 0°C
to 70°C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 1995, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7200L logic symbol
FIFO 256 × 9
Φ
SN74ACT7200L
22
2,4 CT = 0 (RST)
RS
W
8
1
2(CT = 255) G6
4(CT = 255) G6
(CT = 256) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 128
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7201LA logic symbol
FIFO 512 × 9
Φ
SN74ACT7201LA
22
2,4 CT = 0 (RST)
RS
8
1
2(CT = 511) G6
4(CT = 511) G6
(CT = 512) G6
FF
6 (WR PNTR)
6 C1
W
G2
7
21
20
(EXPAND)
XI
23
(CT = 0) G5
EF
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 256
15
R
5 (RD PNTR)
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
D0
5
9
10
11
12
16
17
18
19
13
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
D1
4
D2
3
D3
27
D4
26
D5
25
D6
24
D7
2
D8
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
SN74ACT7202LA logic symbol
FIFO 1024 × 9
Φ
SN74ACT7202LA
22
2,4 CT = 0 (RST)
RS
W
8
1
2(CT = 1023) G6
4(CT = 1023) G6
(CT = 1024) G6
FF
6 (WR PNTR)
6 C1
G2
7
21
20
(EXPAND)
XI
(CT = 0) G5
EF
23
(1ST LOAD)
2,4 (REXMIT)
FL/RT
XO/HF
(EXPAND)
CT > 512
15
5 (RD PNTR)
R
5EN3
G4
(CT = WR PNTR – RD PNTR)
6
9
10
11
12
16
17
18
19
13
D0
D1
D2
D3
D4
D5
D6
D7
D8
1D
3
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
5
4
3
27
26
25
24
2
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the DV and NP packages.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
functional block diagram
9
D0–D8
Location 1
Location 2
256 × 9 or
512 × 9 or
1024 × 9
RAM
Write
Control
Write
Pointer
Read
Pointer
W
†
•
•
9
Q0–Q8
RS
Reset
Logic
FL/RT
Status-
Flag
Logic
FF
EF
Read
Control
R
Expansion
Logic
XO/HF
XI
†
256 × 9 for SN74ACT7200L; 512 × 9 for SN74ACT7201LA; 1024 × 9 for SN74ACT7202LA
RESET AND RETRANSMIT FUNCTION TABLE
(single-device depth; single-or multiple-device width)
INPUTS
INTERNAL TO DEVICE
OUTPUTS
FUNCTION
RS
L
FL/RT
XI
L
READ POINTER
WRITE POINTER
Location zero
Unchanged
EF
L
FF
H
XO/HF
X
L
Location zero
Location zero
H
X
X
Reset device
Retransmit
Read/write
H
L
X
X
H
H
L
Increment if EF high Increment if FF high
X
X
RESET AND FIRST-LOAD FUNCTION TABLE
(multiple-device depth; single-or multiple-device width)
INPUTS
INTERNAL TO DEVICE OUTPUTS
EF
FUNCTION
RS
L
FL/RT
XI
READ POINTER
WRITE POINTER
Location zero
Location zero
X
FF
H
‡
L
H
X
Location zero
Location zero
X
L
L
Reset first device
Reset all other devices
Read/write
‡
‡
L
H
H
X
X
‡
XI is connected to XO/HF of the previous device in the daisy chain (see Figure 15).
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
D0–D8
I
Data inputs
Empty-flag output. EF is low when the read pointer is equal to the write pointer, inhibiting any operation initiated by a read
cycle. When the FIFO is empty, a data word can be read automatically at Q0–Q8 by holding R low when loading the data
word with a low-level pulse on W.
O
O
EF
FF
Full-flag output. FF is low when the write pointer is one location less than the read pointer, indicating that the device is
full and inhibiting any operation initiated by a write cycle. FF goes low when the number of writes after reset exceeds the
number of reads by 256 for the SN74ACT7200L, 512 for the SN74ACT7201LA, and 1024 for the SN74ACT7202LA.
When the FIFO is full, a data word can be written automatically into memory by holding W low while reading out another
data word with a low-level pulse on R.
First-load/retransmitinput. FL/RT performs two separate functions. When cascading two or more devices for word-depth
expansion, FL/RT is tied to ground on the first device in the daisy chain to indicate that it is the first device loaded and
unloaded; it is tied high on all other devices in the depth-expansion chain.
A device is not used in depth expansion when its expansion (XI) input is tied to ground. In that case, FL/RT acts as a
retransmit enable. A retransmit operation is initiated when FL/RT is pulsed low. This sets the internal read pointer to the
first location and does not affect the write pointer. R and W must be at a high logic level during the low-level FL/RT
retransmit pulse. Retransmit should be used only when less than 256/512/1024 writes are performed between resets;
otherwise, an attempt to retransmit can cause the loss of unread data. The retransmit function can affect XO/HF
depending on the relative locations of the read and write pointers.
I
FL/RT
GND
Ground
Q0–Q8
O
I
Data outputs. Q0–Q8 are in the high-impedance state when R is high or the FIFO is empty.
Read-enable input. A read cycle begins on the falling edge of R if EF is high. This activates Q0–Q8 and shifts the next
data value to this bus. The data outputs return to the high-impedance state as R goes high. As the last stored word is
read by the falling edge of R, EF transitions low but Q0–Q8 remain active until R returns high. When the FIFO is empty,
the internal read pointer is unchanged by a pulse on R.
R
Reset input. A reset is performed by taking RS low. This initializes the internal read and write pointers to the first location
and sets EF low, FF high, and HF high. Both R and W must be held high for a reset during the window shown in Figure 7.
A reset is required after power up before a write operation can take place.
I
RS
V
CC
Supply voltage
Write-enable input. A write cycle begins on the falling edge of W if FF is high. The value on D0–D8 is stored in memory
as W returns high. When the FIFO is full, FF is low, inhibiting W from performing any operation on the device.
I
I
W
Expansion-in input. XI performs two functions. XI is tied to ground to indicate that the device is not used in depth
expansion.When the device is used in depth expansion, XI is connected to the expansion-out (XO) output of the previous
device in the depth-expansion chain.
XI
Expansion-out/half-full-flagoutput. XO/HF performs two functions. When the device is not used in depth expansion (i.e.,
when XI is tied to ground), XO/HF indicates when half the memory locations are filled. After half of the memory is filled,
the falling edge on W for the next write operation drives XO/HF low. XO/HF remains low until a rising edge of R reduces
the number of words stored to exactly half of the total memory.
O
XO/HF
Whenthedeviceisusedindepthexpansion, XO/HFis connected to XI of the next device in the daisy chain. XO/HFdrives
the daisy chain by sending a pulse to the next device when the previous device reaches the last memory location.
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range (any input), V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
Continuous output current, I . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 mA
Voltage applied to a disabled 3-state output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
I
O
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM
MAX
UNIT
V
V
V
Supply voltage
4.5
2.6
2
5
5.5
V
CC
XI
High-level input voltage
V
IH
Other inputs
Low-level input voltage
0.8
–2
8
V
IL
I
I
High-level output current
Low-level output current
Operating free-air temperature
mA
mA
°C
OH
OL
T
A
0
70
electrical characteristics over recommended operating free-air temperature range, V
(unless otherwise noted)
= 5.5 V
CC
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
V
V
V
V
V
V
V
= 4.5 V,
= 4.5 V,
I
I
= – 2 mA
= 8 mA
2.4
OH
CC
OH
0.4
±10
±10
1
V
OL
CC
OL
I
I
I
= V
,
R ≥ V
R ≥ V
µA
µA
µA
OZH
OZL
I
O
O
CC
= 0.4 V,
IH
IH
V = 0 to 5.5 V
I
–1
t
a
t
a
t
a
t
a
t
a
t
a
= 15 and 25 ns
= 35 and 50 ns
= 15 and 25 ns
= 35 and 50 ns
= 15 and 25 ns
= 35 and 50 ns
125
80
‡
mA
mA
mA
I
I
I
CC1
CC2
CC3
50
5
15
‡
‡
R, W, RS, and FL/RT at V
IH
8
0.5
0.5
V = V
– 0.2 V
CC
I
§
C
C
V = 0,
T
= 25°C,
T = 25°C,
A
f = 1 MHz
f = 1 MHz
8
8
pF
pF
i
I
A
§
V
O
= 0,
o
‡
I
= supply current; I
= standby current; I
CC3
= power-down current. I
measurements are made with outputs open (only capacitive
CC
CC1
CC2
loading).
§
¶
This parameter is sampled and not 100% tested.
Tested at f = 20 MHz
clock
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
timing requirements over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted)
′ACT7200L-15
′ACT7201LA-15
′ACT7202LA-15
′ACT7200L-25
′ACT7201LA-25
′ACT7202LA-25
′ACT7200L-50
′ACT7201LA-50
′ACT7202LA-50
†
†
′ACT7201LA-35
′ACT7202LA-35
FIGURE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
f
t
t
t
t
t
t
t
t
t
t
t
t
t
Clock frequency, R or W
Cycle time, read
40
28.5
22.2
15
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clock
1(a)
1(b)
7
25
25
25
25
15
15
10
10
15
15
15
10
11
35
35
35
35
25
25
10
10
25
25
25
10
15
45
45
45
45
35
35
10
10
35
35
35
10
18
65
65
65
65
50
50
15
15
50
50
50
10
30
c(R)
Cycle time, write
c(W)
Cycle time, reset
c(RS)
c(RT)
w(RL)
w(WL)
w(RH)
w(WH)
w(RT)
w(RS)
w(XIL)
w(XIH)
su(D)
Cycle time, retransmit
Pulse duration, R low
Pulse duration, W low
Pulse duration, R high
Pulse duration, W high
Pulse duration, FL/RT low
Pulse duration, RS low
Pulse duration, XI low
Pulse duration, XI high
Setup time, data before W↑
Setup time, R and W high
4
1(a)
1(b)
1(a)
1(b)
4
7
10
10
1(b), 6
t
t
t
t
4
7
15
15
10
10
25
25
10
10
35
35
10
10
50
50
15
15
ns
ns
ns
ns
su(RT)
‡
before FL/RT↑
Setup time, R and W high
su(RS)
‡
before RS↑
Setup time, XI low
before R↓
10
10
su(XI-R)
su(XI-W)
Setup time, XI low
before W↓
t
t
t
Hold time, data after W↑
Hold time, R low after EF↑
Hold time, W low after FF↑
1(b), 6
5, 11
0
15
15
0
25
25
0
35
35
5
50
50
ns
ns
ns
h(D)
h(E-R)
h(F-W)
6, 12
Hold time, R and W high
after FL/RT↑
t
4
7
10
10
10
10
10
10
15
15
ns
ns
h(RT)
h(RS)
Hold time, R and W high
after RS↑
t
†
‡
Released in RJ package only
These values are characterized but not currently tested.
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (see Figure 13)
′ACT7200L-15
′ACT7201LA-15 ′ACT7201LA-25
′ACT7202LA-15 ′ACT7202LA-25
′ACT7200L-25
′ACT7200L-50
′ACT7201LA-50
′ACT7202LA-50
†
†
′ACT7201LA-35
′ACT7202LA-35
PARAMETER
FIGURE
UNIT
MIN MAX
MIN MAX
MIN
MAX
MIN
MAX
1(a), 3,
5
Access time, R↓ or EF↑ to
data out valid
t
t
t
15
25
35
50
ns
ns
ns
a
Valid time, data out valid
after R↑
1(a)
1(a)
5
5
5
5
5
5
v(RH)
en(R-QX)
Enable time, R↓ to Q
outputs at low impedance
10
10
‡
Enable time, W↑ to Q
t
t
5
5
5
5
15
ns
ns
outputs at low
impedance
en(W-QX)
dis(R)
‡§
Disable time, R↑ to Q
outputs at high
1(a)
15
18
20
30
‡
impedance
Pulse duration, FF high in
automatic write mode
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
6
15
15
15
15
25
25
15
15
25
25
25
15
15
15
15
25
25
25
25
25
35
35
25
25
35
35
35
25
25
25
25
35
30
30
30
30
45
45
30
30
45
45
45
35
35
35
35
45
45
45
45
45
65
65
45
45
65
65
65
50
50
50
50
65
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
w(FH)
Pulse duration, EF high in
automatic read mode
5
w(EH)
Propagation delay time,
W↓ to FF low
2
pd(W-F)
Propagation delay time,
R↑ to FF high
2, 6, 12
pd(R-F)
Propagation delay time,
RS↓ to FF high
7
pd(RS-F)
pd(RS-HF)
pd(W-E)
Propagation delay time,
RS↓ to XO/HF high
7
Propagation delay time,
W↑ to EF high
3, 5, 11
Propagation delay time,
R↓ to EF low
3
7
8
8
9
9
9
9
4
pd(R-E)
Propagation delay time,
RS↓ to EF low
pd(RS-E)
pd(W-HF)
pd(R-HF)
pd(R-XOL)
pd(W-XOL)
pd(R-XOH)
pd(W-XOH)
pd(RT-FL)
Propagation delay time,
W↓ to XO/HF low
Propagation delay time,
R↑ to XO/HF high
Propagation delay time,
R↓ to XO/HF low
Propagation delay time,
W↓ to XO/HF low
Propagation delay time,
R↑ to XO/HF high
Propagation delay time,
W↑ to XO/HF high
Propagation delay time,
FL/RT↓ to HF, EF, FF valid
†
Released in RJ package only
‡
§
These values are characterized but not currently tested.
Only applies when data is automatically read (see Figure 5)
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
t
c(R)
w(RL)
w(RH)
t
t
a
t
a
R
t
t
t
dis(R)
v(RH)
en(R-QX)
Q0 –Q8
Valid
Valid
(a) READ
t
c(W)
t
t
w(WH)
w(WL)
W
t
t
h(D)
su(D)
D0 –D8
Valid
Valid
(b) WRITE
Figure 1. Asynchronous Waveforms
Ignored
First Read
Write
Last Write
Additional Reads
R
W
t
t
pd(R-F)
pd(W-F)
FF
Figure 2. Full-Flag Waveforms
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Ignored
Read
Last Read
First Write
Additional Writes
W
R
t
pd(R-E)
t
pd(W-E)
EF
t
a
D0 –D8
Valid
Figure 3. Empty-Flag Waveforms
t
c(RT)
t
w(RT)
FL/RT
W, R
t
t
h(RT)
su(RT)
XO/HF, EF, FF
Valid Flag
t
pd(RT-FL)
NOTE A: The EF, FF, and XO/HF status flags are valid after completion of the retransmit cycle.
Figure 4. Retransmit Waveforms
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
W
R
t
h(E-R)
EF
t
w(EH)
t
t
a
pd(W-E)
t
en(W-QX)
Q0 –Q8
Valid
Figure 5. Automatic-Read Waveforms
R
t
h(F-W)
W
t
pd(R-F)
FF
t
w(FH)
t
h(D)
D0 –D8
Valid
su(D)
t
Figure 6. Automatic-Write Waveforms
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
t
c(RS)
t
w(RS)
RS
W
R
EF
t
t
h(RS)
su(RS)
t
pd(RS-E)
XO/HF, FF
t
pd(RS-HF)
t
pd(RS-F)
Figure 7. Master-Reset Waveforms
Half Full or Less
More Than Half Full
Half Full or Less
W
R
t
pd(R-HF)
t
pd(W-HF)
XO/HF
Figure 8. Half-Full Flag Waveforms
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
Write to Last
Physical Location
W
R
Read From Last
Physical Location
t
pd(W-XOH)
t
t
pd(R-XOH)
t
pd(W-XOL)
pd(R-XOL)
XO/HF
Figure 9. Expansion-Out Waveforms
t
t
w(XIH)
w(XIL)
XI
t
su(XI-W)
Write to First
Physical Location
W
R
t
su(XI-R)
Read From First
Physical Location
Figure 10. Expansion-In Waveforms
W
t
pd(W-E)
EF
R
t
h(E-R)
Figure 11. Minimum Timing for an Empty-Flag Coincident-Read Pulse
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
R
t
pd(R-F)
FF
W
t
h(F-W)
Figure 12. Minimum Timing for a Full-Flag Coincident-Write Pulse
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
PARAMETER MEASUREMENT INFORMATION
5 V
1100 Ω
From Output
Under Test
30 pF
(see Note A)
680 Ω
LOAD CIRCUIT
3 V
3 V
Timing
Input
High-Level
Input
1.5 V
t
1.5 V
1.5 V
1.5 V
GND
GND
3 V
t
h
t
su
w
Data,
Enable
Input
3 V
1.5 V
1.5 V
Low-Level
Input
1.5 V
GND
GND
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
3 V
Output
Enable
1.5 V
1.5 V
GND
t
PLZ
t
PZL
≈ 3 V
3 V
Low-Level
Output
1.5 V
1.5 V
1.5 V
Input
V
V
OL
GND
t
PZH
t
t
pd
pd
OH
High-Level
Output
V
V
OH
In-Phase
Output
1.5 V
1.5 V
1.5 V
≈ 0 V
OL
t
PHZ
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
NOTE A: Includes probe and jig capacitance
Figure 13. Load Circuit and Voltage Waveforms
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
Combining two or more devices to create one FIFO with a greater number of memory bits is accomplished in two
different ways. Width expansion increases the number of bits in each word by connecting FIFOs with the same depth
in parallel. Depth expansion uses the built-in expansion logic to daisy-chain two or more devices for applications
requiring more than 256, 512, or 1024 words of storage. Width expansion and depth expansion can be used together.
width expansion
Word-width expansion is achieved by connecting the corresponding input control to multiple devices with the
same depth. Status flags (EF, FF, and HF) can be monitored from any one device. Figure 14 shows two FIFOs
in a width-expansion configuration. Both devices have their expansion-in (XI) inputs tied to ground. This
disables the depth-expansion function of the device, allowing the first-load/retransmit (FL/RT) input to function
as a retransmit (RT) input and the expansion-out/half-full (XO/HF) output to function as a half-full (HF) flag.
depth expansion
The SN74ACT7200L/7201LA/7202LA is easily expanded in depth. Figure 15 shows the connections used to
depth expand three SN74ACT7200L/7201LA/7202LA devices. Any depth can be attained by adding additional
devices to the chain. The SN74ACT7200L/7201LA/7202LA operates in depth expansion under the following
conditions:
The first device in the chain is designated by tying FL to ground.
All other devices must have their FL inputs at a high logic level.
XO of each device must be tied to XI of the next device.
External logic is needed to generate a composite FF and EF. All FF outputs must be ORed together and
all EF outputs must be ORed together.
RT and HF functions are not available in the depth-expanded configuration.
combined depth and width expansion
Both expansion techniques can be used together to increase depth and width. This is done by first creating
depth-expanded units and then connecting them in a width-expanded configuration (see Figure 16).
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
SN74ACT7200L/7201LA/7202LA
D0 – D8
9
Q0 – Q8
18
18
Q0–Q18
EF
D0–D8 Q0–Q8
W
D0–D18
9
W
R
R
EF
RT
RS
FF
HF
FL/RT
RS
FF
XO/HF
XI
SN74ACT7200L/7201LA/7202LA
D9 – D18
9
Q9 – Q18
9
D0–D8 Q0–Q8
W
R
EF
EF
FF
HF
FL/RT
RS
FF
XO/HF
XI
Figure 14. Word-Width Expansion: 256/512/1024 Words × 18 Bits
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
SN74ACT7200L/7201LA/7202LA
9
9
9
9
D0–D8
Q0–Q8
D0–D8 Q0–Q8
W
W
R
R
XO/HF
RS
EF
FF
RS
FL/RT
XI
SN74ACT7200L/7201LA/7202LA
9
9
D0–D8 Q0–Q8
W
EF
FF
R
XO/HF
RS
EF
FF
FL/RT
V
CC
XI
SN74ACT7200L/7201LA/7202LA
9
9
D0–D8 Q0–Q8
W
R
XO/HF
RS
EF
FF
FL/RT
XI
Figure 15. Word-Depth Expansion: 768/1536/3072 Words × 9 Bits
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74ACT7200L, SN74ACT7201LA, SN74ACT7202LA
256 × 9, 512 × 9, 1024 × 9
ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES
SCAS221A – FEBRUARY 1993 – REVISED SEPTEMBER 1995
APPLICATION INFORMATION
Q0–Q17
18
Q0–Q26
27
9
9
9
Q0–Q8
Q9–Q17
Q18–Q26
′ACT7200L,
′ACT7201LA, or
′ACT7202LA
Depth-
′ACT7200L,
′ACT7201LA, or
′ACT7202LA
Depth-
′ACT7200L,
′ACT7201LA, or
′ACT7202LA
Depth-
W, R, RS
Expansion
Block
Expansion
Block
Expansion
Block
9
9
9
D0–D8
D9–D17
D18–D26
27
D0–D26
18
D9–D26
Figure 16. Word-Depth Plus Word-Width Expansion
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
DV
NP
RJ
SN74ACT7200L15DV
SN74ACT7200L15NP
SN74ACT7200L15RJ
SN74ACT7200L20DV
SN74ACT7200L20NP
SN74ACT7200L20RJ
SN74ACT7200L25DV
SN74ACT7200L25NP
SN74ACT7200L25RJ
SN74ACT7200L35DV
SN74ACT7200L35NP
SN74ACT7200L35RJ
SN74ACT7200L50DV
SN74ACT7200L50NP
SN74ACT7200L50RJ
SN74ACT7201LA15DV
SN74ACT7201LA15NP
SN74ACT7201LA15RJ
SN74ACT7201LA20DV
SN74ACT7201LA20NP
SN74ACT7201LA20RJ
SN74ACT7201LA25DV
SN74ACT7201LA25NP
SN74ACT7201LA25RJ
SN74ACT7201LA35DV
SN74ACT7201LA35NP
SN74ACT7201LA35RJ
SN74ACT7201LA50DV
SN74ACT7201LA50NP
SN74ACT7201LA50RJ
SN74ACT7202LA15DV
SN74ACT7202LA15NP
SN74ACT7202LA15RJ
SN74ACT7202LA25DV
SN74ACT7202LA25NP
SN74ACT7202LA25RJ
SN74ACT7202LA35RJ
SN74ACT7202LA35RJR
SN74ACT7202LA50DV
SN74ACT7202LA50NP
SN74ACT7202LA50RJ
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
SOP
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
28
28
32
32
32
28
28
32
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
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RJ
PDIP
PLCC
SOP
DV
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RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
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RJ
PDIP
PLCC
SOP
DV
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RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
SOP
DV
NP
RJ
PDIP
PLCC
PLCC
PLCC
SOP
RJ
RJ
DV
NP
RJ
PDIP
PLCC
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 2
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