SN74F20DG4 [ROCHESTER]
NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, PDSO14, GREEN, PLASTIC, SOIC-14;型号: | SN74F20DG4 |
厂家: | Rochester Electronics |
描述: | NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, PDSO14, GREEN, PLASTIC, SOIC-14 栅 光电二极管 逻辑集成电路 |
文件: | 总16页 (文件大小:800K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
SN54F20, SN74F20
DUAL 4-INPUT POSITIVE-NAND GATES
SDFS041A – MARCH 1987 – REVISED OCTOBER 1993
SN54F20 . . . J PACKAGE
SN74F20 . . . D OR N PACKAGE
(TOP VIEW)
• Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
1A
1B
V
CC
1
2
3
4
5
6
7
14
13
12
11
10
9
2D
2C
NC
2B
2A
2Y
description
NC
1C
These devices contain two independent 4-input
NAND gates. They perform the Boolean functions
Y = A • B • C • D or Y = A + B + C + D in positive
logic.
1D
1Y
GND
8
The SN54F20 is characterized for operation over
the full military temperature range of –55°C to
125°C. The SN74F20 is characterized for
operation from 0°C to 70°C.
SN54F20 . . . FK PACKAGE
(TOP VIEW)
FUNCTION TABLE
(each gate)
3
2
1
20 19
18
NC
NC
1C
NC
1D
2C
NC
NC
NC
2B
4
5
6
7
8
INPUTS
OUTPUT
Y
17
16
15
14
A
H
L
B
C
H
X
X
L
D
H
X
X
X
L
H
X
L
L
H
H
H
H
9 10 11 12 13
X
X
X
X
X
X
NC – No internal connection
†
logic symbol
1
&
1A
1B
1C
1D
2
4
5
6
1Y
9
2A
2B
2C
2D
10
12
13
8
2Y
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
logic diagram, each gate (positive logic)
A
B
C
D
Y
Copyright 1993, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
2–1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F20, SN74F20
DUAL 4-INPUT POSITIVE-NAND GATES
SDFS041A – MARCH 1987 – REVISED OCTOBER 1993
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –1.2 V to 7 V
I
Input current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –30 mA to 5 mA
Voltage range applied to any output in the high state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
CC
Current into any output in the low state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 mA
Operating free-air temperature range: SN54F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C
SN74F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The input voltage ratings may be exceeded provided the input current ratings are observed.
recommended operating conditions
SN54F20
SN74F20
UNIT
MIN NOM
MAX
MIN NOM
MAX
V
V
V
Supply voltage
4.5
2
5
5.5
4.5
2
5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input clamp current
0.8
–18
– 1
0.8
–18
– 1
20
V
I
I
I
mA
mA
mA
°C
IK
High-level output current
Low-level output current
Operating free-air temperature
OH
OL
20
T
A
–55
125
0
70
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
SN54F20
SN74F20
PARAMETER
TEST CONDITIONS
UNIT
V
‡
‡
MIN TYP
MAX
MIN TYP
MAX
V
V
V
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 4.5 V,
= 4.5 V,
= 4.75 V,
= 4.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
= 5.5 V,
I = –18 mA
I
–1.2
–1.2
IK
I
I
I
= – 1 mA
= – 1 mA
= 20 mA
2.5
3.4
0.3
2.5
2.7
3.4
0.3
OH
OH
OL
V
OH
OL
0.5
0.1
0.5
0.1
V
I
I
I
I
I
I
V = 7 V
I
mA
µA
I
V = 2.7 V
I
20
20
IH
IL
V = 0.5 V
I
– 0.6
–150
1.4
– 0.6
–150
1.4
mA
mA
mA
mA
§
V
O
= 0
–60
–60
OS
V = 0
I
0.9
3.4
0.9
3.4
CCH
CCL
V = 4.5 V
I
5.1
5.1
‡
§
All typical values are at V
= 5 V, T = 25°C.
A
CC
Not more than one output should be shorted at a time, and the duration of the short circuit should not exceed one second.
2–2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54F20, SN74F20
DUAL 4-INPUT POSITIVE-NAND GATES
SDFS041A – MARCH 1987 – REVISED OCTOBER 1993
switching characteristics (see Note 2)
V
C
R
= 5 V,
= 50 pF,
= 500 Ω,
= 25°C
V
C
R
= 4.5 V to 5.5 V,
= 50 pF,
CC
L
L
CC
L
L
= 500Ω,
FROM
(INPUT)
TO
(OUTPUT)
†
PARAMETER
UNIT
T
A
T
A
= MIN to MAX
′F20
TYP
3.3
SN54F20
SN74F20
MIN
1.6
1
MAX
5
MIN
1.2
1
MAX
MIN
1.6
1
MAX
t
t
7
6
PLH
A, B, C, or D
Y
ns
2.8
4.3
6.5
5.3
PHL
†
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
NOTE 2: Load circuits and waveforms are shown in Section 1.
2–3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
5962-9758401Q2A
ACTIVE
LCCC
FK
20
1
TBD
POST-PLATE
N / A for Pkg Type
-55 to 125
5962-
9758401Q2A
SNJ54F
20FK
5962-9758401QCA
5962-9758401QDA
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9758401QC
A
SNJ54F20J
W
5962-9758401QD
A
SNJ54F20W
JM38510/33004B2A
JM38510/33004BCA
JM38510/33004BDA
M38510/33004B2A
M38510/33004BCA
M38510/33004BDA
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
LCCC
CDIP
CFP
FK
J
20
14
14
20
14
14
1
1
1
1
1
1
TBD
TBD
TBD
TBD
TBD
TBD
TBD
POST-PLATE
A42
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
JM38510/
33004B2A
JM38510/
33004BCA
W
FK
J
A42
JM38510/
33004BDA
LCCC
CDIP
CFP
POST-PLATE
A42
JM38510/
33004B2A
JM38510/
33004BCA
W
A42
JM38510/
33004BDA
SN54F20J
SN74F20D
ACTIVE
ACTIVE
CDIP
SOIC
J
14
14
1
A42
N / A for Pkg Type
-55 to 125
0 to 70
SN54F20J
D
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
F20
SN74F20DE4
SN74F20DG4
SN74F20DR
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
D
D
D
D
14
14
14
14
50
50
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
0 to 70
0 to 70
0 to 70
F20
F20
F20
F20
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
SN74F20DRE4
Green (RoHS
& no Sb/Br)
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
SN74F20DRG4
SN74F20N
ACTIVE
SOIC
PDIP
D
14
14
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
F20
ACTIVE
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
SN74F20N
SN74F20N3
OBSOLETE
ACTIVE
PDIP
PDIP
N
N
14
14
TBD
Call TI
Call TI
0 to 70
0 to 70
SN74F20NE4
25
2000
2000
2000
1
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
SN74F20N
74F20
SN74F20NSR
SN74F20NSRE4
SN74F20NSRG4
SNJ54F20FK
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SO
SO
NS
NS
NS
FK
14
14
14
20
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
POST-PLATE
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
0 to 70
0 to 70
Green (RoHS
& no Sb/Br)
74F20
SO
Green (RoHS
& no Sb/Br)
0 to 70
74F20
LCCC
TBD
-55 to 125
5962-
9758401Q2A
SNJ54F
20FK
SNJ54F20J
SNJ54F20W
ACTIVE
ACTIVE
CDIP
CFP
J
14
14
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
5962-9758401QC
A
SNJ54F20J
W
5962-9758401QD
A
SNJ54F20W
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
25-Sep-2013
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF SN54F20, SN74F20 :
Catalog: SN74F20
•
Military: SN54F20
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Military - QML certified for Military and Defense Applications
•
Addendum-Page 3
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74F20DR
SOIC
SO
D
14
14
2500
2000
330.0
330.0
16.4
16.4
6.5
8.2
9.0
2.1
2.5
8.0
16.0
16.0
Q1
Q1
SN74F20NSR
NS
10.5
12.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
SN74F20DR
SOIC
SO
D
14
14
2500
2000
367.0
367.0
367.0
367.0
38.0
38.0
SN74F20NSR
NS
Pack Materials-Page 2
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相关型号:
SN74F20N3
NAND Gate, F/FAST Series, 2-Func, 4-Input, TTL, PDIP14, 0.300 INCH, PLASTIC, MS-001AA, DIP-14
ROCHESTER
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