SN74HC563DWRE4 [ROCHESTER]
Bus Driver, HC/UH Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20, GREEN, PLASTIC, SOIC-20;
| 型号： | SN74HC563DWRE4 |
| 厂家： | 
Rochester Electronics |
| 描述： | Bus Driver, HC/UH Series, 1-Func, 8-Bit, Inverted Output, CMOS, PDSO20, GREEN, PLASTIC, SOIC-20 光电二极管 |
| 文件： | 总13页 (文件大小：630K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
Wide Operating Voltage Range of 2 V to 6 V
Typical t = 21 ns
pd
High-Current 3-State Outputs Drive Bus
Lines Directly or Up To 15 LSTTL Loads
±6-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Bus-Structured Pinout
Low Power Consumption, 80-µA Max I
CC
SN54HC563 . . . FK PACKAGE
(TOP VIEW)
SN54HC563 . . . J OR W PACKAGE
SN74HC563 . . . DW OR N PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
OE
1D
2D
3D
4D
5D
6D
7D
8D
V
CC
3
2
1
20 19
18
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
LE
2Q
3Q
4Q
5Q
6Q
3D
4D
5D
6D
7D
4
5
6
7
8
17
16
15
14
9 10 11 12 13
GND
description/ordering information
These 8-bit transparent D-type latches feature 3-state outputs designed specifically for driving highly capacitive
or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
While the latch-enable (LE) input is high, the Q outputs follow the complements of the data (D) inputs. When
LE is taken low, the outputs are latched at the inverses of the levels set up at the D inputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic
levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased high logic level provide the capability to drive bus lines
without interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V through a pullup
CC
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latches. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
ORDERING INFORMATION
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
†
PACKAGE
T
A
PDIP – N
Tube
SN74HC563N
SN74HC563N
–40°C to 85°C
–55°C to 125°C
Tube
SN74HC563DW
SN74HC563DWR
SNJ54HC563J
SNJ54HC563W
SNJ54HC563FK
SOIC – DW
HC563
Tape and reel
Tube
CDIP – J
CFP – W
LCCC – FK
SNJ54HC563J
SNJ54HC563W
SNJ54HC563FK
Tube
Tube
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright 2003, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
FUNCTION TABLE
(each latch)
INPUTS
OUTPUT
Q
OE
L
LE
H
H
L
D
H
L
L
L
H
L
X
X
Q
0
H
X
Z
logic diagram (positive logic)
1
OE
LE
11
2
C1
1D
19
1Q
1D
To Seven Other Channels
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
I
Input clamp current, I (V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
IK
I
CC
Output clamp current, I
(V < 0 or V > V ) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±35 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±70 mA
JA
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51-7.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
recommended operating conditions (see Note 3)
SN54HC563
MIN NOM
SN74HC563
MIN NOM
UNIT
MAX
MAX
V
V
Supply voltage
2
1.5
5
6
2
1.5
5
6
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
= 2 V
High-level input voltage
= 4.5 V
= 6 V
3.15
4.2
3.15
4.2
V
V
IH
= 2 V
0.5
1.35
1.8
0.5
1.35
1.8
V
IL
Low-level input voltage
= 4.5 V
= 6 V
V
V
Input voltage
0
0
V
V
0
0
V
V
V
V
I
CC
CC
Output voltage
O
CC
CC
V
CC
V
CC
V
CC
= 2 V
1000
500
400
125
1000
500
400
85
t
Input transition (rise and fall) time
Operating free-air temperature
= 4.5 V
= 6 V
ns
t
T
–55
–40
°C
A
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= 25°C
SN54HC563
SN74HC563
A
PARAMETER
TEST CONDITIONS
V
UNIT
CC
MIN
TYP
MAX
MIN
1.9
4.4
5.9
3.7
5.2
MAX
MIN
1.9
MAX
2 V
4.5 V
6 V
1.9 1.998
4.4 4.499
5.9 5.999
I
= –20 µA
4.4
OH
V
V = V or V
IH
5.9
V
OH
OL
I
IL
IL
I
I
= –6 mA
4.5 V
6 V
3.98
5.48
4.3
5.8
3.84
5.34
OH
= –7.8 mA
OH
2 V
0.002
0.001
0.001
0.17
0.1
0.1
0.1
0.1
0.1
0.1
I
= 20 µA
4.5 V
6 V
OL
V
V = V or V
0.1
0.1
0.1
V
I
IH
I
I
= 6 mA
4.5 V
6 V
0.26
0.26
±100
±0.5
8
0.4
0.33
0.33
±1000
±5
OL
= 7.8 mA
0.15
0.4
OL
I
I
I
V = V
I
or 0
6 V
±0.1
±1000
±10
160
10
nA
µA
µA
pF
I
CC
CC
V
O
= V
or 0
6 V
±0.01
OZ
CC
CC
V = V
I
or 0,
I
O
= 0
6 V
80
C
2 V to 6 V
3
10
10
i
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
timing requirements over recommended operating free-air temperature range (unless otherwise
noted)
T
= 25°C
SN54HC563
SN74HC563
A
V
UNIT
CC
MIN
80
16
14
50
10
9
MAX
MIN
120
24
20
75
15
13
5
MAX
MIN
100
20
17
63
13
11
5
MAX
2 V
4.5 V
6 V
t
w
t
su
t
h
Pulse duration, LE high
Setup time, data before LE↓
Hold time, data after LE↓
ns
2 V
4.5 V
6 V
ns
ns
2 V
5
4.5 V
6 V
5
5
5
5
5
5
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
77
26
23
90
27
23
70
24
21
47
23
21
28
8
SN54HC563
SN74HC563
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
175
35
MIN
MAX
265
53
MIN
MAX
220
44
2 V
4.5 V
6 V
D
Q
30
45
37
t
pd
ns
2 V
175
35
265
53
220
44
LE
OE
OE
Any Q
Any Q
Any Q
Any Q
4.5 V
6 V
30
45
37
2 V
150
30
225
45
190
38
t
t
t
4.5 V
6 V
ns
ns
ns
en
dis
t
26
38
32
2 V
150
30
225
45
190
38
4.5 V
6 V
26
38
32
2 V
60
90
75
4.5 V
6 V
12
18
15
6
10
15
13
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
switching characteristics over recommended operating free-air temperature range, C = 150 pF
L
(unless otherwise noted) (see Figure 1)
T
A
= 25°C
TYP
95
SN54HC563
SN74HC563
FROM
(INPUT)
TO
(OUTPUT)
PARAMETER
V
UNIT
CC
MIN
MAX
200
40
MIN
MAX
300
60
MIN
MAX
250
50
2 V
4.5 V
6 V
D
Q
33
29
34
51
43
t
pd
ns
2 V
103
33
225
45
335
67
285
57
LE
OE
Any Q
Any Q
Any Q
4.5 V
6 V
29
38
57
48
2 V
85
200
40
300
60
250
50
t
t
4.5 V
6 V
29
ns
ns
en
26
34
51
43
2 V
60
210
42
315
63
265
53
4.5 V
6 V
17
t
14
36
53
45
operating characteristics, T = 25°C
A
PARAMETER
Power dissipation capacitance per latch
TEST CONDITIONS
TYP
UNIT
C
No load
50
pF
pd
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54HC563, SN74HC563
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS145C – DECEMBER 1982 – REVISED MARCH 2003
PARAMETER MEASUREMENT INFORMATION
V
CC
PARAMETER
R
C
L
S1
S2
L
50 pF
or
150 pF
t
Open
Closed
Closed
Open
S1
S2
PZH
Test
Point
t
t
1 kΩ
1 kΩ
en
R
t
L
PZL
From Output
Under Test
t
t
Open
Closed
Open
PHZ
PLZ
50 pF
C
dis
L
Closed
(see Note A)
50 pF
or
150 pF
t
or t
––
Open
Open
pd
t
LOAD CIRCUIT
V
CC
Reference
Input
50%
V
CC
0 V
High-Level
Pulse
50%
50%
t
t
h
su
0 V
V
CC
t
Data
Input
w
90%
90%
50%
10%
50%
10%
V
CC
Low-Level
Pulse
0 V
50%
50%
t
t
f
r
0 V
VOLTAGE WAVEFORMS
SETUP AND HOLD AND INPUT RISE AND FALL TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
Output
V
CC
V
CC
Control
(Low-Level
Enabling)
Input
50%
50%
50%
50%
0 V
0 V
t
t
PLH
PHL
90%
t
t
PLZ
PZL
V
V
OH
≈V
CC
50%
≈V
CC
Output
Waveform 1
(See Note B)
In-Phase
Output
90%
t
50%
10%
50%
10%
10%
t
OL
V
OL
t
r
f
f
t
t
t
PZH
PHZ
PHL
90%
PLH
V
V
OH
V
Output
Waveform 2
(See Note B)
OH
90%
t
90%
Out-of-
Phase
Output
50%
10%
50%
10%
50%
≈0 V
OL
t
r
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES FOR 3-STATE OUTPUTS
VOLTAGE WAVEFORMS
PROPAGATION DELAY AND OUTPUT TRANSITION TIMES
NOTES: A.
C includes probe and test-fixture capacitance.
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t = 6 ns, t = 6 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
E.
F.
G.
t
t
t
and t
and t
and t
are the same as t
are the same as t
are the same as t
.
dis
en
.
pd
PLZ
PZL
PLH
PHZ
PZH
PHL
.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device
SN74HC563DW
Status (1)
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
Drawing
SOIC
DW
20
20
20
20
20
20
20
20
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
SN74HC563DWE4
SN74HC563DWG4
SN74HC563DWR
SN74HC563DWRE4
SN74HC563DWRG4
SN74HC563N
SOIC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
DW
DW
DW
DW
DW
N
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
25 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
2000 Green (RoHS & CU NIPDAU Level-1-260C-UNLIM
no Sb/Br)
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
SN74HC563NE4
N
20
Pb-Free
(RoHS)
CU NIPDAU N / A for Pkg Type
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and
package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS
compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the
accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take
reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on
incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited
information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
SN74HC563DWR
SOIC
DW
20
2000
330.0
24.4
10.8
13.0
2.7
12.0
24.0
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
14-Jul-2012
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC DW 20
SPQ
Length (mm) Width (mm) Height (mm)
367.0 367.0 45.0
SN74HC563DWR
2000
Pack Materials-Page 2
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have not been so designated are neither designed nor intended for automotive use; and TI will not be responsible for any failure of such
components to meet such requirements.
Products
Audio
Applications
www.ti.com/audio
amplifier.ti.com
dataconverter.ti.com
www.dlp.com
Automotive and Transportation www.ti.com/automotive
Communications and Telecom www.ti.com/communications
Amplifiers
Data Converters
DLP® Products
DSP
Computers and Peripherals
Consumer Electronics
Energy and Lighting
Industrial
www.ti.com/computers
www.ti.com/consumer-apps
www.ti.com/energy
dsp.ti.com
Clocks and Timers
Interface
www.ti.com/clocks
interface.ti.com
logic.ti.com
www.ti.com/industrial
www.ti.com/medical
www.ti.com/security
Medical
Logic
Security
Power Mgmt
Microcontrollers
RFID
power.ti.com
Space, Avionics and Defense www.ti.com/space-avionics-defense
microcontroller.ti.com
www.ti-rfid.com
Video and Imaging
www.ti.com/video
OMAP Mobile Processors www.ti.com/omap
Wireless Connectivity www.ti.com/wirelessconnectivity
TI E2E Community
e2e.ti.com
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