SN74LS377DW [ROCHESTER]
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, PLASTIC, SOIC-20;![SN74LS377DW](http://pdffile.icpdf.com/pdf2/p00259/img/icpdf/SN74LS377DWR_1564708_icpdf.jpg)
型号: | SN74LS377DW |
厂家: | ![]() |
描述: | D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, PLASTIC, SOIC-20 光电二极管 逻辑集成电路 触发器 |
文件: | 总7页 (文件大小:851K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
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SN74LS377
Octal D Flip−Flop
with Enable
The SN74LS377 is an 8-bit register built using advanced Low
Power Schottky technology. This register consists of eight D-type
flip-flops with a buffered common clock and a buffered common
clock enable.
http://onsemi.com
• 8-Bit High Speed Parallel Registers
LOW
POWER
SCHOTTKY
• Positive Edge-Triggered D-Type Flip Flops
• Fully Buffered Common Clock and Enable Inputs
• True and Complement Outputs
• Input Clamp Diodes Limit High Speed Termination Effects
MARKING
DIAGRAMS
GUARANTEED OPERATING RANGES
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
SN74LS377N
AWLYYWW
T
A
Operating Ambient
Temperature Range
°C
1
20
I
Output Current − High
Output Current − Low
−0.4
mA
mA
1
OH
PDIP−20
N SUFFIX
CASE 738
I
8.0
OL
LS377
AWLYYWW
20
1
1
SOIC−20
DW SUFFIX
CASE 751D
A
= Assembly Location
WL = Wafer Lot
YY = Year
WW = Work Week
ORDERING INFORMATION
Device
Package
PDIP−20
Shipping
1440 Units/Box
38 Units/Rail
SN74LS377N
SN74LS377DW
SOIC−WIDE
SN74LS377DWR2 SOIC−WIDE 2500/Tape & Reel
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 9
SN74LS377/D
SN74LS377
CONNECTION DIAGRAM DIP (TOP VIEW)
V
Q
D
D
Q
Q
D
D
Q
4
CP
11
CC
7
7
6
6
5
5
4
20 19 18
17
16 15 14 13 12
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
8
9
10
7
E
Q
D
D
Q
Q
D
D
Q
3
GND
0
0
1
1
2
2
3
(Note a)
LOADING
HIGH
LOW
PIN NAMES
E
D − D
Enable (Active LOW) Input
Data Inputs
0.5 U.L.
0.5 U.L.
0.5 U.L.
10 U.L.
10 U.L.
0.25 U.L.
0.25 U.L.
0.25 U.L.
5 U.L.
0
CP
3
Clock (Active HIGH Going Edge) Input
True Outputs
Complemented Outputs
Q − Q
0
Q − Q
3
5 U.L.
0
3
NOTES:
ꢀa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
LOGIC DIAGRAM
3
4
7
8
13
14
17
18
D
D
D
D
D
D
D
D
7
0
1
2
3
4
5
6
E
ENABLE
1
CP
CLOCK
11
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
CP D
Q
Q
Q
Q
Q
Q
Q
Q
Q
7
0
1
2
3
4
5
6
2
5
6
9
12
15
16
19
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2
SN74LS377
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
V
Input HIGH Voltage
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
−0.65
−1.5
V
V
V
V
= MIN, I = −18 mA
IN
IK
CC
2.7
3.5
= MIN, I = MAX, V = V
OH IN
OH
CC
IH
or V per Truth Table
IL
V
V
= V MIN,
0.25
0.35
0.4
0.5
V
V
I
I
= 4.0 mA
= 8.0 mA
CC
CC
OL
OL
= V or V
V
Output LOW Voltage
Input HIGH Current
IN
IL
IH
OL
per Truth Table
20
0.1
μA
mA
mA
mA
mA
V
V
V
V
V
= MAX, V = 2.7 V
IN
CC
CC
CC
CC
CC
I
IH
= MAX, V = 7.0 V
IN
I
I
I
Input LOW Current
−0.4
−100
28
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
Power Supply Current
−20
= MAX
OS
CC
= MAX, NOTE 1
NOTE: With all inputs open and GND applied to all data and enable inputs, I is measured after a momentary GND, then 4.5 V is applied to clock.
CC
1. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Min
Max
Symbol
Parameter
Unit
Test Conditions
= 5.0 V
f
Maximum Clock Frequency
30
40
MHz
MAX
V
CC
t
t
Propagation Delay,
Clock to Output
17
18
27
27
PLH
PHL
C = 15 pF
L
ns
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Min
20
Max
Symbol
Parameter
Unit
ns
Test Conditions
t
Any Pulse Width
W
s
t
Data Setup Time
20
ns
Inactive — State
Active — State
10
ns
V
= 5.0 V
Enable Setup
Time
CC
t
t
s
25
ns
Any Hold Time
5.0
ns
h
DEFINITION OF TERMS
SETUP TIME (ts) — is defined as the minimum time
required for the correct logic level to be present at the logic
input prior to the clock transition from LOW-to-HIGH in
order to be recognized and transferred to the outputs.
logic level must be maintained at the input in order to ensure
continued recognition. A negative HOLD TIME indicates
that the correct logic level may be released prior to the clock
transition from LOW-to-HIGH and still be recognized.
HOLD TIME (t ) — is defined as the minimum time
h
following the clock transition from LOW-to-HIGH that the
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3
SN74LS377
TRUTH TABLE
E
CP
D
n
Q
Q
n
n
H
X
No
No
Change Change
L
L
H
L
H
L
L
H
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
AC WAVEFORM
1/f
max
t
W
1.3 V
1.3 V
CP
t
s(L)
h(H)
t
s(H)
t
t
h(L)
1.3 V
1.3 V
D OR E
Q
*
t
t
PHL
PLH
1.3 V
1.3 V
*The shaded areas indicate when the input is permitted to
change for predictable output performance.
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4
SN74LS377
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738−03
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
F
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
−T−
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.070
1.27
1.77
N
E
G
J
0.100 BSC
2.54 BSC
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
T B
0.25 (0.010)
M
N
0
0.020
15
_
0.040
0
_
0.51
15
1.01
_
_
M
M
T A
0.25 (0.010)
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5
SN74LS377
PACKAGE DIMENSIONS
DW SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D−05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
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SN74LS377/D
相关型号:
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SN74LS377DWR2
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDSO20, PLASTIC, SOIC-20
ROCHESTER
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SN74LS377DWR2
LS SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20
MOTOROLA
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SN74LS377N
OCTAL D FLIP-FLOP WITH ENABLE; HEX D FLIP-FLOP WITH ENABLE; 4-BIT D FLIP-FLOP WITH ENABLE
MOTOROLA
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SN74LS377N
D Flip-Flop, LS Series, 1-Func, Positive Edge Triggered, 8-Bit, True Output, TTL, PDIP20, PLASTIC, DIP-20
ROCHESTER
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