SN74LS393M [ROCHESTER]
LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, EIAJ, SOP-14;
| 型号： | SN74LS393M |
| 厂家： | 
Rochester Electronics |
| 描述： | LS SERIES, ASYN NEGATIVE EDGE TRIGGERED 4-BIT UP BINARY COUNTER, PDSO14, EIAJ, SOP-14 光电二极管 逻辑集成电路 触发器 |
| 文件： | 总9页 (文件大小：895K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LS393
Dual 4−Stage Binary
Counter
The SN74LS393 contains a pair of high-speed 4-stage ripple
counters.
Each half of the LS393 operates as a Modulo-16 binary divider, with
the last three stages triggered in a ripple fashion. In the LS393, the
flip-flops are triggered by a HIGH-to-LOW transition of their CP
inputs. Each half of each circuit type has a Master Reset input which
responds to a HIGH signal by forcing all four outputs to the LOW
state.
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LOW
POWER
SCHOTTKY
• Dual Versions
• Individual Asynchronous Clear for Each Counter
• Typical Max Count Frequency of 50 MHz
• Input Clamp Diodes Minimize High Speed Termination Effects
14
1
GUARANTEED OPERATING RANGES
PLASTIC
N SUFFIX
CASE 646
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
5.25
70
Unit
V
V
CC
T
A
Operating Ambient
Temperature Range
°C
14
I
Output Current − High
Output Current − Low
−0.4
mA
mA
OH
1
I
8.0
OL
SOIC
D SUFFIX
CASE 751A
14
1
SOEIAJ
M SUFFIX
CASE 965
ORDERING INFORMATION
Device
Package
14 Pin DIP
SOIC−14
Shipping
SN74LS393N
SN74LS393D
SN74LS393DR2
SN74LS393M
SN74LS393MEL
2000 Units/Box
55 Units/Rail
2500/Tape & Reel
See Note 1
SOIC−14
SOEIAJ−14
SOEIAJ−14
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 2
SN74LS393/D
SN74LS393
CONNECTION DIAGRAM DIP (TOP VIEW)
V
CP
13
MR
12
Q
Q
Q
Q
3
CC
0
1
2
14
11
10
9
8
NOTE:
The Flatpak version
has the same pinouts
(Connection Diagram) as
the Dual In-Line Package.
1
2
3
4
5
6
7
CP
MR
Q
Q
1
Q
2
Q
3
GND
0
(Note a)
LOW
LOADING
HIGH
PIN NAMES
CP
Clock (Active LOW Going Edge)
Input to +16 (LS393)
Clock (Active LOW Going Edge)
0.5 U.L.
0.5 U.L.
1.0 U.L.
1.0 U.L.
CP
0
1
Input to ÷2 (LS390)
CP
Clock (Active LOW Going Edge)
Input to ÷ 5 (LS390)
Master Reset (Active HIGH) Input
0.5 U.L.
0.5 U.L.
10 U.L.
1.5 U.L.
0.25 U.L.
5 U.L.
MR
Q − Q
Flip−Flop Outputs
0
3
NOTES:
ꢀa) 1 TTL Unit Load (U.L.) = 40 mA HIGH/1.6 mA LOW.
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2
SN74LS393
FUNCTIONAL DESCRIPTION
Each half of the SN74LS393 operates in the Modulo 16
binary sequence, as indicated in the ÷16 Truth Table. The
first flip-flop is triggered by HIGH-to-LOW transitions of
the CP input signal. Each of the other flip-flops is triggered
by a HIGH-to-LOW transition of the Q output of the
preceding flip-flop. Thus state changes of the Q outputs do
not occur simultaneously. This means that logic signals
derived from combinations of these outputs will be subject
to decoding spikes and, therefore, should not be used as
clocks for other counters, registers or flip-flops. A HIGH
signal on MR forces all outputs to the LOW state and
prevents counting.
SN74LS393 LOGIC DIAGRAM (one half shown)
CP
K
CP
J
K
CP
J
K
CP
J
K
CP
J
C
D
C
D
C
D
C
D
Q
Q
Q
Q
MR
Q
0
Q
1
Q
2
Q
3
TRUTH TABLE
OUTPUTS
COUNT
Q
Q
Q
Q
3
2
1
0
0
1
2
3
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
H
4
5
6
7
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
8
9
10
11
H
H
H
H
L
L
L
L
L
L
H
H
L
H
L
H
12
13
14
15
H
H
H
H
H
H
H
H
L
L
H
H
L
H
L
H
H = HIGH Voltage Level
L = LOW Voltage Level
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3
SN74LS393
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
V
2.0
V
IH
0.8
Guaranteed Input LOW Voltage for
All Inputs
Input LOW Voltage
V
IL
V
V
Input Clamp Diode Voltage
Output HIGH Voltage
−0.65
−1.5
V
V
V
V
= MIN, I = −18 mA
IN
IK
CC
2.7
3.5
= MIN, I = MAX, V = V
OH IN IH
OH
CC
or V per Truth Table
IL
V
V
= V MIN,
CC
0.25
0.35
0.4
V
I
I
= 4.0 mA
= 8.0 mA
CC
OL
OL
V
Output LOW Voltage
Input HIGH Current
= V or V
OL
IN
IL
IH
0.5
20
V
per Truth Table
μA
V
V
= MAX, V = 2.7 V
IN
CC
CC
I
IH
0.1
mA
mA
mA
mA
mA
mA
= MAX, V = 7.0 V
IN
MR
CP, CP
−0.4
−1.6
−2.4
−100
26
I
IL
Input LOW Current
V
= MAX, V = 0.4 V
0
CC
IN
CP
1
I
I
Short Circuit Current (Note 2)
Power Supply Current
−20
V
V
= MAX
= MAX
OS
CC
CC
CC
2. Not more than one output should be shorted at a time, nor for more than 1 second.
AC CHARACTERISTICS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Min
Max
Symbol
Parameter
Unit
Test Conditions
Maximum Clock Frequency
CP to Q
f
f
25
35
MHz
MAX
0
0
Maximum Clock Frequency
CP to Q
20
MHz
ns
MAX
1
1
t
t
Propagation Delay,
12
13
20
20
C = 15 pF
L
PLH
PHL
CP to Q
0
t
t
40
40
60
60
PLH
PHL
CP to Q
ns
ns
3
t
MR to Any Output
24
39
PHL
AC SETUP REQUIREMENTS (T = 25°C, V = 5.0 V)
A
CC
Limits
Typ
Min
20
Max
Symbol
Parameter
Unit
ns
Test Conditions
t
W
Clock Pulse Width
t
t
MR Pulse Width
Recovery Time
20
ns
V
CC
= 5.0 V
W
25
ns
rec
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4
SN74LS393
AC WAVEFORMS
*CP
Q
1.3 V
1.3 V
t
W
t
PLH
t
PHL
1.3 V
1.3 V
Figure 1.
MR & MS
1.3 V
1.3 V
t
W
t
rec
CP
Q
1.3 V
t
PHL
1.3 V
Figure 2.
*The number of Clock Pulses required between t
PHL
and t measurements can be determined from the appropriate Truth Table.
PLH
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5
SN74LS393
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 646−06
ISSUE M
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
1
8
7
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
INCHES
DIM MIN MAX
MILLIMETERS
A
F
MIN
18.16
6.10
3.69
0.38
1.02
MAX
18.80
6.60
4.69
0.53
1.78
A
B
C
D
F
0.715
0.240
0.145
0.015
0.040
0.770
0.260
0.185
0.021
0.070
L
N
C
G
H
J
0.100 BSC
2.54 BSC
0.052
0.008
0.115
0.290
−−−
0.095
0.015
0.135
0.310
10
1.32
0.20
2.92
7.37
−−−
2.41
0.38
3.43
7.87
10
−T−
SEATING
PLANE
K
L
J
K
M
N
_
_
0.015
0.039
0.38
1.01
D 14 PL
H
G
M
M
0.13 (0.005)
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6
SN74LS393
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751A−03
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
ISSUE F
−A−
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
14
8
7
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
−B−
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
P 7 PL
M
M
B
0.25 (0.010)
1
MILLIMETERS
DIM MIN MAX
INCHES
MIN
G
MAX
0.344
0.157
0.068
0.019
0.049
F
R X 45
_
C
A
B
C
D
F
8.55
3.80
1.35
0.35
0.40
8.75 0.337
4.00 0.150
1.75 0.054
0.49 0.014
1.25 0.016
−T−
SEATING
PLANE
J
M
G
J
1.27 BSC
0.050 BSC
K
D 14 PL
0.19
0.10
0
0.25 0.008
0.25 0.004
0.009
0.009
7
0.244
0.019
M
S
S
0.25 (0.010)
T
B
A
K
M
P
R
7
0
_
_
_
_
5.80
0.25
6.20 0.228
0.50 0.010
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7
SN74LS393
PACKAGE DIMENSIONS
M SUFFIX
SOEIAJ PACKAGE
CASE 965−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
14
8
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
7
1
DETAIL P
Z
D
MILLIMETERS
INCHES
MIN
VIEW P
DIM MIN
MAX
2.05
0.20
0.50
0.27
10.50
5.45
MAX
0.081
0.008
0.020
0.011
0.413
0.215
A
e
A
−−−
0.05
0.35
0.18
9.90
5.10
−−−
0.002
0.014
0.007
0.390
0.201
c
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
H
M
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
0.13 (0.005)
E
0.10 (0.004)
0.50
L
E
M
0
0.70
−−−
10
10
0.035
0.056
0
_
_
_
_
Q
1
0.90
1.42
0.028
−−−
Z
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SN74LS393/D
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