SN74LS541MEL [ROCHESTER]
Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, PDSO20, EIAJ, SOP-20;
| 型号： | SN74LS541MEL |
| 厂家： | 
Rochester Electronics |
| 描述： | Bus Driver, LS Series, 1-Func, 8-Bit, True Output, TTL, PDSO20, EIAJ, SOP-20 光电二极管 |
| 文件： | 总6页 (文件大小：196K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LS541
Octal Buffer/Line Driver
with 3−State Outputs
The SN74LS541 is an octal buffer and line driver with the same
functions as the LS241, but with pinouts on the opposite side of the
package.
This device type is designed to be used as a memory address driver,
clock driver and bus-oriented transmitter/receiver. This device is
especially useful as output ports for the microprocessors, allowing
ease of layout and greater PC board density.
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LOW
POWER
SCHOTTKY
• Hysteresis at Inputs to Improve Noise Margin
• PNP Inputs Reduce Loading
MARKING
DIAGRAMS
• 3-State Outputs Drive Bus Lines
• Inputs and Outputs Opposite Side of Package, Allowing Easier
Interface to Microprocessors
SN74LS541N
AWLYYWW
• Input Clamp Diodes Limit High-Speed Termination Effects
20
LOGIC AND CONNECTION DIAGRAM DIP (TOP VIEW)
PDIP−20
N SUFFIX
CASE 738
1
1
V
CC
20 19 18 17 16 15 14 13 12 11
LS541
AWLYYWW
20
SOIC−20
DW SUFFIX
CASE 751D
1
1
2
3
4
5
6
8
9
10
7
1
1
GND
74LS541
AWLYWW
GUARANTEED OPERATING RANGES
20
SOEIAJ−20
M SUFFIX
CASE 967
Symbol
Parameter
Supply Voltage
Min
4.75
0
Typ
5.0
25
Max
Unit
V
1
V
CC
5.25
70
T
A
Operating Ambient
Temperature Range
°C
A
= Assembly Location
WL = Wafer Lot
Y, YY= Year
WW = Work Week
I
Output Current − High
Output Current − Low
−15
mA
mA
OH
I
24
OL
ORDERING INFORMATION
Device
Package
PDIP−20
Shipping
1440 Units/Box
38 Units/Rail
SN74LS541N
SN74LS541DW
SOIC−WIDE
SN74LS541DWR2 SOIC−WIDE 2500/Tape & Reel
SOEIAJ−20
SN74LS541M
SN74LS541MEL SOEIAJ−20
See Note 1
See Note 1
1. For ordering information on the EIAJ version of
the SOIC package, please contact your local
ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
July, 2006 − Rev. 4
SN74LS541/D
SN74LS541
BLOCK DIAGRAM
(1)
E
E
1
(19)
INPUTS
OUTPUTS
2
E
1
E
2
D
LS540 LS541
L
L
H
X
X
L
L
H
Z
Z
L
(2)
(18)
D
D
Y1
1
H
X
L
X
H
L
Z
Z
H
(3)
(4)
(5)
(6)
(7)
(8)
(9)
(17)
(16)
(15)
(14)
(13)
(12)
(11)
Y2
Y3
2
L = LOW Voltage Level
H = HIGH Voltage Level
X = Immaterial
D
D
3
Z = High Impedance
4
Y4
Y5
D
5
D
6
D
7
D
8
Y6
Y7
Y8
DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified)
Limits
Min
Typ
Max
Symbol
Parameter
Input HIGH Voltage
Unit
Test Conditions
Guaranteed Input HIGH Voltage for
All Inputs
V
IH
2.0
V
0.8
Guaranteed Input LOW Voltage for
All Inputs
V
V
Input LOW Voltage
V
IL
Input Clamp Diode Voltage
−0.65
−1.5
V
V
V
V
V
V
V
I
= MIN, I = −18 mA
IN
IK
CC
CC
CC
2.4
2.0
3.4
= MIN, I = −3.0 mA
OH
V
OH
Output HIGH Voltage
Output LOW Voltage
= MIN, I = MAX, V = 0.5 V
OH
IL
V
V
= V MIN,
= V or V
0.25
0.35
0.4
0.4
0.5
= 12 mA
CC
CC
OL
V
V
OL
IN
IL
IH
V
I
OL
= 24 mA
per Truth Table
−V
T−
Hysteresis
0.2
V
V
V
V
V
V
V
V
= MIN
T+
CC
CC
CC
CC
CC
CC
CC
I
Output Off Current HIGH
Output Off Current LOW
20
−20
20
μA
μA
μA
mA
mA
mA
= MAX, V
= 2.7 V
= 0.4 V
OZH
OZL
OUT
OUT
I
= MAX, V
= MAX, V = 2.7 V
IN
I
IH
Input HIGH Current
0.1
= MAX, V = 7.0 V
IN
I
I
Input LOW Current
−0.2
−225
= MAX, V = 0.4 V
IL
IN
Short Circuit Current (Note 1)
−40
= MAX
= MAX
OS
Power Supply Current
Total, Output HIGH
32
52
55
mA
mA
mA
I
V
CC
CC
Total, Output LOW
Total Output 3-State
1. Not more than one output should be shorted at a time, nor for more than 1 second.
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2
SN74LS541
AC CHARACTERISTICS (T = 25°C)
A
Limits
Min
Typ
12
Max
15
Symbol
Parameter
Unit
Test Conditions
t
t
PLH
Propagation Delay,
Data to Output
ns
12
18
PHL
PZH
V
CC
= 5.0 V
Output Enable Time
to HIGH Level
C = 45 pF
L
t
t
t
t
15
20
10
15
32
38
18
29
ns
ns
ns
ns
R = 667 Ω
L
Output Enable Time
to LOW Level
PZL
PHZ
PLZ
Output Disable Time
to HIGH Level
C = 5.0 pF
L
Output Disable Time
to LOW Level
AC WAVEFORMS
V
CC
V
V
1.3 V
1.3 V
IN
R
L
t
t
PHL
PLH
1.3 V
1.3 V
OUT
SW1
Figure 1.
TO OUTPUT
UNDER TEST
1.3 V
1.3 V
V
V
IN
t
t
PHL
PLH
5 kΩ
1.3 V
1.3 V
OUT
C *
L
SW2
Figure 2.
V
V
E
1.5 V
1.5 V
E
SWITCH POSITIONS
t
t
PLZ
PZL
≈ 1.5 V
SYMBOL
SW1
Open
SW2
Closed
Open
V
1.5 V
OUT
V
OL
t
PZH
0.5 V
t
t
Closed
Closed
Closed
PZL
PLZ
PHZ
Figure 3.
Closed
Closed
t
V
V
E
1.5 V
t
1.5 V
E
t
PZH
PHZ
≥V
OH
V
OUT
1.5 V
≈ 1.5 V
0.5 V
Figure 4.
Figure 5.
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3
SN74LS541
PACKAGE DIMENSIONS
N SUFFIX
PLASTIC PACKAGE
CASE 738−03
ISSUE E
−A−
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
20
1
11
10
B
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
L
C
INCHES
DIM MIN MAX
1.070 25.66
MILLIMETERS
MIN
MAX
27.17
6.60
4.57
0.55
A
B
C
D
E
1.010
0.240
0.150
0.015
0.260
0.180
0.022
6.10
3.81
0.39
−T−
SEATING
PLANE
K
0.050 BSC
1.27 BSC
M
0.050
0.100 BSC
0.070
1.27
2.54 BSC
1.77
F
G
J
N
E
0.008
0.110
0.015
0.140
0.21
2.80
0.38
3.55
G
F
K
L
J 20 PL
0.300 BSC
7.62 BSC
D 20 PL
M
M
B
0.25 (0.010)
T
M
N
0
0.020
15
_
0.040
0
_
0.51
15
_
1.01
_
M
M
A
0.25 (0.010)
T
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4
SN74LS541
PACKAGE DIMENSIONS
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751D−05
ISSUE F
D
A
q
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
20
11
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
E
B
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION SHALL
BE 0.13 TOTAL IN EXCESS OF B DIMENSION AT
MAXIMUM MATERIAL CONDITION.
1
10
MILLIMETERS
DIM MIN
MAX
2.65
0.25
0.49
0.32
12.95
7.60
A
A1
B
C
D
E
2.35
0.10
0.35
0.23
12.65
7.40
20X B
M
S
S
B
0.25
T A
e
1.27 BSC
A
H
h
10.05
0.25
0.50
0
10.55
0.75
0.90
7
L
SEATING
PLANE
q
_
_
18X e
A1
C
T
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5
SN74LS541
PACKAGE DIMENSIONS
M SUFFIX
SOEIAJ PACKAGE
CASE 967−01
ISSUE O
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
FLASH OR PROTRUSIONS AND ARE MEASURED
AT THE PARTING LINE. MOLD FLASH OR
PROTRUSIONS SHALL NOT EXCEED 0.15 (0.006)
PER SIDE.
L
E
20
11
Q
1
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
H
E
_
E
M
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
L
1
10
DETAIL P
Z
D
VIEW P
MILLIMETERS
INCHES
MIN
e
A
DIM MIN
MAX
2.05
0.20
0.50
0.27
12.80
5.45
MAX
0.081
0.008
0.020
0.011
0.504
0.215
c
A
−−−
0.05
0.35
0.18
12.35
5.10
−−−
0.002
0.014
0.007
0.486
0.201
A
1
b
c
D
E
e
A
b
1
1.27 BSC
0.050 BSC
M
0.10 (0.004)
0.13 (0.005)
H
7.40
0.50
1.10
8.20
0.85
1.50
0.291
0.020
0.043
0.323
0.033
0.059
E
L
L
E
M
Q
0
10
10
_
0.035
0.032
0
_
_
_
0.70
−−−
0.90
0.81
0.028
−−−
1
Z
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SN74LS541/D
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