SN74LVC374DWR [ROCHESTER]
LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20;
| 型号： | SN74LVC374DWR |
| 厂家： | 
Rochester Electronics |
| 描述： | LVC/LCX/Z SERIES, 8-BIT DRIVER, TRUE OUTPUT, PDSO20, PLASTIC, SOIC-20 驱动 光电二极管 输出元件 |
| 文件： | 总7页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SN74LVC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS296B – JANUARY 1993 – REVISED NOVEMBER 1994
DB, DW, OR PW PACKAGE
(TOP VIEW)
• EPIC (Enhanced-Performance Implanted
CMOS) Submicron Process
• Typical V
(Output Ground Bounce)
OLP
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
19 8Q
1
2
3
4
5
6
7
8
9
10
20
< 0.8 V at V
= 3.3 V, T = 25°C
CC
A
• Typical V
(Output V
Undershoot)
OHV
OH
18 8D
> 2 V at V
= 3.3 V, T = 25°C
CC
A
17
16
15
14
13
12
11
7D
7Q
6Q
6D
5D
5Q
CLK
• Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages
description
GND
This octal edge-triggered D-type flip-flop is
designed for 2.7-V to 3.6-V V operation.
CC
The SN74LVC374 features 3-state outputs designed specifically for driving highly capacitive or relatively
low-impedance loads. It is particularly suitable for implementing buffer registers, input/output (I/O) ports,
bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and the increased drive provide the capability to drive bus lines without
interface or pullup components. OE does not affect internal operations of the latch. Old data can be retained
or new data can be entered while the outputs are in the high-impedance state.
The SN74LVC374 is characterized for operation from –40°C to 85°C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
OE
L
CLK
D
H
L
↑
↑
H
L
L
L
H or L
X
X
X
Q
0
H
Z
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 1994, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS296B – JANUARY 1993 – REVISED NOVEMBER 1994
†
logic symbol
logic diagram (positive logic)
1
1
OE
OE
EN
C1
11
11
CLK
CLK
C1
2
1Q
3
3
2
5
1D
1D
1D
2D
3D
4D
5D
6D
7D
8D
1D
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
4
7
6
8
9
13
14
17
18
12
15
16
19
To Seven Other Channels
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and
IEC Publication 617-12.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
CC
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 4.6 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0 ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –50 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA
Continuous current through V
Maximum power dissipation at T = 55°C (in still air) (see Note 2): DB package . . . . . . . . . . . . . . . . . 0.6 W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±100 mA
A
DW package . . . . . . . . . . . . . . . . . 1.6 W
PW package . . . . . . . . . . . . . . . . . 0.7 W
Operating free-air temperature range, T
Storage temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40°C to 85°C
A
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. This value is limited to 4.6 V maximum.
2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
Formoreinformation, refertothePackageThermalConsiderationsapplicationnoteinthe1994ABTAdvancedBiCMOSTechnology
Data Book, literature number SCBD002B.
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS296B – JANUARY 1993 – REVISED NOVEMBER 1994
recommended operating conditions (see Note 3)
MIN
2.7
2
MAX
UNIT
V
V
V
V
V
Supply voltage
3.6
V
V
V
V
V
CC
IH
IL
I
High-level input voltage
Low-level input voltage
Input voltage
V
V
= 2.7 V to 3.6 V
= 2.7 V to 3.6 V
CC
0.8
CC
0
0
V
V
CC
Output voltage
O
CC
V
CC
V
CC
V
CC
V
CC
= 2.7 V
= 3 V
–12
–24
12
I
High-level output current
Low-level output current
mA
mA
OH
OL
= 2.7 V
= 3 V
I
24
∆t/∆v
Input transition rise or fall rate
Operating free-air temperature
0
10
ns/V
T
A
–40
85
°C
NOTE 3: Unused or floating inputs must be held high or low.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
= –40°C to 85°C
A
†
PARAMETER
TEST CONDITIONS
UNIT
V
CC
MIN
–0.2
TYP
MAX
I
I
= –100 µA
MIN to MAX
2.7 V
V
OH
CC
2.2
V
= – 12 mA
V
OH
OL
OH
3 V
2.4
2
I
I
I
I
= – 24 mA
= 100 µA
= 12 mA
= 24 mA
3 V
OH
OL
OL
OL
MIN to MAX
2.7 V
0.2
0.4
V
V
3 V
0.55
±5
I
I
I
V = V
or GND
3.6 V
µA
µA
µA
I
I
CC
V
= V
or GND
3.6 V
±10
20
OZ
CC
O
CC
V = V
or GND,
I
O
= 0
3.6 V
I
CC
V
= 3 V to 3.6 V,
One input at V
– 0.6 V,
CC
CC
Other inputs at V
I
500
µA
CC
or GND
CC
or GND
C
C
V = V
I
3.3 V
3.3 V
5.5
5.8
pF
pF
i
CC
= V or GND
CC
V
O
o
†
For conditions shown as MIN or MAX, use the appropriate values under recommended operating conditions.
timing requirements over recommended operating free-air temperature range (unless otherwise
noted) (see Figure 1)
V = 3.3 V
CC
± 0.3 V
V
CC
= 2.7 V
UNIT
MIN
0
MAX
MIN
0
MAX
f
t
t
t
Clock frequency
100
80
MHz
ns
clock
Pulse duration, CLK high or low
Setup time, data before CLK↑
Hold time, data after CLK↑
5
5
w
2
2
ns
su
h
2
2
ns
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS296B – JANUARY 1993 – REVISED NOVEMBER 1994
switching characteristics over recommended operating free-air temperature range, C = 50 pF
L
(unless otherwise noted) (see Figure 1)
V
= 3.3 V ± 0.3 V
V
CC
= 2.7 V
MAX
FROM
(INPUT)
TO
(OUTPUT)
CC
PARAMETER
UNIT
MIN
100
1.5
TYP
150
4.9
MAX
MIN
80
f
t
t
t
MHz
ns
max
CLK
OE
Q
Q
Q
8.5
8.5
7.5
1.5
1.5
1.5
9.5
9.5
8.5
pd
1.5
4.1
ns
en
1.5
4.2
ns
OE
dis
operating characteristics, V
= 3.3 V, T = 25°C
A
CC
PARAMETER
TEST CONDITIONS
= 50 pF, f = 10 MHz
L
TYP
18
9
UNIT
Outputs enabled
Outputs disabled
C
Power dissipation capacitance
C
pF
pd
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN74LVC374
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCAS296B – JANUARY 1993 – REVISED NOVEMBER 1994
PARAMETER MEASUREMENT INFORMATION
6 V
Open
S1
500 Ω
From Output
Under Test
TEST
S1
GND
t
t
/t
Open
6 V
PLH PHL
/t
C
= 50 pF
L
t
500 Ω
PLZ PZL
/t
(see Note A)
GND
PHZ PZH
LOAD CIRCUIT FOR OUTPUTS
2.7 V
0 V
1.5 V
Timing Input
Data Input
t
w
t
t
h
su
2.7 V
0 V
2.7 V
0 V
Input
1.5 V
1.5 V
1.5 V
1.5 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
2.7 V
0 V
2.7 V
0 V
Input
(see Note B)
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
PZL
t
PHL
t
t
PLH
PHL
t
PLZ
Output
Waveform 1
S1 at 6 V
3 V
V
V
OH
1.5 V
1.5 V
1.5 V
1.5 V
Output
V
+ 0.3 V
– 0.3 V
OL
V
OL
OL
(see Note C)
t
PHZ
t
PLH
t
PZH
Output
Waveform 2
S1 at GND
V
OH
V
V
OH
V
OH
1.5 V
1.5 V
Output
0 V
OL
(see Note C)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A.
C includes probe and jig capacitance.
L
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, Z = 50 Ω, t ≤ 2.5 ns, t ≤ 2.5 ns.
O
r
f
C. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
D. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
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subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
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