TL071IDR [ROCHESTER]

OP-AMP, 8000uV OFFSET-MAX, 3MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8;
TL071IDR
型号: TL071IDR
厂家: Rochester Electronics    Rochester Electronics
描述:

OP-AMP, 8000uV OFFSET-MAX, 3MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8

放大器 光电二极管
文件: 总31页 (文件大小:1388K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀꢁ ꢂꢃ ꢈ  
ꢀ ꢁꢂ ꢃ ꢈ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢈ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢆꢅ ꢀꢁ ꢂꢃ ꢉꢇ  
ꢁ ꢊ ꢋꢌꢍꢊ ꢎꢏ ꢐ ꢑ ꢒ ꢐꢀꢌꢎ ꢍꢓꢔꢀ ꢊ ꢓꢐꢕ ꢆꢀ ꢎꢊ ꢍꢆꢁ ꢆꢖ ꢓ ꢁꢎ ꢒꢎ ꢐꢕ ꢏ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
D
D
D
D
D
Low Power Consumption  
D
Low Noise  
V = 18 nV/Hz Typ at f = 1 kHz  
n
Wide Common-Mode and Differential  
Voltage Ranges  
D
D
D
D
D
High Input Impedance . . . JFET Input Stage  
Low Input Bias and Offset Currents  
Output Short-Circuit Protection  
Internal Frequency Compensation  
Latch-Up-Free Operation  
Low Total Harmonic Distortion  
. . . 0.003% Typ  
High Slew Rate . . . 13 V/µs Typ  
Common-Mode Input Voltage Range  
Includes V  
CC+  
description/ordering information  
The JFET-input operational amplifiers in the TL07x series are similar to the TL08x series, with low input bias  
and offset currents and fast slew rate. The low harmonic distortion and low noise make the TL07x series ideally  
suited for high-fidelity and audio preamplifier applications. Each amplifier features JFET inputs (for high input  
impedance) coupled with bipolar output stages integrated on a single monolithic chip.  
The C-suffix devices are characterized for operation from 0°C to 70°C. The I-suffix devices are characterized  
for operation from −40°C to 85°C. The M-suffix devices are characterized for operation over the full military  
temperature range of −55°C to 125°C.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2004, Texas Instruments Incorporated  
ꢊ ꢚ ꢥ ꢝ ꢜꢨ ꢣꢢ ꢠꢡ ꢢꢜ ꢞꢥ ꢧꢙ ꢟꢚ ꢠ ꢠꢜ ꢖꢎ ꢁꢌ ꢓꢕ ꢒ ꢌꢯꢰꢱ ꢯꢱꢅ ꢟꢧꢧ ꢥꢟ ꢝ ꢟ ꢞꢤ ꢠꢤꢝ ꢡ ꢟ ꢝ ꢤ ꢠꢤ ꢡꢠꢤ ꢨ  
ꢠ ꢤ ꢡ ꢠꢙ ꢚꢮ ꢜꢛ ꢟ ꢧꢧ ꢥꢟ ꢝ ꢟ ꢞ ꢤ ꢠ ꢤ ꢝ ꢡ ꢩ  
ꢣ ꢚꢧ ꢤꢡꢡ ꢜ ꢠꢪꢤ ꢝ ꢬꢙ ꢡꢤ ꢚ ꢜꢠꢤ ꢨꢩ ꢊ ꢚ ꢟꢧ ꢧ ꢜ ꢠꢪꢤ ꢝ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢡ ꢅ ꢥꢝ ꢜ ꢨꢣꢢ ꢠꢙꢜ ꢚ  
1
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
description/ordering information (continued)  
ORDERING INFORMATION  
V
max  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
IO  
PACKAGE  
T
A
AT 25°C  
Tube of 50  
Tube of 50  
Tube of 25  
Tube of 75  
Reel of 2500  
Tube of 75  
Reel of 2500  
Tube of 50  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Reel of 2000  
Tube of 90  
Reel of 2000  
Tube of 50  
Tube of 50  
Tube of 25  
Tube of 75  
Reel of 2500  
Tube of 75  
Reel of 2500  
Tube of 50  
Reel of 2500  
Reel of 2000  
Reel of 2000  
Tube of 50  
Tube of 50  
Tube of 25  
Tube of 75  
Reel of 2500  
Tube of 75  
Reel of 2500  
Tube of 50  
Reel of 2500  
Reel of 2000  
TL071CP  
TL071CP  
PDIP (P)  
PDIP (N)  
TL072CP  
TL072CP  
TL074CN  
TL074CN  
TL071CD  
TL071C  
TL072C  
TL074C  
TL071CDR  
TL072CD  
SOIC (D)  
TL072CDR  
TL074CD  
10 mV  
TL074CDR  
TL074CNSR  
TL071CPSR  
TL072CPSR  
TL072CPWR  
TL074CPW  
TL074CPWR  
TL071ACP  
TL072CP  
SOP (NS)  
SOP (PS)  
TL074  
TL071  
T072  
T072  
TSSOP (PW)  
T074  
TL071ACP  
TL072CP  
PDIP (P)  
PDIP (N)  
TL074ACN  
TL071ACD  
TL071ACDR  
TL072ACD  
TL072ACDR  
TL074ACD  
TL074ACDR  
TL072ACPSR  
TL074ACNSR  
TL071BCP  
TL072BCP  
TL074BCN  
TL071BCD  
TL071BCDR  
TL072BCD  
TL072BCDR  
TL074BCD  
TL074BCDR  
TL074BCNSR  
TL074ACN  
0°C to 70°C  
071AC  
6 mV  
SOIC (D)  
072AC  
TL074AC  
SOP (PS)  
SOP (NS)  
T072A  
TL074A  
TL071BCP  
TL072BCP  
TL074BCN  
PDIP (P)  
PDIP (N)  
071BC  
072BC  
3 mV  
SOIC (D)  
SOP (NS)  
TL074BC  
TL074B  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀꢁ ꢂꢃ ꢈ  
ꢀ ꢁꢂ ꢃ ꢈ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢈ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢆꢅ ꢀꢁ ꢂꢃ ꢉꢇ  
ꢁ ꢊ ꢋꢌꢍꢊ ꢎꢏ ꢐ ꢑ ꢒ ꢐꢀꢌꢎ ꢍꢓꢔꢀ ꢊ ꢓꢐꢕ ꢆꢀ ꢎꢊ ꢍꢆꢁ ꢆꢖ ꢓ ꢁꢎ ꢒꢎ ꢐꢕ ꢏ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
description/ordering information (continued)  
ORDERING INFORMATION  
V
max  
ORDERABLE  
PART NUMBER  
TOP-SIDE  
MARKING  
IO  
PACKAGE  
T
A
AT 25°C  
Tube of 50  
Tube of 50  
Tube of 25  
Tube of 75  
Reel of 2500  
Tube of 75  
Reel of 2500  
Tube of 50  
Reel of 2500  
Tube of 50  
Tube of 150  
Tube of 55  
Tube of 25  
Tube of 25  
Tube of 55  
TL071IP  
TL071IP  
PDIP (P)  
PDIP (N)  
TL072IP  
TL072IP  
TL074IN  
TL074IN  
TL071ID  
TL071I  
TL072I  
TL074I  
TL071IDR  
TL072ID  
−40°C to 85°C  
6 mV  
SOIC (D)  
TL072IDR  
TL074ID  
TL074IDR  
TL072MJGB  
TL072MUB  
TL072MFKB  
TL074MJB  
TL074MWB  
TL074MFKB  
CDIP (JG)  
CFP (U)  
TL072MJGB  
TL072MUB  
TL072MFKB  
TL074MJB  
6 mV  
9 mV  
LCCC (FK)  
CDIP (J)  
−55°C to 125°C  
CFP (W)  
TL074MWB  
TL074MFKB  
LCCC (FK)  
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at  
www.ti.com/sc/package.  
3
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TL071, TL071A, TL071B  
D, P, OR PS PACKAGE  
(TOP VIEW)  
TL072, TL072A, TL072B  
D, JG, P, PS, OR PW PACKAGE  
(TOP VIEW)  
TL074A, TL074B  
D, J, N, NS, OR PW PACKAGE  
TL074 . . . D, J, N, NS, PW,  
OR W PACKAGE  
(TOP VIEW)  
OFFSET N1  
IN−  
NC  
V
OUT  
1OUT  
1IN−  
1IN+  
V
CC+  
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
2OUT  
2IN−  
2IN+  
CC+  
IN+  
1OUT  
1IN−  
1IN+  
1
2
3
4
5
6
7
14 4OUT  
V
OFFSET N2  
V
13  
12  
11  
10  
9
4IN−  
4IN+  
CC−  
CC−  
V
V
CC+  
CC−  
TL072  
2IN+  
2IN−  
3IN+  
3IN−  
3OUT  
U PACKAGE  
(TOP VIEW)  
8
2OUT  
NC  
1OUT  
1IN−  
NC  
1
2
3
4
5
10  
9
V
CC+  
8
2OUT  
2IN−  
2IN+  
1IN+  
7
6
V
CC−  
TL071  
TL072  
TL074  
FK PACKAGE  
(TOP VIEW)  
FK PACKAGE  
(TOP VIEW)  
FK PACKAGE  
(TOP VIEW)  
3
2
1
20 19  
18  
3
2
1
20 19  
18  
NC  
4IN+  
NC  
1IN+  
NC  
4
5
6
7
8
4
5
6
7
8
2OUT  
NC  
NC  
1IN−  
NC  
17  
16  
15  
14  
17  
16  
15  
14  
3
2
1
20 19  
18  
NC  
V
NC  
IN−  
NC  
IN+  
NC  
4
5
6
7
8
V
V
CC−  
CC+  
NC  
17  
16  
15  
14  
CC+  
2IN−  
NC  
NC  
1IN+  
NC  
NC  
3IN+  
2IN+  
9 10 11 12 13  
9 10 11 12 13  
OUT  
NC  
9 10 11 12 13  
NC − No internal connection  
symbols  
TL071  
TL072 (each amplifier)  
TL074 (each amplifier)  
OFFSET N1  
IN+  
+
IN+  
IN−  
+
OUT  
OUT  
IN−  
OFFSET N2  
4
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢄ ꢇꢅ ꢀꢁ ꢂꢃ ꢈ  
ꢀ ꢁꢂ ꢃ ꢈ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢈ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢆꢅ ꢀꢁ ꢂꢃ ꢉꢇ  
ꢊ ꢋꢌꢍꢊ ꢎꢏ ꢐ ꢑ ꢒ ꢐꢀꢌꢎ ꢍꢓꢔꢀ ꢊ ꢓꢐꢕ ꢆꢀ ꢎꢊ ꢍꢆꢁ ꢆꢖ ꢓ ꢁꢎ ꢒꢎ ꢐꢕ ꢏ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
schematic (each amplifier)  
V
CC+  
IN+  
IN−  
64 Ω  
128 Ω  
64 Ω  
OUT  
C1  
18 pF  
1080 Ω  
1080 Ω  
V
CC−  
OFFSET  
N1  
OFFSET  
N2  
TL071 Only  
All component values shown are nominal.  
COMPONENT COUNT  
COMPONENT  
TYPE  
TL071  
TL072  
TL074  
Resistors  
Transistors  
JFET  
11  
14  
2
22  
28  
4
44  
56  
6
Diodes  
1
2
4
Capacitors  
epi-FET  
1
1
2
2
4
4
Includes bias and trim circuitry  
5
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢉꢅ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)  
Supply voltage (see Note 1): V  
V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −18 V  
CC+  
CC−  
Differential input voltage, V (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 V  
ID  
Input voltage, V (see Notes 1 and 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V  
I
Duration of output short circuit (see Note 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Unlimited  
Package thermal impedance, θ (see Notes 5 and 6): D package (8 pin) . . . . . . . . . . . . . . . . . . . . . . 97°C/W  
JA  
D package (14 pin) . . . . . . . . . . . . . . . . . . . . . 86°C/W  
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80°C/W  
NS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 76°C/W  
P package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85°C/W  
PS package . . . . . . . . . . . . . . . . . . . . . . . . . . . 95°C/W  
PW package (8 pin) . . . . . . . . . . . . . . . . . . . 149°C/W  
PW package (14 pin) . . . . . . . . . . . . . . . . . . 113°C/W  
U package . . . . . . . . . . . . . . . . . . . . . . . . . . . 185°C/W  
Package thermal impedance, θ (see Notes 7 and 8): FK package . . . . . . . . . . . . . . . . . . . . . . . . . 5.61°C/W  
JC  
J package . . . . . . . . . . . . . . . . . . . . . . . . . 15.05°C/W  
JG package . . . . . . . . . . . . . . . . . . . . . . . . . 14.5°C/W  
W package . . . . . . . . . . . . . . . . . . . . . . . . 14.65°C/W  
Operating virtual junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150°C  
J
Case temperature for 60 seconds: FK package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C  
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: J, JG, or W package . . . . . . . . . . . . 300°C  
Storage temperature range, T  
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C  
stg  
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and  
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
NOTES: 1. All voltage values, except differential voltages, are with respect to the midpoint between V  
2. Differential voltages are at IN+, with respect to IN−.  
and V .  
CC−  
CC+  
3. The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15 V, whichever is less.  
4. The output may be shorted to ground or to either supply. Temperature and/or supply voltages must be limited to ensure that the  
dissipation rating is not exceeded.  
5. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable  
J
JA  
A
ambient temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
D
J
A
JA  
J
6. The package thermal impedance is calculated in accordance with JESD 51-7.  
7. Maximum power dissipation is a function of T (max), θ , and T . The maximum allowable power dissipation at any allowable case  
J
JC  
C
temperature is P = (T (max) − T )/θ . Operating at the absolute maximum T of 150°C can affect reliability.  
D
J
C
JC  
J
8. The package thermal impedance is calculated in accordance with MIL-STD-883.  
6
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢀ ꢁꢂ ꢃ ꢄ ꢅ ꢲꢀ ꢁꢂ ꢃ ꢄ ꢆꢅ ꢲꢀ ꢁ ꢂ ꢃꢄ ꢇꢅ ꢲ ꢀꢁ ꢂꢃ ꢈ  
ꢀ ꢁꢂ ꢃ ꢈ ꢆꢅ ꢲꢀ ꢁ ꢂ ꢃꢈ ꢇꢅ ꢲꢀ ꢁ ꢂ ꢃ ꢉ ꢅꢲ ꢀ ꢁ ꢂ ꢃ ꢉ ꢆꢅ ꢲ ꢀꢁ ꢂꢃ ꢉꢇ  
ꢁ ꢊ ꢋꢌꢍꢊ ꢎꢏ ꢐꢲ ꢑ ꢒꢐ ꢀꢌꢎ ꢍꢓꢔꢀ ꢲꢊ ꢓ ꢐꢕꢆꢀ ꢎꢊ ꢍꢆꢁꢲꢆꢖꢓ ꢁꢎ ꢒ ꢎꢐ ꢕꢏ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
7
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
electrical characteristics, V  
= 15 V (unless otherwise noted)  
CC  
TL071M  
TL072M  
TYP MAX  
TL074M  
TYP MAX  
PARAMETER  
TEST CONDITIONS  
T
UNIT  
A
MIN  
MIN  
25°C  
3
6
9
3
9
V
Input offset voltage  
V
= 0,  
= 0,  
R
R
= 50 Ω  
mV  
IO  
O
S
S
Full range  
15  
Temperature coefficient of  
input offset voltage  
α
V
V
V
V
= 50 Full range  
18  
5
18  
5
µV/°C  
O
IO  
25°C  
Full range  
25°C  
100  
20  
100  
20  
pA  
nA  
pA  
nA  
Input offset current  
I
IO  
= 0  
= 0  
O
O
65  
200  
50  
65  
200  
50  
Input bias current  
I
IB  
−12  
to  
15  
−12  
to  
15  
Common-mode input  
voltage range  
V
V
25°C  
11  
11  
V
ICR  
R
R
R
= 10 kΩ  
10 kΩ  
2 kΩ  
25°C  
12  
12  
10  
35  
15  
13.5  
12  
12  
10  
35  
15  
13.5  
L
L
L
Maximum peak output  
voltage swing  
V
OM  
Full range  
25°C  
200  
3
200  
3
Large-signal differential  
voltage amplification  
A
VD  
V
O
=
10 V,  
R
2 kΩ  
V/mV  
L
B
1
Unity-gain bandwidth  
Input resistance  
T
A
= 25°C  
= 25°C  
= V  
MHz  
12  
10  
12  
10  
T
A
r
i
V
V
min,  
R
Common-mode rejection  
ratio  
IC  
O
ICR  
CMRR  
25°C  
80  
80  
86  
86  
80  
80  
86  
86  
dB  
dB  
= 0,  
= 50 Ω  
S
V
V
=
= 0,  
9 V to 15 V,  
= 50 Ω  
Supply-voltage rejection  
CC  
O
k
25°C  
SVR  
R
S
ratio (V  
CC  
/V )  
IO  
Supply current (each  
amplifier)  
I
V
= 0,  
= 100  
No load  
25°C  
25°C  
1.4  
2.5  
1.4  
2.5  
mA  
dB  
CC  
O
V
/V  
Crosstalk attenuation  
A
VD  
120  
120  
O1 O2  
Input bias currents of an FET-input operational amplifier are normal junction reverse currents, which are temperature sensitive, as shown in  
Figure 4. Pulse techniques must be used that will maintain the junction temperature as close to the ambient temperature as possible.  
All characteristics are measured under open-loop conditions with zero common-mode voltage, unless otherwise specified. Full range is  
T
A
= −55°C to 125°C.  
8
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
operating characteristics, V  
= 15 V, T = 25°C  
CC  
A
TL07xM  
TYP  
ALL OTHERS  
PARAMETER  
TEST CONDITIONS  
UNIT  
MIN  
MAX  
MIN  
TYP  
MAX  
V = 10 V,  
R = 2 k,  
L
I
SR  
Slew rate at unity gain  
5
13  
8
13  
V/µs  
µs  
C
= 100 pF,  
See Figure 1  
L
0.1  
20%  
18  
0.1  
20%  
18  
Rise-time overshoot  
factor  
V = 20 mV,  
R
L
= 2 kΩ,  
See Figure 1  
I
L
t
r
C
= 100 pF,  
f = 1 kHz  
nV/Hz  
µV  
Equivalent input noise  
voltage  
V
I
R
= 20 Ω  
n
S
f = 10 Hz to 10 kHz  
f = 1 kHz  
4
4
Equivalent input noise  
current  
R
= 20 Ω,  
0.01  
0.01  
pA/Hz  
n
S
V rms = 6 V,  
A
R
= 1,  
1 k,  
S
I
VD  
0.003  
%
R
2 k,  
THD Total harmonic distortion  
0.003%  
L
f = 1 kHz  
PARAMETER MEASUREMENT INFORMATION  
10 kΩ  
+
V
O
1 kΩ  
+
V
I
V
I
V
O
C
= 100 pF  
L
R
= 2 kΩ  
L
R
C
= 100 pF  
L
L
Figure 1. Unity-Gain Amplifier  
Figure 2. Gain-of-10 Inverting Amplifier  
TL071  
+
IN−  
OUT  
N2  
IN+  
N1  
100 kΩ  
1.5 kΩ  
CC−  
V
Figure 3. Input Offset-Voltage Null Circuit  
9
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ꢉꢅ  
ꢆꢀ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
Table of Graphs  
FIGURE  
I
IB  
Input bias current  
vs Free-air temperature  
4
vs Frequency  
5, 6, 7  
vs Free-air temperature  
vs Load resistance  
vs Supply voltage  
8
9
10  
V
OM  
Maximum output voltage  
vs Free-air temperature  
vs Frequency  
11  
12  
A
VD  
Large-signal differential voltage amplification  
Phase shift  
vs Frequency  
12  
13  
13  
14  
Normalized unity-gain bandwidth  
Normalized phase shift  
Common-mode rejection ratio  
vs Free-air temperature  
vs Free-air temperature  
vs Free-air temperature  
CMRR  
vs Supply voltage  
vs Free-air temperature  
15  
16  
I
Supply current  
CC  
P
Total power dissipation  
Normalized slew rate  
vs Free-air temperature  
vs Free-air temperature  
vs Frequency  
17  
18  
19  
20  
21  
22  
D
V
n
Equivalent input noise voltage  
Total harmonic distortion  
Large-signal pulse response  
Output voltage  
THD  
vs Frequency  
vs Time  
V
O
vs Elapsed time  
10  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
MAXIMUM PEAK OUTPUT VOLTAGE  
INPUT BIAS CURRENT  
vs  
vs  
FREQUENCY  
FREE-AIR TEMPERATURE  
100  
10  
15  
12.5  
10  
V
=
15 V  
10 V  
5 V  
R
= 10 kΩ  
= 25°C  
CC  
V
CC  
= 15 V  
L
T
A
See Figure 2  
V
=
CC  
7.5  
5
1
0.1  
V
CC  
=
2.5  
0
0.01  
100  
1 k  
10 k  
100 k  
1 M  
10 M  
−75 −50 −25  
0
25  
50  
75  
100 125  
f − Frequency − Hz  
T
A
− Free-Air Temperature − °C  
Figure 4  
Figure 5  
MAXIMUM PEAK OUTPUT VOLTAGE  
MAXIMUM PEAK OUTPUT VOLTAGE  
vs  
vs  
FREQUENCY  
FREQUENCY  
15  
12.5  
10  
15  
12.5  
10  
V
R
=
15 V  
R
T
= 2 kΩ  
= 25°C  
CC  
L
L
A
= 2 kΩ  
T
A
= 25°C  
V
=
15 V  
10 V  
CC  
See Figure 2  
See Figure 2  
T
A
= −55°C  
V
CC  
=
7.5  
5
7.5  
5
T
A
= 125°C  
V
CC  
=
5 V  
2.5  
0
2.5  
0
100  
1 k  
10 k  
100 k  
1 M  
10 M  
10 k  
40 k 100 k  
400 k 1 M  
4 M 10 M  
f − Frequency − Hz  
f − Frequency − Hz  
Figure 6  
Figure 7  
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.  
11  
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ꢉꢅ  
ꢆꢀ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
MAXIMUM PEAK OUTPUT VOLTAGE  
MAXIMUM PEAK OUTPUT VOLTAGE  
vs  
vs  
LOAD RESISTANCE  
FREE-AIR TEMPERATURE  
15  
12.5  
10  
15  
12.5  
10  
R
R
= 10 kΩ  
= 2 kΩ  
L
L
V
=
15 V  
CC  
T
= 25°C  
A
See Figure 2  
7.5  
5
7.5  
5
2.5  
0
2.5  
0
V
=
15 V  
CC  
See Figure 2  
−75 −50 −25  
0
25  
50  
75 100 125  
0.1  
0.2  
0.4 0.7  
1
2
4
7 10  
T
A
− Free-Air Temperature − °C  
R
− Load Resistance − kΩ  
L
Figure 8  
Figure 9  
LARGE-SIGNAL  
DIFFERENTIAL VOLTAGE AMPLIFICATION  
MAXIMUM PEAK OUTPUT VOLTAGE  
vs  
vs  
SUPPLY VOLTAGE  
FREE-AIR TEMPERATURE  
15  
12.5  
10  
1000  
R
T
A
= 10 kΩ  
= 25°C  
L
400  
200  
100  
40  
20  
10  
7.5  
5
4
2
1
V
V
R
=
15 V  
10 V  
= 2 kΩ  
CC  
2.5  
0
=
O
L
0
2
4
6
8
10  
12  
14  
16  
−75 −50 −25  
0
25  
50  
75 100 125  
|V  
CC  
| − Supply Voltage − V  
T
A
− Free-Air Temperature − °C  
Figure 10  
Figure 11  
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.  
12  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
LARGE-SIGNAL  
DIFFERENTIAL VOLTAGE AMPLIFICATION  
AND PHASE SHIFT  
vs  
FREQUENCY  
6
5
10  
V
CC  
= 5 V to 15 V  
R
T
A
= 2 kΩ  
= 25°C  
L
10  
4
10  
3
10  
2
10  
1
10  
1
0°  
Differential  
Voltage  
Amplification  
45°  
90°  
Phase Shift  
135°  
180°  
1
10  
100  
1 k  
10 k 100 k 1 M 10 M  
f − Frequency − Hz  
Figure 12  
NORMALIZED UNITY-GAIN BANDWIDTH  
AND PHASE SHIFT  
vs  
FREE-AIR TEMPERATURE  
1.3  
1.2  
1.1  
1
1.03  
1.02  
Unity-Gain Bandwidth  
1.01  
1
Phase Shift  
0.99  
0.98  
0.97  
0.9  
0.8  
0.7  
V
=
15 V  
CC  
R
= 2 kΩ  
L
f = B for Phase Shift  
1
−75 −50 −25  
0
25  
50  
75  
100 125  
T
A
− Free-Air Temperature − °C  
Figure 13  
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.  
13  
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ꢉꢅ  
ꢆꢀ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
SUPPLY CURRENT PER AMPLIFIER  
COMMON-MODE REJECTION RATIO  
vs  
vs  
FREE-AIR TEMPERATURE  
89  
SUPPLY VOLTAGE  
2
1.8  
1.6  
1.4  
1.2  
1
V
=
15 V  
CC  
T
= 25°C  
A
R
= 10 kΩ  
No Signal  
No Load  
L
88  
87  
86  
85  
84  
83  
0.8  
0.6  
0.4  
0.2  
0
−75 −50 −25  
0
25  
50  
75  
100 125  
0
2
4
6
8
10  
12  
14  
16  
|V  
CC  
| − Supply Voltage − V  
T
A
− Free-Air Temperature − °C  
Figure 14  
Figure 15  
SUPPLY CURRENT PER AMPLIFIER  
TOTAL POWER DISSIPATION  
vs  
FREE-AIR TEMPERATURE  
vs  
FREE-AIR TEMPERATURE  
2
1.8  
1.6  
1.4  
1.2  
1
250  
225  
200  
175  
150  
125  
100  
75  
V
= 15 V  
CC  
V
= 15 V  
CC  
No Signal  
No Load  
No Signal  
No Load  
TL074  
0.8  
0.6  
0.4  
0.2  
0
TL072  
TL071  
25  
50  
25  
0
−75 −50 −25  
0
25  
50  
75  
100 125  
−75 −50 −25  
0
50  
75  
100 125  
T
A
− Free-Air Temperature − °C  
T
A
− Free-Air Temperature − °C  
Figure 16  
Figure 17  
Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices.  
14  
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ꢀ ꢁꢂ ꢃ ꢈ ꢆꢅ ꢀ ꢁꢂ ꢃ ꢈ ꢇꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢅ ꢀ ꢁꢂ ꢃ ꢉ ꢆꢅ ꢀꢁ ꢂꢃ ꢉꢇ  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
NORMALIZED SLEW RATE  
vs  
FREE-AIR TEMPERATURE  
EQUIVALENT INPUT NOISE VOLTAGE  
vs  
FREQUENCY  
1.15  
1.10  
1.05  
1
50  
40  
30  
20  
10  
0
V
A
= 15 V  
CC  
V
R
C
=
15 V  
CC  
L
L
= 10  
= 20 Ω  
= 25°C  
VD  
= 2 kΩ  
= 100 pF  
R
T
S
A
0.95  
0.90  
0.85  
10  
40 100  
400 1 k  
4 k 10 k 40 k 100 k  
−75 −50 −25  
0
25  
50  
75  
100 125  
f − Frequency − Hz  
T
A
− Free-Air Temperature − °C  
Figure 18  
Figure 19  
TOTAL HARMONIC DISTORTION  
VOLTAGE-FOLLOWER  
vs  
LARGE-SIGNAL PULSE RESPONSE  
FREQUENCY  
1
6
V
= 15 V  
V
=
= 1  
15 V  
= 6 V  
CC  
CC  
A
R
C
T
= 2 kΩ  
= 100 pF  
VD  
L
L
0.4  
V
I(RMS)  
4
2
= 25°C  
T
A
= 25°C  
A
Output  
0.1  
0.04  
0
0.01  
−2  
−4  
−6  
Input  
0.004  
0.001  
100  
400  
1 k  
4 k 10 k  
40 k 100 k  
0
0.5  
1
1.5  
2
2.5  
3
3.5  
f − Frequency − Hz  
t − Time − µs  
Figure 20  
Figure 21  
15  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
ꢆꢀ  
SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
TYPICAL CHARACTERISTICS  
OUTPUT VOLTAGE  
vs  
ELAPSED TIME  
28  
24  
Overshoot  
20  
16  
12  
8
90%  
4
10%  
V
CC  
= 15 V  
R
T
A
= 2 kΩ  
= 25°C  
0
L
t
r
−4  
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7  
t − Elapsed Time − µs  
Figure 22  
16  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
APPLICATION INFORMATION  
Table of Application Diagrams  
PART  
APPLICATION DIAGRAM  
FIGURE  
NUMBER  
TL071  
TL071  
TL074  
TL072  
TL071  
0.5-Hz square-wave oscillator  
High-Q notch filter  
23  
24  
25  
26  
27  
Audio-distribution amplifier  
100-kHz quadrature oscillator  
AC amplifier  
R
= 100 kΩ  
F
V
CC+  
15 V  
3.3 kΩ  
TL071  
R1  
C3  
R2  
Output  
+
Input  
Output  
TL071  
+
V
CC−  
C
= 3.3 µF  
1 kΩ  
F
−15 V  
R1 + R2 + 2R3 + 1.5 MW  
R3  
C3  
C1  
C2  
3.3 kΩ  
C1 + C2 +  
+ 110 pF  
2
9.1 kΩ  
1
F
1
f +  
fO  
+
+
1 kHz  
2p R  
C
2p R1 C1  
F
Figure 23. 0.5-Hz Square-Wave Oscillator  
Figure 24. High-Q Notch Filter  
V
CC+  
1 MΩ  
TL074  
+
Output A  
V
CC+  
V
V
CC−  
1 µF  
TL074  
+
CC+  
Input  
TL074  
+
Output B  
V
CC−  
100 kΩ  
100 µF  
100 kΩ  
V
CC−  
100 kΩ  
V
CC+  
V
CC+  
100 kΩ  
TL074  
+
Output C  
V
CC−  
Figure 25. Audio-Distribution Amplifier  
17  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
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SLOS080I − SEPTEMBER 1978 − REVISED APRIL 2004  
APPLICATION INFORMATION  
1N4148  
18 k(see Note A)  
6 sin ωt  
−15 V  
18 pF  
1 kΩ  
18 pF  
V
CC+  
V
CC+  
88.4 kΩ  
TL072  
+
6 cos ωt  
TL072  
+
88.4 kΩ  
V
CC−  
1 kΩ  
18 pF  
V
CC−  
15 V  
18 k(see Note A)  
1N4148  
88.4 kΩ  
NOTE A: These resistor values may be adjusted for a symmetrical output.  
Figure 26. 100-kHz Quadrature Oscillator  
V
CC+  
0.1 µF  
10 kΩ  
10 kΩ  
1 MΩ  
IN−  
IN+  
TL071  
OUT  
50 Ω  
+
N2  
N1  
10 kΩ  
0.1 µF  
100 kΩ  
Figure 27. AC Amplifier  
18  
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MECHANICAL DATA  
MCER001A – JANUARY 1995 – REVISED JANUARY 1997  
JG (R-GDIP-T8)  
CERAMIC DUAL-IN-LINE  
0.400 (10,16)  
0.355 (9,00)  
8
5
0.280 (7,11)  
0.245 (6,22)  
1
4
0.065 (1,65)  
0.045 (1,14)  
0.310 (7,87)  
0.290 (7,37)  
0.063 (1,60)  
0.015 (0,38)  
0.020 (0,51) MIN  
0.200 (5,08) MAX  
0.130 (3,30) MIN  
Seating Plane  
0.023 (0,58)  
0.015 (0,38)  
0°–15°  
0.100 (2,54)  
0.014 (0,36)  
0.008 (0,20)  
4040107/C 08/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification.  
E. Falls within MIL STD 1835 GDIP1-T8  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MCFP001A – JANUARY 1995 – REVISED DECEMBER 1995  
U (S-GDFP-F10)  
CERAMIC DUAL FLATPACK  
Base and Seating Plane  
0.250 (6,35)  
0.246 (6,10)  
0.045 (1,14)  
0.026 (0,66)  
0.008 (0,20)  
0.004 (0,10)  
0.080 (2,03)  
0.050 (1,27)  
0.300 (7,62) MAX  
0.019 (0,48)  
0.015 (0,38)  
1
10  
0.050 (1,27)  
0.280 (7,11)  
0.230 (5,84)  
5
6
4 Places  
0.005 (0,13) MIN  
0.350 (8,89)  
0.250 (6,35)  
0.350 (8,89)  
0.250 (6,35)  
4040179/B 03/95  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification only.  
E. Falls within MIL STD 1835 GDFP1-F10 and JEDEC MO-092AA  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MCFP002A – JANUARY 1995 – REVISED FEBRUARY 2002  
W (R-GDFP-F14)  
CERAMIC DUAL FLATPACK  
Base and Seating Plane  
0.260 (6,60)  
0.235 (5,97)  
0.045 (1,14)  
0.026 (0,66)  
0.008 (0,20)  
0.004 (0,10)  
0.080 (2,03)  
0.045 (1,14)  
0.280 (7,11) MAX  
0.019 (0,48)  
0.015 (0,38)  
1
14  
0.050 (1,27)  
0.390 (9,91)  
0.335 (8,51)  
0.005 (0,13) MIN  
4 Places  
7
8
0.360 (9,14)  
0.250 (6,35)  
0.360 (9,14)  
0.250 (6,35)  
4040180-2/C 02/02  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a ceramic lid using glass frit.  
D. Index point is provided on cap for terminal identification only.  
E. Falls within MIL STD 1835 GDFP1-F14 and JEDEC MO-092AB  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MLCC006B – OCTOBER 1996  
FK (S-CQCC-N**)  
LEADLESS CERAMIC CHIP CARRIER  
28 TERMINAL SHOWN  
A
B
NO. OF  
TERMINALS  
**  
18 17 16 15 14 13 12  
MIN  
MAX  
MIN  
MAX  
0.342  
(8,69)  
0.358  
(9,09)  
0.307  
(7,80)  
0.358  
(9,09)  
19  
20  
11  
10  
9
20  
28  
44  
52  
68  
84  
0.442  
(11,23)  
0.458  
(11,63)  
0.406  
(10,31)  
0.458  
(11,63)  
21  
B SQ  
22  
0.640  
(16,26)  
0.660  
(16,76)  
0.495  
(12,58)  
0.560  
(14,22)  
8
A SQ  
23  
0.739  
(18,78)  
0.761  
(19,32)  
0.495  
(12,58)  
0.560  
(14,22)  
7
24  
25  
6
0.938  
(23,83)  
0.962  
(24,43)  
0.850  
(21,6)  
0.858  
(21,8)  
5
1.141  
(28,99)  
1.165  
(29,59)  
1.047  
(26,6)  
1.063  
(27,0)  
26 27 28  
1
2
3
4
0.080 (2,03)  
0.064 (1,63)  
0.020 (0,51)  
0.010 (0,25)  
0.020 (0,51)  
0.010 (0,25)  
0.055 (1,40)  
0.045 (1,14)  
0.045 (1,14)  
0.035 (0,89)  
0.045 (1,14)  
0.035 (0,89)  
0.028 (0,71)  
0.022 (0,54)  
0.050 (1,27)  
4040140/D 10/96  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. This package can be hermetically sealed with a metal lid.  
D. The terminals are gold plated.  
E. Falls within JEDEC MS-004  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MPDI001A – JANUARY 1995 – REVISED JUNE 1999  
P (R-PDIP-T8)  
PLASTIC DUAL-IN-LINE  
0.400 (10,60)  
0.355 (9,02)  
8
5
0.260 (6,60)  
0.240 (6,10)  
1
4
0.070 (1,78) MAX  
0.325 (8,26)  
0.300 (7,62)  
0.020 (0,51) MIN  
0.015 (0,38)  
Gage Plane  
0.200 (5,08) MAX  
Seating Plane  
0.010 (0,25) NOM  
0.125 (3,18) MIN  
0.100 (2,54)  
0.021 (0,53)  
0.430 (10,92)  
MAX  
0.010 (0,25)  
M
0.015 (0,38)  
4040082/D 05/98  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-001  
For the latest package information, go to http://www.ti.com/sc/docs/package/pkg_info.htm  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001  
D (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
8 PINS SHOWN  
0.020 (0,51)  
0.014 (0,35)  
0.050 (1,27)  
8
0.010 (0,25)  
5
0.244 (6,20)  
0.228 (5,80)  
0.008 (0,20) NOM  
0.157 (4,00)  
0.150 (3,81)  
Gage Plane  
1
4
0.010 (0,25)  
0°– 8°  
A
0.044 (1,12)  
0.016 (0,40)  
Seating Plane  
0.010 (0,25)  
0.069 (1,75) MAX  
0.004 (0,10)  
0.004 (0,10)  
PINS **  
8
14  
16  
DIM  
A MAX  
0.197  
(5,00)  
0.344  
(8,75)  
0.394  
(10,00)  
0.189  
(4,80)  
0.337  
(8,55)  
0.386  
(9,80)  
A MIN  
4040047/E 09/01  
NOTES: A. All linear dimensions are in inches (millimeters).  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15).  
D. Falls within JEDEC MS-012  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
MECHANICAL DATA  
MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999  
PW (R-PDSO-G**)  
PLASTIC SMALL-OUTLINE PACKAGE  
14 PINS SHOWN  
0,30  
0,19  
M
0,10  
0,65  
14  
8
0,15 NOM  
4,50  
4,30  
6,60  
6,20  
Gage Plane  
0,25  
1
7
0°8°  
A
0,75  
0,50  
Seating Plane  
0,10  
0,15  
0,05  
1,20 MAX  
PINS **  
8
14  
16  
20  
24  
28  
DIM  
3,10  
2,90  
5,10  
4,90  
5,10  
4,90  
6,60  
6,40  
7,90  
9,80  
9,60  
A MAX  
A MIN  
7,70  
4040064/F 01/97  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.  
D. Falls within JEDEC MO-153  
POST OFFICE BOX 655303 DALLAS, TEXAS 75265  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications,  
enhancements, improvements, and other changes to its products and services at any time and to discontinue  
any product or service without notice. Customers should obtain the latest relevant information before placing  
orders and should verify that such information is current and complete. All products are sold subject to TI’s terms  
and conditions of sale supplied at the time of order acknowledgment.  
TI warrants performance of its hardware products to the specifications applicable at the time of sale in  
accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI  
deems necessary to support this warranty. Except where mandated by government requirements, testing of all  
parameters of each product is not necessarily performed.  
TI assumes no liability for applications assistance or customer product design. Customers are responsible for  
their products and applications using TI components. To minimize the risks associated with customer products  
and applications, customers should provide adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right,  
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Use of such information may require a license from a third party under the patents or other intellectual property  
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Following are URLs where you can obtain information on other Texas Instruments products and application  
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dsp.ti.com  
Broadband  
Digital Control  
Military  
www.ti.com/broadband  
www.ti.com/digitalcontrol  
www.ti.com/military  
Interface  
Logic  
interface.ti.com  
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Microcontrollers  
power.ti.com  
Optical Networking  
Security  
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Copyright 2004, Texas Instruments Incorporated  

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