TLC081CD [ROCHESTER]
OP-AMP, 3000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8;
| 型号： | TLC081CD |
| 厂家： | 
Rochester Electronics |
| 描述： | OP-AMP, 3000uV OFFSET-MAX, 10MHz BAND WIDTH, PDSO8, GREEN, PLASTIC, MS-012AA, SOIC-8 放大器 光电二极管 |
| 文件： | 总54页 (文件大小：2702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
FAMILY OF WIDE-BANDWIDTH HIGH-OUTPUT-DRIVE SINGLE SUPPLY
OPERATIONAL AMPLIFIERS
Check for Samples: TLC080 , TLC081, TLC082, TLC083, TLC084, TLC085, TLC08xA
1
FEATURES
DESCRIPTION
The first
members
of
TI’s
new BiMOS
23
•
Wide Bandwidth: 10 MHz
High Output Drive:
general-purpose operational amplifier family are the
TLC08x. The BiMOS family concept is simple:
provide an upgrade path for BiFET users who are
moving away from dual-supply to single-supply
systems and demand higher ac and dc performance.
With performance rated from 4.5 V to 16 V across
commercial (0°C to 70°C) and an extended industrial
temperature range (–40°C to 125°C), BiMOS suits a
wide range of audio, automotive, industrial, and
instrumentation applications. Familiar features like
offset nulling pins, and new features like MSOP
PowerPAD™ packages and shutdown modes, enable
•
–
–
IOH: 57 mA at VDD – 1.5 V
IOL: 55 mA at 0.5 V
•
High Slew Rate:
–
–
SR+: 16 V/µs
SR–: 19 V/µs
•
•
•
Wide Supply Range: 4.5 V to 16 V
Supply Current: 1.9 mA/Channel
Ultralow Power Shutdown Mode:
higher levels of performance in
applications.
a
variety of
–
IDD: 125 µA/Channel
•
•
•
Low Input Noise Voltage: 8.5 nV√Hz
Input Offset Voltage: 60 µV
Ultra-Small Packages:
Developed in TI’s patented LBC3 BiCMOS process,
the new BiMOS amplifiers combine a very high input
impedance, low-noise CMOS front end with
a
high-drive bipolar output stage, thus providing the
optimum performance features of both. AC
performance improvements over the TL08x BiFET
predecessors include a bandwidth of 10 MHz (an
increase of 300%) and voltage noise of 8.5 nV/√Hz
(an improvement of 60%). DC improvements include
an ensured VICR that includes ground, a factor of 4
reduction in input offset voltage down to 1.5 mV
(maximum) in the standard grade, and a power
supply rejection improvement of greater than 40 dB to
130 dB. Added to this list of impressive features is
the ability to drive ±50-mA loads comfortably from an
ultrasmall-footprint MSOP PowerPAD package, which
positions the TLC08x as the ideal high-performance
general-purpose operational amplifier family.
–
8- or 10-Pin MSOP (TLC080/1/2/3)
–
+
FAMILY PACKAGE TABLE
PACKAGE TYPES
NO. OF
DEVICE
UNIVERSAL
EVM BOARD
CHANNELS
MSOP
PDIP
8
SOIC
8
TSSOP SHUTDOWN
TLC080
TLC081
TLC082
TLC083
TLC084
TLC085
1
1
2
2
4
4
8
8
—
—
—
—
20
20
Yes
8
8
Refer to the EVM
Selection Guide
(Lit# SLOU060)
8
8
8
—
Yes
—
10
14
14
16
14
14
16
Yes
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
PowerPAD is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 1999–2011, Texas Instruments Incorporated
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
TLC080 and TLC081 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)(1)
SMALL OUTLINE
PLASTIC DIP
SYMBOL
(DGN)(1)
TLC080CDGN
TLC081CDGN
TLC080IDGN
TLC081IDGN
—
(P)
TLC080CD
TLC081CD
TLC080ID
TLC081ID
TLC080AID
TLC081AID
xxTIACW
xxTIACY
xxTIACX
xxTIACZ
—
TLC080CP
TLC081CP
TLC080IP
TLC081IP
TLC080AIP
TLC081AIP
0°C to 70°C
–40°C to 125°C
—
—
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC080CDR).
TLC082 and TLC083 AVAILABLE OPTIONS
PACKAGED DEVICES
SMALL
OUTLINE
(D)(1)
MSOP
SYMBOL(2)
PLASTIC
DIP
PLASTIC
DIP
TA
(DGN)(1)
(DGQ)(1)
SYMBOL(2)
(N)
(P)
TLC082CD
TLC083CD
TLC082ID
TLC083ID
TLC082AID
TLC083AID
TLC082CDGN
xxTIADZ
—
—
xxTIAEB
—
—
TLC083CN
—
TLC082CP
0°C to 70°C
—
—
xxTIAEA
—
TLC083CDGQ
—
TLC082IP
—
TLC082IDGN
—
—
—
—
TLC083IDGQ
xxTIAEC
—
TLC083IN
—
–40°C to 125°C
—
—
—
TLC082AIP
—
—
—
TLC083AIN
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC082CDR).
(2) xx represents the device date code.
TLC084 and TLC085 AVAILABLE OPTIONS
PACKAGED DEVICES
TA
SMALL OUTLINE
(D)(1)
PLASTIC DIP
(N)
TSSOP
(PWP)(1)
TLC084CD
TLC085CD
TLC084ID
TLC085ID
TLC084AID
TLC085AID
TLC084CN
TLC085CN
TLC084IN
TLC085IN
TLC084AIN
TLC085AIN
TLC084CPWP
TLC085CPWP
TLC084IPWP
TLC085IPWP
TLC084AIPWP
TLC085AIPWP
0°C to 70°C
–40°C to 125°C
(1) This package is available taped and reeled. To order this packaging option, add an R suffix to the part number (e.g., TLC084CDR).
space
For the most current package and ordering information, see the Package Option Addendum at the end of this
data sheet, or see the TI web site at www.ti.com.
2
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Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TLC080
TLC081
D, DGN, OR P PACKAGE
(TOP VIEW)
TLC082
D, DGN, OR P PACKAGE
(TOP VIEW)
D, DGN, OR P PACKAGE
(TOP VIEW)
NULL
IN
SHDN
NULL
IN
NC
V
1OUT
1IN
V
DD
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
1
2
3
4
8
7
6
5
V
2OUT
2IN
DD
DD
IN+
GND
OUT
IN+
GND
OUT
1IN+
GND
NULL
NULL
2IN+
TLC084
TLC083
D OR N PACKAGE
(TOP VIEW)
TLC083
D OR N PACKAGE
(TOP VIEW)
DGQ PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
1OUT
1IN
1OUT
1IN
V
DD
1
2
3
4
5
6
7
14
13
12
11
10
9
4OUT
4IN
1
1OUT
1IN
V
10
DD
2OUT
2
3
4
5
2OUT
2IN
9
8
7
6
1IN+
1IN+
GND
NC
2IN
4IN+
GND
3IN+
3IN
1IN+
V
2IN+
NC
GND
2IN+
DD
1SHDN
2SHDN
2IN+
2IN
1SHDN
NC
2SHDN
NC
8
2OUT
8
3OUT
TLC085
TLC084
TLC085
PWP PACKAGE
(TOP VIEW)
PWP PACKAGE
D OR N PACKAGE
(TOP VIEW)
(TOP VIEW)
1
20
19
18
17
16
15
14
13
12
11
4OUT
4IN
1OUT
1IN
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1OUT
1IN
4OUT
4IN
1OUT
1IN
4OUT
4IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
2
3
1IN+
VDD
4IN+
GND
3IN+
3IN
1IN+
VDD
2IN+
2IN
4IN+
GND
3IN+
3IN
1IN+
4IN+
4
V
GND
3IN+
3IN
DD
5
2IN+
2IN
2IN+
2IN
6
7
2OUT
1/2SHDN
NC
3OUT
3/4SHDN
NC
2OUT
NC
3OUT
NC
2OUT
3OUT
3/4SHDN
8
1/2SHDN
9
NC
NC
10
NC
NC
NC
NC
NC - No internal connection
TYPICAL PIN 1 INDICATORS
Pin 1
Printed or
Pin 1
Pin 1
Pin 1
Molded Dot
Stripe
Bevel Edges
Molded ”U” Shape
Copyright © 1999–2011, Texas Instruments Incorporated
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3
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)(1)
VALUE
UNIT
(2)
Supply voltage, VDD
17
V
Differential input voltage range, VID
Continuous total power dissipation
±VDD
See Dissipation Rating Table
C suffix
Operating free-air temperature range, TA:
I suffix
0 to 70
−40 to 125
150
°C
°C
°C
°C
°C
Maximum junction temperature, TJ
Storage temperature range, Tstg
–65 to 150
260
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating
conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values, except differential voltages, are with respect to GND .
DISSIPATION RATING TABLE
θJC
(°C/W)
θJA
(°C/W)
TA ≤ 25°C
POWER RATING
PACKAGE
D (8)
D (14)
38.3
26.9
25.7
4.7
176
122.3
114.7
52.7
52.3
78
710 mW
1022 mW
1090 mW
2.37 W
D (16)
DGN (8)
DGQ (10)
N (14, 16)
P (8)
4.7
2.39 W
32
1600 mW
1200 mW
4.79 W
41
104
PWP (20)
1.40
26.1
RECOMMENDED OPERATING CONDITIONS
MIN
4.5
MAX
UNIT
Single supply
Split supply
16
±8
Supply voltage, VDD
V
V
V
±2.25
GND
2
Common-mode input voltage, VICR
Shutdown on/off voltage level(1)
VDD–2
VIH
VIL
0.8
70
C-suffix
I-suffix
0
Operating free-air temperature, TA
°C
–40
125
(1) Relative to the voltage on the GND terminal of the device.
4
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Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC080/1/2/3,
TA(1)
25°C
MIN
TYP
MAX
1900
3000
1400
2000
UNIT
390
TLC084/5
Full range
25°C
VIO
Input offset voltage
µV
VDD = 5 V,
VIC = 2.5 V,
VO = 2.5 V,
TLC080/1/2/3A,
TLC084/5A
390
Full range
Temperature coefficient of
input offset voltage
RS = 50 Ω
∝VIO
1.2
1.9
µV/°C
25°C
Full range
25°C
50
100
700
50
IIO
Input offset current
Input bias current
VDD = 5 V,
VIC = 2.5 V,
VO = 2.5 V,
RS = 50 Ω
TLC08XC
TLC08XI
pA
3
IIB
TLC08XC
TLC08XI
100
700
pA
V
Full range
25°C
Full range
25°C
0 to 3.0
0 to 3.0
4.1
0 to 3.5
0 to 3.5
4.3
VICR
Common-mode input voltage RS = 50 Ω
IOH = –1 mA
IOH = –20 mA
IOH = –35 mA
Full range
25°C
3.9
3.7
4
3.8
3.6
Full range
25°C
3.5
VOH
High-level output voltage
VIC = 2.5 V
V
3.4
Full range
25°C
3.2
3.2
IOH = –50 mA
–40°C to
85°C
3
25°C
Full range
25°C
0.18
0.35
0.43
0.45
0.25
0.35
0.39
0.45
0.55
0.7
IOL = 1 mA
IOL = 20 mA
IOL = 35 mA
Full range
25°C
VOL
Low-level output voltage
VIC = 2.5 V
V
Full range
25°C
0.63
IOL = 50 mA
–40°C to
85°C
0.7
Sourcing
Sinking
25°C
25°C
100
100
57
IOS
Short-circuit output current
Output current
mA
mA
dB
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
25°C
IO
25°C
55
25°C
100
100
120
Large-signal differential
voltage amplification
AVD
VO(PP) = 3 V,
RL = 10 kΩ
Full range
25°C
ri(d)
CIC
Differential input resistance
1000
22.9
GΩ
Common-mode input
capacitance
f = 10 kHz
f = 10 kHz,
25°C
25°C
pF
Closed-loop output
impedance
zo
AV = 10
0.25
110
Ω
25°C
Full range
25°C
80
80
80
80
CMRR
Common-mode rejection ratio VIC = 0 to 3 V,
RS = 50 Ω
dB
VDD = 4.5 V to 16 V, VIC = VDD/2,
No load
100
Supply voltage rejection ratio
(ΔVDD /ΔVIO
kSVR
dB
)
Full range
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Submit Documentation Feedback
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
Copyright © 1999–2011, Texas Instruments Incorporated
5
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA(1)
25°C
MIN
TYP
MAX
2.5
UNIT
1.8
IDD
Supply current (per channel)
VO = 2.5 V, No load
mA
Full range
25°C
3.5
Supply current in shutdown
125
200
IDD(SHDN) mode (per channel) (TLC080, SHDN ≤ 0.8 V
µA
Full range
250
TLC083, TLC085)
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 5 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
10
TYP
MAX
UNIT
VO(PP) = 0.8 V,
CL = 50 pF,
CL = 50 pF,
25°C
16
Positive slew rate at unity
gain
SR+
V/µs
RL = 10 kΩ
VO(PP) = 0.8 V,
RL = 10 kΩ
f = 100 Hz
f = 1 kHz
Full range
25°C
9.5
12.5
10
19
Negative slew rate at unity
gain
SR–
V/µs
Full range
25°C
12
Equivalent input noise
voltage
Vn
In
nV/√Hz
fA /√Hz
25°C
8.5
Equivalent input noise
current
f = 1 kHz
25°C
0.6
VO(PP) = 3 V,
AV = 1
0.002
0.012
0.085
0.15
1.3
Total harmonic distortion
plus noise
THD + N
RL = 10 kΩ and 250 Ω,
f = 1 kHz
AV = 10
AV = 100
25°C
%
t(on)
t(off)
Amplifier turnon time(2)
Amplifier turnoff time(2)
Gain-bandwidth product
25°C
25°C
25°C
µs
µs
RL = 10 kΩ
f = 10 kHz,
RL = 10 kΩ
10
MHz
V(STEP)PP = 1 V,
AV = −1,
0.1%
0.18
CL = 10 pF,
RL = 10 kΩ
0.01%
0.1%
0.39
0.18
0.39
ts
Settling time
25°C
µs
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF,
RL = 10 kΩ
0.01%
RL = 10 kΩ,
RL = 10 kΩ,
RL = 10 kΩ,
RL = 10 kΩ,
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 0 pF
32
40
φm
Phase margin
Gain margin
25°C
25°C
°
2.2
3.3
dB
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
6
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Copyright © 1999–2011, Texas Instruments Incorporated
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
ELECTRICAL CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TLC080/1/2/3,
TA(1)
25°C
MIN
TYP
MAX
1900
3000
1400
2000
UNIT
390
TLC084/5
Full range
25°C
VIO
Input offset voltage
µV
VDD = 12 V,
VIC = 6 V,
VO = 6 V,
TLC080/1/2/3A,
TLC084/5A
390
Full range
Temperature coefficient of
input offset voltage
RS = 50 Ω
∝VIO
1.2
1.5
µV/°C
25°C
Full range
25°C
50
100
700
50
IIO
Input offset current
Input bias current
VDD = 12 V,
VIC = 6 V,
VO = 6 V,
RS = 50 Ω
TLC08xC
TLC08xI
pA
3
IIB
TLC08xC
TLC08xI
100
700
pA
V
Full range
25°C
0 to 10.0 0 to 10.5
VICR
Common-mode input voltage RS = 50 Ω
Full range 0 to 10.0 0 to 10.5
25°C
Full range
25°C
11.1
11
11.2
IOH = –1 mA
IOH = –20 mA
IOH = –35 mA
10.8
10.7
10.6
10.3
10.3
11
Full range
25°C
VOH
High-level output voltage
VIC = 6 V
V
10.7
10.5
Full range
25°C
IOH = –50 mA
–40°C to
85°C
10.2
25°C
Full range
25°C
0.17
0.35
0.4
0.25
0.35
0.45
0.5
IOL = 1 mA
IOL = 20 mA
IOL = 35 mA
Full range
25°C
VOL
Low-level output voltage
VIC = 6 V
V
0.52
0.6
Full range
25°C
0.45
0.6
IOL = 50 mA
–40°C to
85°C
0.65
Sourcing
Sinking
25°C
25°C
150
150
57
IOS
Short-circuit output current
Output current
mA
mA
dB
VOH = 1.5 V from positive rail
VOL = 0.5 V from negative rail
25°C
IO
25°C
55
25°C
120
120
140
Large-signal differential
voltage amplification
AVD
VO(PP) = 8 V,
RL = 10 kΩ
Full range
25°C
ri(d)
CIC
Differential input resistance
1000
21.6
GΩ
Common-mode input
capacitance
f = 10 kHz
f = 10 kHz,
25°C
25°C
pF
Closed-loop output
impedance
zo
AV = 10
0.25
110
Ω
25°C
Full range
25°C
80
80
80
80
CMRR
Common-mode rejection ratio VIC = 0 to 10 V,
RS = 50 Ω
dB
VDD = 4.5 V to 16 V, VIC = VDD/2,
No load
100
Supply voltage rejection ratio
(ΔVDD /ΔVIO
kSVR
dB
)
Full range
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
Submit Documentation Feedback
Product Folder Link(s): TLC080 TLC081 TLC082 TLC083 TLC084 TLC085 TLC08xA
Copyright © 1999–2011, Texas Instruments Incorporated
7
TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
PARAMETER
TEST CONDITIONS
TA(1)
25°C
MIN
TYP
MAX
2.9
UNIT
1.9
IDD
Supply current (per channel)
VO = 7.5 V, No load
mA
Full range
25°C
3.5
Supply current in shutdown
125
200
IDD(SHDN) mode (TLC080, TLC083,
TLC085) (per channel)
SHDN ≤ 0.8 V
µA
Full range
250
OPERATING CHARACTERISTICS
at specified free-air temperature, VDD = 12 V (unless otherwise noted)
(1)
PARAMETER
TEST CONDITIONS
TA
MIN
10
TYP
MAX
UNIT
VO(PP) = 2 V,
CL = 50 pF,
CL = 50 pF,
25°C
16
Positive slew rate at unity
gain
SR+
V/µs
RL = 10 kΩ
VO(PP) = 2 V,
RL = 10 kΩ
f = 100 Hz
f = 1 kHz
Full range
25°C
9.5
12.5
10
19
Negative slew rate at unity
gain
SR–
V/µs
Full range
25°C
14
Equivalent input noise
voltage
Vn
In
nV/√Hz
fA /√Hz
25°C
8.5
Equivalent input noise
current
f = 1 kHz
25°C
0.6
VO(PP) = 8 V,
AV = 1
0.002
0.005
0.022
0.47
2.5
Total harmonic distortion
plus noise
THD + N
RL = 10 kΩ and 250 Ω,
f = 1 kHz
AV = 10
AV = 100
25°C
%
t(on)
t(off)
Amplifier turnon time(2)
Amplifier turnoff time(2)
Gain-bandwidth product
25°C
25°C
25°C
µs
µs
RL = 10 kΩ
f = 10 kHz,
RL = 10 kΩ
10
MHz
V(STEP)PP = 1 V,
AV = −1,
0.1%
0.17
CL = 10 pF,
RL = 10 kΩ
0.01%
0.1%
0.22
0.17
0.29
ts
Settling time
25°C
µs
V(STEP)PP = 1 V,
AV = –1,
CL = 47 pF,
RL = 10 kΩ
0.01%
RL = 10 kΩ,
RL = 10 kΩ,
RL = 10 kΩ,
RL = 10 kΩ,
CL = 50 pF
CL = 0 pF
CL = 50 pF
CL = 0 pF
37
42
3.1
4
φm
Phase margin
Gain margin
25°C
25°C
°
dB
(1) Full range is 0°C to 70°C for C suffix and –40°C to 125°C for I suffix. If not specified, full range is –40°C to 125°C.
(2) Disable time and enable time are defined as the interval between application of the logic signal to SHDN and the point at which the
supply current has reached half its final value.
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
Table of Graphs
FIGURE
VIO
Input offset voltage
Input offset current
Input bias current
vs Common-mode input voltage
vs Free-air temperature
1, 2
3, 4
3, 4
5, 7
6, 8
9
IIO
IIB
vs Free-air temperature
vs High-level output current
vs Low-level output current
vs Frequency
VOH
VOL
Zo
High-level output voltage
Low-level output voltage
Output impedance
Supply current
IDD
vs Supply voltage
vs Frequency
10
PSRR
CMRR
Vn
Power supply rejection ratio
Common-mode rejection ratio
Equivalent input noise voltage
Peak-to-peak output voltage
Crosstalk
11
vs Frequency
12
vs Frequency
13
VO(PP)
vs Frequency
14, 15
16
vs Frequency
Differential voltage gain
Phase
vs Frequency
17, 18
17, 18
19, 20
21, 22
23
vs Frequency
φm
Phase margin
vs Load capacitance
vs Load capacitance
vs Supply voltage
Gain margin
Gain-bandwidth product
vs Supply voltage
vs Free-air temperature
24
25, 26
SR
Slew rate
vs Frequency
27, 28
29, 30
31, 32
33
THD + N
Total harmonic distortion plus noise
vs Peak-to-peak output voltage
Large-signal follower pulse response
Small-signal follower pulse response
Large-signal inverting pulse response
Small-signal inverting pulse response
Shutdown forward isolation
34, 35
36
vs Frequency
37, 38
39, 40
41
Shutdown reverse isolation
vs Frequency
vs Supply voltage
vs Free-air temperature
Shutdown supply current
Shutdown pulse
42
43, 44
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
INPUT BIAS CURRENT AND
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET VOLTAGE
vs
INPUT OFFSET CURRENT
vs
COMMON-MODE INPUT VOLTAGE
COMMON-MODE INPUT VOLTAGE
FREE-AIR TEMPERATURE
1000
1500
300
250
V
= 5 V
DD
= 25° C
V
= 12 V
DD
= 25° C
V
= 5 V
DD
1300
1100
900
T
800
600
400
200
0
T
A
A
200
150
700
500
300
100
50
I
IB
100
-100
-300
-500
-200
-400
-600
0
I
IO
-50
-100
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
0
1
2
3
4
5
6
7
8
9 10 11 12
-55 -40 -25 -10
5 20 35 50 65 80 95 110125
V
– Common-Mode Input Voltage – V
V
– Common-Mode Input Voltage – V
ICR
TA – Free-Air Temperature – °C
ICR
Figure 1.
Figure 2.
Figure 3.
INPUT BIAS CURRENT AND
INPUT OFFSET CURRENT
vs
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
FREE-AIR TEMPERATURE
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
20
0
V
= 5 V
V
= 5 V
DD
DD
I
IO
T
= 70°C
A
-20
-40
T
= 25°C
A
T
= 125°C
A
T
= 70°C
A
-60
T
= 40 °C
A
T
= 25°C
A
-80
T
= 125°C
A
-100
-120
-140
T
= 40 °C
A
I
IB
V
= 12 V
DD
-160
0
5
10 15 20 25 30 35 40 45 50
0
5
10 15 20 25 30 35 40 45 50
-55 -40 -25 -10
5 20 35 50 65 80 95 110 125
I
- High-Level Output Current - mA
I
– Low-Level Output Current – mA
OH
OL
TA – Free-Air Temperature – °C
Figure 4.
Figure 5.
Figure 6.
HIGH-LEVEL OUTPUT VOLTAGE
vs
LOW-LEVEL OUTPUT VOLTAGE
vs
OUTPUT IMPEDANCE
vs
HIGH-LEVEL OUTPUT CURRENT
LOW-LEVEL OUTPUT CURRENT
FREQUENCY
1000
100
10
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
12.0
11.5
11.0
10.5
10.0
9.5
V
T
= 5 V and 12 V
DD
T
= 125°C
A
= 25°C
A
T
= 70°C
A
T
= 125°C
A
T
= 70°C
A
A
= 100
V
T
= 25°C
A
T
= 40 °C
A
T
= 25°C
A
1
0.10
0.01
A
A
= 10
= 1
V
T
= 40 °C
A
V
V
= 12 V
V
= 12 V
DD
5
DD
5
9.0
0
10 15 20 25 30 35 40 45 50
0
10 15 20 25 30 35 40 45 50
100
1k
10k
100k
1M
10M
f – Frequency – Hz
IOL – Low-Level Output Current – mA
I
– High-Level Output Current – mA
OH
Figure 7.
Figure 8.
Figure 9.
10
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
POWER SUPPLY REJECTION
RATIO
SUPPLY CURRENT
vs
COMMON-MODE REJECTION RATIO
vs
vs
SUPPLY VOLTAGE
FREQUENCY
FREQUENCY
140
2.4
2.2
2.0
1.8
1.6
1.4
140
120
V
T
= 5 V and 12 V
DD
= 25°C
T
= 25°C
120
100
80
60
40
20
0
A
A
V
= 12 V
DD
T
= 40 °C
100
80
60
40
20
0
A
T
= 125°C
A
T
= 70°C
A
V
= 5 V
DD
A
V
= 1
1.2
1.0
SHDN = V
DD
Per Channel
4
5
6
7
8
9 10 11 12 13 14 15
0
10 100
1k
10k 100k 1M 10M
100
1k
10k
100k
1M
10M
f – Frequency – Hz
f – Frequency – Hz
VDD – Supply Voltage – V
Figure 10.
Figure 11.
Figure 12.
PEAK-TO-PEAK OUTPUT
VOLTAGE
PEAK-TO-PEAK OUTPUT
VOLTAGE
EQUIVALENT INPUT NOISE
VOLTAGE
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
12
10
8
12
10
8
40
V
= 12 V
DD
V
= 12 V
35
30
25
20
15
10
5
DD
6
6
V
= 5 V
DD
V
= 5 V
DD
V
= 12 V
4
4
DD
THD+N < = 5%
THD+N < = 5%
2
2
V
= 5 V
DD
R = 10 kΩ
L
R
T
= 600 Ω
L
T
A
= 25°C
= 25°C
A
0
0
0
10k
100k
1M
10M
10k
100k
1M
10M
10
100
1k
10k
100k
f – Frequency – Hz
f – Frequency – H
f – Frequency – Hz
Figure 13.
Figure 14.
Figure 15.
CROSSTALK
vs
FREQUENCY
0
V
= 5 V and 12 V
DD
-20
A
= 1
V
R
= 10 kΩ
L
= 2 V
I(PP)
-40
-60
-80
V
For All Channels
-100
-120
-140
-160
10
100
1k
10k
100k
f – Frequency – Hz
Figure 16.
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
DIFFERENTIAL VOLTAGE GAIN AND
DIFFERENTIAL VOLTAGE GAIN AND
PHASE
vs
PHASE
vs
FREQUENCY
FREQUENCY
80
70
0
80
70
0
Gain
60
50
40
30
20
10
0
Gain
-45
60
50
40
30
20
10
0
-45
Phase
Phase
-90
-90
-135
-180
-225
-135
-180
-225
V
R
C
T
= ±2.5 V
V
R
C
= ±6 V
= 10 kΩ
DD
L
L
DD
L
L
= 10 kΩ
= 0 pF
= 25°C
-10
-10
= 0 pF T
A
= 25°C
A
-20
-20
1k
10k
100k
1M
10M
100M
1k
10k
100k
1M
10M 100M
f – Frequency – Hz
f – Frequency – Hz
Figure 17.
Figure 18.
PHASE MARGIN
vs
PHASE MARGIN
vs
GAIN MARGIN
vs
LOAD CAPACITANCE
LOAD CAPACITANCE
LOAD CAPACITANCE
45°
4
40°
35°
R
= 0 Ω
R
R
= 0 Ω
null
null
null
R
= 0 Ω
null
40°
35°
= 100 Ω
3.5
3
R
= 100 Ω
null
30°
R
= 50 Ω
null
30°
25°
20°
2.5
R
= 100 Ω
25°
20°
15°
null
R
= 50 Ω
R
null
2
R
= 50 Ω
null
R
= 20 Ω
= 20 Ω
null
null
1.5
15°
1
0.5
0
10°
V
= 12 V
V
= 5 V
DD
V
= 5 V
DD
DD
10°
5°
R
= 20 Ω
null
R
T
= 10 kΩ
R
T
= 10 kΩ
L
= 25°C
R
T
= 10 kΩ
L
L
5°
0°
= 25°C
= 25°C
A
A
A
0°
10
100
10
100
10
100
C
– Load Capacitance – pF
L
C
– Load Capacitance – pF
C
– Load Capacitance – pF
L
L
Figure 19.
Figure 20.
Figure 21.
GAIN MARGIN
vs
GAIN BANDWIDTH PRODUCT
SLEW RATE
vs
vs
LOAD CAPACITANCE
SUPPLY VOLTAGE
SUPPLY VOLTAGE
5
10.0
9.9
9.8
9.7
9.6
9.5
9.4
9.3
9.2
9.1
9.0
22
21
20
19
18
17
16
15
14
13
12
R
= 0 Ω
null
R
C
= 600 Ω and 10 kΩ
= 50 pF
= 1
C
= 11 pF
L
L
L
4.5
4
T = 25°C
A
A
R
= 100 Ω
V
null
3.5
3
Slew Rate
R
= 10 kΩ
L
2.5
2
R
= 50 Ω
null
R
= 600 Ω
R
= 20 Ω
L
null
Slew Rate +
1.5
V
= 12 V
DD
1
0.5
0
R
T
= 10 kΩ
L
= 25°C
A
4
5
6
7
8
9
10 11 12 13 14 15 16
4
5
6
7
8
9 10 11 12 13 14 15 16
10
100
V
– Supply Voltage – V
V
– Supply Voltage – V
DD
C
– Load Capacitance – pF
DD
L
Figure 22.
Figure 23.
Figure 24.
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
TOTAL HARMONIC DISTORTION
SLEW RATE
vs
SLEW RATE
vs
PLUS NOISE
vs
FREE-AIR TEMPERATURE
FREE-AIR TEMPERATURE
FREQUENCY
1
25
20
15
10
5
25
V
= 5 V
DD
L
L
V
V
= 5 V
DD
R
C
A
= 600 Ω and 10 kΩ
= 50 pF
= 1
Slew Rate –
V
= 2 V
O(PP)
= 10 kΩ
Slew Rate
R
20
L
A
= 100
V
0.1
15
Slew Rate +
Slew Rate +
A
A
= 10
10
V
V
0.01
V
= 12 V
= 600 Ω and 10 kΩ
= 50 pF
DD
L
L
V
5
R
C
A
= 1
= 1
0
0
0.001
-55 -35 -15
5
25 45 65 85 105 125
-55 -35 -15
5
25 45 65 85 105 125
100
1k
10k
100k
T
– Free-Air Temperature –°C
T
– Free-Air Temperature –°C
A
f – Frequency– Hz
A
Figure 25.
Figure 26.
Figure 27.
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
TOTAL HARMONIC DISTORTION
PLUS NOISE
vs
PLUS NOISE
vs
PLUS NOISE
vs
FREQUENCY
PEAK-TO-PEAK OUTPUT VOLTAGE
PEAK-TO-PEAK OUTPUT VOLTAGE
0.1
10
10
V
= 5 V
V
= 12 V
DD
= 1
DD
A = 1
V
V
= 12 V
DD
R
= 250Ω
A
L
V
f = 1 kHz
V
= 8 V
O(PP)
= 10 kΩ
f = 1 kHz
R
L
1
1
R
= 250Ω
A
= 100
L
V
0.1
0.1
0.01
R
= 600Ω
R
= 600Ω
L
L
0.01
0.01
A
A
= 10
= 1
V
V
R
= 10 kΩ
L
0.001
0.001
R
= 10 kΩ
L
0.0001
0.0001
0.001
0.25 0.75 1.25 1.75 2.25 2.75 3.25 3.75
0.5
2.5
4.5
6.5
8.5
10.5
100
1k
10k
100k
V
– Peak-to-Peak Output Voltage – V
V – Peak-to-Peak Output Voltage – V
O(PP)
f – Frequency – Hz
O(PP)
Figure 28.
Figure 29.
Figure 30.
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
LARGE SIGNAL FOLLOWER
PULSE RESPONSE
SMALL SIGNAL FOLLOWER
PULSE RESPONSE
V (1 V/Div)
I
V (5 V/Div)
I
V (100mV/Div)
I
V
(2 V/Div)
O
V
(500 mV/Div)
= 5 V
O
V
(50mV/Div)
O
V
= 12 V
V
DD
DD
R
= 600 Ω
L
and 10 kΩ
R
= 600 Ω
L
and 10 kΩ
V
= 5 V and 12 V
= 600Ω and 10 kΩ
= 8 pF
DD
L
L
R
C
T
C
T
= 8 pF
L
= 25°C
C
= 8 pF
L
T
A
= 25°C
A
= 25°C
A
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1 1.2 1.4 1.6 1.8 2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.10
t – Time – ms
t – Time – ms
t – Time – ms
Figure 31.
Figure 32.
Figure 33.
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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TYPICAL CHARACTERISTICS
LARGE SIGNAL INVERTING
PULSE RESPONSE
LARGE SIGNAL INVERTING
PULSE RESPONSE
SMALL SIGNAL INVERTING
PULSE RESPONSE
V
(2 V/div)
V (5 V/div)
I
I
V
(100 mV/div)
I
V
R
C
T
= 5 V and 12 V
DD
= 600 Ω and 10 kΩ
= 8 pF
L
L
V
= 5 V
DD
V
= 12 V
DD
R
= 600 Ω
L
and 10 kΩ
R
= 600 Ω
L
and 10 kΩ
= 25°C
A
C
= 8 pF
L
C
T
= 8 pF
L
= 25°C
T
A
= 25°C
A
V
(50 mV/Div)
O
V
(2 V/Div)
V
(500 mV/Div)
O
O
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6 1.8
2
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
t – Time – ms
t – Time – ms
t – Time – ms
Figure 34.
Figure 35.
Figure 36.
SHUTDOWN FORWARD
ISOLATION
SHUTDOWN FORWARD
ISOLATION
SHUTDOWN REVERSE
ISOLATION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
140
120
100
80
140
120
100
80
140
120
100
80
V
= 5 V
V
= 5 V
DD
C = 0 pF
DD
C = 0 pF
V
= 12 V
DD
C = 0 pF
L
L
L
T
A
V
= 25°C
T
A
V
= 25°C
T
A
V
= 25°C
= 0.1, 2.5, and 5 V
= 0.1, 2.5, and 5 V
I(PP)
I(PP)
= 0.1, 8, 12 V
I(PP)
R
= 600 Ω
L
R
= 600 Ω
L
R
= 600 Ω
L
60
R
= 10 kΩ
60
60
L
R
= 10 kΩ
R
= 10 kΩ
L
L
40
40
40
20
20
20
100
1k
10k 100k
1M
10M 100M
100
1k
10k 100k
1M
10M 100M
100
1k
10k 100k
1M
10M 100M
f – Frequency – Hz
f – Frequency – Hz
f – Frequency – Hz
Figure 37.
Figure 38.
Figure 39.
SHUTDOWN REVERSE
ISOLATION
vs
SHUTDOWN SUPPLY CURRENT
SHUTDOWN SUPPLY CURRENT
vs
vs
FREQUENCY
SUPPLY VOLTAGE
FREE-AIR TEMPERATURE
140
136
134
132
130
128
126
124
122
120
118
180
160
140
120
100
80
A
= 1
= V
DD/2
V
V
= 12 V
Shutdown On
R
DD
C = 0 pF
V
IN
= open
= V
L
IN
L
120
100
80
V
DD/2
T
A
V
= 25°C
= 0.1, 8, 12 V
I(PP)
V
= 12 V
DD
R
= 600 Ω
L
V
= 5 V
DD
60
R
= 10 kΩ
L
40
20
60
4
5
6
7
8
9
10 11 12 13 14 15 16
–55
–25
5
35
65
95
125
100
1k
10k 100k
1M
10M 100M
V
– Supply Voltage – V
T
– Free-Air Temperature –°C
f – Frequency – Hz
DD
A
Figure 40.
Figure 41.
Figure 42.
14
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
TYPICAL CHARACTERISTICS
SHUTDOWN PULSE
SHUTDOWN PULSE
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6.0
5.5
5.0
4.5
4.0
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0.0
6
4
6
SD Off
SD Off
4
Shutdown Pulse
Shutdown Pulse
2
0
2
V
= 5 V
V
= 12 V
DD
= 8 pF
DD
= 8 pF
C
T
C
T
L
L
= 25°C
= 25°C
0
A
A
I
R
= 10 kΩ
I R = 10 kΩ
DD L
DD
L
-2
-4
-6
-2
-4
-6
I
R
= 600 Ω
I R = 600 Ω
DD L
DD
L
0
10 20 30 40 50 60 70 80
0
10 20 30 40 50 60 70
80
t – Time –ms
t – Time –ms
Figure 43.
Figure 44.
PARAMETER MEASUREMENT INFORMATION
R
_
+
null
R
L
C
L
Figure 45
Figure 45.
APPLICATION INFORMATION
Input Offset Voltage Null Circuit
The TLC080 and TLC081 has an input offset nulling function. Refer to Figure 46 for the diagram.
IN
OUT
+
N2
IN+
N1
100 kΩ
R1
V
DD
A. R1 = 5.6 kΩ for offset voltage adjustment of ±10 mV. R1 = 20 kΩ for offset voltage adjustment of ±3 mV.
Figure 46. Input Offset Voltage Null Circuit
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Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device’s phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (RNULL) with the output of the amplifier, as
shown in Figure 47. A minimum value of 20 Ω should work well for most applications.
R
F
R
G
_
+
R
NULL
Input
Output
LOAD
C
Figure 47. Driving a Capacitive Load
Offset Voltage
The output offset voltage, (VOO) is the sum of the input offset voltage (VIO) and both input bias currents (IIB) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
R
F
I
IB–
R
G
+
V
I
V
O
+
R
S
I
IB+
R
R
R
R
F
F
V
V
1
± I + R
IB
1
± I
R
+
)
)
+
)
)
G
(
(
=
(
(
OO
IO
S
IB–
F
G
Figure 48. Output Offset Voltage Model
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
High Speed CMOS Input Amplifiers
The TLC08x is a family of high-speed low-noise CMOS input operational amplifiers that has an input capacitance
of the order of 20 pF. Any resistor used in the feedback path adds a pole in the transfer function equivalent to the
input capacitance multiplied by the combination of source resistance and feedback resistance. For example, a
gain of –10, a source resistance of 1 kΩ, and a feedback resistance of 10 kΩ add an additional pole at
approximately 8 MHz. This is more apparent with CMOS amplifiers than bipolar amplifiers due to their greater
input capacitance.
This is of little consequence on slower CMOS amplifiers, as this pole normally occurs at frequencies above their
unity-gain bandwidth. However, the TLC08x with its 10-MHz bandwidth means that this pole normally occurs at
frequencies where there is on the order of 5dB gain left and the phase shift adds considerably.
The effect of this pole is the strongest with large feedback resistances at small closed loop gains. As the
feedback resistance is increased, the gain peaking increases at a lower frequency and the 180° phase shift
crossover point also moves down in frequency, decreasing the phase margin.
For the TLC08x, the maximum feedback resistor recommended is 5 kΩ; larger resistances can be used but a
capacitor in parallel with the feedback resistor is recommended to counter the effects of the input capacitance
pole.
The TLC083 with a 1-V step response has an 80% overshoot with a natural frequency of 3.5 MHz when
configured as a unity gain buffer and with a 10-kΩ feedback resistor. By adding a 10-pF capacitor in parallel with
the feedback resistor, the overshoot is reduced to 40% and eliminates the natural frequency, resulting in a much
faster settling time (see Figure 49). The 10-pF capacitor was chosen for convenience only.
Load capacitance had little effect on these measurements due to the excellent output drive capability of the
TLC08x.
2
V
10 pF
IN
1
0
1
With
= 10 pF
10 kΩ
C
F
1.5
_
+
1
IN
V
A
R
R
C
= ±5 V
0.5
DD
= +1
600 Ω
V
22 pF
V
OUT
= 10 kΩ
= 600 Ω
= 22 pF
50 Ω
F
L
L
0
0.5
0
0.2 0.4 0.6 0.8
1
1.2 1.4 1.6
t - Time - ms
Figure 49. 1-V Step Response
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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General Configurations
When receiving low-level signals, limiting the bandwidth of the incoming signals into theFigure 50 system is often
required. The simplest way to accomplish this is to place an RC filter at the noninverting terminal of the amplifier
(see ).
R
R
F
G
V
1
O
+
V
I
R1
C1
f
=
–3dB
2pR1C1
V
R
O
F
1
( )( )
1 +
=
V
R
1
sR1C1
+
I
G
Figure 50. Single-Pole Low-Pass Filter
If even more attenuation is needed, a multiple pole filter is required. The Sallen-Key filter can be used for this
task. For best results, the amplifier should have a bandwidth that is 8 to 10 times the filter frequency bandwidth.
Failure to do this can result in phase shift of the amplifier.
C1
R1 = R2 = R
C1 = C2 = C
Q = Peaking Factor
(Butterworth Q = 0.707)
+
_
V
I
1
2pRC
R1
R2
f
=
2
–3dB
C2
R
F
R
=
G
1
R
F
–
)
R
(
Q
G
Figure 51. 2-Pole Low-Pass Sallen-Key Filter
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TLC080 , TLC081, TLC082
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
Shutdown Function
Three members of the TLC08x family (TLC080/3/5) have a shutdown terminal (SHDN) for conserving battery life
in portable applications. When the shutdown terminal is tied low, the supply current is reduced to
125 µA/channel, the amplifier is disabled, and the outputs are placed in a high-impedance mode. To enable the
amplifier, the shutdown terminal can either be left floating or pulled high. When the shutdown terminal is left
floating, care should be taken to ensure that parasitic leakage current at the shutdown terminal does not
inadvertently place the operational amplifier into shutdown. The shutdown terminal threshold is always
referenced to the voltage on the GND terminal of the device. Therefore, when operating the device with split
supply voltages (e.g. ±2.5 V), the shutdown terminal needs to be pulled to VDD– (not system ground) to disable
the operational amplifier.
The amplifier’s output with a shutdown pulse is shown in Figure 43 and Figure 44. The amplifier is powered with
a single 5-V supply and is configured as noninverting with a gain of 5. The amplifier turnon and turnoff times are
measured from the 50% point of the shutdown pulse to the 50% point of the output waveform. The times for the
single, dual, and quad are listed in the data tables.
Figure 37 through Figure 40 show the amplifiers forward and reverse isolation in shutdown. The operational
amplifier is configured as a voltage follower (AV = 1). The isolation performance is plotted across frequency using
0.1 VPP, 2.5 VPP, and 5 VPP input signals at ±2.5 V supplies and 0.1 VPP, 8 VPP, and 12 VPP input signals at ±6 V
supplies.
Circuit Layout Considerations
To achieve the levels of high performance of the TLC08x, follow proper printed-circuit board design techniques.
A general set of guidelines is given in the following.
•
Ground planes – It is highly recommended that a ground plane be used on the board to provide all
components with a low inductive ground connection. However, in the areas of the amplifier inputs and output,
the ground plane can be removed to minimize the stray capacitance.
•
Proper power supply decoupling – Use a 6.8-µF tantalum capacitor in parallel with a 0.1-µF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-µF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-µF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
•
•
Sockets – Sockets can be used but are not recommended. The additional lead inductance in the socket pins
will often lead to stability problems. Surface-mount packages soldered directly to the printed-circuit board is
the best implementation.
Short trace runs/compact part placements – Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This will help to minimize stray capacitance at the
input of the amplifier.
•
Surface-mount passive components – Using surface-mount passive components is recommended for high
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
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General PowerPAD Design Considerations
The TLC08x is available in a thermally-enhanced PowerPAD family of packages. These packages are
constructed using a downset leadframe upon which the die is mounted [see Figure 52(a) and Figure 52(b)]. This
arrangement results in the lead frame being exposed as a thermal pad on the underside of the package [see
Figure 52(c)]. Because this thermal pad has direct thermal contact with the die, excellent thermal performance
can be achieved by providing a good thermal path away from the thermal pad.
DIE
Thermal
Side View (a)
Pad
DIE
Bottom View (c)
End View (b)
A. The thermal pad is electrically isolated from all terminals in the package.
Figure 52. Views of Thermally-Enhanced DGN Package
The PowerPAD package allows for both assembly and thermal management in one manufacturing operation.
During the surface-mount solder operation (when the leads are being soldered), the thermal pad must be
soldered to a copper area underneath the package. Through the use of thermal paths within this copper area,
heat can be conducted away from the package into either a ground plane or other heat dissipating device.
Soldering the PowerPAD to the printed circuit board (PCB) is always required, even with applications
that have low power dissipation. This soldering provides the necessary thermal and mechanical connection
between the lead frame die pad and the PCB.
Although there are many ways to properly heatsink the PowerPAD package, the following steps illustrate the
recommended approach.
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TLC080 , TLC081, TLC082
TLC083, TLC084, TLC085, TLC08xA
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
The PowerPAD must be connected to the most negative supply voltage (GND pin potential) of the device.
1. Prepare the PCB with a top side etch pattern (see the landing patterns at the end of this data sheet). There
should be etch for the leads as well as etch for the thermal pad.
2. Place five holes (dual) or nine holes (quad) in the area of the thermal pad. These holes should be 13 mils in
diameter. Keep them small so that solder wicking through the holes is not a problem during reflow.
3. Additional vias may be placed anywhere along the thermal plane outside of the thermal pad area. This helps
dissipate the heat generated by the TLC08x IC. These additional vias may be larger than the 13-mil diameter
vias directly under the thermal pad. They can be larger because they are not in the thermal pad area to be
soldered so that wicking is not a problem.
4. Connect all holes to the internal plane that is at the same potential as the ground pin of the device.
5. When connecting these holes to this internal plane, do not use the typical web or spoke via connection
methodology. Web connections have a high thermal resistance connection that is useful for slowing the heat
transfer during soldering operations. This makes the soldering of vias that have plane connections easier. In
this application, however, low thermal resistance is desired for the most efficient heat transfer. Therefore, the
holes under the TLC08x PowerPAD package should make their connection to the internal ground plane with
a complete connection around the entire circumference of the plated-through hole.
6. The top-side solder mask should leave the terminals of the package and the thermal pad area with its five
holes (dual) or nine holes (quad) exposed. The bottom-side solder mask should cover the five or nine holes
of the thermal pad area. This prevents solder from being pulled away from the thermal pad area during the
reflow process.
7. Apply solder paste to the exposed thermal pad area and all of the IC terminals.
8. With these preparatory steps in place, the TLC08x IC is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
For a given θJA, the maximum power dissipation is shown in Figure 53 and is calculated by the following formula:
T
-
æ
A ö
T
MAX
PD=
ç
è
÷
ø
θJA
(1)
Where:
PD =
TMAX
TA =
Maximum power dissipation of TLC08x IC (watts)
Absolute maximum junction temperature (150°C)
Free-ambient air temperature (°C)
=
θJA
=
θJC + θCA
θJC = Thermal coefficient from junction to case
θCA = Thermal coefficient from case to ambient air (°C/W)
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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7
PWP Package
T
= 150°C
J
Low-K Test PCB
θ
= 29.7°C/W
JA
6
5
SOT-23 Package
Low-K Test PCB
= 324°C/W2
θ
JA
DGN Package
Low-K Test PCB
θ
= 52.3°C/W
JA
4
3
2
SOIC Package
Low-K Test PCB
θ
= 176°C/W
JA
PDIP Package
Low-K Test PCB
θ
= 104°C/W
JA
1
0
-55 -40 -25 -10
5
20 35 50 65 80 95 110 125
TA – Free-Air Temperature – °C
A. Results are with no air flow and using JEDEC Standard Low-K test PCB.
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
The next consideration is the package constraints. The two sources of heat within an amplifier are quiescent
power and output power. The designer should never forget about the quiescent heat generated within the device,
especially multi-amplifier devices. Because these devices have linear output stages (Class A-B), most of the heat
dissipation is at low output voltages with high output currents.
The other key factor when dealing with power dissipation is how the devices are mounted on the PCB. The
PowerPAD devices are extremely useful for heat dissipation. But, the device should always be soldered to a
copper plane to fully use the heat dissipation properties of the PowerPAD. The SOIC package, on the other
hand, is highly dependent on how it is mounted on the PCB. As more trace and copper area is placed around the
device, θJA decreases and the heat dissipation capability increases. The currents and voltages shown in these
graphs are for the total package. For the dual or quad amplifier packages, the sum of the RMS output currents
and voltages should be used to choose the proper package.
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
Macromodel Information
Macromodel information provided was derived using Microsim Parts™, the model generation software used with
Microsim PSpice™. The Boyle macromodel (see (1)) and subcircuit in Figure 54 are generated using the TLC08x
typical electrical and operating characteristics at TA = 25°C. Using this information, output simulations of the
following key parameters can be generated to a tolerance of 20% (in most cases):
•
•
•
•
•
•
•
•
•
•
•
•
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
(1) G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE
Journal of Solid-State Circuits, SC-9, 353 (1974).
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SLOS254F –JUNE 1999–REVISED DECEMBER 2011
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Figure 54. Boyle Macromodel and Subcircuit
24
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TLC080 , TLC081, TLC082
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www.ti.com
SLOS254F –JUNE 1999–REVISED DECEMBER 2011
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision E (April 2006) to Revision F
Page
•
Updated Figure 9 ................................................................................................................................................................ 10
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PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
PACKAGING INFORMATION
Orderable Device
TLC080AIDR
TLC080AIDRG4
TLC080AIP
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
C080AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
P
2500
50
Green (RoHS
& no Sb/Br)
C080AI
TLC080AI
TLC080AI
C080C
C080C
ACW
Pb-Free
(RoHS)
TLC080AIPE4
TLC080CD
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC080CDG4
TLC080CDGNR
TLC080CDGNRG4
TLC080CDR
D
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
DGN
DGN
D
2500
2500
2500
2500
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
ACW
SOIC
SOIC
SOIC
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
C080C
C080C
C080I
TLC080CDRG4
TLC080ID
D
Green (RoHS
& no Sb/Br)
0 to 70
D
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLC080IDG4
TLC080IDGNR
TLC080IDGNRG4
TLC080IDR
D
75
Green (RoHS
& no Sb/Br)
C080I
MSOP-
PowerPAD
DGN
DGN
D
2500
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
ACX
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ACX
SOIC
SOIC
PDIP
Green (RoHS
& no Sb/Br)
C080I
TLC080IDRG4
TLC080IP
D
Green (RoHS
& no Sb/Br)
C080I
P
Pb-Free
(RoHS)
TLC080I
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC080IPE4
TLC081AID
ACTIVE
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
P
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
50
Pb-Free
(RoHS)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC080I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
D
D
75
75
Green (RoHS
& no Sb/Br)
C081AI
C081AI
C081AI
C081AI
TLC081AI
TLC081AI
C081C
C081C
ACY
TLC081AIDG4
TLC081AIDR
TLC081AIDRG4
TLC081AIP
Green (RoHS
& no Sb/Br)
D
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
TLC081AIPE4
TLC081CD
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC081CDG4
TLC081CDGN
TLC081CDGNG4
TLC081CDGNR
TLC081CDGNRG4
TLC081CDR
D
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
80
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
0 to 70
ACY
MSOP-
PowerPAD
2500
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
ACY
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
0 to 70
ACY
SOIC
SOIC
PDIP
PDIP
SOIC
Green (RoHS
& no Sb/Br)
0 to 70
C081C
C081C
TLC081C
TLC081C
C081I
TLC081CDRG4
TLC081CP
D
Green (RoHS
& no Sb/Br)
0 to 70
P
Pb-Free
(RoHS)
0 to 70
TLC081CPE4
TLC081ID
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
-40 to 125
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC081IDG4
TLC081IDGNR
TLC081IDGNRG4
TLC081IDR
ACTIVE
SOIC
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
C081I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGN
DGN
D
2500
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
ACZ
MSOP-
PowerPAD
Green (RoHS
& no Sb/Br)
ACZ
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
Green (RoHS
& no Sb/Br)
C081I
C081I
TLC081I
TLC081I
C082AI
C082AI
C082AI
C082AI
C082AI
C082AI
C082C
C082C
ADZ
TLC081IDRG4
TLC081IP
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
TLC081IPE4
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
TLC082AID
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC082AIDG4
TLC082AIDR
TLC082AIDRG4
TLC082AIP
D
75
Green (RoHS
& no Sb/Br)
D
2500
2500
50
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
P
Pb-Free
(RoHS)
TLC082AIPE4
TLC082CD
P
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
TLC082CDG4
TLC082CDGN
TLC082CDGNG4
TLC082CDGNR
D
75
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
DGN
DGN
DGN
80
Green (RoHS
& no Sb/Br)
0 to 70
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
0 to 70
ADZ
MSOP-
2500
Green (RoHS
& no Sb/Br)
0 to 70
ADZ
PowerPAD
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC082CDGNRG4
TLC082CDR
TLC082CDRG4
TLC082CP
ACTIVE
MSOP-
PowerPAD
DGN
8
8
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
ADZ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
D
D
2500
2500
50
Green (RoHS
& no Sb/Br)
0 to 70
C082C
C082C
C082C
C082C
C082I
C082I
AEA
8
Green (RoHS
& no Sb/Br)
0 to 70
P
8
Pb-Free
(RoHS)
0 to 70
TLC082CPE4
TLC082ID
P
8
50
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
D
8
75
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLC082IDG4
TLC082IDGN
TLC082IDGNG4
TLC082IDGNR
TLC082IDGNRG4
TLC082IDR
D
8
75
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
DGN
DGN
DGN
DGN
D
8
80
Green (RoHS
& no Sb/Br)
MSOP-
PowerPAD
8
80
Green (RoHS
& no Sb/Br)
AEA
MSOP-
PowerPAD
8
2500
2500
2500
2500
50
Green (RoHS
& no Sb/Br)
AEA
MSOP-
PowerPAD
8
Green (RoHS
& no Sb/Br)
AEA
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
PDIP
8
Green (RoHS
& no Sb/Br)
C082I
C082I
C082I
C082I
C083AI
C083AI
C083AI
TLC082IDRG4
TLC082IP
D
8
Green (RoHS
& no Sb/Br)
P
8
Pb-Free
(RoHS)
TLC082IPE4
TLC083AID
P
8
50
Pb-Free
(RoHS)
N / A for Pkg Type
D
14
14
14
50
Green (RoHS
& no Sb/Br)
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC083AIDG4
TLC083AIN
D
50
Green (RoHS
& no Sb/Br)
N
25
Pb-Free
(RoHS)
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC083AINE4
ACTIVE
PDIP
N
14
25
Pb-Free
(RoHS)
CU NIPDAU
N / A for Pkg Type
-40 to 125
C083AI
TLC083CD
TLC083CDG4
TLC083CDGQR
OBSOLETE
OBSOLETE
ACTIVE
SOIC
SOIC
D
D
14
14
10
TBD
TBD
Call TI
Call TI
Call TI
Call TI
0 to 70
0 to 70
0 to 70
C083C
MSOP-
PowerPAD
DGQ
2500
2500
2500
2500
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-1-260C-UNLIM
AEB
TLC083CDGQRG4
TLC083CDR
TLC083CDRG4
TLC083CN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
MSOP-
PowerPAD
DGQ
D
10
14
14
14
14
10
10
14
14
14
14
14
14
14
14
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
N / A for Pkg Type
0 to 70
0 to 70
AEB
SOIC
SOIC
PDIP
PDIP
Green (RoHS
& no Sb/Br)
C083C
C083C
C083C
C083C
AEC
D
Green (RoHS
& no Sb/Br)
0 to 70
N
Pb-Free
(RoHS)
0 to 70
TLC083CNE4
TLC083IDGQ
TLC083IDGQG4
TLC083IN
N
25
Pb-Free
(RoHS)
0 to 70
MSOP-
PowerPAD
DGQ
DGQ
N
80
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
MSOP-
PowerPAD
80
Green (RoHS
& no Sb/Br)
AEC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
25
Pb-Free
(RoHS)
C083I
TLC083INE4
TLC084AID
N
25
Pb-Free
(RoHS)
C083I
D
50
Green (RoHS
& no Sb/Br)
TLC084AI
TLC084AI
TLC084AI
TLC084AI
TLC084AI
TLC084AI
TLC084AIDG4
TLC084AIDR
TLC084AIDRG4
TLC084AIN
D
50
Green (RoHS
& no Sb/Br)
D
2500
2500
25
Green (RoHS
& no Sb/Br)
D
Green (RoHS
& no Sb/Br)
N
Pb-Free
(RoHS)
TLC084AINE4
N
25
Pb-Free
(RoHS)
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC084AIPWP
TLC084AIPWPG4
TLC084AIPWPR
TLC084AIPWPRG4
TLC084CD
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
20
20
20
20
14
14
14
14
14
14
20
20
20
20
14
14
14
14
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC084AI
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
D
70
2000
2000
50
Green (RoHS
& no Sb/Br)
TLC084AI
TLC084AI
TLC084AI
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084C
TLC084I
TLC084I
TLC084I
TLC084I
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
TLC084CDG4
TLC084CDR
SOIC
D
50
Green (RoHS
& no Sb/Br)
0 to 70
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
0 to 70
TLC084CDRG4
TLC084CN
SOIC
D
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
N
Pb-Free
(RoHS)
0 to 70
TLC084CNE4
TLC084CPWP
TLC084CPWPG4
TLC084CPWPR
TLC084CPWPRG4
TLC084ID
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
PWP
PWP
PWP
D
70
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
0 to 70
70
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
50
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TLC084IDG4
SOIC
D
50
Green (RoHS
& no Sb/Br)
TLC084IDR
SOIC
D
2500
2500
Green (RoHS
& no Sb/Br)
TLC084IDRG4
SOIC
D
Green (RoHS
& no Sb/Br)
Addendum-Page 6
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
TLC084IPWP
TLC084IPWPG4
TLC084IPWPR
TLC084IPWPRG4
TLC085AID
ACTIVE
HTSSOP
HTSSOP
HTSSOP
HTSSOP
SOIC
PWP
20
20
20
20
16
16
16
16
16
16
20
20
16
16
16
16
20
20
70
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
TLC084I
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
PWP
PWP
PWP
D
70
2000
2000
40
Green (RoHS
& no Sb/Br)
TLC084I
Green (RoHS
& no Sb/Br)
TLC084I
Green (RoHS
& no Sb/Br)
TLC084I
Green (RoHS
& no Sb/Br)
TLC085AI
TLC085AI
TLC085AI
TLC085AI
TLC085AI
TLC085AI
TLC085AI
TLC085AI
TLC085C
TLC085C
TLC085C
TLC085C
TLC085C
TLC085C
TLC085AIDG4
TLC085AIDR
SOIC
D
40
Green (RoHS
& no Sb/Br)
SOIC
D
2500
2500
25
Green (RoHS
& no Sb/Br)
TLC085AIDRG4
TLC085AIN
SOIC
D
Green (RoHS
& no Sb/Br)
PDIP
N
Pb-Free
(RoHS)
TLC085AINE4
TLC085AIPWP
TLC085AIPWPG4
TLC085CD
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
HTSSOP
HTSSOP
SOIC
PWP
PWP
D
70
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-1-260C-UNLIM
Level-1-260C-UNLIM
N / A for Pkg Type
70
Green (RoHS
& no Sb/Br)
40
Green (RoHS
& no Sb/Br)
TLC085CDG4
TLC085CN
SOIC
D
40
Green (RoHS
& no Sb/Br)
0 to 70
PDIP
N
25
Pb-Free
(RoHS)
0 to 70
TLC085CNE4
TLC085CPWP
TLC085CPWPG4
PDIP
N
25
Pb-Free
(RoHS)
N / A for Pkg Type
0 to 70
HTSSOP
HTSSOP
PWP
PWP
70
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
0 to 70
70
Green (RoHS
& no Sb/Br)
0 to 70
Addendum-Page 7
PACKAGE OPTION ADDENDUM
www.ti.com
11-Apr-2013
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF TLC082, TLC084 :
Automotive: TLC082-Q1, TLC084-Q1
•
NOTE: Qualified Version Definitions:
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Addendum-Page 8
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TLC080AIDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLC080CDGNR
MSOP-
Power
PAD
DGN
TLC080CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLC080IDGNR
MSOP-
Power
PAD
DGN
TLC080IDR
TLC081AIDR
TLC081CDGNR
SOIC
SOIC
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
5.3
5.2
5.2
3.4
2.1
2.1
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
MSOP-
Power
PAD
DGN
TLC081CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLC081IDGNR
MSOP-
Power
PAD
DGN
TLC081IDR
TLC082AIDR
TLC082CDGNR
SOIC
SOIC
D
D
8
8
8
2500
2500
2500
330.0
330.0
330.0
12.4
12.4
12.4
6.4
6.4
5.3
5.2
5.2
3.4
2.1
2.1
1.4
8.0
8.0
8.0
12.0
12.0
12.0
Q1
Q1
Q1
MSOP-
Power
DGN
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
PAD
TLC082CDR
SOIC
D
8
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLC082IDGNR
MSOP-
Power
PAD
DGN
TLC082IDR
SOIC
D
8
2500
2500
330.0
330.0
12.4
12.4
6.4
5.3
5.2
3.4
2.1
1.4
8.0
8.0
12.0
12.0
Q1
Q1
TLC083CDGQR
MSOP-
Power
PAD
DGQ
10
TLC083CDR
TLC084AIDR
TLC084AIPWPR
TLC084CDR
SOIC
SOIC
D
D
14
14
20
14
20
14
20
16
2500
2500
2000
2500
2000
2500
2000
2500
330.0
330.0
330.0
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
16.4
16.4
16.4
6.5
6.5
9.0
9.0
7.1
9.0
7.1
9.0
7.1
10.3
2.1
2.1
1.6
2.1
1.6
2.1
1.6
2.1
8.0
8.0
8.0
8.0
8.0
8.0
8.0
8.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Q1
Q1
Q1
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
HTSSOP PWP
SOIC
6.95
6.5
D
TLC084CPWPR
TLC084IDR
6.95
6.5
D
TLC084IPWPR
TLC085AIDR
6.95
6.5
D
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SOIC
SPQ
2500
Length (mm) Width (mm) Height (mm)
340.5 338.1 20.6
TLC080AIDR
D
8
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
5-Jul-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TLC080CDGNR
TLC080CDR
TLC080IDGNR
TLC080IDR
MSOP-PowerPAD
SOIC
DGN
D
8
8
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2500
2000
2500
2000
2500
2000
2500
358.0
340.5
358.0
340.5
340.5
358.0
340.5
358.0
340.5
340.5
358.0
340.5
358.0
340.5
358.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
335.0
338.1
335.0
338.1
338.1
335.0
338.1
335.0
338.1
338.1
335.0
338.1
335.0
338.1
335.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
35.0
20.6
35.0
20.6
20.6
35.0
20.6
35.0
20.6
20.6
35.0
20.6
35.0
20.6
35.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
38.0
MSOP-PowerPAD
SOIC
DGN
D
8
8
TLC081AIDR
TLC081CDGNR
TLC081CDR
TLC081IDGNR
TLC081IDR
SOIC
D
8
MSOP-PowerPAD
SOIC
DGN
D
8
8
MSOP-PowerPAD
SOIC
DGN
D
8
8
TLC082AIDR
TLC082CDGNR
TLC082CDR
TLC082IDGNR
TLC082IDR
SOIC
D
8
MSOP-PowerPAD
SOIC
DGN
D
8
8
MSOP-PowerPAD
SOIC
DGN
D
8
8
TLC083CDGQR
TLC083CDR
TLC084AIDR
TLC084AIPWPR
TLC084CDR
TLC084CPWPR
TLC084IDR
MSOP-PowerPAD
SOIC
DGQ
D
10
14
14
20
14
20
14
20
16
SOIC
D
HTSSOP
SOIC
PWP
D
HTSSOP
SOIC
PWP
D
TLC084IPWPR
TLC085AIDR
HTSSOP
SOIC
PWP
D
Pack Materials-Page 3
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