TMS27C256-10JL [ROCHESTER]
UVPROM, 32KX8, 100ns, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28;
| 型号： | TMS27C256-10JL |
| 厂家： | 
Rochester Electronics |
| 描述： | UVPROM, 32KX8, 100ns, CMOS, CDIP28, 0.600 INCH, SIDE BRAZED, CERAMIC, DIP-28 可编程只读存储器 CD 内存集成电路 |
| 文件： | 总13页 (文件大小：206K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
D
D
D
Organization . . . 32768 by 8 Bits
Single 5-V Power Supply
J PACKAGE
(TOP VIEW)
Pin Compatible With Existing 256K MOS
ROMs, PROMs, and EPROMs
V
A12
A7
A6
A5
A4
A3
A2
A1
A0
DQ0
DQ1
DQ2
GND
V
CC
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PP
A14
A13
A8
A9
A11
G
2
D
All Inputs /Outputs Fully TTL Compatible
Max Access/Min Cycle Time
3
D
4
V
10%
5
CC
6
’27C/PC256-10
’27C/PC256-12
’27C/PC256-15
’27C/PC256-17
’27C/PC256-20
’27C/PC256-25
100 ns
120 ns
150 ns
170 ns
200 ns
250 ns
7
A10
E
8
9
DQ7
DQ6
DQ5
DQ4
DQ3
10
11
12
13
14
D
D
Power Saving CMOS Technology
Very High-Speed SNAP! Pulse
Programming
D
3-State Output Buffers
FM PACKAGE
(TOP VIEW)
D
400-mV Minimum DC Noise Immunity With
Standard TTL Loads
D
D
Latchup Immunity of 250 mA on All Input
and Output Lines
4
3 2 1 32 31 30
Low Power Dissipation (V
= 5.5 V)
CC
5
6
7
8
9
29
A6
A5
A4
A3
A2
A1
A0
NC
A8
A9
A11
− Active . . . 165 mW Worst Case
− Standby . . . 1.4 mW Worst Case
(CMOS Input Levels)
28
27
26 NC
D
D
Temperature Range Options
G
A10
E
DQ7
DQ6
25
24
23
22
21
256K EPROM Available With MIL-STD-883C
Class B High Reliability Processing
(SMJ27C256)
10
11
12
13
DQ0
description
14 15 16 17 18 19 20
The TMS27C256 series are 32768 by 8-bit
(262144-bit), ultraviolet (UV) light erasable,
electrically programmable read-only memories
(EPROMs).
PIN NOMENCLATURE
The TMS27PC256 series are 32768 by 8-bit
(262144-bit), one-time programmmable (OTP)
electrically programmable read-only memories
(PROMs).
A0−A14
DQ0−DQ7
E
G
GND
NC
NU
Address Inputs
Inputs (programming)/Outputs
Chip Enable/Powerdown
Output Enable
Ground
No Internal Connection
Make No External Connection
5-V Power Supply
V
CC
V
PP
†
13-V Power Supply
†
Only in program mode
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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Copyright 1997, Texas Instruments Incorporated
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1
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
description (continued)
These devices are fabricated using power-saving CMOS technology for high speed and simple interface with
MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits
without the use of external pull-up resistors. Each output can drive one Series 74 TTL circuit without external
resistors.
The data outputs are 3-state for connecting multiple devices to a common bus. The TMS27C256 and the
TMS27PC256 are pin compatible with 28-pin 256K MOS ROMs, PROMs, and EPROMs.
The TMS27C256 EPROM is offered in a dual-in-line ceramic package (J suffix) designed for insertion in
mounting-hole rows on 15,2-mm (600-mil) centers. The TMS27PC256 OTP PROM is supplied in a 32-lead
plastic leaded chip-carrier package using 1,25-mm (50-mil) lead spacing (FM suffix).
The TMS27C256 and TMS27PC256 are offered with two choices of temperature ranges of 0°C to 70°C (JL and
FML suffixes) and − 40°C to 85°C (JE and FME suffixes). See Table 1.
All package styles conform to JEDEC standards.
Table 1. Temperature Range Suffixes
SUFFIX FOR OPERATING
EPROM
FREE-AIR TEMPERATURE RANGES
AND
OTP PROM
0°C TO 70°C
− 40°C TO 85°C
TMS27C512-xxx
TMS27PC512-xxx
JL
JE
FML
FME
These EPROMs and OTP PROMs operate from a single 5-V supply (in the read mode), thus are ideal for use
in microprocessor-based systems. One other 13-V supply is needed for programming . All programming signals
are TTL level. These devices are programmable by the SNAP! Pulse programming algorithm. The SNAP! Pulse
programming algorithm uses a V of 13 V and a V
of 6.5 V for a nominal programming time of four seconds.
PP
CC
For programming outside the system, existing EPROM programmers can be used. Locations can be
programmed singly, in blocks, or at random.
2
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁꢂ ꢃ ꢄ ꢔꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊ ꢋ ꢉꢌ ꢊ ꢍꢀ
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
operation
The seven modes of operation are listed in Table 2. The read mode requires a single 5-V supply. All inputs are
TTL level except for V during programming (13 V for SNAP! Pulse), and 12 V on A9 for the signature mode.
PP
Table 2. Operation Modes
†
MODE
FUNCTION
OUTPUT
DISABLE
PROGRAM
INHIBIT
SIGNATURE
MODE
READ
STANDBY PROGRAMMING
VERIFY
E
V
V
V
V
V
V
V
V
V
IL
IL
IH
IL
IH
IH
IL
G
V
IH
X
V
IH
V
X
IL
IL
IL
V
V
V
V
V
V
V
V
V
PP
CC
CC
CC
PP
PP
PP
CC
CC
V
CC
V
CC
X
V
CC
X
V
CC
X
V
CC
X
V
CC
X
V
CC
X
A9
A0
V ‡
V ‡
H
H
X
X
X
X
X
X
V
IL
V
IH
CODE
MFG
97
DEVICE
04
DQ0−DQ7
Data Out
Hi-Z
Hi-Z
Data In
Data Out
Hi-Z
†
‡
X can be V or V
IL IH
H
.
V
= 12 V 0.5 V.
read/output disable
When the outputs of two or more TMS27C256s or TMS27PC256s are connected in parallel on the same bus,
the output of any particular device in the circuit can be read with no interference from the competing outputs
of the other devices. To read the output of a single device, a low-level signal is applied to the E and G pins. All
other devices in the circuit should have their outputs disabled by applying a high-level signal to one of these
pins. Output data is accessed at pins DQ0 through DQ7.
latchup immunity
Latchup immunity on the TMS27C256 and TMS27PC256 is a minimum of 250 mA on all inputs and outputs.
This feature provides latchup immunity beyond any potential transients at the P.C. board level when the devices
are interfaced to industry-standard TTL or MOS logic devices. Input-output layout approach controls latchup
without compromising performance or packing density.
power down
Active I
supply current can be reduced from 30 mA to 500 µA (TTL-level inputs) or 250 µA (CMOS-level
CC
inputs) by applying a high TTL or CMOS signal to the E pin. In this mode all outputs are in the high-impedance
state.
erasure (TMS27C256)
Before programming, the TMS27C256 EPROM is erased by exposing the chip through the transparent lid
to a high intensity ultraviolet light (wavelength 2537 Å). EPROM erasure before programming is necessary to
assure that all bits are in the logic high state. Logic lows are programmed into the desired locations. A
programmed logic low can be erased only by ultraviolet light. The recommended minimum exposure dose (UV
2
2
intensity × exposure time) is 15-W•s/cm . A typical 12-mW/cm , filterless UV lamp erases the device in 21
minutes. The lamp should be located about 2.5 cm above the chip during erasure. It should be noted that normal
ambient light contains the correct wavelength for erasure. Therefore, when using the TMS27C256, the window
should be covered with an opaque label.
3
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
initializing (TMS27PC256)
The one-time programmable TMS27PC256 PROM is provided with all bits in the logic high state, then logic lows
are programmed into the desired locations. Logic lows programmed into an OTP PROM cannot be erased.
SNAP! Pulse programming
The 256K EPROM and OTP PROM are programmed using the TI SNAP! Pulse programming algorithm
illustrated by the flowchart in Figure 1, which programs in a nominal time of four seconds. Actual programming
time varies as a function of the programmer used.
Data is presented in parallel (eight bits) on pins DQ0 to DQ7. Once addresses and data are stable, E is pulsed.
The SNAP! Pulse programming algorithm uses initial pulses of 100 microseconds (µs) followed by a byte
verification to determine when the addressed byte has been successfully programmed. Up to 10 (ten) 100-µs
pulses per byte are provided before a failure is recognized.
The programming mode is achieved when V = 13 V, V
= 6.5 V, G = V , and E = V . More than one device
IH IL
PP
CC
can be programmed when the devices are connected in parallel. Locations can be programmed in any order.
When the SNAP! Pulse programming routine is complete, all bits are verified with V = V = 5 V.
CC
PP
program inhibit
Programming can be inhibited by maintaining a high level input on the E pin.
program verify
Programmed bits can be verified with V = 13 V when G = V and E = V .
PP
IL
IH
signature mode
The signature mode provides access to a binary code identifying the manufacturer and type. This mode is
activated when A9 is forced to 12 V. Two identifier bytes are accessed by toggling A0. All other addresses must
be held low. The signature code for these devices is 9704. A0 selects the manufacturer’s code 97 (Hex), and
A0 high selects the device code 04, as shown in Table 3.
Table 3. Signature Mode
PINS
†
IDENTIFIER
A0
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
HEX
97
MANUFACTURER CODE
DEVICE CODE
V
1
0
0
0
0
0
1
0
0
0
1
1
1
0
1
0
IL
V
IH
04
†
E = G = V , A9 = V , A1−A8 = V , A10−A15 = V , V
IL IL IL PP
= V , PGM = V or V .
CC IH IL
H
4
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢀ ꢁꢂ ꢃ ꢄ ꢔꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊ ꢋ ꢉꢌ ꢊ ꢍꢀ
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
Start
Address = First Location
Program
Mode
V
CC
= 6.5 V, V
= 13 V
PP
Program One Pulse = t = 100 µs
Increment Address
w
No
Last
Address?
Yes
Address = First Location
X = 0
Program One Pulse = t = 100 µs
w
No
Fail
Increment
Address
Verify
One Byte
X = X + 1
X = 10?
Interactive
Mode
Pass
No
Last
Address?
Yes
Yes
Device Failed
V
CC
= V = 5 V 10%
PP
Compare
All Bytes
To Original
Data
Fail
Final
Verification
Pass
Device Passed
Figure 1. SNAP! Pulse Programming Flowchart
5
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
†
logic symbol
EPROM
32 768 × 8
OTP PROM
32 768 × 8
10
9
8
7
6
5
4
3
25
24
21
23
2
10
9
8
7
6
5
4
3
25
24
21
23
2
0
0
A0
A1
A2
A3
A4
A5
A6
A7
A8
A0
A1
A2
A3
A4
A5
A6
A7
A8
11
12
13
15
16
17
18
19
11
12
13
15
16
17
18
19
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
0
0
A
A
32 767
32 767
A9
A9
A10
A11
A12
A13
A14
A10
A11
A12
A13
A14
26
27
26
27
14
14
20
22
20
22
[PWR DWN]
[PWR DWN]
E
E
&
&
EN
EN
G
G
†
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for J package.
‡
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
(see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 7 V
CC
Supply voltage range, V : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 14 V
PP
Input voltage range (see Note 1): All inputs except A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V
+ 1 V
CC
A9 : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to 13.5 V
Output voltage range (see Note 1) : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.6 V to V + 1 V
CC
Operating free-air temperature range (’27C256-_ _JL, ’27PC256-_ _FML) T : . . . . . . . . . . . . . . 0°C to 70°C
A
Operating free-air temperature range (’27C5256-_ _JE, ’27PC256-_ _FME) T : . . . . . . . . . . . −40°C to 85°C
A
Storage temperature range, T : . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65°C to 150°C
stg
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: All voltage values are with respect to GND.
6
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ꢀ ꢁꢂ ꢃ ꢄ ꢔꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊ ꢋ ꢉꢌ ꢊ ꢍꢀ
ꢔ
ꢑꢕ ꢖ ꢑꢒꢁ ꢁ ꢒꢊꢓ ꢐ ꢑꢐꢒ ꢗꢌꢕ ꢘꢓꢋ ꢁ ꢐꢁ ꢕ ꢑ ꢍ ꢐꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
recommended operating conditions
MIN
4.5
NOM
5
MAX
5.5
UNIT
Read mode (see Note 2)
V
V
V
V
Supply voltage
V
CC
PP
IH
SNAP! Pulse programming algorithm
6.25
6.5
6.75
Read mode
V
−0.6
V
+0.6
CC
13.25
CC
Supply voltage
V
V
SNAP! Pulse programming algorithm
12.75
2
13
TTL
V
V
+1
+1
CC
High-level dc input voltage
CMOS
TTL
V
− 0.2
CC
− 0.5
CC
0.8
0.2
Low-level dc input voltage
V
IL
CMOS
− 0.5
’27C256-_ _JL
’27PC256-_ _FML
T
Operating free-air temperature
Operating free-air temperature
0
70
85
°C
°C
A
’27C256-_ _JE
’27PC256-_ _FME
T
A
− 40
NOTE 2:
V
must be applied before or at the same time as V
PP
and removed after or at the same time as V . The device must not be inserted
PP
CC
into or removed from the board when V
or V
is applied.
PP
CC
electrical characteristics over recommended ranges of operating conditions
†
PARAMETER
TEST CONDITIONS
= − 2.5 mA
MIN
TYP
MAX
UNIT
I
I
I
I
3.5
OH
OH
OL
OL
V
V
High-level dc output voltage
V
OH
= − 20 µA
= 2.1 mA
= 20 µA
V
− 0.1
CC
0.4
0.1
1
Low-level dc output voltage
V
OL
I
I
I
I
Input current (leakage)
Output current (leakage)
V = 0 V to 5.5 V
µA
µA
µA
mA
I
I
V
V
V
V
V
V
= 0 V to V
CC
1
O
O
V
supply current
= V
CC
= 5.5 V
1
10
50
500
250
PP1
PP2
PP
PP
PP
PP
CC
CC
V
supply current (during program pulse)
= 13 V
35
250
100
TTL-input level
= 5.5 V,
= 5.5 V,
= 5.5 V,
E = V
E = V
E = V
V
supply current
IH
CC
I
µA
CC1
CC2
(standby)
CMOS-input level
CC
,
IL
CC
I
V
CC
supply current (active)
t
= minimum cycle time,
outputs open
15
30
mA
cycle
capacitance over recommended ranges of supply voltage and operating free-air temperature,
†
f = 1 MHz
‡
PARAMETER
Input capacitance
Output capacitance
TEST CONDITIONS
V = 0, f = 1 MHz
= 0, f = 1 MHz
MIN TYP
MAX
10
UNIT
pF
C
C
6
i
I
V
O
10
14
pF
o
†
‡
Capacitance measurements are made on a sample basis only.
Typical values are at T = 25°C and nominal voltages.
A
7
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢀ
ꢁ
ꢁ
ꢂ
ꢂ
ꢃ
ꢃ
ꢄ
ꢄ
ꢅ
ꢃ
ꢆ
ꢃ
ꢇ
ꢆ
ꢈ
ꢇ
ꢃ
ꢈ
ꢄ
ꢃ
ꢇ
ꢄ
ꢉ
ꢇ
ꢊ
ꢋ
ꢋ
ꢉ
ꢌ
ꢉ
ꢊ
ꢍ
ꢀ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢒ
ꢊ
ꢓ
ꢐ
ꢔ
ꢅ
ꢉ
ꢊ
ꢌ
ꢊ
ꢍ
ꢀ
ꢔ
ꢑ
ꢕ
ꢖ
ꢑ
ꢒ
ꢁ
ꢁ
ꢒ
ꢊ
ꢓ
ꢐ
ꢑ
ꢐ
ꢒ
ꢗ
ꢌ
ꢕ
ꢘ
ꢓꢋ
ꢁ
ꢐ
ꢁ
ꢕ
ꢑ
ꢍ
ꢐ
ꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
switching characteristics over recommended range of operating conditions
’27C256-10
’27PC256-10
’27C256-12
’27PC256-12
’27C256-15
’27PC256-15
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
UNIT
MIN MAX
MIN
MAX MIN
MAX
150
150
75
t
t
t
Access time from address
100
100
55
120
120
55
ns
ns
ns
a(A)
Access time from chip enable
Output enable time from G
a(E)
C
= 100 pF,
L
en(G)
1 Series 74 TTL Load,
Output disable time from G or E, whichever
occurs first
Input t ≤ 20 ns,
r
t
0
0
45
0
0
45
0
0
60
ns
ns
dis
†
Input t ≤ 20 ns
f
Output data valid time after change of
address, E, or G, whichever occurs first
t
v(A)
†
’27C256-17
’27PC256-17
’27C256-20
’27PC256-20
’27C256-25
’27PC256-25
TEST CONDITIONS
(SEE NOTES 3 AND 4)
PARAMETER
UNIT
MIN
MAX
170
170
75
MIN
MAX
200
200
75
MIN
MAX
250
250
100
t
t
t
Access time from address
Access time from chip enable
Output enable time from G
ns
ns
ns
a(A)
a(E)
C
= 100 pF,
L
en(G)
1 Series 74 TTL Load,
Input t ≤ 20 ns,
Output disable time from G or E, whichever
occurs first
r
t
0
0
60
0
0
60
0
0
60
ns
ns
dis
†
Input t ≤ 20 ns
f
Output data valid time after change of
address, E, or G, whichever occurs first
t
v(A)
†
†
Value calculated from 0.5 V delta to measured level. This parameter is only sampled and not 100% tested.
NOTES: 3. For all switching characteristics the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low) (see Figure 2).
4. Common test conditions apply for the t
dis
except during programming.
switching characteristics for programming: V
(see Note 3)
= 6.50 V and V = 13 V (SNAP! Pulse), T = 25°C
PP A
CC
PARAMETER
MIN
MAX
UNIT
ns
t
t
Output disable time from G
Output enable time from G
0
130
150
dis(G)
ns
en(G)
NOTE 3: For all switching characteristics, the input pulse levels are 0.4 V to 2.4 V. Timing measurements are made at 2 V for logic high and
0.8 V for logic low).
timing requirements for programming
MIN NOM
MAX
UNIT
µs
t
t
t
t
t
t
t
t
t
Hold time, address
Hold time, data
0
2
h(A)
µs
h(D)
Pulse duration, initial program
Setup time, address
Setup time, G
95
2
100
105
µs
w(IPGM)
su(A)
µs
2
µs
su(G)
Setup time, E
2
µs
su(E)
Setup time, data
2
µs
su(D)
Setup time, V
Setup time, V
2
µs
su(VPP)
su(VCC)
PP
2
µs
CC
8
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊꢋ ꢉ ꢌꢊꢍ ꢀ ꢎꢏ ꢐ ꢑꢒ ꢂ ꢒꢊ ꢓꢐ
ꢀ ꢁꢂ ꢃ ꢄ ꢔꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊ ꢋ ꢉꢌ ꢊ ꢍꢀ
ꢔ
ꢑꢕ ꢖ ꢑꢒꢁ ꢁ ꢒꢊꢓ ꢐ ꢑꢐꢒ ꢗꢌꢕ ꢘꢓꢋ ꢁ ꢐꢁ ꢕ ꢑ ꢍ ꢐꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
2.08 V
R
C
= 800 Ω
L
L
Output
Under Test
= 100 pF
(see Note A)
NOTE A: C includes probe and fixture capacitance.
L
ac testing input/output wave forms
2.4 V
0.4 V
2 V
2 V
0.8 V
0.8 V
AC testing inputs are driven at 2.4 V for logic high and 0.4 V for logic low. Timing measurements are made at
2 V for logic high and 0.8 V for logic low for both inputs and outputs.
Figure 2. AC Testing Output Load Circuit
V
V
IH
A0−A14
Addresses Valid
IL
V
V
IH
E
IL
t
a(E)
t
V
V
IH
G
IL
t
dis
en(G)
t
v(A)
t
a(A)
V
V
OH
DQ0−DQ7
Output Valid
Hi-Z
Hi-Z
OL
Figure 3. Read-Cycle Timing
9
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢃ
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ꢃ
ꢆ
ꢃ
ꢇ
ꢆ
ꢈ
ꢇ
ꢃ
ꢈ
ꢄ
ꢃ
ꢇ
ꢄ
ꢉ
ꢇ
ꢊ
ꢋ
ꢋ
ꢉ
ꢌ
ꢉ
ꢊ
ꢍ
ꢀ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢒ
ꢊ
ꢓ
ꢐ
ꢔ
ꢅ
ꢉ
ꢊ
ꢌ
ꢊ
ꢍ
ꢀ
ꢔ
ꢑ
ꢕ
ꢖ
ꢑ
ꢒ
ꢁ
ꢁ
ꢒ
ꢊ
ꢓ
ꢐ
ꢑ
ꢐ
ꢒ
ꢗ
ꢌ
ꢕ
ꢘ
ꢓꢋ
ꢁ
ꢐ
ꢁ
ꢕ
ꢑ
ꢍ
ꢐ
ꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
PARAMETER MEASUREMENT INFORMATION
Program
Verify
V
V
IH
Address
N+1
Address Stable
A0−A14
IL
t
t
h(A)
su(A)
V / V
IH OH
DQ0−DQ7
Hi-Z
Data-In Stable
Data-Out Valid
V / V
IL OH
t
†
t
dis(G)
su(D)
V
V
‡
PP
V
PP
CC
t
su(VPP)
V
V
‡
CC
V
CC
t
t
CC
su(VCC)
su(E)
t
h(D)
V
V
IH
E
t
†
en(G)
IL
t
t
w(IPGM)
su(G)
V
V
IH
G
IL
†
‡
t
and t
en(G)
are characteristics of the device but must be accommodated by the programmer
for SNAP! Pulse programming
dis(G)
13-V V
and 6.5-V V
PP
CC
Figure 4. Program-Cycle Timing (SNAP! Pulse Programming)
10
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
ꢀ
ꢁꢂ ꢃ ꢄ ꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊꢋ ꢉ ꢌꢊꢍ ꢀ ꢎꢏ ꢐ ꢑꢒ ꢂ ꢒꢊ ꢓꢐ
ꢀ ꢁꢂ ꢃ ꢄ ꢔꢅꢃ ꢆ ꢇ ꢈ ꢃ ꢄ ꢇ ꢉ ꢊ ꢋ ꢉꢌ ꢊ ꢍꢀ
ꢔ
ꢑꢕ ꢖ ꢑꢒꢁ ꢁ ꢒꢊꢓ ꢐ ꢑꢐꢒ ꢗꢌꢕ ꢘꢓꢋ ꢁ ꢐꢁ ꢕ ꢑ ꢍ ꢐꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
FM (R-PQCC-J32)
PLASTIC J-LEADED CHIP CARRIER
Seating Plane
0.004 (0,10)
0.140 (3,56)
0.132 (3,35)
0.495 (12,57)
0.485 (12,32)
0.129 (3,28)
0.123 (3,12)
0.453 (11,51)
0.447 (11,35)
0.049 (1,24)
0.043 (1,09)
0.008 (0,20) NOM
1
30
4
29
5
0.020 (0,51)
0.015 (0,38)
0.595 (15,11)
0.585 (14,86)
0.553 (14,05)
0.547 (13,89)
0.030 (0,76)
TYP
21
13
14
20
0.050 (1,27)
4040201-4/B 03/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-016
11
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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ꢃ
ꢇ
ꢆ
ꢈ
ꢇ
ꢃ
ꢈ
ꢄ
ꢃ
ꢇ
ꢄ
ꢉ
ꢇ
ꢊ
ꢋ
ꢋ
ꢉ
ꢌ
ꢉ
ꢊ
ꢍ
ꢀ
ꢎ
ꢏ
ꢐ
ꢑ
ꢒ
ꢂ
ꢒ
ꢊ
ꢓ
ꢐ
ꢔ
ꢅ
ꢉ
ꢊ
ꢌ
ꢊ
ꢍ
ꢀ
ꢔ
ꢑ
ꢕ
ꢖ
ꢑ
ꢒ
ꢁ
ꢁ
ꢒ
ꢊ
ꢓ
ꢐ
ꢑ
ꢐ
ꢒ
ꢗ
ꢌ
ꢕ
ꢘ
ꢓꢋ
ꢁ
ꢐ
ꢁ
ꢕ
ꢑ
ꢍ
ꢐ
ꢂ
SMLS256H− SEPTEMBER 1984 − REVISED NOVEMBER 1997
J (R-CDIP-T**)
CERAMIC SIDE-BRAZE DUAL-IN-LINE PACKAGE
24 PIN SHOWN
B
13
24
C
12
1
Lens Protrusion
0.010 (0,25) MAX
0.065 (1,65)
0.045 (1,14)
0.090 (2,29)
0.060 (1,53)
0.175 (4,45)
A
0.140 (3,56)
0.018 (0,46) MIN
Seating Plane
0°−ā10°
0.125 (3,18) MIN
0.022 (0,56)
0.014 (0,36)
0.100 (2,54)
0.012 (0,30)
0.008 (0,20)
PINS**
24
28
32
40
DIM
NARR
WIDE
NARR
WIDE
NARR
WIDE
NARR
WIDE
0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85) 0.624(15,85)
0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99) 0.590(14,99)
1.265(32,13) 1.265(32,13) 1.465(37,21) 1.465(37,21) 1.668(42,37) 1.668(42,37) 2.068(52,53) 2.068(52,53)
1.235(31,37) 1.235(31,37) 1.435(36,45) 1.435(36,45) 1.632(41,45) 1.632(41,45) 2.032(51,61) 2.032(51,61)
0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19) 0.541(13,74) 0.598(15,19)
0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50) 0.514(13,06) 0.571(14,50)
MAX
MIN
MAX
MIN
MAX
MIN
A
B
C
4040084/B 04/95
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. This package can be hermetically sealed with a ceramic lid using glass frit.
D. Index point is provided on cap for terminal identification only on press ceramic glass frit seal only.
12
POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251−1443
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相关型号：
TMS27C256-150JE
TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
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TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES
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