TPS78625DCQ [ROCHESTER]
2.5V FIXED POSITIVE LDO REGULATOR, PDSO6, GREEN, PLASTIC, SOT-223, 6 PIN;
| 型号： | TPS78625DCQ |
| 厂家： | 
Rochester Electronics |
| 描述： | 2.5V FIXED POSITIVE LDO REGULATOR, PDSO6, GREEN, PLASTIC, SOT-223, 6 PIN 信息通信管理 光电二极管 输出元件 调节器 |
| 文件： | 总30页 (文件大小：1910K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
ULTRALOW-NOISE, HIGH-PSRR, FAST, RF, 1.5-A
LOW-DROPOUT LINEAR REGULATORS
Check for Samples: TPS786xx
1
FEATURES
DESCRIPTION
234
•
1.5-A Low-Dropout Regulator With Enable
The TPS786xx family of low-dropout (LDO)
low-power linear voltage regulators features high
power-supply rejection ratio (PSRR), ultralow noise,
fast start-up, and excellent line and load transient
responses in small outline, SOT223-6 and DDPAK-5
packages. Each device in the family is stable, with a
small 1-mF ceramic capacitor on the output. The
family uses an advanced, proprietary BiCMOS
fabrication process to yield extremely low dropout
voltages (for example, 390 mV at 1.5 A). Each device
achieves fast start-up times (approximately 50 ms with
a 0.001-mF bypass capacitor) while consuming very
low quiescent current (265 mA, typical). Moreover,
when the device is placed in standby mode, the
supply current is reduced to less than 1 mA. The
TPS78630 exhibits approximately 48 mVRMS of output
voltage at 3.0-V output noise with a 0.1-mF bypass
capacitor. Applications with analog components that
are noise sensitive, such as portable RF electronics,
benefit from the high PSRR, low noise features, and
the fast response time.
•
Available in Fixed and Adjustable (1.2-V to
5.5-V) Output Versions
•
•
•
•
•
•
High PSRR (49 dB at 10 kHz)
Ultralow Noise (48 mVRMS, TPS78630)
Fast Start-Up Time (50 ms)
Stable With a 1-mF Ceramic Capacitor
Excellent Load/Line Transient Response
Very Low Dropout Voltage (390 mV at Full
Load, TPS78630)
•
3 × 3 SON PowerPAD™, 6-Pin SOT223 and
5-Pin DDPAK Package
APPLICATIONS
•
•
•
•
•
RF: VCOs, Receivers, ADCs
Audio
Bluetooth® , Wireless LAN
Cellular and Cordless Telephones
Handheld Organizers, PDAs
DRB PACKAGE
3mm x 3mm SON
(TOP VIEW)
TPS78630
TPS78630
RIPPLE REJECTION
vs
OUTPUT SPECTRAL NOISE DENSITY
vs
DCQ PACKAGE
SOT223-6
(TOP VIEW)
IN
IN
1
2
3
4
8
7
6
5
EN
FREQUENCY
FREQUENCY
NC
80
70
60
50
40
30
20
10
0
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0.0
OUT
OUT
GND
NR/FB
V
= 4 V
V
= 5.5 V
IN
IN
1
2
3
4
EN
IN
C
OUT
= 10 mF
C
OUT
= 2.2 mF
I
= 1 mA
= 1.5 A
C
NR
= 0.01 mF
OUT
C
NR
= 0.1 mF
6
GND
OUT
GND
I
5
OUT
NR/FB
KTT (DDPAK) PACKAGE
(TOP VIEW)
I
= 1 mA
OUT
EN
1
2
IN
GND
I
= 1.5 A
OUT
3
4
OUT
1
10
100
1k
10k 100k 1M 10M
100
1k
10k
100k
NR/FB
Frequency (Hz)
5
Frequency (Hz)
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2
3
4
PowerPAD is a trademark of Texas Instruments Inc.
Bluetooth is a registered trademark of Bluetooth SIG, Inc.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2002–2010, Texas Instruments Incorporated
TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION(1)
(2)
PRODUCT
VOUT
TPS786xx yyy z
XX is nominal output voltage (for example, 28 = 2.8 V, 285 = 2.85 V, 01 = Adjustable).
YYY is package designator.
Z is package quantity.
(1) For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Output voltages from 1.3 V to 5.0 V in 100-mV increments are available; minimum order quantities may apply. Contact factory for details
and availability.
ABSOLUTE MAXIMUM RATINGS
Over operating temperature (unless otherwise noted)(1)
VALUE
VIN range
–0.3 V to 6 V
–0.3 V to VIN + 0.3 V
6 V
VEN range
VOUT range
Peak output current
ESD rating, HBM
Internally limited
2 kV
ESD rating, CDM
500 V
Continuous total power dissipation
Junction temperature range, TJ
Storage temperature range, Tstg
See Thermal Information table
–40°C to +150°C
–65°C to +150°C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
2
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Product Folder Link(s): TPS786xx
TPS786xx
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
THERMAL INFORMATION
TPS786xx(3)
THERMAL METRIC(1)(2)
DRB
8 PINS
47.8
83
DCQ
6 PINS
70.4
70
KTT
5 PINS
25
UNITS
qJA
Junction-to-ambient thermal resistance(4)
Junction-to-case (top) thermal resistance(5)
Junction-to-board thermal resistance(6)
Junction-to-top characterization parameter(7)
Junction-to-board characterization parameter(8)
Junction-to-case (bottom) thermal resistance(9)
qJCtop
qJB
35
N/A
N/A
N/A
1.5
°C/W
yJT
2.1
6.8
yJB
17.8
12.1
30.1
6.3
8.52
0.4
qJCbot
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953A.
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.
(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as
specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through
ii. DCQ: The exposed pad is connected to the PCB ground layer through
a
a
2x2 thermal via array.
3x2 thermal via array.
.
. iii. KTT: The exposed pad is connected to the PCB ground layer through a 5x4 thermal via array.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
. iii. KTT: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper
coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To
understand the effects of the copper area on thermal performance, see the Power Dissipation and Estimating Junction Temperature
sections of this data sheet.
(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as
specified in JESD51-7, in an environment described in JESD51-2a.
(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific
JEDEC-standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB
temperature, as described in JESD51-8.
(7) The junction-to-top characterization parameter, yJT, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(8) The junction-to-board characterization parameter, yJB, estimates the junction temperature of a device in a real system and is extracted
from the simulation data to obtain qJA using a procedure described in JESD51-2a (sections 6 and 7).
(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.
Copyright © 2002–2010, Texas Instruments Incorporated
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
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ELECTRICAL CHARACTERISTICS
Over recommended operating temperature range (TJ = –40°C to +125°C), VEN = VIN, VIN = VOUT(nom) + 1 V(1), IOUT = 1 mA,
COUT = 10 mF, and CNR = 0.01 mF, unless otherwise noted. Typical values are at +25°C.
PARAMETER
TEST CONDITIONS
MIN
2.7
TYP
MAX
5.5
UNIT
(1)
Input voltage, VIN
V
V
A
V
V
Internal reference, VFB (TPS78601)
Continuous output current IOUT
1.200
1.225
1.250
0
1.5
Output voltage range TPS78601
1.225
5.5 – VDO
TPS78601(2) 0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1)
(0.98)VOUT
VOUT (1.02)VOUT
+2.0
Output
voltage
Fixed VOUT
< 5 V
0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1)
–2.0
–3.0
%
%
Accuracy
Fixed VOUT
= 5 V
0 mA ≤ IOUT ≤ 1.5 A, VOUT + 1 V ≤ VIN ≤ 5.5 V(1)
+3.0
(1)
Output voltage line regulation (ΔVOUT%/VIN
)
VOUT + 1 V ≤ VIN ≤ 5.5 V
0 mA ≤ IOUT ≤ 1.5 A
IOUT = 1.5 A
5
7
12
%/V
mV
Load regulation (ΔVOUT%/VOUT
)
TPS78628
TPS78630
TPS78633
TPS78650
410
390
340
310
580
550
510
470
4.2
385
1
Dropout voltage(3)
VIN = VOUT(nom) – 0.1 V
IOUT = 1.5 A
mV
IOUT = 1.5 A
IOUT = 1.5 A
Output current limit
Ground pin current
Shutdown current(4)
FB pin current
VOUT = 0 V
2.4
A
0 mA ≤ IOUT ≤ 1.5 A
VEN = 0 V, 2.7 V ≤ VIN ≤ 5.5 V
VFB = 1.225 V
260
mA
mA
mA
0.07
1
f = 100 Hz, IOUT = 10 mA
f = 100 Hz, IOUT = 1.5 A
f = 10 kHz, IOUT = 1.5 A
f = 100 kHz, IOUT = 1.5 A
59
52
49
32
66
51
49
48
50
75
110
Power-supply ripple rejection
TPS78630
dB
CNR = 0.001 mF
CNR = 0.0047 mF
CNR = 0.01 mF
CNR = 0.1 mF
BW = 100 Hz to 100 kHz,
IOUT = 1.5 A
Output noise voltage (TPS78630)
Time, start-up (TPS78630)
mVRMS
CNR = 0.001 mF
CNR = 0.0047 mF
CNR = 0.01 mF
RL = 2 Ω, COUT = 1 mF
ms
High-level enable input voltage
Low-level enable input voltage
EN pin current
2.7 V ≤ VIN ≤ 5.5 V
2.7 V ≤ VIN ≤ 5.5 V
VEN = 0
1.7
0
VIN
0.7
1
V
V
–1
mA
V
UVLO threshold
VCC rising
2.25
2.65
UVLO hysteresis
100
mV
(1) Minimum VIN = VOUT + VDO or 2.7 V, whichever is greater. The TPS78650 is tested at VIN = 5.5 V.
(2) Tolerance of external resistors not included in this specification.
(3) Dropout is not measured for TPS78618 or TPS78625 since minimum VIN = 2.7 V.
(4) For adjustable version, this applies only after VIN is applied; then VEN transitions high to low.
4
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TPS786xx
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
FUNCTIONAL BLOCK DIAGRAM—ADJUSTABLE VERSION
IN
OUT
Ω
300
Current
Sense
UVLO
Overshoot
Detect
GND
EN
ILIM
SHUTDOWN
R1
R2
FB
UVLO
Thermal
Shutdown
Quickstart
External to
the Device
Bandgap
Reference
1.225 V
VREF
VIN
Ω
250 k
FUNCTIONAL BLOCK DIAGRAM—FIXED VERSION
IN
OUT
Ω
300
Current
Sense
UVLO
Overshoot
Detect
GND
EN
ILIM
SHUTDOWN
R1
R2
UVLO
Thermal
Shutdown
Ω
R2 = 40 k
Quickstart
Bandgap
Reference
1.225 V
VREF
VIN
NR
Ω
250 k
PIN CONFIGURATIONS
TERMINAL
KTT
DCQ
DRB
NAME
(SOT223)
(DDPAK)
(SON)
DESCRIPTION
Noise-reduction pin for fixed versions only. An external bypass capacitor, connected to this terminal, in
conjunction with an internal resistor, creates a low-pass filter to further reduce regulator noise.
NR
5
5
5
8
The EN terminal is an input that enables or shuts down the device. When EN is a logic high, the device
is enabled. When the device is a logic low, the device is in shutdown mode.
EN
1
1
FB
GND
IN
5
3, 6
2
5
5
Feedback input voltage for the adjustable device.
Regulator ground
3, TAB
6
2
4
1, 2
3, 4
Input supply
OUT
4
Regulator output
Copyright © 2002–2010, Texas Instruments Incorporated
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
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TYPICAL CHARACTERISTICS
TPS78630
TPS78628
TPS78628
OUTPUT VOLTAGE
OUTPUT VOLTAGE
GROUND CURRENT
vs
vs
vs
OUTPUT CURRENT
JUNCTION TEMPERATURE
JUNCTION TEMPERATURE
2.798
3.05
3.04
3.03
3.02
3.01
3.00
2.99
2.98
2.97
2.96
2.95
350
340
330
320
310
300
290
V
C
= 4 V
= 10 µF
OUT
= 25°C
V
C
= 3.8 V
V
= 3.8 V
IN
IN
IN
= 10 µF
C
OUT
= 10 µF
OUT
2.794
T
J
I
= 1 mA
OUT
2.790
I
= 1.5 A
OUT
2.786
I
= 1.5 A
OUT
I
= 1 mA
OUT
2.782
2.778
0.0
0.3
0.6
0.9
(A)
1.2
1.5
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
I
T
J
T
J
OUT
Figure 1.
Figure 2.
Figure 3.
TPS78630
TPS78630
TPS78630
OUTPUT SPECTRAL
NOISE DENSITY
OUTPUT SPECTRAL
NOISE DENSITY
OUTPUT SPECTRAL
NOISE DENSITY
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
0.6
0.5
0.4
0.3
0.2
0.1
0.0
3.0
2.5
2.0
1.5
1.0
0.5
0.0
0.80
0.70
0.60
0.50
0.40
0.30
0.20
0.10
0.00
V
C
C
= 5.5 V
V
C
C
= 5.5 V
V
= 5.5 V
IN
= 10 µF
OUT
= 1.5 A
IN
IN
= 2.2 µF
= 10 µF
C
I
OUT
= 0.1 µF
OUT
= 0.1 µF
NR
NR
OUT
I
= 1.5 A
OUT
C
NR
= 0.1 µF
C
NR
= 0.0047 µF
I
= 1 mA
C
NR
= 0.01 µF
OUT
C
= 0.001 µF
NR
I
= 1 mA
OUT
I
= 1.5 A
OUT
100
1k
10k
100k
100
1k
10k
100k
100
1k
10k
100k
Frequency (Hz)
Frequency (Hz)
Frequency (Hz)
Figure 4.
Figure 5.
Figure 6.
6
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS78630
ROOT MEAN SQUARED
TPS78628
TPS78630
OUTPUT NOISE
vs
DROPOUT VOLTAGE
vs
RIPPLE REJECTION
vs
BYPASS CAPACITANCE
JUNCTION TEMPERATURE
FREQUENCY
80
70
60
50
40
30
20
600
500
400
300
200
100
0
80
70
60
50
40
30
20
10
0
V
C
C
= 4 V
V
C
= 2.7 V
= 10 µF
OUT
= 1.5 A
IN
IN
= 10 µF
OUT
= 0.01 µF
I
= 1 mA
I
OUT
NR
OUT
I
= 1.5 A
OUT
I
C
= 1.5 A
= 10 µF
OUT
10
0
OUT
BW = 100 Hz to 100 kHz
0.001 µF
0.0047 µF
0.01 µF
(µF)
0.1 µF
−40−25−10
5
20 35 50 65 80 95 110 125
(°C)
1
10
100
1k 10k 100k 1M 10M
C
NR
f (Hz)
T
J
Figure 7.
Figure 8.
Figure 9.
TPS78630
TPS78630
TPS78630
RIPPLE REJECTION
RIPPLE REJECTION
RIPPLE REJECTION
vs
vs
vs
FREQUENCY
FREQUENCY
FREQUENCY
80
80
70
60
50
40
30
20
10
80
70
60
50
40
30
20
10
0
V
= 4 V
V
C
C
= 4 V
V
C
C
= 4 V
IN
= 2.2 µF
OUT
= 0.01 µF
NR
IN
IN
70
60
50
40
30
20
10
0
C
C
= 2.2 µF
= 10 µF
OUT
= 0.1 µF
OUT
= 0.1 µF
I
= 1 mA
I
= 1 mA
I
= 1 mA
= 1.5 A
OUT
OUT
OUT
NR
NR
I
OUT
I
= 1.5 A
OUT
I
= 1.5 A
OUT
0
1
1
10
100
1k 10k 100k 1M 10M
10
100
1k 10k 100k 1M 10M
1
10
100
1k 10k 100k 1M 10M
f (Hz)
f (Hz)
f (Hz)
Figure 10.
Figure 11.
Figure 12.
TPS78618
TPS78630
TPS78628
LINE TRANSIENT RESPONSE
LINE TRANSIENT RESPONSE
LOAD TRANSIENT RESPONSE
5
4
3
2
2
1
0
6
5
4
3
V
C
C
= 3.8 V
I
C
C
= 1.5 A
IN
di
dt
dv
dt
OUT
1.5 A
ms
1 V
ms
dv
dt
1 V
ms
−1
I
C
C
= 1.5 A
= 10 µF
OUT
= 0.01 µF
OUT
+
+
+
= 10 µF
= 10 µF
OUT
= 0.01 µF
OUT
= 0.01 µF
NR
NR
60
30
150
75
80
40
NR
0
0
0
−30
−60
−75
−150
−40
−80
0
20 40 60 80 100 120 140 160 180 200
0
100 200 300 400 500 600 700 800 900 1000
0
20 40 60 80 100 120 140 160 180 200
t (µs)
t (µs)
t (µs)
Figure 13.
Figure 14.
Figure 15.
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TYPICAL CHARACTERISTICS (continued)
TPS78630
TPS78601
TPS78625
POWER-UP/
POWER-DOWN
DROPOUT VOLTAGE
DROPOUT VOLTAGE
vs
vs
OUTPUT CURRENT
INPUT VOLTAGE
600
500
400
300
200
100
0
4.0
3.5
3.0
2.5
500
450
400
350
300
250
200
150
100
50
V
R
C
= 2.5 V
= 1.6 Ω
= 0.01 µF
OUT
L
NR
T
= 125°C
J
T
= 125°C
J
T
J
= 25°C
T
J
= 25°C
2.0
1.5
1.0
0.5
0
T
= −40°C
J
V
IN
T
J
= −40°C
I
C
C
= 1.5 A
= 10 µF
OUT
= 0.01 µF
OUT
V
OUT
NR
0
0
200 400 600 800 1000 1200 1400
(mA)
0
400
800
1200
1600
2000
2.5
3.0
3.5
4.0
(V)
4.5
5.0
I
V
Time (µs)
OUT
IN
Figure 16.
Figure 17.
Figure 18.
TPS78630
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE
(ESR)
MINIMUM REQUIRED
INPUT VOLTAGE
vs
vs
vs
OUTPUT VOLTAGE
OUTPUT CURRENT
OUTPUT CURRENT
100
10
5.0
100
10
I
= 1.5 A
OUT
C
OUT
= 1 µF
C
OUT
= 2.2 µF
4.5
4.0
3.5
3.0
2.5
2.0
Region of
Instability
Region of
Instability
T
= +125°C
J
1
0.1
1
0.1
T
J
= +25°C
Region of Stability
Region of Stability
0.01
0.01
1
30
125
500
(mA)
1000
1500
1.5
2.0
2.5
3.0
3.5
4.0
1
30
125
500
(mA)
1000
1500
I
I
OUT
OUT
V
(V)
OUT
Figure 19.
Figure 20.
Figure 21.
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Product Folder Link(s): TPS786xx
TPS786xx
www.ti.com
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
TYPICAL CHARACTERISTICS (continued)
TPS78630
TYPICAL REGIONS OF STABILITY
EQUIVALENT SERIES RESISTANCE (ESR)
vs
OUTPUT CURRENT
START-UP
100
3
V
C
= 4 V,
IN
C
OUT
= 10 µF
2.75
2.50
2.25
2
C
=
NR
= 10 µF,
OUT
0.0047 µF
I
= 1.5 A
IN
Region of
Instability
10
Enable
C
=
NR
0.001 µF
1.75
1.50
1.25
1
1
0.1
C
=
NR
0.01 µF
Region of Stability
0.75
0.50
0.25
0
0.01
0
100
200
300
400
500
600
1
30
125
500
(mA)
1000
1500
t (µs)
I
OUT
Figure 22.
Figure 23.
Copyright © 2002–2010, Texas Instruments Incorporated
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TPS786xx
SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
APPLICATION INFORMATION
order for the regulator to operate properly, the current
flow out of the NR pin must be at a minimum,
because any leakage current creates an IR drop
across the internal resistor, thus creating an output
error. Therefore, the bypass capacitor must have
minimal leakage current. The bypass capacitor
should be no more than 0.1-mF to ensure that it is
fully charged during the quickstart time provided by
the internal switch shown in the functional block
diagram.
The TPS786xx family of low-dropout (LDO) regulators
has been optimized for use in noise-sensitive
equipment. The device features extremely low
dropout voltages, high PSRR, ultralow output noise,
low quiescent current (265 mA, typically), and enable
input to reduce supply currents to less than 1 mA
when the regulator is turned off.
A typical application circuit is shown in Figure 24.
VIN
VOUT
For example, the TPS78630 exhibits only 48 mVRMS
of output voltage noise using a 0.1-mF ceramic
IN
OUT
TPS786xx
GND
2.2 mF
2.2 mF
bypass capacitor and
a 10-mF ceramic output
EN
NR
capacitor. Note that the output starts up slower as the
bypass capacitance increases due to the RC time
constant at the bypass pin that is created by the
internal 250-kΩ resistor and external capacitor.
0.01 mF
Figure 24. Typical Application Circuit
BOARD LAYOUT RECOMMENDATIONS TO
IMPROVE PSRR AND NOISE PERFORMANCE
EXTERNAL CAPACITOR REQUIREMENTS
To improve ac measurements like PSRR, output
noise, and transient response, it is recommended that
the board be designed with separate ground planes
for VIN and VOUT, with each ground plane connected
only at the ground pin of the device. In addition, the
ground connection for the bypass capacitor should
connect directly to the ground pin of the device.
A 2.2-mF or larger ceramic input bypass capacitor,
connected between IN and GND and located close to
the TPS786xx, is required for stability and improves
transient response, noise rejection, and ripple
rejection. A higher-value input capacitor may be
necessary if large, fast-rise-time load transients are
anticipated and the device is located several inches
from the power source.
REGULATOR MOUNTING
Like most low-dropout regulators, the TPS786xx
requires an output capacitor connected between OUT
and GND to stabilize the internal control loop. The
minimum recommended capacitor is 1 mF. Any 1 mF
or larger ceramic capacitor is suitable.
The tab of the SOT223-6 package is electrically
connected to ground. For best thermal performance,
the tab of the surface-mount version should be
soldered directly to a circuit-board copper area.
Increasing the copper area improves heat dissipation.
The internal voltage reference is a key source of
noise in an LDO regulator. The TPS786xx has an NR
pin which is connected to the voltage reference
through a 250-kΩ internal resistor. The 250-kΩ
internal resistor, in conjunction with an external
bypass capacitor connected to the NR pin, creates a
low pass filter to reduce the voltage reference noise
and, therefore, the noise at the regulator output. In
Solder pad footprint recommendations for the devices
are presented in Application Report SBFA015, Solder
Pad Recommendations for Surface-Mount Devices,
available from the TI web site at www.ti.com.
10
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TPS786xx
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
PROGRAMMING THE TPS78601
ADJUSTABLE LDO REGULATOR
The approximate value of this capacitor can be
calculated using Equation 3:
−7
(3 x 10 ) x (R ) R )
1
2
The output voltage of the TPS78601 adjustable
regulator is programmed using an external resistor
divider as shown in Figure 25. The output voltage is
calculated using Equation 1:
C
+
1
(R x R )
1
2
(3)
The suggested value of this capacitor for several
resistor ratios is shown in the table below. If this
capacitor is not used (such as in a unity-gain
configuration), then the minimum recommended
output capacitor is 2.2 mF instead of 1 mF.
R
ǒ Ǔ
1
V
+ V
1 )
OUT
REF
R
2
(1)
where:
REGULATOR PROTECTION
•
VREF = 1.2246 V typ (the internal reference
voltage)
The TPS786xx PMOS-pass transistor has a built-in
back diode that conducts reverse current when the
input voltage drops below the output voltage (for
example, during power down). Current is conducted
from the output to the input and is not internally
limited. If extended reverse voltage operation is
anticipated, external limiting might be appropriate.
Resistors R1 and R2 should be chosen for
approximately 40-mA divider current. Lower value
resistors can be used for improved noise
performance, but the device wastes more power.
Higher values should be avoided, as leakage current
at FB increases the output voltage error.
The TPS786xx features internal current limiting and
thermal protection. During normal operation, the
TPS786xx limits output current to approximately
2.8 A. When current limiting engages, the output
voltage scales back linearly until the overcurrent
condition ends. While current limiting is designed to
prevent gross device failure, care should be taken not
to exceed the power dissipation ratings of the
package. If the temperature of the device exceeds
approximately +165°C, thermal-protection circuitry
shuts it down. Once the device has cooled down to
below approximately +140°C, regulator operation
resumes.
The recommended design procedure is to choose
R2 = 30.1 kΩ to set the divider current at 40 mA,
C1 = 15 pF for stability, and then calculate R1 using
Equation 2:
V
ǒ Ǔ
OUT
R +
* 1 R
1
2
V
REF
(2)
In order to improve the stability of the adjustable
version, it is suggested that a small compensation
capacitor be placed between OUT and FB.
OUTPUT VOLTAGE
PROGRAMMING GUIDE
VIN
VOUT
IN
OUT
TPS78601
OUTPUT
VOLTAGE
R1
C1
EN
R1
R2
C1
2.2 mF
2.2 mF
GND
FB
1.8 V
3.6 V
14.0 kW
30.1 kW
33 pF
R2
57.9 kW
30.1 kW
15 pF
Figure 25. TPS78601 Adjustable LDO Regulator Programming
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
THERMAL INFORMATION
Knowing the maximum RqJA, the minimum amount of
PCB copper area needed for appropriate heatsinking
can be estimated using Figure 26.
POWER DISSIPATION
Knowing the device power dissipation and proper
sizing of the thermal plane that is connected to the
tab or pad is critical to avoiding thermal shutdown
and ensuring reliable operation.
160
DCQ
140
DRB
Power dissipation of the device depends on input
voltage and load conditions and can be calculated
using Equation 4:
KTT
120
100
80
60
40
20
0
ǒ
Ǔ
PD + VIN * VOUT IOUT
(4)
Power dissipation can be minimized and greater
efficiency can be achieved by using the lowest
possible input voltage necessary to achieve the
required output voltage regulation.
On the SON (DRB) package, the primary conduction
path for heat is through the exposed pad to the
printed circuit board (PCB). The pad can be
connected to ground or be left floating; however, it
should be attached to an appropriate amount of
copper PCB area to ensure the device does not
overheat. On both SOT-223 (DCQ) and DDPAK
(KTT) packages, the primary conduction path for heat
is through the tab to the PCB. That tab should be
4
5
7
0
1
2
3
6
8
9
10
Board Copper Area (in2)
Note: qJA value at board size of 9in2 (that is, 3in ×
3in) is a JEDEC standard.
Figure 26. qJA vs Board Size
Figure 26 shows the variation of qJA as a function of
ground plane copper area in the board. It is intended
only as a guideline to demonstrate the effects of heat
spreading in the ground plane and should not be
used to estimate actual thermal performance in real
application environments.
connected
to
ground.
The
maximum
junction-to-ambient thermal resistance depends on
the maximum ambient temperature, maximum device
junction temperature, and power dissipation of the
device and can be calculated using Equation 5:
O
(
)125 C * TA
+
)
NOTE: When the device is mounted on an
application PCB, it is strongly recommended to use
ΨJT and ΨJB, as explained in the Estimating Junction
Temperature section.
R
qJA
PD
(5)
12
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
ESTIMATING JUNCTION TEMPERATURE
35
30
25
20
15
10
5
Using the thermal metrics ΨJT and ΨJB, as shown in
the Thermal Information table, the junction
temperature can be estimated with corresponding
formulas (given in Equation 6). For backwards
compatibility, an older qJC,Top parameter is listed as
well.
DCQ
YJB
DRB
KTT
YJT: TJ = TT + YJT · PD
YJB: TJ = TB + YJB · PD
(6)
DCQ YJT
DRB YJT
KTT YJT
Where PD is the power dissipation shown by
Equation 5, TT is the temperature at the center-top of
the IC package, and TB is the PCB temperature
measured 1mm away from the IC package on the
PCB surface (as Figure 28 shows).
0
0
1
2
3
4
5
6
7
8
9
10
Board Copper Area (in2)
Figure 27. ΨJT and ΨJB vs Board Size
NOTE: Both TT and TB can be measured on actual
application boards using a thermo-gun (an infrared
thermometer).
For a more detailed discussion of why TI does not
recommend using qJC(top) to determine thermal
characteristics, refer to application report SBVA025,
Using New Thermal Metrics, available for download
at www.ti.com. For further information, refer to
application report SPRA953, IC Package Thermal
Metrics, also available on the TI website.
For more information about measuring TT and TB, see
the application note SBVA025, Using New Thermal
Metrics, available for download at www.ti.com.
By looking at Figure 27, the new thermal metrics (ΨJT
and ΨJB) have very little dependency on board size.
That is, using ΨJT or ΨJB with Equation 6 is a good
way to estimate TJ by simply measuring TT or TB,
regardless of the application board size.
(1)
TB
TT on top of IC
X
1mm
TT on top
of IC
TB on PCB
surface
TB on PCB
(2)
TT
surface
1mm
X
1mm
(c) Example KTT (DDPAK) Package Measurement
(a) Example DRB (SON) Package Measurement
(b) Example DCQ (SOT-223) Package Measurement
(1) TT is measured at the center of both the X- and Y-dimensional axes.
(2) TB is measured below the package lead on the PCB surface.
Figure 28. Measuring Points for TT and TB
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SLVS389L –SEPTEMBER 2002–REVISED OCTOBER 2010
www.ti.com
REVISION HISTORY
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision K (August, 2010) to Revision L
Page
•
Corrected typo in Figure 28 ................................................................................................................................................ 13
Changes from Revision J (May, 2009) to Revision K
Page
•
•
Replaced the Dissipation Ratings table with the Thermal Information Table ....................................................................... 3
Revised Thermal Information section ................................................................................................................................. 12
14
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PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS78601DCQ
ACTIVE
SOT-223
DCQ
6
78
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
-40 to 125
PS78601
TPS78601DCQG4
TPS78601DCQR
ACTIVE
ACTIVE
SOT-223
SOT-223
DCQ
DCQ
6
6
TBD
Call TI
CU SN
Call TI
-40 to 125
-40 to 125
2500
2500
3000
250
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
PS78601
PS78601
OCI
TPS78601DCQRG4
TPS78601DRBR
TPS78601DRBT
TPS78601KTT
ACTIVE
ACTIVE
ACTIVE
SOT-223
SON
DCQ
DRB
DRB
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
6
8
8
5
5
5
5
5
6
6
6
6
5
5
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Green (RoHS
& no Sb/Br)
SON
Green (RoHS
& no Sb/Br)
OCI
OBSOLETE DDPAK/
TO-263
TBD
TPS78601KTTR
TPS78601KTTRG3
TPS78601KTTT
TPS78601KTTTG3
TPS78618DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
78601
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78601
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS
78601
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
78601
SOT-223
SOT-223
SOT-223
SOT-223
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
PS78618
PS78618
PS78618
PS78618
TPS78618DCQG4
TPS78618DCQR
TPS78618DCQRG4
TPS78618KTT
78
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
TPS78618KTTR
ACTIVE
DDPAK/
TO-263
500
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
TPS
78618
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS78618KTTRE3
TPS78618KTTRG3
TPS78618KTTT
TPS78618KTTTG3
TPS78625DCQ
ACTIVE
DDPAK/
TO-263
KTT
5
5
5
5
6
6
6
6
5
5
5
5
5
6
6
5
5
5
500
Green (RoHS
& no Sb/Br)
CU SN
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
78618
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
DCQ
DCQ
KTT
KTT
KTT
500
50
Green (RoHS
& no Sb/Br)
TPS
78618
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS
78618
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
78618
SOT-223
SOT-223
SOT-223
SOT-223
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
PS78625
PS78625
PS78625
PS78625
TPS78625DCQG4
TPS78625DCQR
TPS78625DCQRG4
TPS78625KTT
78
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
TPS78625KTTR
TPS78625KTTRG3
TPS78625KTTT
TPS78625KTTTG3
TPS78628DCQR
TPS78628DCQRG4
TPS78628KTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
78625
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78625
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
TPS
78625
DDPAK/
TO-263
50
Green (RoHS
& no Sb/Br)
CU SN
TPS
78625
SOT-223
2500
2500
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Call TI
PS78628
SOT-223
Green (RoHS
& no Sb/Br)
PS78628
OBSOLETE DDPAK/
TO-263
TBD
TPS78628KTTT
TPS78628KTTTG3
ACTIVE
DDPAK/
TO-263
50
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
78628
ACTIVE
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78628
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
-40 to 125
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
TPS78630DCQ
TPS78630DCQG4
TPS78630DCQR
TPS78630DCQRG4
TPS78630KTT
ACTIVE
SOT-223
SOT-223
SOT-223
SOT-223
DCQ
6
6
6
6
5
5
5
6
6
6
6
5
5
5
5
5
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
PS78630
ACTIVE
ACTIVE
ACTIVE
DCQ
DCQ
DCQ
KTT
KTT
KTT
DCQ
DCQ
DCQ
DCQ
KTT
KTT
KTT
KTT
KTT
78
Green (RoHS
& no Sb/Br)
PS78630
PS78630
PS78630
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
TPS78630KTTT
TPS78630KTTTG3
TPS78633DCQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
50
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Call TI
TPS
78630
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78630
SOT-223
SOT-223
SOT-223
SOT-223
78
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
Call TI
PS78633
PS78633
PS78633
PS78633
TPS78633DCQG4
TPS78633DCQR
TPS78633DCQRG4
TPS78633KTT
78
Green (RoHS
& no Sb/Br)
2500
2500
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
OBSOLETE DDPAK/
TO-263
TBD
TPS78633KTTR
TPS78633KTTRE3
TPS78633KTTRG3
TPS78633KTTT
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DDPAK/
TO-263
500
500
500
50
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
TPS
78633
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78633
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
TPS
78633
DDPAK/
TO-263
Green (RoHS
& no Sb/Br)
CU SN
-40 to 125
TPS
78633
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
18-Jul-2013
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 4
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS78601DCQRG4
TPS78601DRBR
TPS78601DRBT
TPS78601KTTT
SOT-223 DCQ
6
8
8
5
2500
3000
250
50
330.0
330.0
180.0
330.0
12.4
12.4
12.4
24.4
7.05
3.3
7.45
3.3
1.88
1.1
1.1
4.9
8.0
8.0
12.0
12.0
12.0
24.0
Q3
Q2
Q2
Q2
SON
SON
DRB
DRB
KTT
3.3
3.3
8.0
DDPAK/
TO-263
10.6
15.6
16.0
TPS78618DCQR
TPS78618KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
KTT
KTT
10.6
15.6
16.0
TPS78618KTTRE3
TPS78618KTTT
DDPAK/
TO-263
5
5
500
50
330.0
330.0
24.4
24.4
10.6
10.6
15.6
15.6
4.9
4.9
16.0
16.0
24.0
24.0
Q2
Q2
DDPAK/
TO-263
TPS78625DCQR
TPS78625KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
10.6
15.6
16.0
TPS78625KTTT
DDPAK/
TO-263
KTT
5
50
330.0
24.4
10.6
15.6
4.9
16.0
24.0
Q2
TPS78628DCQR
TPS78628KTTT
SOT-223 DCQ
6
5
2500
50
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
10.6
15.6
16.0
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS78630DCQR
TPS78630KTTT
SOT-223 DCQ
6
5
2500
50
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
10.6
15.6
16.0
TPS78633DCQR
TPS78633KTTR
SOT-223 DCQ
6
5
2500
500
330.0
330.0
12.4
24.4
6.8
7.3
1.88
4.9
8.0
12.0
24.0
Q3
Q2
DDPAK/
TO-263
KTT
KTT
KTT
10.6
15.6
16.0
TPS78633KTTRE3
TPS78633KTTT
DDPAK/
TO-263
5
5
500
50
330.0
330.0
24.4
24.4
10.6
10.6
15.6
15.6
4.9
4.9
16.0
16.0
24.0
24.0
Q2
Q2
DDPAK/
TO-263
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS78601DCQRG4
TPS78601DRBR
TPS78601DRBT
TPS78601KTTT
TPS78618DCQR
TPS78618KTTR
TPS78618KTTRE3
TPS78618KTTT
SOT-223
SON
DCQ
DRB
DRB
KTT
DCQ
KTT
KTT
KTT
6
8
8
5
6
5
5
5
2500
3000
250
50
358.0
367.0
210.0
367.0
358.0
367.0
367.0
367.0
335.0
367.0
185.0
367.0
335.0
367.0
367.0
367.0
35.0
35.0
35.0
45.0
35.0
45.0
45.0
45.0
SON
DDPAK/TO-263
SOT-223
2500
500
500
50
DDPAK/TO-263
DDPAK/TO-263
DDPAK/TO-263
Pack Materials-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
26-Mar-2013
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPS78625DCQR
TPS78625KTTR
TPS78625KTTT
TPS78628DCQR
TPS78628KTTT
TPS78630DCQR
TPS78630KTTT
TPS78633DCQR
TPS78633KTTR
TPS78633KTTRE3
TPS78633KTTT
SOT-223
DDPAK/TO-263
DDPAK/TO-263
SOT-223
DCQ
KTT
KTT
DCQ
KTT
DCQ
KTT
DCQ
KTT
KTT
KTT
6
5
5
6
5
6
5
6
5
5
5
2500
500
50
358.0
367.0
367.0
358.0
367.0
358.0
367.0
358.0
367.0
367.0
367.0
335.0
367.0
367.0
335.0
367.0
335.0
367.0
335.0
367.0
367.0
367.0
35.0
45.0
45.0
35.0
45.0
35.0
45.0
35.0
45.0
45.0
45.0
2500
50
DDPAK/TO-263
SOT-223
2500
50
DDPAK/TO-263
SOT-223
2500
500
500
50
DDPAK/TO-263
DDPAK/TO-263
DDPAK/TO-263
Pack Materials-Page 3
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