TVP3703-135CFN [ROCHESTER]
1600X1280 PIXELS PALETTE-DAC DSPL CTLR, PQCC68, PLASTIC, LCC-68;
| 型号： | TVP3703-135CFN |
| 厂家： | 
Rochester Electronics |
| 描述： | 1600X1280 PIXELS PALETTE-DAC DSPL CTLR, PQCC68, PLASTIC, LCC-68 外围集成电路 |
| 文件： | 总23页 (文件大小：1002K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
• Fully Integrated Dual Clock Synthesizer
• On-Chip PLL Clock Reference Requires
and 16-Bit Pixel Port True-Color RAMDAC
Single External Crystal
• Two Phase-Locked-Loop (PLL)
Synthesizers Provide Independently
Controlled Video and Memory Clock
Outputs
• 16-Bit Pixel Port Supports VGA High-Color
and True-Color Standards Up to 170 MHz
• Programmable Power-Down Features
• On-Chip Cyclic Redundancy Check (CRC)
• Functionally Interchangeable with STG1703
Test
description
The TVP3703 is a super video graphics array (SVGA) compatible, true-color CMOS RAMDAC with integrated
clock synthesizers that can provide the memory and pixel clock signals for a PC graphics subsystem. The video
clock can be one of two VGA base frequencies or fourteen Video Electronics Standards Association (VESA)
standard frequencies which can also be reprogrammed through the standard micro port interface.
The memory clock output is also user programmable at frequencies up to 80 MHz. The pixel modes supported
by the TVP3703 include:
•
Serializing 16-bit pixel port providing 170 MHz, 8-bit and 73 MHz, 24-bit packed pixel modes using an
internal PLL
•
•
16-bit pixel port providing faster, high-color/true-color operation up to the 110 MHz sampling rate
8-bit pixel port providing standard SVGA and high-color/true-color modes up to the 110 MHz sampling rate
The 68 terminal FN package is designed to be interchangeable with the STG1703.
FN PACKAGE
(TOP VIEW)
9
8
7
6 5 4 3 2 1 68 67 66 65 64 63 62 61
GND
BLANK
D0
10
60 GND
59 P7
11
12
13
14
15
16
17
58
P6
P5
P4
P3
P2
P1
P0
REF
RS2
COMP
RSET
VS3
VS2
VS1
VS0
D1
D2
D3
D4
57
56
55
54
53
52
51
50
49
48
47
46
45
44
D5
D6 18
D7 19
WR 20
21
22
23
24
25
26
RS0
RS1
P14
PIXMIX
P15
NC
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
NC – No internal connection
Copyright 1996, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
applications
•
Screen resolutions (noninterlaced)
–
–
–
–
–
1600 × 1280, 8-bit/pixel, 60 Hz
1280 × 1024, 16-bit/pixel, 60 Hz
1024 × 768, 16-bit/pixel, 85 Hz
1024 × 768, 24-bit/pixel, packed, 70 Hz
800 × 600, 24-bit/pixel, unpacked, 72 Hz
•
True-color desktop, PC add-in cards
functional block diagram
MCLK
XIN
XOUT
VCLK
Crystal
Oscillator
MCLK
PLL
VCLK
PLL
D0–D7
RD
MCLK
Registers
VCLK
Registers
WR
Micro Port
RS0-RS2
VS0-VS3
STROBE
24
DAC
256×8 Bit
RED
Color Palette
DAC
DAC
PIXMIX
Pixel
256×8 Bit
Color Palette
Multiplexor
Mask
Latches
P0–P15
GREEN
BLUE
256×8 Bit
Color Palette
3
Pipeline
Timing
Internal
REF
DAC
Control
DAC
Comparators
PCLK
REF
BLANK
RSET
COMP SENSE
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
Terminal Functions
micro port
TERMINAL
I/O
DESCRIPTION
NAME
NO.
5,
I
Read enable and write enable. RD or WR control the timing of read and write operations on the micro port.
RD,
20
WR
Most of the operations on the micro port can take place asynchronously to the pixel stream being processed
by the color palette. Various minimum periods between operations are specified (in terms of pixel clocks) to
allow this asynchronous behavior.
RD and WR should not be low at the same time.
RS0–RS2
21, 22,
50
I
Registerselect. RS0–RS2 specify which internal register is to be accessed. The RS0–RS2inputsaresampled
on the falling edge of the active enable signal (RD or WR). Information on register access and contents is given
in the micro port section.
The additional RS2 signal allows access to the extended features without the need for performing an indirect
access sequence.
D0–D7
12–19
I/O Input/outputdata. Datatransfersbetweenthe8-bitwideprogramdatabusandtheregisterswithintheTVP3703
under control of the active enable signal (RD or WR).
In a write cycle, the rising edge of WR validates the data on the program data bus and causes it to be written
to the register selected.
The rising edge of RD signifies the end of a read cycle, after which the program data bus ceases to carry the
contents of the register addressed and goes to a high impedance state.
VS0–VS3
STROBE
44–47
43
I
I
Video clock PLL select.VS0–VS3 select the frequency (default or user programmed) of the video clock PLL.
VS0–VS3 are ignored if the video clock frequency is selected by register control.
Strobe input.The falling edge of STROBE latches VS0–VS3.
pixel port
TERMINAL
I/O
DESCRIPTION
NAME
NO.
PCLK
63
I
Pixel clock. The rising edge of PCLK controls the sampling of data on P0–P15, BLANK, and PIXMIX in all
modes.
P0–P15
1, 4, 23,
25,
I
Pixel data word. The selected pixel mode determines how this pixel data is interpreted.
52–59,
64–67
PIXMIX
BLANK
24
I
I
Pixel mode select. PIXMIX controls the switching between primary and secondary pixel modes when the
extended pixel modes are selected (PIXMIX = 0 selects primary mode).
11
Blank in. A low value sampled on BLANK, after the pipeline delay, turns the DAC outputs off.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
DAC interface
TERMINAL
I/O
DESCRIPTION
NAME
NO.
RED,
38–40
O
DAC video outputs. These signals are designed to drive a doubly terminated 75-Ω load.
GREEN,
BLUE
REF
51
48
I
I
External 1.235-V reference voltage. An external bypass capacitor should be connected from REF to GND.
RSET
AprecisionresistorplacedbetweenRSETandGNDsetsthefull-scaleDACcurrent. Therequiredresistorvalue
can be calculated from:
2.1
V
ref
R
( )
set
whereV istheexternalorinternalreferencevoltageandI istherequiredDACfull-scaleoutputcurrent. R
set
I
O
ref
O
is typically 147 Ω for VGA (see application information section).
COMP
49
68
I
External compensation capacitor connection for DACs.
SENSE
O
Sense out. SENSE is a logical 0 if one or more of the DAC outputs exceeds the internal DAC comparator trip
voltage (which is midway between the DAC full scale and GND potentials).
frequency synthesizer interface
TERMINAL
I/O
DESCRIPTION
NAME
XOUT
XIN
NO.
6
O
I
Crystal output and input connections. A series-resonant crystal must be connected between XOUT and XIN
to provide the reference clock for the PLLs.
7
VCLK
MCLK
9
O
O
Video clock PLL out
61
Memory clock PLL out
power supply
TERMINAL
I/O
DESCRIPTION
NAME
NO.
V
DD
8, 27, 35,
62
Digital power
AV
DD
3, 42
Analog power for the DACs and PLL.
Common ground rail for all circuitry.
GND
2, 10, 36,
37, 41, 60
NC
26, 28–34
No internal connection. For future upgrade to a 24-bit pixel port the controller. Outputs P16–P23 can be routed
to terminals 26, 28–34 respectively.
detailed description
micro port
The TVP3703 micro port (see Table 1) is an extension of the standard VGA micro port and powers up with a
register configuration compatible with standard and high-color VGA. There are two methods for accessing the
register set of the TVP3703 – direct register space (RS) access and indirect access.
direct RS access
This feature supports direct RS mapping to eight address locations that access the VGA color palette, pixel
command register, and an indexed register. The index low/high registers increment after every access to the
indexed register.
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POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
direct RS access (continued)
Table 1. Direct RS Micro Port Accesses
RS(2–0)
000
VGA REGISTER
Address register (palette write)
Palette color value
001
010
Pixel mask/indirect access
Address register (palette read)
Index low byte
011
100
101
Indexed register
110
Pixel command register
Index high byte
111
indirect access
The indexed register space can also be accessed by a special mechanism of successive reads to the mask
register location 2h, as shown in Table 2. Reads from RS location 2h cause a state counter to be advanced by
one. Five successive reads of RS location 2h returns the mask register contents four times followed by the pixel
command register value.
If the indexed register space is not enabled, the next access is directed to the pixel mask (state 1 in Table 2).
States 3 to 4 require three reads from the pixel mask register and, when the pixel command register is written
to enable the indexed register space, the next access is again directed to the mask register (the next state after
state 5 is state 1).
The indirect access sequence can now enter states 6 and 7 to access the lower and higher byte of the index
register respectively. Subsequent reads or writes to location 2h access the register space pointed to by the index
register. After each indexed register access, the index register increments automatically. In this way, the entire
indexed register space can be moved as a block without the need to keep writing to the index register.
At any point in the above sequence, a read or write to any location other than 2h resets the state counter to
state 1.
On power up, the indirect access is truncated through the default setting of pixel command register bit 4 so that
the TVP3703 is identified by existing video basic input/output system (BIOS) code as a fast ATT20C490
RAMDAC.
Table 2. Indirect Access Sequence
†
CURRENT STATE
NEXT STATE
READ FROM
READ FROM
RS = 2h AND INDEX
SPACE ENABLED
REGISTER MAPPED
AT RS = 2h
WRITE TO
RS = 2h
READ/WRITE TO
OTHER RS LOCATION
RS = 2h AND INDEX
SPACE DISABLED
(DEFAULT)
STATE
1
2
3
4
5
6
7
8
Pixel mask
2
3
4
5
6
7
8
2
3
4
5
1
1
1
1
1
1
7
8
1
1
1
1
1
1
1
1
Pixel mask
Pixel mask
Pixel mask
Pixel command
Index low byte
Index high byte
Indexed register
‡
8
‡
8
†
‡
Power-up state is state 1.
Increment index register after access
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
indexed register space
The TVP3703 indexed register space including the indexes, register contents, and values is shown in Table 3.
Table 3. Indexed Register Space
†
‡
†
‡
VALUE
INDEX
00 00h
INDEX REGISTER CONTENTS
VALUE
INDEX
00 34h
INDEX REGISTER CONTENTS
Company ID = 97h
VCLK V10 parameters low
VCLK V10 parameters high
VCLK V11 parameters low
VCLK V11 parameters high
VCLK V12 parameters low
VCLK V12 parameters high
VCLK V13 parameters low
VCLK V13 parameters high
VCLK V14 parameters low
VCLK V14 parameters high
VCLK V15 parameters low
VCLK V15 parameters high
MCLK M0 parameters low
MCLK M0 parameters high
MCLK M1 parameters low
MCLK M1 parameters high
MCLK M2 parameters low
MCLK M2 parameters high
MCLK M3 parameters low
MCLK M3 parameters high
Clock synthesizer control
(41h)
(0Ah)
(56h)
(48h)
(43h)
(07h)
(59h)
(28h)
(28h)
(06h)
(40h)
(08h)
(3Dh)
(28h)
(51h)
(27h)
(2Ah)
(07h)
(36h)
(08h)
(00h)
80.0
00 35h
00 36h
00 37h
00 38h
00 39h
00 3Ah
00 3Bh
00 3Ch
00 3Dh
00 3Eh
00 3Fh
00 40h
00 41h
00 42h
00 43h
00 44h
00 45h
00 46h
00 47h
00 48h
00 01h
00 02h
00 03h
00 04h
00 05h
00 06h
00 07h
00 08h
Device ID = 03h
Reserved (see Note 1)
Primary pixel mode select
Secondary pixel mode select
Pipeline timing control
Soft reset
31.50
110.0
65.0
75.0
94.50
45.0
66.0
70.0
80.0
Power management A
Power management B
00 09h –
00 1Fh
Reserved (see Note 1)
00 20h
00 21h
00 22h
00 23h
00 24h
00 25h
00 26h
00 27h
00 28h
00 29h
00 2Ah
VCLK V0 parameters low
VCLK V0 parameters high
VCLK V1 parameters low
VCLK V1 parameters high
VCLK V2 parameters low
VCLK V2 parameters high
VCLK V3 parameters low
VCLK V3 parameters high
VCLK V4 parameters low
VCLK V4 parameters high
VCLK V5 parameters low
(3Dh)
(47h)
(55h)
(49h)
(41h)
(2Ah)
(26h)
(06h)
(36h)
(26h)
(29h)
25.175
28.332
40.0
72.0
50.0
00 49h –
FF D5h
77.0
Reserved (see Note 1)
00 2Bh
00 2Ch
00 2Dh
00 2Eh
00 2Fh
00 30h
00 31h
00 32h
00 33h
VCLK V5 parameters high
VCLK V6 parameters low
VCLK V6 parameters high
VCLK V7 parameters low
VCLK V7 parameters high
VCLK V8 parameters low
VCLK V8 parameters high
VCLK V9 parameters low
VCLK V9 parameters high
(06h)
(26h)
(26h)
(43h)
(29h)
(59h)
(08h)
(41h)
(06h)
FF D6h
FF D7h
FF D8h
CRC Test
36.0
CRC low byte
CRC high byte
44.90
130.00
120.00
Red, green, blue (RGB) DAC input
data test
FF D9h
FF DAh –
FF FFh
Reserved (see Note 1)
†
‡
Register power-up values for given synthesizer frequencies are shown in parentheses.
Synthesizer frequencies given for f = 14.31818 MHz
I(XIN)
NOTE 1: Do not write to reserved locations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
register content descriptions
A write to any register containing reserved bits should always write 0s to the reserved bits (the exception being
bit 7 of power management register A). On reads, all reserved bits should be masked out.
The values of register bits that are reset on power-up are listed in the reset value columns below.
PIXEL COMMAND REGISTER (RS0–RS2 = 110)
PIXEL MODE SELECT REGISTERS
(Primary and Secondary) (Indexes 0003h, 0004h)
RESET
VALUE
BIT VALUE
FUNCTION
MAX
MAX
PCLK
(MHz)
RESET
VALUE
VIDEO
RATE
(MHz)
000
001
010
8-bit color
Reserved
Reserved
Reserved
Reserved
BIT VALUE
FUNCTION
00h
01h
02h
03h
04h
05h
8-bit indexed color
110
110
110
110
110
67.5
110
110
110
110
55
011
7–5
15-bit direct color or
8-bit indexed color
000
100
101
15-bit direct color
15-bit direct color
110
16-bit direct color
16-bit 5–6–5 direct
color
111
24-bit direct color
24-bit direct color
4
3
2
1 = Enable extended register space
1 = Enable extended pixel modes
0
0
0
Double 8-bit indexed
color
135
†
Not
Reset
1 = Add 7.5 IRE blanking pedestal
7–0
06h
16-bit 5–6–5 direct
color (2 × 8-bit input)
110
110
110
85
55
55
1 = Micro port interface to RAM is
8-bit not 6-bit
1
0
8-bit indexed color
(2 × 4-bit input)
07h
08h
09h
1 = Sleep mode (micro port and
palette RAM still enabled, see power
management features section)
0
0
15-bit direct color
(2 × 4-bit input)
55
†
Institute of Radio Engineers
Double 24-bit direct
color
56.5
INDEX LOW AND HIGH BYTE REGISTERS
0Ah–
FFh
(RS0–RS2 = 100, RS0–RS2 = 111)
Reserved
RESET
VALUE
BIT
FUNCTION
PIPELINE TIMING CONTROL REGISTER
(Double 8-bit and 24-bit modes only)
(Index 0005h)
7–0 Low/high byte of 16-bit index
0
COMPANY ID REGISTER (Index 0000h)
The TVP3703 uses an internal PLL and timing control circuitry to
automatically adjust pipeline. There are no register bits to program,
since the device accounts for all desired frequency ranges.
RESET
VALUE
BIT VALUE
7–0 97h
FUNCTION
Texas Instruments
Read only
SOFT RESET REGISTER (Index 0006h)
RESET
DEVICE ID REGISTER (Index 0001h)
BIT VALUE FUNCTION
7–0 03h
BIT
FUNCTION
VALUE
RESET
VALUE
7–1 Reserved
0
0
0
1 = Reset all registers to power-on default state
TVP3703
Read only
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
register content descriptions (continued)
POWER MANAGEMENT REGISTER A (Index 0007h)
CLOCK SYNTHESIZER CONTROL REGISTER
(Index 0048h)
RESET
VALUE MODE†
SLEEP
BIT
FUNCTION
RESET
VALUE
BIT
7
FUNCTION
7
6
5
4
3
Reserved (write 1)
1
0
0
0
1
0
1
1
0
1
1
1
Reserved
0
Reserved (write 0)
1 = Power-down palette RAM
Reserved (write 0)
Reserved
0 = Select VCLK by terminals VS0–VS3
1 = Select VCLK by bits 3–0
6
0
5–4 MCLK select (M0–M3)
0
0
3–0 VCLK select (V0–V15) if enabled by bit 6
2–0 Reserved (write 0)
†
Indicatesthe effect of selecting sleep mode (the power management
register is not modified).
CRC TEST REGISTER
(Index FFD6h)
RESET
VALUE
POWER MANAGEMENT REGISTER B (Index 0008h)
RESET
BIT VALUE
FUNCTION
Blue selection
BIT
FUNCTION
VALUE
7–6
0 0
0 1
Green selection
Red selection
None selected
Bit 0 selected
7–3 Reserved
Not reset
Not reset
1 0
2
1
0
1 = Power-down crystal oscillator
1 = Power-down VCLK generator
1 = Power-down MCLK generator
0
0
0
1 1
5–3
0 0 0
Not reset
1
PLL PARAMETERS LOW REGISTERS
(Indexes 0020h, 0022h, . . . 0046h)
1 1 1
Bit 7 selected
2
1
1 → 0 Transition initializes start of CRC
RESET
VALUE
BIT
FUNCTION
0
1
0
Use pixel bus input
Use self-test-generated patterns
Reserved
7
VCLK/MCLK source select 0 (see Table 4)
See Table 3
0
6–0 M value
CRC LOW BYTE (Bits 7–0)
(Index FFD7h)
PLL PARAMETERS HIGH REGISTERS
(Indexes 0021h, 0023h, . . . 0047h)
RESET
VALUE
RESET
VALUE
BIT
FUNCTION
BIT
FUNCTION
7–0 Low byte of CRC value
Not reset
7
VCLK/MCLK source select 1 (see Table 4)
6–5 N2 value
4–0 N1 value
See Table 3
CRC HIGH BYTE (Bits 15–8)
(Index FFD8h)
RESET
VALUE
BIT
FUNCTION
Table 4. VCLK/MCLK Source Select
(PLL parameters high and low registers – bit 7)
7–0 High byte of CRC value
Not reset
SOURCE SOURCE
SELECT SELECT
PLL
USED
VCLK/MCLK FUNCTION
1
0
0
0
0
1
M
2
‡
f
f
Yes
O
I XIN
N2
2
(
)
2
N1
Reserved
f
I XIN
1
0
No
No
f
O
N2
2
direct
1
1
f
= f
I(XIN)
O
‡
See power management features section.
8
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TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
programming the PLL clock generators
The conditions shown in the following equations must be followed when programming the PLL clock generators.
6
f
10
I XIN
6
(1)
2
N1
f
10
2
I XIN
2
Where:
Where:
0
N1
31 and N1 must be an integer
135 10
6
6
64 10
f
(2)
(3)
(
)
2
(
)
2
N1
2
M
N1
2
f
I XIN
I XIN
0
M
f
127 and M must be an integer
(M 2)
I XIN
N2
2
f (N1 2)
O
Where:
0
N2
3 and N2 must be integer
power management features
Two power reduction options are available on the TVP3703.
1. Bit 0 of the pixel command register (sleep mode) provides a default power-down mode in which the following
sections of the device are powered down:
•
•
•
•
All pixel multiplexor modes
All post-RAM logic
The triple DAC
The mask logic
Micro port and palette-RAM power is maintained to allow read and write access to the internal registers or
palette locations. A typical value of I in sleep mode is listed in the electrical characteristics section.
DD
2. The power management register, located in the indexed register space (index 0007h), allows selective
power down of the device.
use of the hardware CRC feature
The TVP3703 hardware CRC feature supports testing of the entire pixel data path from the pixel port through
to the DAC inputs at full video rates up to 170 MHz on the TVP3703. Each of the three colors (red, green and
blue) are tested independently. CRCs are accumulated during active display, with accumulation being gated by
the BLANK signal.
A TVP3703 CRC can be accumulated in either active screen or self-test-pattern generation mode and is
controlled by bit 1 of the CRC test register (index FFD6h). To use the pattern generated CRC feature, perform
the following test procedure:
1. Set the mode and verify the PIXMIX signal is low.
2. Set the proper values in the CRC test register for the desired CRC mode. Set BLANK low. Wait for ten
PCLKS cycles.
3. Set bit 2 of the CRC test register to 1 and bit 1 to 0.
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
use of the hardware CRC feature (continued)
4. Set BLANK high.
5. Run for ten PCLK cycles.
6. Set BLANK low.
7. Run for 1200 dot clock cycles.
8. Set 0x5555 on pixel bus input.
9. Run for 20 PCLK cycles.
10. Set 0x0000 on the pixel bus input.
11. Run for three PCLK cycles.
12. Set bit 2 of the CRC test register to 0 and bit 1 to 1.
13. Wait for > 240 PCLK cycles.
14. Wait 1200 dot clock cycles.
15. Read the CRC low and high byte registers for the CRC result.
The CRC technique allows an authoritative check to be performed between the intended display and the actual
display at full video rates. For a given image (which can be an application’s image or a specially prepared test
screen), theoretically derived CRC values are calculated for each RGB color, which are then compared with the
TVP3703 hardware CRC values. Alternatively, the CRC value from a known good screen can be used as the
reference.
The CRC facility on the TVP3703 can be used to validate correct operation of:
•
•
•
•
•
The TVP3703 device in isolation
The TVP3703 device designed into, and working in, a VGA board
The DRAM, controller, and data path on the VGA board
The disk and bus operation of the host PC
MS-Windows (and device drivers) on the PC
The horizontal and vertical synchronization waveforms or timings do not affect hardware CRC accumulation.
Any discrepancy between the calculated and TVP3703 hardware accumulated CRC values indicates a problem
in the device or system being used.
The CRC logic on the TVP3703 is normally powered down. To perform a CRC test, bit 2 of the CRC test register
(index FFD6h) should be reset to 0 and returned to 1 afterwards to return to the default condition.
The CRC mechanism does not check the DAC outputs (i.e., what is physically being displayed on the monitor);
these can be tested using the TVP3703 SENSE output (generally readable as a register bit on the VGA
controller).
MS-Windows is a registered trademark of Microsoft Corporation.
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
identification of the TVP3703
One of the two following sequences of micro port accesses identifies the existence of the TVP3703 in a graphics
system:
OPERATION
RESULT
Read any valid register other than pixel mask Resets the indirect access sequence
(e.g., read I/O location 03C7h)
Read pixel mask (I/O location 03C6h) four times Provides indirect access procedure
Write pixel mask with 10h
Providesindirectaccesstopixelcommandregister,enabling
indexed registers. This also resets the indirect procedure.
Read pixel mask five times
Provides indirect access procedure
Write pixel mask twice with 00h
Provides indirect access procedure setting the index
registers to 0
Read pixel mask
Read pixel mask
Returns company ID (97h)
Returns device ID (03h)
or:
OPERATION
Write zero to RS(2–0) = 4h
Write zero to RS(2–0) = 7h
Read RS(2–0) = 5h
RESULT
Sets the index low byte to zero
Sets the index high byte to zero
Returns company ID (97h)
Read RS(2–0) = 5h
Returns device ID (03h)
pixel port
The rising edge of PCLK latches all of the pixels. Modes requiring more than one word per pixel accumulate
the least significant bytes of the pixel first. BLANK going high always identifies the first word within a pixel. The
VGA, SVGA, and extended pixel modes are listed in Tables 5 and 6.
Table 5. VGA and SVGA Modes
‡
USE OF PIXEL INPUT TERMINALS
SVGA
MODE
PIXEL WORD
LATCHED
†
P15 P14 P13 P12 P11 P10 P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
8-bit indexed
single P(7–0)
X
X
X
X
X
X
X
X
P7
P6
P5
P4
P3
P2
P1
P0
15-bit direct
(5–5–5)
first P(7–0)
second P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
G5
X
G4
R7
G3
R6
B7
R5
B6
R4
B5
R3
B4
G7
B3
G6
16-bit direct
(5–6–5)
first P(7–0)
second P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
G4
R7
G3
R6
G2
R5
B7
R4
B6
R3
B5
G7
B4
G6
B3
G5
24-bit direct
(8–8–8)
first P(7–0)
second P(7–0)
third P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B7
G7
R7
B6
G6
R6
B5
G5
R5
B4
G4
R4
B3
G3
R3
B2
G2
R2
B1
G1
R1
B0
G0
R0
†
‡
Pipe delay for all modes = 3 PCLK + 7 dot clocks
Unspecified bits = 0
11
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
pixel port (continued)
Table 6. Extended Pixel Modes
USE OF PIXEL INPUT TERMINALS
PIXEL WORD
LATCHED
†
SVGA MODE
P15 P14 P13 P12 P11 P10 P9
P8
X
P7
P7
P7
P6
P6
P6
P5
P5
P5
P4
P4
P4
P3
P3
P3
P2
P2
P2
P1
P1
P1
P0
P0
P0
00h 8-bit indexed
single P(7–0)
single P(15–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
01h
15-bit mixed
0
or
1
X
R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 B7
R7 R6 R5 F4 F3 G7 G6 G5 G4 G3 B7
B6
B6
B6
B3
B5
B5
B5
B2
B4
B4
B4
B1
B3
B3
B3
B0
02h
03h
04h
15-bit direct
16-bit direct
24-bit direct
single P(15–0)
X
single P(15–0) R7 R6 R5 R4 R3 G7 G6 G5 G4 G3 G2 B7
first P(15–0) G7 G6 G5 G4 G3 G2 G1 G0 B7 B6 B5 B4
second P(15–0)
X
X
X
X
X
X
X
X
R7 R6 R5 R4 R3 R2 R1 R0
05h
06h
Double 8-bit
indexed
single P(15–0) P7
P6
P5
P4
P3
P2
P1
P0
P7
6
P5
first displayed pixel
G4 G3 G2 B7 B6 B5
P4
P3
P2
P1
P0
‡,§
second displayed pixel
16-bit direct
(5–6–5)
first P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
B4
B3
second P(7–0)
R7 R6 R5 R4 R3 G7 G6 G5
07h 8-bit indexed
first P(3–0)
second P(3–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
P3
P7
P2
P6
P1
P5
P0
P4
08h
15-bit direct
(5–5–5)
first P(7–0)
second P(7–0)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
G5 G4 G3 B7
B6
B5
B4
B3
X
R7 R6 R5 R4 R3 G7 G6
B6 B5 B4 B3 B2 B1 B0
first displayed pixel
R7 R6 R5 R4 R3 R2 R1 R0
09h Double 24-bit
first P(15–0) G7 G6 G5 G4 G3 G2 G1 G0 B7
§
direct
second P(15–0) B7
B6
B5
second displayed pixel
third P(15–0) R7 R6 R5 R4 R3 R2 R1 R0 G7 G6 G5 G4 G3 G2 G1 G0
B4
B3
B2
B1
B0
†
‡
§
Pipe delay for mode = 3 PCLK + 7 dot clocks
Unspecified bits = 0
Modes 5 (05h) and 9 (09h) use PLL, DAC CLK = 2 × PCLK or 2/3 PCLK respectively.
primary and secondary pixel mode combinations
Writing to the pixel command register enables the extended pixel modes. A primary pixel mode and a secondary
pixel mode are defined for the TVP3703. The TVP3703 switches between these two modes on the fly under
control of the PIXMIX terminal.
The PIXMIX terminal and the pixel terminals are sampled on PCLK. If the primary or secondary pixel mode
format requires two PCLK edges to build a whole pixel, then PIXMIX should only change state on every second
PCLK edge after BLANK has gone high at the start of a line.
When PIXMIX is not in use, the primary and secondary pixel mode select registers should be written with the
same value.
The primary and secondary pixel mode combinations are listed in Table 7.
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
primary and secondary pixel mode combinations (continued)
Table 7. Primary and Secondary Pixel Mode Combinations
SECONDARY MODE
PRIMARY
MODE
00h 01h 02h 03h 04h 05h 06h 07h 08h 09h
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
NOTE 2: Pixel switching can only be performed when the PCLK to dot clock ratios for the
primary and secondary modes are the same.
programming of pixel modes using the PLL
The TVP3703 uses an internal PLL to generate the internal dot clock. This PLL automatically adjusts the PCLK
to dot clock ratio based on the multiplexing mode selected. Therefore no further programming is necessary.
pixel resolution and blanking periods in mode 09h
In mode 09h (packed 24-bit), latching 16 bits of data from 3 PCLK cycles generates a group of 2 pixels. This
means that the horizontal screen resolution must be an even number of pixels, and the number of PCLK cycles
during active display must be a multiple of 3.
Due to the internal phase relationships between PCLK and the pixel clock generated by the internal PLL, the
horizontal and vertical blanking period must also be an integral multiple of 3 PCLK cycles. This must be satisfied
so that the first pixel of each line always appears at the same point horizontally on the screen, from line to line
and from frame to frame.
Therefore mode 09h requires the following relationships must be satisfied:
Horizontally:
The total horizontal duration must be an integral multiple of 3 PCLKs.
HTOT
i.e.,
integer, where HTOT
total horizontal duration in standard VGA registers.
3
Vertically:
The total vertical duration must be an integral multiple of 3 PCLKs.
VTOT HTOT
i.e.,
integer, where VTOT
total vertical duration in standard VGA registers.
3
In all standard VGA systems, if the horizontal requirement is met, the vertical requirement is also met.
VGA standard controllers normally satisfy the requirements described in this section because the horizontal
blanking period is specified in character widths (8 pixels wide), vertical blanking in terms of scan lines, and
resolution in even pixels.
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
(see Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V
DD
Input voltage range, V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V +0.5 V
Analog output short-circuit duration to any power supply or common . . . . . . . . . . . . . . . . . . . . . . . . . . unlimited
I
DD
Operating free-air temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C
A
Storage temperature range, T
Junction temperature, T . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55°C to 150°C
stg
J
Case temperature for 10 seconds: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260°C
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 3: All voltage values are with respect to GND.
recommended operating conditions
MIN NOM
4.75
MAX
5.25
1.26
UNIT
V
Supply voltages, AV , DV
DD
5
DD
Reference voltage, V
ref
1.15 1.235
2.4
V
High-level input voltage, V
V
+0.5
DD
0.8
V
IH
Low-level input voltage, V
V
IL
Output load resistance, R
37.5
Ω
L
FS ADJUST resistor, R
147
0
Ω
SET
Operating free-air temperature, T
70
°C
A
electrical characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
270
MAX
340
150
250
UNIT
mA
mA
mA
µA
µA
V
Supply current, average power (see Note 4)
Supply current, average power (sleep mode) (see Note 5)
Supply current, average power (palette RAM powered down) (see Note 4)
Digital input current
I
60
220
DD
I
I
±100
I
Off-state-digital output current
±50
O
V
High-level output voltage
I
I
= –1 mA
= 4 mA
2.4
OH
OL
L
V
Low-level output voltage
0.4
V
L
NOTES: 4. Typical and maximum figures are both measured at 135 MHz, with differences due to V , pixel mode, and part to part variations.
DD
5. Typical figure measured at 35 MHz, with differences due to V , pixel mode, and part to part variations.
DD
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
timing requirements
micro port
TVP3703-170
TVP3703-135
PARAMETER
UNIT
MIN
50
MAX
MIN
75
MAX
t
t
t
t
t
t
t
t
Pulse duration, WR low
ns
ns
ns
ns
ns
ns
ns
ns
w(WLWH)
w(RLRH)
rec(WHWL)
rec(RHRL)
su(SVL)
Pulse duration, RD low
50
50
Recovery time preceding a write (see Notes 6 and 7)
Recovery time preceding a read (see Notes 6 and 7)
Setup time, RS0-RS2
3×t
6×t
3×t
6×t
c(CHCH)
c(CHCH)
c(CHCH)
10
c(CHCH)
10
Hold time, RS0-RS2
4
10
10
4
10
10
h(LSX)
Setup time, write data
su(DVWH)
h(WHDX)
Hold time, write data
NOTES: 6. t
c(CHCH)
(PCLK period) is specified in the pixel port timing requirements table.
7. Access recovery times are specified as the time before a particular access because the worst case access (reading a red palette
color value) can occur after either reading a blue palette color value or after writing to the address register (read mode).
PLL frequency select
TVP3703-170 TVP3703-135
PARAMETER
UNIT
MIN
50
MAX
MIN
50
MAX
t
t
t
t
Pulse duration, STROBE high
ns
ns
ns
ns
w(SHSL)
w(SLSH)
su(SVSL)
h(SLSX)
Pulse duration, STROBE low
50
50
Setup time, VS0–VS3 (see Note 8)
Hold time, VS0–VS3 (see Note 8)
20
30
20
30
NOTE 8: The VS0–VS3 latches are transparent when STROBE is at logic 1.
pixel port
TVP3703-170 TVP3703-135
PARAMETER
UNIT
MIN
11.7
9.08
9.08
2.9
2.9
2
MAX
MIN
14.8
9.08
9.08
4
MAX
PCLK cycle time (pixel mode 05h – double 8-bit, indexed)
ns
ns
ns
ns
ns
ns
ns
t
PCLK cycle time (pixel mode 09h – double 24-bit, direct)
PCLK cycle time (all other pixel modes)
Pulse duration, PCLK low
c(CHCH)
t
t
t
t
w(CLCH)
w(CHCL)
su(PVCH)
h(CHPX)
Pulse duration, PCLK high
3
Setup time, pixel data (see Note 9)
Hold time, pixel data (see Note 9)
2
2
2
NOTE 9: The pixel address input to the color palette should be set up as a valid logic level with the appropriate setup and hold times to each rising
edge of PCLK (this requirement must also be met during the blanking period).
15
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
switching characteristics
micro port
TVP3703-170 TVP3703-135
PARAMETER
UNIT
MIN
MAX
MIN
MAX
t
t
t
t
Delay time, output turn on
Access time, read enable
Hold time, output
5
5
ns
ns
ns
ns
d(RLQX)
a(RLQV)
h(RHQX)
d(RHQZ)
40
40
5
5
Delay time, output turn off
20
20
pixel port
TVP3703-170
TVP3703-135
PARAMETER
Analog output skew
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
1
1
ns
frequency synthesis
TVP3703-170
TVP3703-135
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
f
f
XIN crystal frequency range
Internal VCO frequency
VCLK output frequency (C = 15 pF)
14.3
14.3
MHz
MHz
MHz
MHz
ms
I(XIN)
64
170
110
80
64
135
110
80
L
O
MCLK output frequency (C = 15 pF)
L
Synthesizer lock time
5
5
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
operating characteristics
DAC
TVP3703-170
TVP3703-135
PARAMETER
UNIT
MIN
TYP
MAX
MIN
TYP
MAX
Resolution
8
8
bits
MHz
mA
DAC operating frequency
170
1.9
135
1.9
Output current, black level pedestal (see Note 10)
Output current, white relative to black (see Note 10)
DAC-to-DAC matching (see Notes 10 and 11)
Integral linearity error (see Note 10)
Differential linearity error (see Note 10)
DAC output compliance (see Note 10)
DAC output impedance
0.95
1.44
0.95
1.44
16.74 17.62 18.50
17.6 17.62
20.4
±5%
±1
mA
±2%
±5%
±1
±2%
E
E
LSB
LSB
V
L
±1
±1
D
–1
1.2
–1
1.2
50
3
50
kΩ
ns
t
t
Rise time (black to white level) (see Notes 10, 12, and 13)
Settling time (black to white) (see Notes 10, 12, and 14)
Glitch energy (see Notes 10 and 12)
Comparator trip voltage
1
3
r
5
10
50
ns
s
50
pVs
mV
µA
V
340
100
1.235
340
I
Reference input current
100
ref
Internal reference voltage
1.235
Internal reference voltage accuracy
1.15 1.235
1.27
1.15 1.235
1.27
V
NOTES: 10. V = 1.235 V and R
ref SET
= 147 Ω
11. About the midpoint of the distribution of the three DACs
12. 37.5 Ω and 30 pF load
13. Measured between 10% and 90% of full scale transition.
14. Settling to within 2% of frame sync delay (fsd)
timing diagrams
t
, t
t
, t
rec(RHRL) rec(WHWL)
w(RLRH) w(WLWH)
WR, RD
t
t
h(LSX)
su(SVL)
RS0–RS2
D0–D7
(Read)
t
d(RLQX)
t
h(RHQX)
t
a(RLQV)
t
d(RHQZ)
D0–D7
(Write)
t
t
h(WHDX)
su(DVWH)
Figure 1. Micro Port Read/Write Cycle Timing
17
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
timing diagrams (continued)
t
t
w(SLSH)
w(SHSL)
STROBE
t
t
h(SLSX)
su(SVSL)
VS0–VS3
Figure 2. PLL Frequency Select Write Cycle Timing
t
w(CLCH)
t
c(CHCH)
t
w(CHCL)
PCLK
t
su(PVCH)
t
h(CHPX)
P0–P15, BLANK
PIXMIX
Valid
Figure 3. Pixel Port Timing
18
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
APPLICATION INFORMATION
POWER SUPPLY
V
DD
L1
Local AV
DD
Plane
C4
AV
DD
V
DD
COMP
XIN
R1
D5–D7
X1
TVP3703
Monitor
XOUT
RED,
GREEN,
BLUE
75 Ω
REF
RSET
75 Ω
GND
D2–D4
R2
R3–R5
D1
C1
C2
C3
Figure 4. Analog Interface – Recommended Circuit in Internal Voltage Reference Mode
Table of Parts for Recommended Circuit (see Figure 4)
PART NUMBER
VALUE
47 µF
DESCRIPTION
Capacitor
C1
†
‡
C2 –C3
100 nF
100 nF
1 kΩ
Surface-mount capacitor
Surface-mount capacitor
5% resistor
†
§
†
C4
R1
R2
147 Ω
75 Ω
1% resistor
†
R3–R5
1% resistor
§
D1
LM385BZ-1.2 Voltage reference
D2–D7
L1
1N4148
Diode
1 µH
Inductor
X1
14.31818 MHz Crystal
†
‡
PlacethesecomponentsasclosetothepaletteDACaspossible.
Placing this component between REF and AV
performance.
does not affect
DD
§
Omit these components when using the TVP3703 in internal
voltage reference mode.
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TVP3703
VIDEO INTERFACE PALETTE
TRUE-COLOR CMOS RAMDAC
SLAS100 – MARCH 1996
MECHANICAL DATA
FN (S-PQCC-J**)
PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
0.180 (4,57)
MAX
D
0.120 (3,05)
0.090 (2,29)
D
1
0.008 (0,20) NOM
0.020 (0,51) MIN
3
1
19
4
18
D /E
2
2
E
E
1
0.032 (0,81)
0.026 (0,66)
D /E
2
2
8
14
9
13
0.050 (1,27)
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
M
D/E
D /E
D /E
2 2
1
1
NO. OF
PINS**
MIN
0.385 (9,78)
MAX
0.395 (10,03)
MIN
0.350 (8,89)
MAX
0.356 (9,04)
MIN
MAX
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
20
28
44
52
68
84
0.485 (12,32) 0.495 (12,57) 0.450 (11,43) 0.456 (11,58)
0.685 (17,40) 0.695 (17,65) 0.650 (16,51) 0.656 (16,66)
0.785 (19,94) 0.795 (20,19) 0.750 (19,05) 0.756 (19,20)
0.985 (25,02) 0.995 (25,27) 0.950 (24,13) 0.956 (24,28) 0.441 (11,20) 0.469 (11,91)
1.185 (30,10) 1.195 (30,35) 1.150 (29,21) 1.158 (29,41) 0.541 (13,74) 0.569 (14,45)
4040005/B–10/94
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable Device
Status (1)
Package Package
Pins Package Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3)
Qty
Type
PLCC
PLCC
Drawing
TVP3703-135CFN
TVP3703-170CFN
OBSOLETE
OBSOLETE
FN
68
68
TBD
TBD
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FN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan
-
The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS
&
no Sb/Br)
-
please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
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Addendum-Page 1
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