UC3823ADWTR [ROCHESTER]
2.2 A SWITCHING CONTROLLER, 1150 kHz SWITCHING FREQ-MAX, PDSO16, GREEN, SOIC-16;
| 型号： | UC3823ADWTR |
| 厂家： | 
Rochester Electronics |
| 描述： | 2.2 A SWITCHING CONTROLLER, 1150 kHz SWITCHING FREQ-MAX, PDSO16, GREEN, SOIC-16 信息通信管理 开关 光电二极管 |
| 文件： | 总21页 (文件大小：1624K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
HIGH-SPEED PWM CONTROLLER
FEATURES
DESCRIPTION
D
D
D
Improved Versions of the UC3823/UC3825
PWMs
The UC3823A and UC3823B and the UC3825A and
UC3825B family of PWM controllers are improved
versions of the standard UC3823 and UC3825 family.
Performance enhancements have been made to several
of the circuit blocks. Error amplifier gain bandwidth product
is 12 MHz, while input offset voltage is 2 mV. Current limit
threshold is assured to a tolerance of 5%. Oscillator
discharge current is specified at 10 mA for accurate dead
time control. Frequency accuracy is improved to 6%.
Startup supply current, typically 100 μA, is ideal for off-line
applications. The output drivers are redesigned to actively
sink current during UVLO at no expense to the startup
current specification. In addition each output is capable of
2-A peak currents during transitions.
Compatible with Voltage-Mode or
Current-Mode Control Methods
Practical Operation at Switching Frequencies
to 1 MHz
D
50-ns Propagation Delay to Output
D
High-Current Dual Totem Pole Outputs
(2-A Peak)
D
D
D
D
Trimmed Oscillator Discharge Current
Low 100-μA Startup Current
Pulse-by-Pulse Current Limiting Comparator
Latched Overcurrent Comparator With Full
Cycle Restart
BLOCK DIAGRAM
CLK/LEB 4
(60%)
13 VC
RT
CT
5
6
7
3
2
1
11 OUTA
*
OSC
R
S
T
RAMP
EAOUT
NI
D
1.25 V
E/A
14 OUTB
12 PGND
PWM
LATCH
PWM COMPARATOR
9 mA
INV
SOFT−START COMPLETE
RESTART
CURRENT
5 V
250mA
LIMIT
DELAY
LATCH
SS
8
1.0 V
1.2 V
0.2 V
OVER CURRENT
ILIM 9
S
S
D
RESTART
DELAY
R
R
FAULT LATCH
UVLO
VCC 15
GND 10
”B” 16V/10V
”A” 9.2V/8.4V
INTERNAL
BIAS
VREF
5.1 V
ON/OFF
4 V
V
REF
GOOD
16 5.1 VREF
UDG−02091
* On the UC1823A version, toggles Q and Q are always low.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments
semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date. Products
conform to specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all parameters.
Copyright © 2004 −2008, Texas Instruments Incorporated
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during
storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
Functional improvements have also been implemented in this family. The UC3825 shutdown comparator is now a
high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that ensures full
discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs are in the low state.
In the event of continuous faults, the soft-start capacitor is fully charged before discharge to insure that the fault frequency
does not exceed the designed soft start period. The UC3825 CLOCK pin has become CLK/LEB. This pin combines the
functions of clock output and leading edge blanking adjustment and has been buffered for easier interfacing.
The UC3825A and UC3825B have dual alternating outputs and the same pin configuration of the UC3825. The UC3823A
and UC3823B outputs operate in phase with duty cycles from zero to less than 100%. The pin configuration of the UC3823A
and UC3823B is the same as the UC3823 except pin 11 is now an output pin instead of the reference pin to the current
limit comparator. “A” version parts have UVLO thresholds identical to the original UC3823 and UC3825. The “B” versions
have UVLO thresholds of 16 V and 10 V, intended for ease of use in off-line applications.
Consult the application note, The UC3823A,B and UC3825A,B Enhanced Generation of PWM Controllers, (SLUA125) for
detailed technical and applications information.
ORDERING INFORMATION
UVLO
9.2 V / 8.4 V
16 V / 10 V
MAXIMUM
DUTY CYCLE
T
A
(1)
(1)
(1)
SOIC−16
PDIP−16
PLCC−20
SOIC−16
PDIP−16
PLCC−20
(DW)
(N)
(Q)
(DW)
(N)
(Q)
< 100%
< 50%
< 100%
< 50%
UC2823ADW
UC2825ADW
UC3823ADW
UC3825ADW
UC2823AN
UC2825AN
UC3823AN
UC3825AN
UC2823AQ
UC2825AQ
UC3823AQ
UC3825AQ
UC2823BDW
UC2825BDW
UC3823BDW
UC3825BDW
UC2823BN
UC2825BN
UC3823BN
UC3825BN
−
−40°C to 85°C
−0°C to 70°C
−
−
UC3825BQ
(1)
The DW and Q packages are also available taped and reeled. Add TR suffix to the device type (i.e., UC2823ADWR). To order quantities of 1000
devices per reel for the Q package and 2000 devices per reel for the DW package.
UVLO
9.2 V / 8.4 V
MAXIMUM
DUTY CYCLE
T
A
CDIP−16
LCCC−20
(J)
(L)
< 100%
< 50%
UC1823AJ, UC1823AJ883B, UC1823AJQMLV
UC1825AJ, UC1825AJ883B, UC1825AJQMLV
UC1823AL, UC1823AL883B
−55°C to 125°C
UC1825AL, UC1825AL883B, UC1825ALQMLV
PIN ASSIGNMENTS
Q OR L PACKAGES
(TOP VIEW)
DW, J, OR N PACKAGES
(TOP VIEW)
INV
NI
EAOUT
CLK/LEB
RT
VREF
VCC
OUTB
VC
1
2
3
4
5
6
7
8
16
15
14
13
12
3
2
1
20 19
18
OUTB
VC
NC
EAOUT
CLK/LEB
NC
4
5
6
7
8
17
16
15
PGND
CT
RAMP
SS
11 OUTA
PGND
RT
CT
10
9
GND
ILIM
14 OUTA
9 10 11 12 13
NC = no connection
2
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
TERMINAL FUNCTIONS
TERMINAL
NO.
J or DW
I/O
DESCRIPTION
NAME
Q or L
CLK/LEB
CT
4
5
O
I
Output of the internal oscillator
Timing capacitor connection pin for oscillator frequency programming. The timing capacitor should
be connected to the device ground using minimal trace length.
6
8
EAOUT
GND
ILIM
3
10
9
4
O
−
I
Output of the error amplifier for compensation
Analog ground return pin
13
12
2
Input to the current limit comparator
Inverting input to the error amplifier
INV
1
I
NI
2
3
I
Non-inverting input to the error amplifier
High current totem pole output A of the on-chip drive stage.
High current totem pole output B of the on-chip drive stage.
Ground return pin for the output driver stage
OUTA
OUTB
PGND
11
14
12
14
18
15
O
O
−
Non-inverting input to the PWM comparator with 1.25-V internal input offset. In voltage mode
operation, this serves as the input voltage feed-forward function by using the CT ramp. In peak
current mode operation, this serves as the slope compensation input.
RAMP
7
9
I
RT
SS
5
8
7
I
I
Timing resistor connection pin for oscillator frequency programming
Soft-start input pin which also doubles as the maximum duty cycle clamp.
10
Power supply pin for the output stage. This pin should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor with minimal trace lengths.
VC
13
15
16
17
19
20
−
−
Power supply pin for the device. This pin should be bypassed with a 0.1-μF monolithic ceramic low
ESL capacitor with minimal trace lengths
VCC
VREF
5.1-V reference. For stability, the reference should be bypassed with a 0.1-μF monolithic ceramic
low ESL capacitor and minimal trace length to the ground plane.
O
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range unless otherwise noted
UNIT
22 V
V
Supply voltage,
VC, VCC
OUTA, OUTB
OUTA, OUTB
INV, NI, RAMP
ILIM, SS
IN
I
I
Source or sink current, DC
Source or sink current, pulse (0.5 μs)
0.5 A
O
2.2 A
O
−0.3 V to 7 V
−0.3 V to 6 V
0.2 V
Analog inputs
Power ground
PGND
Outputs
OUTA, OUTB limits
CLK/LEB
EAOUT
PGND −0.3 V to V +0.3 V
C
I
I
I
I
Clock output current
Error amplifier output current
Soft-start sink current
Oscillator charging current
−5 mA
5 mA
CLK
O(EA)
SS
SS
20 mA
RT
−5 mA
OSC
T
Operating virtual junction temperature range
Storage temperature
−55°C to 150°C
−65°C to 150°C
−55C°C to 150°C
−65°C to 150°C
300°C
J
T
stg
Lead temperature 1,6 mm (1/16 inch) from case for 10 seconds
Storage temperature
t
STG
Lead temperature 1,6 mm (1/16 inch) from cases for 10 seconds
(1)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
3
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
ELECTRICAL CHARACTERISTICS
T = −55°C to 125°C for the UC1823A/UC1825A, T = −40°C to 85°C for the UC2823x/UC2825x, T = 0°C to 70°C for the UC3823x/UC3825x,
A
A
A
R = 3.65 kΩ, C = 1 nF, V = 12 V, T = T (unless otherwise noted)
T
T
CC
A
J
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
REFERENCE, V
REF
V
O
Ouput voltage range
Line regulation
T = 25°C,
I = 1 mA
O
5.05
5.1
2
5.15
15
V
J
12 V ≤ VCC ≤ 20 V
mV
V
Load regulation
1 mA ≤ I ≤ 10 mA
5
20
O
Total output variation
Temperature stability
Output noise voltage
Line, load, temperature
5.03
30
5.17
(1)
(1)
T
(min)
< T < T
(max)
0.2
50
5
0.4 mV/°C
μV
A
10 Hz < f < 10 kHz
RMS
(1)
Long term stability
T = 125°C, 1000 hours
J
25
90
mV
Short circuit current
VREF = 0 V
60
mA
OSCILLATOR
T = 25°C
375
0.9
400
1
425
1.1
kHz
MHz
kHz
J
(1)
f Initial accuracy
OSC
R = 6.6 kΩ, C = 220 pF, T = 25°C
T
T
A
Line, temperature
R = 6.6 kΩ, C = 220 pF,
350
0.85
450
1.15
1%
(1)
Total variation
MHz
T
T
Voltage stability
12 V < VCC < 20 V
< T < T
(max)
(1)
Temperature stability
T
(min)
+/−
5%
4
A
High-level output voltage, clock
Low-level output voltage, clock
Ramp peak
3.7
0
0.2
3
2.6
0.7
1.6
9
2.8
1
V
Ramp valley
1.25
2
Ramp valley-to-peak
Oscillator discharge current
1.8
10
I
R = OPEN,
T
V = 2 V
CT
11
mA
OSC
ERROR AMPLIFIER
Input offset voltage
2
0.6
0.1
95
10
3
mV
Input bias current
Input offset current
μA
1
Open loop gain
1 V < V < 4 V
60
75
85
1
O
CMRR Common mode rejection ratio
1.5 V < V < 5.5 V
95
dB
CM
PSRR
Power supply rejection ratio
Output sink current
12 V < V < 20 V
110
2.5
−1.3
4.7
0.5
12
CC
I
I
V
V
= 1 V
= 4 V
O(sink)
O(src)
EAOUT
EAOUT
mA
V
Output source current
High-level output voltage
Low-level output voltage
Gain bandwidth product
−0.5
5
I
I
= −0.5 mA
= −1 mA
4.5
0
EAOUT
EAOUT
1
f = 200 kHz
6
Mhz
(1)
Slew rate
6
9
V/μs
(1)
Ensured by design. Not production tested.
4
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
ELECTRICAL CHARACTERISTICS
T = −55°C to 125°C for the UC1823A/UC1825A, T = −40°C to 85°C for the UC2823x/UC2825x, T = 0°C to 70°C for the UC3823x/UC3825x,
A
A
A
R = 3.65 kΩ, C = 1 nF, V = 12 V, T = T (unless otherwise noted)
T
T
CC
A
J
PWM COMPARATOR
I
Bias current, RAMP
Minimum duty cycle
Maximum duty cycle
V
= 0 V
−1
−8
μA
BIAS
RAMP
0%
85%
300
8.5
t
Leading edge blanking time
R
= 2 kΩ,
C
LEB
= 470 pF
375
10.0
1.25
50
450
11.5
1.4
ns
kΩ
V
LEB
LEB
R
Leading edge blanking resistance
Zero dc threshold voltage, EAOUT
V
V
V
= 3 V
LEB
CLK/LEB
V
= 0 V
1.10
ZDC
RAMP
(1)
t
Delay-to-output time
= 2.1 V,
V = 0 V to 2 V step
ILIM
80
ns
DELAY
EAOUT
CURRENT LIMIT / START SEQUENCE / FAULT
I
Soft-start charge current
Full soft-start threshold voltage
Restart discharge current
Restart threshold voltage
ILIM bias current
V
V
V
= 2.5 V
8
4.3
14
5
20
μA
V
SS
SS
V
SS
DSCH
SS
I
I
I
I
= 2.5 V
SS
100
250
0.3
350
0.5
μA
V
= 0 V to 2 V step
= 0 V to 2 V step
15
μA
BIAS
CL
ILIM
Current limit threshold voltage
Overcurrent threshold voltage
0.95
1.14
1
1.2
50
1.05
1.26
80
V
(1)
t
d
Delay-to-output time, ILIM
V
ILIM
ns
OUTPUT
I
I
I
I
= 20 mA
= 200 mA
= 20 mA
= 200 mA
0.25
1.2
1.9
2
0.4
2.2
2.9
3
OUT
OUT
OUT
OUT
Low-level output saturation voltage
High-level output saturation voltage
V
t
r,
t
f
(1)
Rise/fall time
C = 1 nF
L
20
45
ns
UNDERVOLTAGE LOCKOUT (UVLO)
Start threshold voltage
Stop threshold voltage
OVLO hysteresis
UC2823B, UC2825B, UC3825B, UC3825B
16
9.2
10
0.8
6
17
UC1823A, UC1825A, UC2823A, UC2825A
UC3825A, UC3825A
8.4
9
9.6
UC2823B, UC2825B, UC3825B, UC3825B
V
UC1823A, UC1825A, UC2823A, UC2825A
UC3825A, UC3825A
0.4
5
1.2
7
UC2823B, UC2825B, UC3825B, UC3825B
SUPPLY CURRENT
I
I
Startup current
Input current
VC = VCC = V (start) − 0.5 V
100
28
300
36
μA
su
TH
mA
CC
(1)
Ensured by design. Not production tested.
5
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
APPLICATION INFORMATION
The oscillator of the UC3823A, UC3823B, UC3825A, and UC3825B is a saw tooth. The rising edge is governed by a current
controlled by the RT pin and value of capacitance at the CT pin (C ). The falling edge of the sawtooth sets dead time for
CT
the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT can then be chosen based
on the desired frequency (RT) and D . The design equations are:
MAX
ǒ1.6 DMAXǓ
3 V
R +
C +
T
T
ǒ
MAXǓ
ǒR fǓ
(
)
10 mA 1 * D
T
(1)
Recommended values for R range from 1 kΩ to 100 kΩ. Control of D
less than 70% is not recommended.
T
MAX
UDG−95102
Figure 1. Oscillator
OSCILLATOR FREQUENCY
vs
MAXIMUM DUTY CYCLE
vs
TIMING RESISTANCE
TIMING RESISTANCE
100
95
10 M
1 M
90
85
80
100 k
10 k
75
70
10 k
1 k
10 k
100 k
1 k
100 k
R
T
− Timing Resistance − W
RT − Timing Resistance − W
Figure 3
Figure 2
6
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
LEADING EDGE BLANKING
The UC3823A, UC2823B, UC3825A, and UC3825B perform fixed frequency pulse width modulation control. The
UC3823A, and UC3823B outputs operate together at the switching frequency and can vary from zero to some value less
than 100%. The UC3825A and UC3825B outputs are alternately controlled. During every other cycle, one output is off.
Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%.
To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.
On the falling edge of the clock, the appropriate output(s) is driven high. The end of the pulse is controlled by the PWM
comparator, current limit comparator, or the overcurrent comparator.
Normally the PWM comparator senses a ramp crossing a control voltage (error amplifier output) and terminates the pulse.
Leading edge blanking (LEB) causes the PWM comparator to be ignored for a fixed amount of time after the start of the
pulse. This allows noise inherent with switched mode power conversion to be rejected. The PWM ramp input may not
require any filtering as result of leading edge blanking.
To program a leading edge blanking (LEB) period, connect a capacitor, C, to CLK/LEB. The discharge time set by C and
the internal 10-kΩ resistor determines the blanked interval. The 10-kΩ resistor has a 10% tolerance. For more accuracy,
an external 2-kΩ 1% resistor (R) can be added, resulting in an equivalent resistance of 1.66 kΩ with a tolerance of 2.4%.
The design equation is:
ǒ Ǔ
+ 0.5 R ø 10 kW C
t
LEB
(2)
Values of R less than 2 kΩ should not be used.
Leading edge blanking is also applied to the current limit comparator. After LEB, if the ILIM pin exceeds the 1-V threshold,
the pulse is terminated. The overcurrent comparator, however, is not blanked. It catches catastrophic overcurrent faults
without a blanking delay. Any time the ILIM pin exceeds 1.2 V, the fault latch is set and the outputs driven low. For this
reason, some noise filtering may be required on the ILIM pin.
UDG−95105
Figure 4. Leading Edge Blanking Operational Waveforms
7
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
UVLO, SOFT-START AND FAULT MANAGEMENT
Soft-start is programmed by a capacitor on the SS pin. At power up, SS is discharged. When SS is low, the error amplifier
output is also forced low. While the internal 9-μA source charges the SS pin, the error amplifier output follows until closed
loop regulation takes over.
Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low. The soft-start cap is then discharged
by a 250-μA current sink. No more output pulses are allowed until soft-start is fully discharged and ILIM is below 1.2 V. At
this point the fault latch resets and the chip executes a soft-start.
Should the fault latch get set during soft-start, the outputs are immediately terminated, but the soft-start capacitor does not
discharge until it has been fully charged first. This results in a controlled hiccup interval for continuous fault conditions.
UDG−95106
Figure 5. Soft-Start and Fault Waveforms
ACTIVE LOW OUTPUTS DURING UVLO
The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate.
UDG−95108
UDG−95106
Figure 6. Output Voltage vs Output Current
Figure 7. Output V and I During UVLO
8
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
CONTROL METHODS
Current Mode
Voltage Mode
UDG−95110
UDG−95109
.
Figure 8. Control Methods
SYNCHRONIZATION
The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free
running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width
should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin
can be used to generate a synchronizing pulse for other chips. Note that the CLK/LEB pin no longer accepts an incoming
synchronizing signal.
UDG−95111
UDG−95113
Figure 9. General Oscillator Synchronization
Figure 10. Two Unit Interface
UDG−95112
Figure 11. Operational Waveforms
9
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
www.ti.com
HIGH CURRENT OUTPUTS
Each totem pole output of the UC3823A and UC3823AB, UC3825A, and UC3825B can deliver a 2-A peak current into a
capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC)
and power ground (PGND) pins help decouple the device’s analog circuitry from the high-power gate drive noise. The use
of 3-A Schottky diodes (1N5120, USD245, or equivalent) as shown in the Figure 13 from each output to both VC and PGND
are recommended. The diodes clamp the output swing to the supply rails, necessary with any type of inductive/capacitive
load, typical of a MOSFET gate. Schottky diodes must be used because a low forward voltage drop is required. DO NOT
USE standard silicon diodes.
Although they are single-ended devices, two output drivers are available on the UC3823A and UC3823B devices. These
can be paralleled by the use of a 0.5 Ω (noninductive) resistor connected in series with each output for a combined peak
current of 4 A.
UDG−95114
Figure 12. Power MOSFET Drive Circuit
GROUND PLANES
Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the
chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents
associated with the output stages. This point is the power ground to which the PGND pin is connected. Power ground can
be separated from the rest of the ground plane and connected at a single point, although this is not necessary if the high
di/dt paths are well understood and accounted for. VCC should be bypassed directly to power ground with a good high
frequency capacitor. The sources of the power MOSFET should connect to power ground as should the return connection
for input power to the system and the bulk input capacitor. The output should be clamped with a high current Schottky diode
to both VCC and PGND. Nothing else should be connected to power ground.
VREF should be bypassed directly to the signal portion of the ground plane with a good high frequency capacitor. Low
ESR/ESL ceramic 1-mF capacitors are recommended for both VCC and VREF. All analog circuitry should likewise be
bypassed to the signal ground plane.
10
UC1823A, UC2823A, UC2823B,
UC3823A, UC3823B, UC1825A,
www.ti.com
UC2825A, UC2825B, UC3825A, UC3825B
SLUS334E − AUGUST 1995 − REVISED SEPTEMBER 2010
UDG−95115
Figure 13. Ground Planes Diagram
OPEN LOOP TEST CIRCUIT
This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any
wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly
recommended.
UDG−95116
Figure 14. Open Loop Test Circuit Schematic
11
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
5962-87681022A
ACTIVE
LCCC
FK
20
1
TBD
Call TI
Call TI
-55 to 125
5962-
87681022A
UC1825AL/
883B
5962-8768102EA
5962-8768103XA
ACTIVE
CDIP
J
16
28
1
1
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
5962-8768102EA
UC1825AJ/883B
OBSOLETE
TO-92
LP
5962-
8768103XA
UC1825BLP/
883B
5962-89905022A
ACTIVE
LCCC
FK
20
TBD
Call TI
Call TI
-55 to 125
-55 to 125
5962-
89905022A
UC1823AL/
883B
5962-8990502EA
5962-8990502VEA
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
Call TI
A42
Call TI
5962-8990502EA
UC1823AJ/883B
N / A for Pkg Type
5962-8990502VE
A
UC1823AJQMLV
UC1823AJ
ACTIVE
ACTIVE
CDIP
CDIP
J
J
16
16
1
1
TBD
TBD
A42
A42
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1823AJ
UC1823AJ883B
5962-8990502EA
UC1823AJ/883B
UC1823AL
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1823AL
UC1823AL883B
5962-
89905022A
UC1823AL/
883B
UC1823BJ
UC1823BJ883B
UC1823BL
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
CDIP
CDIP
LCCC
LCCC
CDIP
J
J
16
16
20
20
16
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
A42
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
0 to 70
FK
FK
J
Call TI
UC1823BL883B
UC1825AJ
Call TI
1
N / A for Pkg Type
-55 to 125
UC1825AJ
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC1825AJ883B
ACTIVE
CDIP
J
16
1
TBD
A42
N / A for Pkg Type
-55 to 125
5962-8768102EA
UC1825AJ/883B
UC1825AL
ACTIVE
ACTIVE
LCCC
LCCC
FK
FK
20
20
1
1
TBD
TBD
POST-PLATE
POST-PLATE
N / A for Pkg Type
N / A for Pkg Type
-55 to 125
-55 to 125
UC1825AL
UC1825AL883B
5962-
87681022A
UC1825AL/
883B
UC1825ALP883B
OBSOLETE
TO-92
LP
28
TBD
Call TI
N / A for Pkg Type
-55 to 125
5962-
8768102XA
UC1825ALP/
883B
UC1825BJ
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
OBSOLETE
CDIP
CDIP
J
J
16
16
20
20
28
TBD
TBD
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
Call TI
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
UC1825BJ883B
UC1825BL/81047
UC1825BL883B
UC1825BLP883B
TO/SOT
LCCC
TO-92
L
Call TI
FK
LP
Call TI
N / A for Pkg Type
5962-
8768103XA
UC1825BLP/
883B
UC2823ADW
UC2823ADWG4
UC2823ADWTR
UC2823ADWTRG4
UC2823AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PLCC
PLCC
DW
DW
DW
DW
N
16
16
16
16
16
16
20
20
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
UC2823ADW
UC2823ADW
UC2823ADW
UC2823ADW
UC2823AN
UC2823AN
UC2823AQ
UC2823AQ
Green (RoHS
& no Sb/Br)
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2823ANG4
UC2823AQ
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
FN
FN
46
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC2823AQG3
46
Green (RoHS
& no Sb/Br)
CU SN
Addendum-Page 2
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
-40 to 85
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC2823BDW
ACTIVE
SOIC
SOIC
DW
16
16
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
Level-2-260C-1 YEAR
UC2823BDW
UC2823BDWG4
ACTIVE
DW
40
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
-40 to 85
UC2823BDW
UC2823BN
UC2823BJ
UC2823BN
OBSOLETE
OBSOLETE
OBSOLETE
ACTIVE
CDIP
PDIP
PDIP
SOIC
J
N
16
16
16
16
TBD
TBD
TBD
Call TI
Call TI
Call TI
Call TI
-40 to 85
-40 to 85
-40 to 85
-40 to 85
UC2823BNG4
UC2825ADW
N
Call TI
Call TI
DW
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
UC2825ADW
UC2825ADW
UC2825ADW
UC2825ADW
UC2825AN
UC2825ADWG4
UC2825ADWTR
UC2825ADWTRG4
UC2825AN
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
PLCC
PLCC
SOIC
SOIC
DW
DW
DW
N
16
16
16
16
16
20
20
16
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
-40 to 85
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC2825ANG4
UC2825AQ
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC2825AN
FN
FN
DW
DW
46
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
UC2825AQ
UC2825AQG3
UC2825BDW
46
Green (RoHS
& no Sb/Br)
CU SN
UC2825AQ
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
UC2825BDW
UC2825BDW
UC2825BDWG4
40
Green (RoHS
& no Sb/Br)
UC2825BJ
UC2825BN
OBSOLETE
ACTIVE
CDIP
PDIP
J
16
16
TBD
Call TI
Call TI
-40 to 85
-40 to 85
N
25
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
UC2825BN
UC2825BN
UC2825BNG4
ACTIVE
PDIP
N
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
N / A for Pkg Type
-40 to 85
UC3823A-W
UC3823ADW
ACTIVE WAFERSALE
ACTIVE SOIC
YS
0
1431
40
TBD
Call TI
Call TI
DW
16
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
0 to 70
UC3823ADW
Addendum-Page 3
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC3823ADWG4
UC3823ADWTR
UC3823ADWTRG4
UC3823AN
ACTIVE
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
PLCC
DW
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
20
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3823ADW
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
N
2000
2000
25
Green (RoHS
& no Sb/Br)
UC3823ADW
UC3823ADW
UC3823AN
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3823ANG4
UC3823BDW
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC3823AN
DW
DW
DW
DW
N
40
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3823BDW
UC3823BDW
UC3823BDW
UC3823BDW
UC3823BN
UC3823BDWG4
UC3823BDWTR
UC3823BDWTRG4
UC3823BN
40
Green (RoHS
& no Sb/Br)
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3823BNG4
UC3825ADW
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC3823BN
DW
DW
DW
DW
N
40
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3825ADW
UC3825ADW
UC3825ADW
UC3825ADW
UC3825AN
UC3825ADWG4
UC3825ADWTR
UC3825ADWTRG4
UC3825AN
40
Green (RoHS
& no Sb/Br)
2000
2000
25
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
Green (RoHS
& no Sb/Br)
UC3825ANG4
UC3825AQ
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
UC3825AN
FN
46
Green (RoHS
& no Sb/Br)
Level-2-260C-1 YEAR
UC3825AQ
Addendum-Page 4
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Orderable Device
Status Package Type Package Pins Package
Eco Plan Lead/Ball Finish
MSL Peak Temp
Op Temp (°C)
0 to 70
Top-Side Markings
Samples
Drawing
Qty
(1)
(2)
(3)
(4)
UC3825AQG3
UC3825BDW
ACTIVE
PLCC
SOIC
SOIC
SOIC
SOIC
PDIP
PDIP
FN
20
16
16
16
16
16
16
46
Green (RoHS
& no Sb/Br)
CU SN
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
Level-2-260C-1 YEAR
N / A for Pkg Type
UC3825AQ
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
ACTIVE
DW
DW
DW
DW
N
40
40
Green (RoHS
& no Sb/Br)
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
CU NIPDAU
0 to 70
UC3825BDW
UC3825BDW
UC3825BDW
UC3825BDW
UC3825BN
UC3825BDWG4
UC3825BDWTR
UC3825BDWTRG4
UC3825BN
Green (RoHS
& no Sb/Br)
0 to 70
2000
2000
25
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
Green (RoHS
& no Sb/Br)
0 to 70
UC3825BNG4
N
25
Green (RoHS
& no Sb/Br)
N / A for Pkg Type
0 to 70
UC3825BN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Addendum-Page 5
PACKAGE OPTION ADDENDUM
www.ti.com
13-May-2013
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
OTHER QUALIFIED VERSIONS OF UC1823A, UC1823A-SP, UC1823B, UC1825A, UC1825B, UC2825A, UC3823A, UC3823B, UC3825A, UC3825B :
Catalog: UC3823A, UC1823A, UC3823B, UC3825A, UC3825B
•
Automotive: UC2825A-Q1
•
Enhanced Product: UC2825A-EP
•
Military: UC1823A, UC1823B, UC1825A, UC1825B
•
Space: UC1823A-SP, UC1825A-SP
•
NOTE: Qualified Version Definitions:
Catalog - TI's standard catalog product
•
Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects
•
Enhanced Product - Supports Defense, Aerospace and Medical Applications
•
Military - QML certified for Military and Defense Applications
•
Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application
•
Addendum-Page 6
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
UC2823ADWTR
UC2825ADWTR
UC3823ADWTR
UC3823BDWTR
UC3825ADWTR
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
16
16
16
16
16
2000
2000
2000
2000
2000
330.0
330.0
330.0
330.0
330.0
16.4
16.4
16.4
16.4
16.4
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
10.75 10.7
2.7
2.7
2.7
2.7
2.7
12.0
12.0
12.0
12.0
12.0
16.0
16.0
16.0
16.0
16.0
Q1
Q1
Q1
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
8-May-2013
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
UC2823ADWTR
UC2825ADWTR
UC3823ADWTR
UC3823BDWTR
UC3825ADWTR
SOIC
SOIC
SOIC
SOIC
SOIC
DW
DW
DW
DW
DW
16
16
16
16
16
2000
2000
2000
2000
2000
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
367.0
38.0
38.0
38.0
38.0
38.0
Pack Materials-Page 2
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changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest
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