UCC5510MWP-TR [ROCHESTER]
9-LINE 105ohm SCSI BUS TERMINATOR, PDSO36, SSOP-36;
| 型号： | UCC5510MWP-TR |
| 厂家： | 
Rochester Electronics |
| 描述： | 9-LINE 105ohm SCSI BUS TERMINATOR, PDSO36, SSOP-36 信息通信管理 光电二极管 接口集成电路 |
| 文件： | 总8页 (文件大小：773K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UCC5510
Low Voltage Differential (LVD/SE) SCSI 9 Line Terminator
FEATURES
DESCRIPTION
• Auto Selection Multi-Mode Single
Ended or Low Voltage Differential
Termination
The UCC5510 Multi-Mode Low Voltage Differential and Single Ended
Terminator is specially designed for automatic termination of Single-
Ended or Low Voltage Differential SCSI Bus. The Multi-Mode operation of
this device allows for a transition system design for the next generation
SCSI Parallel Interface (SPI-2). Compliant with SPI-2, with SPI and Fast-
20 the UCC5510 incorporates all the functions necessary to properly ter-
minate the SCSI Bus and has internal thermal shut down and short cir-
cuit limiting.
• 3.0V to 5.25V Operation
• Differential Failsafe Bias
• Thermal Packaging for Low Junction
Temperature and Better MTBF
• Master/Slave Inputs
• Supports Active Negation
• 3pF Channel Capacitance
BLOCK DIAGRAM
SOURCE 5 < 15mA
SINK 200µA MAXIMUM (NOISE LOAD)
TRMPWR 38
MSTR/SLV 19
+VDD
REF 1.3V
20 DIFFSENS
1.3V ± –0.1V
2.2 > 1.9V
0.7 > 0.6V
DEVICE MODE
SELECT LOGIC
DIFFB 21
110
REF 2.7V
125
+50mV TO +62.5mV
52
52
REF 1.25V
5
4
L1–
L1+
HS/GND
8
110
125
HS/GND 28
HS/GND 27
HS/GND 26
HS/GND 10
+50mV TO +62.5mV
52
52
32 L9–
31 L9+
HS/GND
9
SWITCHES UP ARE SINGLE
ENDED SWITCHES DOWN ARE
LOW VOLTAGE DIFFERENTIAL
SE GND
SWITCH
GND 18
1
REG
Circuit Design Patented
UDG-98033
SLUS332A - OCTOBER 1999
UC5510
CONNECTION DIAGRAM
ABSOLUTE MAXIMUM RATINGS
SSOP-36 (Top View)
MWP Package
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6V
Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . 0V to TRMPWR
Package Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . 2W
Storage Temperature . . . . . . . . . . . . . . . . . . . –65°C to +150°C
Junction Temperature. . . . . . . . . . . . . . . . . . . –55°C to +150°C
Lead Temperature (Soldering, 10sec.) . . . . . . . . . . . . . +300°C
REG
N/C
1
2
3
4
5
6
7
8
9
36 TRMPWR
35
34
33
N/C
N/C
N/C
N/C
RECOMMENDED OPERATING CONDITIONS
TRMPWR Voltage . . . . . . . . . . . . . . . . . . . . . . . 3.0V TO 5.25V
L1+
L1–
32 L9–
All voltages are with respect to pin 1. Currents are positive into,
negative out of the specified terminal. Consult Packaging Sec-
tion of the Databook for thermal limitations and considerations of
packages.
L2+
31 L9+
L2–
30 L8–
HS/GND
HS/GND
29 L8+
28 HS/GND
27 HS/GND
26 HS/GND
25 L7–
HS/GND 10
L3+ 11
L3– 12
L4+ 13
L4– 14
L5+ 15
L5– 16
N/C 17
GND 18
24 L7+
23 L6–
22 L6+
21 DIFF B
20 DIFFSENS
19 MSTR/SLV
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V.
PARAMETER
TRMPWR Supply Current Section
TRMPWR Supply Current
TEST CONDITIONS
MIN
TYP
MAX UNITS
20
35
mA
Disable Terminator, in DISCNCT mode.
µA
Regulator Section
1.25V Regulator
LVD Mode
1.15
–80
80
1.25
–100
100
1.35
V
1.25V Regulator Source Current
1.25V Regulator Sink Current
1.3V Regulator
LVD Mode, Differential Sense Floating
LVD Mode, Differential Sense Floating
DIFFSENS
mA
mA
V
1.2
–5
1.3
1.4
–15
200
3
1.3V Regulator Source Current
1.3V Regulator Sink Current
2.7V Regulator
DIFFSENS
mA
µA
V
DIFFSENS
50
Single Ended Mode
Single Ended Mode
Single Ended Mode
VTRMPWR – (VREG – 3.0 Min)
2.5
2.7
2.7V Regulator Source Current
2.7V Regulator Sink Current
2.7V Regulator Dropout Voltage
–200 –400 –800
mA
mA
mV
100
200
400
200
2
UC5510
ELECTRICAL CHARACTERISTICS: Unless otherwise specified, TA = 0°C to 70°C, TRMPWR = 3.3V.
PARAMETER
Differential Termination Section
Differential Impedance
Common Mode Impedance
Differential Bias Voltage
Common Mode Bias
TEST CONDITIONS
MIN
TYP
MAX UNITS
100
110
100
105
125
110
165
125
Ω
Ω
Drivers Tri-stated
mV
V
1.25
Output Capacitance
Single Ended Measurement to Ground (Note 1)
3
pF
Single Ended Termination Section
Impedance
102.3
–21
110
–23
117.7
–24
–22.4
400
3
Ω
mA
mA
nA
pF
Ω
Termination Current
Signal Level 0.2V
Signal Level 0.5V
Output Leakage
Disabled, TRMPWR = 0V to 5.25V
Single Ended Measurement to Ground (Note 1)
Output Capacitance
Single Ended GND SW Impedance
Differential Sense (DIFF B) Input Sections
DIFFB Single Ended Threshold
DIFFB Sense LVD Threshold
DIFFB Input Current
60
0.6
1.9
0.7
2.2
10
V
V
VDIFFB = 0V and 3.3V
–10
µA
Master/Slave (MSTR/SLV) Input Section
MSTR/SLV Threshold
0.8
2
V
MSTR/SLV Input Current
–30
30
µA
Note 1: Guaranteed by design. Not 100% tested in production.
PIN DESCRIPTIONS
negative line in differential applications for the SCSI bus.
DIFFB: DIFF SENSE filter pin should be connected to a
0.1µF capacitor to GND and 20k resistor to SCSI/Bus
DIFF SENSE Line.
L1+ thru L9+: Ground line for single ended or positive
line for differential applications for the SCSI bus.
DIFFSENS: The SCSI bus DIFF SENSE line is driven to
1.3V to detect what type of devices are connected to the
SCSI bus.
MSTR/SLV: Mode select for the non-controlling termina-
tor. MSTR enables the 1.3V regulator, when the termina-
tor is enabled. Note: This function will be removed on
further generations of the multimode terminators.
HS/GND: Heat Sink GND. Connect to large area PC
board traces to increase power dissipation capability.
REG: Regulator bypass, must be connected to a 4.7µF
capacitor.
GND: Power Supply Return.
TRMPWR: VIN 3.0V to 5.25V supply.
L1– thru L9–: Signal line/active line for single ended or
3
UC5510
APPLICATION INFORMATION
L1+
L1–
L1+
L1–
TRMPWR
36 TRMPWR
TRMPWR 36
MSTR/SLV 19
TRMPWR
19 MSTR/SLV
CONTROL LINES (9)
L9+
L9–
L9+
L9–
DIFFSENS 20
DIFFB 21
20 DIFFSENS
21 DIFFB
1
REG
REG
1
20k
20k
4.7µF
4.7µF
0.1µF
0.1µF
4.7µF
4.7µF
L10+
L10–
L10+
L10–
36 TRMPWR
19 MSTR/SLV
TRMPWR 36
MSTR/SLV 19
DATA LINES + PARITY
L18+
L18–
L18+
L18–
DIFFSENS 20
DIFFB 21
NO CONNECT
20 DIFFSENS
21 DIFFB
1
REG
REG
1
4.7µF
4.7µF
L19+
L19–
L19+
L19–
36 TRMPWR
19 MSTR/SLV
TRMPWR 36
MSTR/SLV 19
DATA LINES + PARITY
L27+
L27–
L27+
L27–
1
REG
REG
1
DIFFSENS 20
DIFFB 21
NO CONNECT
20 DIFFSENS
21 DIFFB
4.7µF
4.7µF
UDG-98034a
Figure 1. Application Drawing
The master is selected by placing TRMPWR on in the MWP package where between L8 and L9 the bal-
MSTR/SLV and enabling the 1.3V regulator. The master ance is 0.23pF and 0.4pF respecitvely The negative (–)
is the only terminator connected directly to the DIFF- signal line has a higher capacitance than the positive (+)
SENS bus line. All the other terminators receive a mode signal line. The FQP package has typically 0.2pF less
signal by connecting the DIFFB pins together.
capacitance than the MWP package, where the typical
balance is 0.1pF except for L8 and L3, where the bal-
ance is 0.4pF.
The balancing capacitor is very important during high
speed operation. The typical capacitor balance between
the positive (+) and negative (–) signals is 0.1pF, except
Note: The master/slave function will not be included in future
Unitrode terminators.
UNITRODE CORPORATION
7 CONTINENTAL BLVD. • MERRIMACK, NH 03054
TEL. (603) 424-2410 • FAX (603) 424-3460
4
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
1 of 2
Applications
Products
Development Tools
Search
>> Semiconductor Home > Products > Analog & Mixed-Signal > Interface Products > Bus Terminators > SCSI >
UCC5510, 9-LINE MULTIMODE TERMINATOR FOR PLUGS AND CONNECTORS
Device Status: Active
> Description
> Features
> Datasheets
Parameter Name
Number of Lines
UCC5510
9
> Pricing/Samples/Availability
> Application Notes
> Applications
Driver Types Supported
LVD, SE
5.25
TERMPWR Voltage (max) (V)
TERMPWR Voltage (min) (V)
3.0
Integrated SPI-3 Mode Switching Filter/Delay No
Process
Bi-CMOS
Active Negation Support
Channel Capacitance (pF)
Resistor Tolerance (ppm)
Typical Sink Current (mA)
Current Tolerance (%)
Yes
3
500
100
4
Single-Ended Termination Impedance (ohms) 110
Single-Ended Tolerance (%)
LVD Termination Impedance (ohms)
LVD Tolerance (%)
7
105
5
Commonmode Impedance (ohms)
Integrated TERMPWR Regulation
125
No
Description
The UCC5510 Multi-Mode Low Voltage Differential and Single Ended Terminator is
specially designed for automatic termination of Single-Ended or Low Voltage Differential
SCSI Bus. The Multi-Mode operation of this device allows for a transition system design for
the next generation SCSI Parallel Interface (SPI-2). Compliant with SPI-2, with SPI and
Fast-20 the UCC5510 incorporates all the functions necessary to properly terminate the
SCSI Bus and has internal thermal shut down and short circuit limiting.
2 of 2
Features
l
l
l
l
l
l
l
Auto Selection Multi-Mode Single Ended or Low Voltage Differential Termination
3.0V to 5.25V Operation
Differential Failsafe Bias
Thermal Packaging for Low Junction Temperature and Better MTBF
Master/Slave Inputs
Supports Active Negation
3pF Channel Capacitance
To view the following documents, Acrobat Reader 3.x is required.
To download a document to your hard drive, right-click on the link and choose 'Save'.
Datasheets
Full datasheet in Acrobat PDF: slus332a.pdf (47 KB)
Full datasheet in Zipped PostScript: slus332a.psz (35 KB)
Pricing/Samples/Availability
Price/unit
USD (100-999)
Orderable Device Package Pins Temp (ºC)
Status
Pack Qty Availability / Samples
UCC5510MWP
DGK
36 0 TO 70
36 0 TO 70
36 0 TO 70
ACTIVE
3.43
1
Check stock or order
UCC5510MWP-TR UTR
UCC5510MWPTR DGK
OBSOLETE
ACTIVE
3.07
1
Check stock or order
Application Reports
l COMPARING BUS SOLUTIONS (SLLA067 - Updated: 03/06/2000)
l ELECTROSTATIC DISCHARGE APPLICATION NOTE (SSYA008 - Updated: 05/05/1999)
l JITTER ANALYSIS (SLLA075 - Updated: 03/31/2000)
l THERMAL CHARACTERISTICS OF LINEAR AND LOGIC PACKAGES USING JEDEC PCB
DESIGNS (SZZA017A - Updated: 09/10/1999)
Table Data Updated on: 8/15/2000
© Copyright 2000 Texas Instruments Incorporated. All rights reserved. Trademarks | Privacy Policy
相关型号：
UCC5606DP
Lowest Capacitance 9-Line 3-5V SE Terminator for SCSI Through Ultra SCSI with Reverse Disconnect 16-SOIC 0 to 70
TI
©2020 ICPDF网 联系我们和版权申明