W132-10BX [ROCHESTER]

132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-153AE, TSSOP-24;


型号：	W132-10BX
厂家：	Rochester Electronics
描述：	132 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO24, MO-153AE, TSSOP-24 驱动光电二极管输出元件逻辑集成电路
文件：	总8页 (文件大小：886K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

THIS SPEC IS OBSOLETE

Spec No: 38-07216

Spec Title: W132 Spread Aware(TM), Ten/Eleven Output Zero

Delay Buffer

Sunset Owner: RGL

Replaced by: N/A

1W132

W132

Spread Awareª, Ten/Eleven Output Zero Delay Buffer

Features

Key Specifications

• Spread Aware™—designed to work with SSFTG refer-

Operating Voltage: ................................................ 3.3V±10%

Operating Range: ........................25 MHz < f_OUT< 140 MHz

Cycle-to-Cycle Jitter: ................................................<150 ps

Output to Output Skew: ............................................<100 ps

Phase Error Jitter: .....................................................<125 ps

ence signals

• Well suited to both 100- and 133-MHz designs

• Ten (-09B) or Eleven (-10B) LVCMOS/LVTTL outputs

• Single output enable pin for -10 version, dual pins on

-09 devices allow shutting down a portion of the out-

puts.

• 3.3V power supply

• On board 25W damping resistors

• Available in 24-pin TSSOP package

Block Diagram

Pin Configurations

FBIN

FBOUT

PLL

AGND

VDD

GND

CLK

AVDD

VDD

CLK

OE0:4

GND

VDD

OE5:8

VDD

FBIN

FBOUT

AGND

VDD

GND

CLK

AVDD

VDD

configuration of these blocks dependent upon specific option being used

GND

VDD

OE0:4

FBOUT

VDD

OE5:8

FBIN

Spread Aware is a trademark of Cypress Semiconductor Corporation.

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07216 Rev. OBS

Revised December 02, 2004

W132

Pin Definitions

Pin No.

(-10B)

Name

CLK

(-09B)

Type

Pin Description

Reference Input: Output signals Q0:9 will be synchronized to this signal.

FBIN

Feedback Input: This input must be fed by one of the outputs (typically FBOUT)

to ensure proper functionality. If the trace between FBIN and FBOUT is equal in

length to the traces between the outputs and the signal destinations, then the

signals received at the destinations will be synchronized to the CLK signal input.

Q0:8

3, 4, 5, 8,

9, 16, 17,

20, 21

3, 4, 5, 8,

9, 15, 16,

17, 20

Integrated Series Resistor Outputs: The frequency and phase of the signals

provided by these pins will be equal to the reference signal if properly laid out.

Each output has a 25Ω series damping resistor integrated.

Integrated Series Resistor Output: The frequency and phase of the signal

provided by this pin will be equal to the reference signal if properly laid out. This

output has a 25Ω series damping resistor integrated.

Feedback Output: This output has a 25Ω series resistor integrated on chip.

Typically it is connected directly to the FBIN input with a trace equal in length to

the traces between outputs Q0:9 and the destination points of these output

signals.

n/a

FBOUT

AVDD

2, 10, 15,

2, 10, 14,

Analog Power Connection: Connect to 3.3V. Use ferrite beads to help reduce

noise for optimal jitter performance.

AGND

VDD

Analog Ground Connection: Connect to common system ground plane.

Power Connections: Connect to 3.3V. Use ferrite beads to help reduce noise

for optimal jitter performance.

GND

6, 7, 18,

n/a

6, 7, 18,

Ground Connections: Connect to common system ground plane.

n/a

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) all outputs are disabled to a LOW state.

OE0:4

OE5:8

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) outputs Q0:4 are disabled to a LOW state.

Output Enable Input: Tie to V_DD(HIGH, 1) for normal operation. when brought

to GND (LOW, 0) outputs Q5:8 are disabled to a LOW state.

on the DIMM. The W132 takes in the signal from the mother-

board and buffers out clock signals with enough drive to sup-

Overview

The W132 is a PLL-based clock driver designed for use in dual

inline memory modules. The clock driver has output frequen-

cies of up to 133 MHz and output to output skews of less than

250 ps. The W132 provides minimum cycle-to-cycle and long

term jitter, which is of significant importance to meet the tight

input-to-input skew budget in DIMM applications.

The current generation of 256 and 512 megabyte memory

modules needs to support 100-MHz clocking speeds. Espe-

cially for cards configured in 16x4 or 8x8 format, the clock

signal provided from the motherboard is generally not strong

enough to meet all the requirements of the memory and logic

port all the DIMM board clocking needs. The W132 is also

designed to meet the needs of new PC133 SDRAM designs,

operating to 133 MHz.

The W132 was specifically designed to accept SSFTG signals

currently being used in motherboard designs to reduce EMI.

Zero delay buffers which are not designed to pass this feature

through may cause skewing failures.

Output enable pins allow for shutdown of output when they are

not being used. This reduces EMI and power consumption.

Document #: 38-07216 Rev. OBS

Page 2 of 6

W132

AGND

VDD

GND

AVDD

VDD

3.3V

0.1µ

10µF

0.1µ

10µ

VDD

GND

VDD

0.1µF

VDD

FBIN

VDD

0.1µ

FBOUT

Figure 1. Schematic

If it is desirable to either add a little delay, or slightly precede

the input signal, this may also be affected by either making the

trace to the FBIN pin a little shorter or a little longer than the

traces to the devices being clocked.

Spread Aware

Many systems being designed now utilize a technology called

Spread Spectrum Frequency Timing Generation. Cypress has

been one of the pioneers of SSFTG development, and we de-

signed this product so as not to filter off the Spread Spectrum

feature of the Reference input, assuming it exists. When a zero

delay buffer is not designed to pass the SS feature through,

the result is a significant amount of tracking skew which may

cause problems in systems requiring synchronization.

For more details on Spread Spectrum timing technology,

please see the Cypress application note titled, ÒEMI Suppres-

sion Techniques with Spread Spectrum Frequency Timing

Generator (SSFTG) ICs.Ó

Inserting Other Devices in Feedback Path

Another nice feature available due to the external feedback is

the ability to synchronize signals up to the signal coming from

some other device. This implementation can be applied to any

device (ASIC, multiple output clock buffer/driver, etc.) which is

put into the feedback path.

Referring to Figure 2, if the traces between the ASIC/buffer

and the destination of the clock signal(s) (A) are equal in length

to the trace between the buffer and the FBIN pin, the signals

at the destination(s) device will be driven high at the same time

the Reference clock provided to the ZDB goes high. Synchro-

nizing the other outputs of the ZDB to the outputs form the

ASIC/Buffer is more complex however, as any propagation de-

lay in the ASIC/Buffer must be accounted for.

How to Implement Zero Delay

Typically, zero delay buffers (ZDBs) are used because a de-

signer wants to provide multiple copies of a clock signal in

phase with each other. The whole concept behind ZDBs is that

the signals at the destination chips are all going HIGH at the

same time as the input to the ZDB. In order to achieve this,

layout must compensate for trace length between the ZDB and

the target devices. The method of compensation is described

below.

External feedback is the trait that allows for this compensation.

The PLL on the ZDB will cause the feedback signal to be in

phase with the reference signal. When laying out the board,

match the trace lengths between the output being used for

feed back and the FBIN input to the PLL.

Reference

Zero

Signal

Delay

Buffer

ASIC/

Buffer

Feedback

Input

Figure 2. 6 Output Buffer in the Feedback Path

Document #: 38-07216 Rev. OBS

Page 3 of 6

W132

Absolute Maximum Ratings^[1]

Stresses greater than those listed in this table may cause per-

above those specified in the operating sections of this specifi-

cation is not implied. Maximum conditions for extended peri-

ods may affect reliability.

manent damage to the device. These represent a stress rating

only. Operation of the device at these or any other conditions

Parameter

V_DD, V_IN

T_STG

T_A

T_B

P_D

Description

Voltage on any pin with respect to GND

Storage Temperature

Operating Temperature

Ambient Temperature under Bias

Power Dissipation

Rating

Ð0.5 to +7.0

Ð65 to +150

0 to +70

Ð55 to +125

0.5

Unit

ûC

DC Electrical Characteristics: T_A=0ûC to 70ûC, V_DD= 3.3V ±10%

Parameter

Description

Supply Current

Test Condition

Unloaded, 100 MHz

Min

Typ

Max

200

0.8

Unit

µA

I_DD

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Voltage

Input High Voltage

Output Low Voltage

Output High Voltage

Input Low Current

Input High Current

2.0

2.1

I_OL= 12 mA

I_OH= Ð12 mA

V_IN= 0V

0.8

I_IH

V_IN= V_DD

AC Electrical Characteristics: T_A= 0ûC to +70ûC, V_DD= 3.3V ±10%

Parameter

f_OUT

t_R

Description

Test Condition

Min

Typ

Max

140

2.1

2.5

4.5

350

100

Unit

MHz

Output Frequency

30-pF load^[5]

Output Rise Time

0.8V to 2.0V, 30-pF load

2.0V to 0.8V, 30-pF load

t_F

Output Fall Time

t_ICLKR

t_ICLKF

t_PEJ

Input Clock Rise Time^[2]

Input Clock Fall Time^[2]

CLK to FBIN Skew Variation^{[3, 4]}

Output to Output Skew

Duty Cycle

Measured at V_DD/2

All outputs loaded equally

30-pF load

Ð350

Ð100

t_SK

t_D

t_LOCK

PLL Lock Time

Power supply stable

1.0

150

t_JC

Jitter, Cycle-to-Cycle

Notes:

1. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

2. Longer input rise and fall time will degrade skew and jitter performance.

3. Skew is measured at V /2 on rising edges.

4. Duty cycle is measured at V /2.

5. Production tests are run at 133 MHz.

Ordering Information

Ordering Code

W132

Option

Package Type

-09B, -10B X = 24-pin TSSOP

Document #: 38-07216 Rev. OBS

Page 4 of 6

W132

Package Diagram

24-Pin Thin Shrink Small Outline Package (TSSOP)

Document #: 38-07216 Rev. OBS

Page 5 of 6

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W132

Document Title: W132 Spread Awareª, Ten/Eleven Output Zero Delay Buffer

Document Number: 38-07216

Issue

Orig. of

REV.

ECN NO.

110481

122835

294835

Date

Change

Description of Change

Change from Spec number: 38-00792 to 38-07216

Add Power up Requirements to Maximum Ratings Information

To Obsolete the DS

12/15/01

12/22/02

See ECN

SZV

RBI

RGL

OBS

Document #: 38-07216 Rev. OBS

Page 6 of 6

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