X9258US24-2.7 [ROCHESTER]
QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, 0.300 INCH, PLASTIC, MS-013ADC, SOIC-24;
| 型号： | X9258US24-2.7 |
| 厂家： | 
Rochester Electronics |
| 描述： | QUAD 100K DIGITAL POTENTIOMETER, 2-WIRE SERIAL CONTROL INTERFACE, 256 POSITIONS, PDSO24, 0.300 INCH, PLASTIC, MS-013ADC, SOIC-24 光电二极管 转换器 电阻器 |
| 文件： | 总21页 (文件大小：1328K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
X9258
Low Noise/Low Power/2-Wire Bus/256 Taps
Data Sheet
April 14, 2011
FN8168.5
Quad Digital Controlled Potentiometers
(XDCP™)
Features
• Four potentiometers in one package
The X9258 integrates 4 digitally controlled potentiometers
(XDCP™) on a monolithic CMOS integrated circuit.
• 256 resistor taps/potentiometer................. 0.4% resolution
• 2-wire serial interface
The digitally controlled potentiometer is implemented using
255 resistive elements in a series array. Between each
element are tap points connected to the wiper terminal
through switches. The position of the wiper on the array is
controlled by the user through the 2-wire bus interface. Each
potentiometer has associated with it a volatile Wiper Counter
Register (WCR) and 4 non-volatile Data Registers
(DR0:DR3) that can be directly written to and read by the
user. The contents of the WCR controls the position of the
wiper on the resistor array though the switches. Power-up
recalls the contents of DR0 to the WCR.
• Wiper resistance, 40Ω typical @ V+ = 5V, V- = -5V
• Four nonvolatile data registers for each potentiometer
• Nonvolatile storage of wiper position
• Standby current <5µA max (total package)
• Power supplies
- V
CC
= 2.7V to 5.5V
- V+ = 2.7V to 5.5V
- V- = -2.7V to -5.5V
• 100kΩ, 50kΩ total potentiometer resistance
The XDCP™ can be used as a three-terminal potentiometer
or as a two-terminal variable resistor in a wide variety of
applications including control, parameter adjustments, and
signal processing.
• High reliability
- Endurance: 100,000 data changes per bit per register
- Register data retention . . . . . . . . . . . . . . . . . . 100 years
• 24 Ld SOIC, 24 Ld TSSOP
• Dual supply version of X9259
• Pb-free available (RoHS compliant)
Block Diagram
POT 0
V
CC
SS
V
R
R
R
R
V
/R
R
R
R
R
0
2
1
3
H0 H0
0
2
1
3
WIPER
COUNTER
REGISTER
(WCR)
WIPER
COUNTER
REGISTER
(WCR)
V
/R
H2 H2
RESISTOR
ARRAY
POT 2
V+
V-
V
/R
L0 L0
WP
V
/R
L2 L2
V
/R
SCL
SDA
A0
W0 W0
V
/R
W2 W2
INTERFACE
AND
CONTROL
CIRCUITRY
A1
8
A2
V
/R
A3
W1 W1
DATA
V
/R
W3 W3
R
R
R
R
0
2
1
3
V
/R
H1 H1
R
R
R
WIPER
COUNTER
REGISTER
(WCR)
0
2
1
3
V
/R
WIPER
COUNTER
REGISTER
(WCR)
H3 H3
RESISTOR
ARRAY
POT 1
RESISTOR
ARRAY
POT 3
R
V
/R
L1 L1
V
/R
L3 L3
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas Inc. 2005, 2006, 2011. All Rights Reserved
XDCP is a trademark of Intersil Americas Inc. Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
X9258
Ordering Information
POTENTIOMETER TEMPERATURE
PART
MARKING
V
LIMITS
(V)
ORGANIZATION
RANGE
(°C)
PKG.
DWG. #
CC
PART NUMBER
(kΩ)
PACKAGE
,
X9258US24* **
X9258US
5 ±10
100
0 to +70
0 to +70
24 Ld SOIC (300 mil)
M24.3
,
X9258US24Z* ** (Note)
X9258US Z
X9258US I
X9258US ZI
X9258UV
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
,
X9258US24I* **
-40 to +85
-40 to +85
0 to +70
,
X9258US24IZ* ** (Note)
X9258UV24
50
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
MDP0044
MDP0044
X9258UV24I
X9258UV I
X9258UV ZI
X9258TS
-40 to +85
-40 to +85
0 to +70
X9258UV24IZ (Note)
X9258TS24*
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
100
X9258TS24Z (Note)
X9258TS24I*
X9258TS Z
X9258TS I
X9258TS ZI
X9258TV
0 to +70
-40 to +85
-40 to +85
0 to +70
X9258TS24IZ* (Note)
X9258TV24
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
24 Ld SOIC (300 mil)
MDP0044
X9258TV24I
X9258TV I
X9258US F
X9258US ZF
X9258US G
-40 to +85
0 to +70
MDP0044
M24.3
X9258US24-2.7*
X9258US24Z-2.7* (Note)
2.7 to 5.5
0 to +70
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
X9258US24I-2.7*
,
-40 to +85
-40 to +85
0 to +70
X9258US24IZ-2.7* ** (Note) X9258US ZG
X9258UV24-2.7*
X9258UV F
X9258UV G
X9258UV ZG
X9258TS F
X9258TS ZF
X9258TS G
X9258TS ZG
X9258TV F
X9258TV G
X9258TV ZG
X9258TV ZF
50
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
MDP0044
MDP0044
X9258UV24I-2.7
-40 to +85
-40 to +85
0 to +70
X9258UV24IZ-2.7 (Note)
X9258TS24-2.7*
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
24 Ld SOIC (300 mil) M24.3
24 Ld SOIC (300 mil) (Pb-free) M24.3
100
X9258TS24Z-2.7* (Note)
X9258TS24I-2.7*
0 to +70
-40 to +85
-40 to +85
0 to +70
X9258TS24IZ-2.7* (Note)
X9258TV24-2.7
24 Ld TSSOP (4.4mm)
24 Ld TSSOP (4.4mm)
MDP0044
MDP0044
X9258TV24I-2.7
-40 to +85
-40 to +85
0 to +70
X9258TV24IZ-2.7 (Note)
X9258TV24Z-2.7 (Note)
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
24 Ld TSSOP (4.4mm) (Pb-free) MDP0044
*Add “T1” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
**Add “T2” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100%
matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-
020.
FN8168.5
April 14, 2011
2
X9258
Pinout
X9258
(24 LD SOIC, TSSOP)
TOP VIEW
A3
NC
A0
1
24
SCL
2
3
23
22
V
/R
W3 W3
V
V
V
/R
L2 L2
V
/R
H3 H3
/R
4
5
21
20
H2 H2
V
/R
/R
L3 L3
W2 W2
V–
V
V+
6
7
19
18
X9258
V
CC
SS
V
V
V
/R
V
/R
8
9
17
16
W1 W1
L0 L0
V
/R
/R
H0 H0
H1 H1
V
/R
/R
W0 W0
10
15
14
L1 L1
A1
A2
11
12
WP
13
SDA
Analog Supplies V+, V-
Pin Descriptions
Host Interface Pins
SERIAL CLOCK (SCL)
The Analog Supplies V+, V- are the supply voltages for the
DCP analog section.
Pin Names
The SCL input is used to clock data into and out of the
X9258.
SYMBOL
DESCRIPTION
Serial Clock
SERIAL DATA (SDA)
SCL
SDA is a bidirectional pin used to transfer data into and out
of the device. It is an open drain output and may be wire-
ORed with any number of open drain or open collector
outputs. An open drain output requires the use of a pull-up
resistor. For selecting typical values, refer to “Guidelines for
Calculating Typical Values of Bus Pull-Up Resistors” on
page 10.
SDA
Serial Data
A0 thru A3
Device Address
V
V
/R thru V /R
,
Potentiometer Pins
(terminal equivalent)
H0 H0 H3 H3
/R thru V /R
L0 L0 L3 L3
V
/R
thru V /R
Potentiometers Pins
(wiper equivalent)
W0 W0 W3 W3
WP
V+, V-
Hardware Write Protection
Analog Supplies
DEVICE ADDRESS (A - A )
0
3
The Address inputs are used to set the least significant 4 bits
of the 8-bit slave address. A match in the slave address
serial data stream must be made with the address input in
order to initiate communication with the X9258. A maximum
of 16 devices may occupy the 2-wire serial bus.
V
System Supply Voltage
System Ground
CC
V
SS
NC
No Connection (Allowed)
Potentiometer Pins
Principles Of Operation
V /R (V /R - V /R ), V /R (V /R - V /R
)
H
H
H0 H0 H3 H3 L0 L0 L3 L3
L
L
The X9258 is a highly integrated microcircuit incorporating
four resistor arrays and their associated registers and
counters and the serial interface logic providing direct
communication between the host and the DCP
potentiometers.
The V /R and V /R inputs are equivalent to the terminal
H
H
L
L
connections on either end of a mechanical potentiometer.
V
/R (V /R - V /R
)
W
W
W0 W0 W3 W3
The wiper outputs are equivalent to the wiper output of a
mechanical potentiometer.
Serial Interface (2-Wire)
The X9258 supports a bidirectional bus oriented protocol.
The protocol defines any device that sends data onto the
bus as a transmitter and the receiving device as the receiver.
The device controlling the transfer is a master and the
device being controlled is the slave. The master will always
Hardware Write Protect Input (WP)
The WP pin when low prevents nonvolatile writes to the Data
Registers.
FN8168.5
April 14, 2011
3
X9258
initiate data transfers and provide the clock for both transmit
and receive operations. Therefore, the X9258 will be
considered a slave device in all applications.
Device Addressing
Following a start condition the master must output the
address of the slave it is accessing. The most significant
4 bits of the slave address are the device type identifier
(refer to Figure 1). For the X9258 this is fixed as 0101[B].
Clock and Data Conventions
Data states on the SDA line can change only during SCL
DEVICE TYPE
IDENTIFIER
LOW periods (t
are reserved for indicating start and stop conditions.
). SDA state changes during SCL HIGH
LOW
Start Condition
0
1
0
1
A3
A2
A1
A0
All commands to the X9258 are preceded by the start
condition, which is a HIGH to LOW transition of SDA while
SCL is HIGH (t
). The X9258 continuously monitors the
DEVICE ADDRESS
HIGH
SDA and SCL lines for the start condition and will not
respond to any command until this condition is met.
FIGURE 1. SLAVE ADDRESS
The next 4 bits of the slave address are the device address.
The physical device address is defined by the state of the A0
thru A3 inputs. The X9258 compares the serial data stream
with the address input state; a successful compare of all
4 address bits is required for the X9258 to respond with an
Stop Condition
All communications must be terminated by a stop condition,
which is a LOW to HIGH transition of SDA while SCL is
HIGH.
acknowledge. The A thru A inputs can be actively driven
0
3
Acknowledge
by CMOS input signals or tied to V
or V .
SS
CC
Acknowledge is a software convention used to provide a
positive handshake between the master and slave devices
on the bus to indicate the successful receipt of data. The
transmitting device, either the master or the slave, will
release the SDA bus after transmitting 8 bits. The master
generates a ninth clock cycle and during this period the
receiver pulls the SDA line LOW to acknowledge that it
successfully received the 8 bits of data.
Acknowledge Polling
The disabling of the inputs (during the internal nonvolatile
write operation), can be used to take advantage of the
typical 5ms nonvolatile write cycle time. Once the stop
condition is issued to indicate the end of the nonvolatile write
command, the X9258 initiates the internal write cycle. ACK
polling can be initiated immediately. This involves issuing the
start condition followed by the device slave address. If the
X9258 is still busy with the write operation, no ACK will be
returned. If the X9258 has completed the write operation an
ACK will be returned and the master can then proceed with
the next operation.
The X9258 will respond with an acknowledge after
recognition of a start condition and its slave address and
once again after successful receipt of the command byte. If
the command is followed by a data byte, the X9258 will
respond with a final acknowledge.
Array Description
The X9258 is comprised of four resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (V /R
H
H
and V /R inputs).
L
L
At both ends of each array and between each resistor
segment is a CMOS switch connected to the wiper (V )
W
output. Within each individual array only one switch may be
turned on at a time. These switches are controlled by the
Wiper Counter Register (WCR). The 8 bits of the WCR are
decoded to select, and enable, one of 256 switches.
The WCR may be written directly, or it can be changed by
transferring the contents of one of four associated data
registers into the WCR. These data registers and the WCR
can be read and written by the host system.
FN8168.5
April 14, 2011
4
X9258
.
ACK Polling Sequence
REGISTER
SELECT
NONVOLATILE WRITE
COMMAND COMPLETED
ENTER ACK POLLING
I3
I2
I1
I0
R1
R0
P1
P0
WIPER COUNTER
REGISTER SELECT
INSTRUCTIONS
ISSUE
START
FIGURE 2. INSTRUCTION BYTE FORMAT
The four high order bits define the instruction. The next 2 bits
(R1 and R0) select one of the four registers that is to be
acted upon when a register oriented instruction is issued.
The last bits (P1, P0) select which one of the four
ISSUE SLAVE
ADDRESS
ISSUE STOP
potentiometers is to be affected by the instruction.
ACK
NO
RETURNED?
Four of the nine instructions end with the transmission of the
instruction byte. The basic sequence is illustrated in
Figure 3. These two-byte instructions exchange data
between the Wiper Counter Register and one of the data
registers. A transfer from a Data Register to a Wiper Counter
Register is essentially a write to a static RAM. The response
YES
FURTHER
OPERATION?
NO
of the wiper to this action will be delayed t
from the Wiper Counter Register (current wiper position), to
a data register is a write to nonvolatile memory and takes a
. A transfer
WRL
YES
ISSUE
INSTRUCTION
ISSUE STOP
PROCEED
minimum of t
to complete. The transfer can occur
WR
between one of the four potentiometers and one of its
associated registers; or it may occur globally, wherein the
transfer occurs between all of the potentiometers and one of
their associated registers.
PROCEED
Four instructions require a three-byte sequence to complete.
These instructions transfer data between the host and the
X9258; either between the host and one of the data registers
or directly between the host and the Wiper Counter Register.
These instructions are: Read Wiper Counter Register (read
the current wiper position of the selected potentiometer),
Write Wiper Counter Register (change current wiper position
of the selected potentiometer), Read Data Register (read the
contents of the selected nonvolatile register) and Write Data
Register (write a new value to the selected data register).
The sequence of operations is shown in Figure 4.
Instruction Structure
The next byte sent to the X9258 contains the instruction and
register pointer information. The four most significant bits are
the instruction. The next four bits point to one of the two
potentiometers and when applicable they point to one of four
associated registers. The format is shown in Figure 2.
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1 I0
R1 R0 P1 P0
A
C
K
S
T
O
P
FIGURE 3. TWO-BYTE INSTRUCTION SEQUENCE
FN8168.5
April 14, 2011
5
X9258
The Increment/Decrement command is different from the
other commands. Once the command is issued and the
X9258 has responded with an acknowledge, the master can
clock the selected wiper up and/or down in one segment
steps; thereby, providing a fine tuning capability to the host.
Similarly, for each SCL clock pulse while SDA is LOW, the
selected wiper will move one resistor segment towards the
V /R terminal. A detailed illustration of the sequence and
L
L
timing for this operation are shown in Figures 5 and 6
respectively.
For each SCL clock pulse (t
) while SDA is HIGH, the
HIGH
selected wiper will move one resistor segment towards the
terminal.
V
H
TABLE 1. INSTRUCTION SET
INSTRUCTION SET
INSTRUCTION
I
I
I
I
R
R
P
P
OPERATION
3
2
1
0
1
0
1
0
Read Wiper Counter Register
Write Wiper Counter Register
Read Data Register
1
1
1
1
1
1
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
0
1/0
1/0
1/0
1/0
1/0
1/0
0
1/0 Read the contents of the Wiper Counter Register pointed to
by P - P
1
0
0
0
1/0 Write new value to the Wiper Counter Register pointed to by
P - P
1
0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0 Read the contents of the Data Register pointed to by P - P
1 0
and R - R
1
0
Write Data Register
1/0 Write new value to the Data Register pointed to by P - P
1 0
and R - R
1
0
XFR Data Register to Wiper
Counter Register
1/0 Transfer the contents of the Data Register pointed to by
P - P and R - R to its associated Wiper Counter Register
1
0
1
0
XFR Wiper Counter Register to
Data Register
1/0 Transfer the contents of the Wiper Counter Register pointed
to by P - P to the Data Register pointed to by R - R
1
0
1
0
Global XFR Data Registers to
Wiper Counter Registers
0
Transfer the contents of the Data Registers pointed to by
R - R of all four potentiometers to their respective Wiper
1
0
Counter Registers
Global XFR Wiper Counter
Registers to Data Register
1
0
0
0
0
1
0
0
1/0
0
1/0
0
0
0
Transfer the contents of both Wiper Counter Registers to
their respective data Registers pointed to by R - R of all
1
0
four potentiometers
Increment/Decrement Wiper
Counter Register
1/0
1/0 Enable Increment/decrement of the Control Latch pointed to
by P - P
1
0
NOTE:
1. 1/0 = data is one or zero.
FN8168.5
April 14, 2011
6
X9258
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3 I2
I1 I0
R1 R0 P1 P0
A
C
K
D7 D6 D5 D4 D3 D2 D1 D0
A
C
K
S
T
O
P
FIGURE 4. THREE-BYTE INSTRUCTION SEQUENCE
I
SCL
SDA
S
T
A
R
T
0
1
0
1
A3 A2 A1 A0
A
C
K
I3
I2
I1 I0
R1 R0 P1 P0
A
C
K
I
I
D
E
C
1
S
T
O
P
I
D
N
C
1
N
C
2
N
C
n
E
C
n
FIGURE 5. INCREMENT/DECREMENT INSTRUCTION SEQUENCE
F
I
INC/DEC
CMD
ISSUED
t
WRID
SCL
SD A
VOLTAGE OUT
V
/R
W
W
FIGURE 6. INCREMENT/DECREMENT TIMING LIMITS
SCL FROM
MASTER
1
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACKNOWLEDGE
FIGURE 7. ACKNOWLEDGE RESPONSE FROM RECEIVER
FN8168.5
April 14, 2011
7
X9258
SERIAL DATA PATH
V /R
H H
SERIAL
BUS
FROM INTERFACE
CIRCUITRY
INPUT
REGISTER 0
REGISTER 1
8
8
PARALLEL
BUS
INPUT
WIPER
REGISTER 2
REGISTER 3
COUNTER
REGISTER
(WCR)
INC/DEC
LOGIC
If WCR = 00[H] then V /R = V /R
L
W
W
L
UP/DN
UP/DN
CLK
If WCR = FF[H] then V /R = V /R
H
W
W
H
V /R
L
L
MODIFIED SCL
V
/R
W
W
FIGURE 8. DETAILED POTENTIOMETER BLOCK DIAGRAM DETAILED OPERATION
All DCP potentiometers share the serial interface and share
a common architecture. Each potentiometer has a Wiper
Counter Register and four Data Registers. A detailed
discussion of the register organization and array operation
follows.
Data Registers
Each potentiometer has four nonvolatile Data Registers.
These can be read or written directly by the host and data
can be transferred between any of the four Data Registers
and the WCR. It should be noted all operations changing
data in one of these registers is a nonvolatile operation and
will take a maximum of 10ms.
Wiper Counter Register
The X9258 contains four Wiper Counter Registers, one for
each DCP potentiometer. The Wiper Counter Register can
be envisioned as a 8-bit parallel and serial load counter with
its outputs decoded to select one of 256 switches along its
resistor array. The contents of the WCR can be altered in
four ways:
If the application does not require storage of multiple
settings for the potentiometer, these registers can be used
as regular memory locations that could possibly store
system parameters or user preference data.
Register Descriptions
1. Written directly by the host via the Write Wiper Counter
Register instruction (serial load)
Data Registers, (8-bit), Nonvolatile
2. Written indirectly by transferring the contents of one of
four associated Data Registers via the XFR Data
Register instruction (parallel load)
WP7
NV
WP6
WP5
WP4
WP3
WP2
WP1
WP0
NV
NV
NV
NV
NV
NV
NV
3. Can be modified one step at a time by the
Increment/Decrement instruction.
(MSB)
(LSB)
4. Loaded with the contents of its data register zero (R0)
upon power-up.
Four 8-bit Data Registers for each DCP (sixteen 8-bit
registers in total).
The WCR is a volatile register; that is, its contents are lost
when the X9258 is powered-down. Although the register is
automatically loaded with the value in R0 upon power-up, it
should be noted this may be different from the value present
at power-down.
{D7~D0}: These bits are for general purpose not volatile data
storage or for storage of up to four different wiper values.
The contents of Data Register 0 are automatically moved to
the wiper counter register on power-up.
FN8168.5
April 14, 2011
8
X9258
the WCR can be loaded from any of the other Data Register
or directly. The contents of the WCR can be saved in a DR.
Wiper Counter Register, (8-bit), Volatile
WP7
V
WP6
WP5
WP4
WP3
WP2
WP1
WP0
V
Instruction Format
V
V
V
V
V
V
NOTES:
(MSB)
(LSB)
2. “MACK”/”SACK”: stands for the acknowledge sent by the
master/slave.
3. “A3 ~ A0”: stands for the device addresses sent by the master.
One 8-bit Wiper Counter Register for each DCP (four 8-bit
registers in total.)
4. “X”: indicates that it is a “0” for testing purpose but physically it is
a “don’t care” condition.
{D7~D0}: These bits specify the wiper position of the
respective DCP. The Wiper Counter Register is loaded on
power-up by the value in Data Register 0. The contents of
5. “I”: stands for the increment operation, SDA held high during
active SCL phase (high).
6. “D”: stands for the decrement operation, SDA held low during
active SCL phase (high).
Read Wiper Counter Register (WCR)
S DEVICE TYPE
DEVICE
INSTRUCTION
OPCODE
WCR
WIPER POSITION
(SENT BY SLAVE ON SDA)
T
A
R
T
IDENTIFIER ADDRESSES S
ADDRESSES S
A
M S
A T
C O
K P
A
C
K
0
1
0
1
A3 A2 A1 A0
1
0
0
1
0 0 P1 P0
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
C
K
Write Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER ADDRESSES
DEVICE
S
A
C
K
INSTRUCTION
OPCODE
WCR
ADDRESSES
S
A
C
K
DATA BYTE
(SENT BY MASTER ON SDA)
S
A
C
K
S
T
O
P
0
1
0
1
A3 A2 A1 A0
1
0
1
0
0
0
P1 P0
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
Read Data Register (DR)
S
T
A
R
T
DEVICETYPE
IDENTIFIER ADDRESSES
DEVICE
INSTRUCTION DR AND WCR
DATA BYTE
(SENT BY SLAVE ON SDA)
S
A
C
K
OPCODE
ADDRESSES
S
A
C
K
M
S
A
C
K
T
O
P
0
1
0
1
A3 A2 A1 A0
1
0
1
1
R1 R0 P1 P0
WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0
Write Data Register (WR)
DEVICE
S
HIGH-VOLTAGE
WRITE CYCLE
TYPE
DEVICE
INSTRUCTION DR AND WCR
DATA BYTE
(SENT BY MASTER ON SDA)
T
A
S
A
C
K
S
A
S S
A T
IDENTIFIER ADDRESSES
OPCODE
ADDRESSES
R 0
1
0
1
A
3
A
2
A
1
A
0
1
1
0
0
R1 R0 P1 P0 C WP7 WP6 WP5 WP4 WP3 WP2 WP1 WP0 C O
K P
T
K
FN8168.5
April 14, 2011
9
X9258
XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER ADDRESSES
DEVICE
S
A
C
K
INSTRUCTION DR AND WCR
S
A
C
K
S
T
O
P
OPCODE
ADDRESSES
0
1
0
1
A3 A2 A1 A0
1
1
0
1
R1 R0 P1 P0
XFR Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER ADDRESSES
HIGH-VOLTAGE
WRITE CYCLE
DEVICE
S
A
C
K
INSTRUCTION DR AND WCR
S
A
C
K
S
T
O
P
OPCODE
ADDRESSES
0
1
0
1
A3 A2 A1 A0
1
1
1
0
R1 R0 P1 P0
Increment/Decrement Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER ADDRESSES
DEVICE
INSTRUCTION
OPCODE
WCR
ADDRESSES
INCREMENT/DECREMENT
(SENT BY MASTER ON SDA)
S
A
C
K
S
S
T
O
P
A
C
K
0
1
0
1
A3 A2 A1 A0
0
0
1
0
0
0
P1 P0
I/D I/D
.
.
.
.
I/D I/D
Global XFR Data Register (DR) to Wiper Counter Register (WCR)
S
T
A
R
T
DEVICE TYPE
IDENTIFIER ADDRESSES
DEVICE
INSTRUCTION
OPCODE
DR
S
A
C
K
ADDRESSES
S
A
C
K
S
T
O
P
0
1
0
1
A3 A2 A1 A0
0
0
0
1
R1 R0
0
0
Global XFR Wiper Counter Register (WCR) to Data Register (DR)
S
T
A
R
T
DEVICE
TYPE
IDENTIFIER ADDRESSES
HIGH-VOLTAGE
WRITE CYCLE
DEVICE
S
A
C
K
INSTRUCTION
OPCODE
DR
S
A
C
K
S
T
O
P
ADDRESSES
0
1
0
1
A3 A2 A1 A0
1
0
0
0
R1 R0
0
0
Guidelines for Calculating Typical Values of Bus
Pull-Up Resistors
Symbol Table
120
V
CC MAX
WAVEFORM
INPUTS
OUTPUTS
R
=
=1.8kΩ
MIN
IOL MIN
100
80
60
40
20
0
Must be
steady
Will be
steady
t
R
R
=
MAX
C
BUS
MAXIMUM
RESISTANCE
May change
from Low to
High
Will change
from Low to
High
May change
from High to
Low
Will change
from High to
Low
MINIMUM
RESISTANCE
0
20
40
60
80
100
120
Don’t Care:
Changes
Allowed
Changing:
State Not
Known
BUS CAPACITANCE (pF)
N/A
Center Line
is High
Impedance
FN8168.5
April 14, 2011
10
X9258
Absolute Maximum Ratings
Thermal Information
Voltage on SDA, SCL or any address input
Thermal Resistance (Typical, Note 7)
θ
(°C/W)
JA
with respect to V
. . . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +7V
SS
24 Lead SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
24 Lead TSSOP. . . . . . . . . . . . . . . . . . . . . . . . . . . .
Temperature under bias. . . . . . . . . . . . . . . . . . . . . .-65°C to +135°C
Storage temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
65
75
Voltage on V+ (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . .10V
Voltage on V- (referenced to V ) . . . . . . . . . . . . . . . . . . . . . . . -10V
SS
(V+) - (V-). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V
SS
Any V /R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .V+
H
H
Any V /R . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . V-
L
L
I
(10s) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±15mA
W
Operating Conditions
Temperature Range. . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Typical)
X9258. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5V ±10%
X9258-2.7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.7V to 5.5V
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
7. θ is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
JA
8. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
Analog Specifications Over recommended operating conditions, unless otherwise specified.
MIN
MAX
SYMBOL
PARAMETER
End-to-end Resistance Tolerance
Power Rating
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
%
±20
50
+25°C, each potentiometer
Wiper current = ± 1mA
mW
mA
Ω
I
Wiper Current
±7.5
250
100
+5.5
+5.5
-4.5
-2.7
V+
W
R
Wiper Resistance
I
I
= ± 1mA @ V+ = 3V, V- = -3V
= ± 1mA @ V+ = 5V, V- = -5V
150
40
W
W
W
W
R
Wiper Resistance
Ω
V+
Voltage on V+ Pin
X9258
+4.5
+2.7
-5.5
-5.5
V-
V
X9258-2.7
X9258
V
V-
Voltage on V- Pin
V
X9258 -2.7
V
V
Voltage on any V /R or V /R Pin
V
TERM
H
H
L
L
Noise
Resolution (Note 12)
Absolute Linearity (Note 9)
Ref: 1kHz
-120
0.6
dBV
%
V
V
- V
±1
MI
(Note 11)
w(n)(actual)
w(n)(expected)
Relative Linearity (Note 10)
Temperature Coefficient of R
- [V
]
w(n) + MI
±0.6
MI
(Note 11)
w(n + 1)
±300
ppm/°C
ppm/°C
pF
TOTAL
Ratiometric Temperature Coefficient
Potentiometer Capacitance
±20
C /C /C
W
See “Test Circuit #3 SPICE Macro
Model” on page 14
10/10/25
H
L
FN8168.5
April 14, 2011
11
X9258
DC Operating Characteristics Over recommended operating conditions, unless otherwise specified.
MIN
MAX
SYMBOL
PARAMETER
TEST CONDITIONS
(Note 8)
TYP
(Note 8)
UNIT
I
V
Supply Current (Nonvolatile
f = 400kHz, SDA = Open,
SCL
1
mA
CC1
CC2
CC
Write)
Other Inputs = V
SS
I
V
Supply Current (Move Wiper,
f
= 400kHz, SDA = Open,
100
µA
CC
Write, Read)
SCL
Other Inputs = V
SS
SCL = SDA = V , Addr. = V
SS
I
V
Current (Standby)
5
µA
µA
µA
V
SB
CC
CC
I
Input Leakage Current
Output Leakage Current
Input HIGH Voltage
Input LOW Voltage
V
V
= V to V
SS CC
10
10
LI
IN
I
= V to V
SS CC
LO
OUT
V
V
x 0.7
V
CC
+ 0.1
x 0.3
IH
CC
V
-0.5
V
V
IL
CC
V
Output LOW Voltage
I
= 3mA
0.4
V
OL
OL
NOTES:
9. Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used as a
potentiometer.
10. Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potentiometer. It is
a measure of the error in step size.
11. MI = R O /255 or (V /R —V /R )/255, single potentiometer.
T
T
H
H
L
L
12. Max = all four arrays cascaded together; typical = individual array resolutions.
Endurance and Data Retention
MIN
PARAMETER
Minimum Endurance
(Note 8)
100,000
100
UNIT
Data changes per bit per register
years
Data Retention
Capacitance
SYMBOL
MAX
PARAMETER
TEST CONDITIONS
(Note 8)
UNIT
pF
C
(Note 13) Input/Output Capacitance (SDA)
V
= 0V
= 0V
8
6
I/O
I/O
C
(Note 13) Input Capacitance (A0, A1, A2, A3, and SCL)
V
pF
IN
IN
Power-Up Timing
MIN
MAX
SYMBOL
PARAMETER
(Note 8)
(Note 8)
UNIT
t
(Note 14) Power-up to Initiation of Read Operation
(Note 14) Power-up to Initiation of Write Operation
1
5
ms
ms
PUR
t
PUW
t
V
(Note 15)
V Power-up Ramp
CC
0.2
50
V/ms
R
CC
NOTES:
13. This parameter is periodically sampled and not 100% tested.
14. t and t are the delays required from the time the third (last) power supply (V , V+ or V-) is stable until the specific instruction can be
PUR
PUW
CC
issued. These parameters are periodically sampled and not 100% tested.
15. Sample tested only.
FN8168.5
April 14, 2011
12
X9258
Power-Up and Power-Down Requirement
AC Test Conditions
The are no restrictions on the sequencing of the bias supplies
Input Pulse Levels
V
x 0.1 to V
x 0.5
x 0.9
CC
CC
V
, V+, and V- provided that all three supplies reach their final
CC
Input Rise and Fall Times
Input and Output Timing Level
10ns
values within 1ms of each other. At all times, the voltages on
the potentiometer pins must be less than V+ and more than V-.
The recall of the wiper position from nonvolatile memory is not
V
CC
in effect until all supplies reach their final value. The V
rate specification is always in effect.
ramp
Equivalent AC Load Circuit
CC
5V
2.7V
1533Ω
SDA OUTPUT
100pF
100pF
FN8168.5
April 14, 2011
13
X9258
Test Circuit #3 SPICE Macro Model
MACRO MODEL
R
TOTAL
R
R
L
H
C
L
C
H
C
W
10pF
10pF
25pF
R
W
AC Timing
Over recommended operating conditions, unless otherwise specified.
MIN
MAX
SYMBOL
PARAMETER
Clock Frequency
(Note 8)
(Note 8)
UNIT
kHz
ns
f
400
SCL
t
Clock Cycle Time
2500
600
1300
600
600
600
100
30
CYC
t
Clock High Time
ns
HIGH
t
Clock Low Time
ns
LOW
t
Start Setup Time
ns
SU:STA
HD:STA
SU:STO
t
Start Hold Time
ns
t
Stop Setup Time
ns
t
SDA Data Input Setup Time
SDA Data Input Hold Time
ns
SU:DAT
t
ns
HD:DAT
t
SCL and SDA Rise Time (Note 16)
SCL and SDA Fall Time (Note 16)
SCL Low to SDA Data Output Valid Time
SDA Data Output Hold Time
Noise Suppression Time Constant at SCL and SDA Inputs
Bus Free Time (Prior to any Transmission)
WP, A0, A1, A2 and A3 Setup Time
WP, A0, A1, A2 and A3 Hold Time
300
300
900
ns
R
t
ns
F
t
ns
AA
DH
t
50
50
ns
T
ns
I
t
1300
0
ns
BUF
t
ns
SU:WPA
HD:WPA
t
0
ns
NOTE:
16. A device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region of the falling edge of SCL.
FN8168.5
April 14, 2011
14
X9258
High-Voltage Write Cycle Timing
MAX
SYMBOL
PARAMETER
TYP
(Note 8)
UNIT
t
High-Voltage Write Cycle Time (Store Instructions)
5
10
ms
WR
DCP Timing
MIN
MAX
SYMBOL
PARAMETER
(Note 8) (Note 7) UNIT
t
Wiper Response Time After the Third (Last) Power Supply is Stable
10
10
10
µs
µs
µs
WRPO
t
Wiper Response Time After Instruction Issued (All Load Instructions)
Wiper Response Time from an Active SCL/SCK Edge (Increment/Decrement Instruction)
WRL
t
WRID
Timing Diagrams 2-Wire Interface
Start and Stop Timing
(START)
(STOP)
t
t
F
R
SCL
t
t
t
SU:STO
SU:STA
HD:STA
t
t
F
R
SDA
Input Timing
t
t
CYC
HIGH
SCL
t
LOW
SDA
t
t
t
BUF
SU:DAT
HD:DAT
Output Timing
SCL
SDA
t
t
DH
AA
FN8168.5
April 14, 2011
15
X9258
DCP Timing (for All Load Instructions)
(STOP)
SCL
LSB
SDA
VWx
t
WRL
DCP Timing (for Increment/Decrement Instruction)
SCL
WIPER REGISTER ADDRESS
INCREMENT/DECREMENT
INCREMENT/DECREMENT
WRID
SDA
VWx
t
Write Protect and Device Address Pins Timing
(START)
(STOP)
SCL
...
(ANY INSTRUCTION)
...
SDA
...
t
SU:WPA
t
HD:WPA
WP
A0, A1
A2, A3
FN8168.5
April 14, 2011
16
X9258
Applications information
Basic Configurations of Electronic Potentiometers
V
+V
R
R
V
/R
W
W
I
FIGURE 9. THREE TERMINAL POTENTIOMETER; VARIABLE
VOLTAGE DIVIDER
FIGURE 10. TWO-TERMINAL VARIABLE RESISTOR; VARIABLE
CURRENT
Application Circuits
V
+
–
S
V
V
V (REG)
O
317
O
IN
R
1
R
2
I
ADJ
R
R
1
2
V
= (1+ R /R ) V
V
(REG) = 1.25V (1+ R /R )+ I
R
ADJ 2
O
2
1
S
O
2
1
FIGURE 11. NON-INVERTING AMPLIFIER
FIGURE 12. VOLTAGE REGULATOR
R
R
2
1
V
S
V
100kΩ
–
+
S
V
–
+
O
V
O
TL072
10kΩ
10kΩ
R
R
1
2
10kΩ
V
V
= {R /(R +R )} V (MAX)
1 1 2 O
= {R /(R +R )} V (MIN)
UL
LL
1
1
2
O
+12V
-12V
FIGURE 14. COMPARATOR WITH HYSTERESIS
FIGURE 13. OFFSET VOLTAGE ADJUSTMENT
FN8168.5
April 14, 2011
17
X9258
Application Circuits (Continued)
C
V
+
–
S
V
R
O
R
R
2
1
3
–
+
R
V
O
V
S
R
2
R
4
All R = 10kΩ
S
R
1
V
= G V
S
G
= 1 + R /R
2 1
O
O
-1/2 ≤ G ≤ +1/2
fc = 1/(2πRC)
FIGURE 15. ATTENUATOR
FIGURE 16. FILTER
R
2
C
1
R
R
V
+
–
1
2
S
V
S
R
R
1
3
–
+
Z
IN
V
O
V
= G V
O
S
1
Z
= R + s R (R + R ) C = R + s Leq
2 2 1 3 1 2
IN
G = - R /R
2
(R + R ) >> R
2
1
3
FIGURE 18. EQUIVALENT L-R CIRCUIT
FIGURE 17. INVERTING AMPLIFIER
C
R
R
1
2
–
+
–
+
R
}
A
B
R
}
FREQUENCY ∝ R , R , C
1
2
AMPLITUDE ∝ R , R
A
B
FIGURE 19. FUNCTION GENERATOR
FN8168.5
April 14, 2011
18
X9258
Thin Shrink Small Outline Package Family (TSSOP)
MDP0044
THIN SHRINK SMALL OUTLINE PACKAGE FAMILY
0.25 M C A B
D
A
(N/2)+1
MILLIMETERS
N
SYMBOL 14 LD 16 LD 20 LD 24 LD 28 LD TOLERANCE
A
A1
A2
b
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
5.00
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
6.50
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
7.80
6.40
4.40
0.65
0.60
1.00
1.20
0.10
0.90
0.25
0.15
9.70
6.40
4.40
0.65
0.60
1.00
Max
±0.05
PIN #1 I.D.
E
E1
±0.05
+0.05/-0.06
+0.05/-0.06
±0.10
0.20 C B A
2X
1
(N/2)
c
N/2 LEAD TIPS
B
D
TOP VIEW
E
Basic
E1
e
±0.10
Basic
0.05
H
e
L
±0.15
C
L1
Reference
Rev. F 2/07
SEATING
PLANE
NOTES:
0.10 M C A B
b
1. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.15mm per side.
0.10 C
N LEADS
SIDE VIEW
2. Dimension “E1” does not include interlead flash or protrusions.
Interlead flash and protrusions shall not exceed 0.25mm per
side.
SEE DETAIL “X”
3. Dimensions “D” and “E1” are measured at dAtum Plane H.
4. Dimensioning and tolerancing per ASME Y14.5M-1994.
c
END VIEW
L1
A2
A
GAUGE
PLANE
0.25
L
A1
0° - 8°
DETAIL X
FN8168.5
April 14, 2011
19
X9258
Small Outline Plastic Packages (SOIC)
M24.3 (JEDEC MS-013-AD ISSUE C)
N
24 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
INDEX
AREA
0.25(0.010)
M
B M
H
INCHES
MILLIMETERS
E
SYMBOL
MIN
MAX
MIN
2.35
0.10
0.33
0.23
MAX
2.65
NOTES
-B-
A
A1
B
C
D
E
e
0.0926
0.0040
0.013
0.1043
0.0118
0.020
-
0.30
-
1
2
3
L
0.51
9
SEATING PLANE
A
0.0091
0.5985
0.2914
0.0125
0.32
-
-A-
0.6141 15.20
15.60
7.60
3
h x 45°
D
0.2992
7.40
4
-C-
0.05 BSC
1.27 BSC
-
α
H
h
0.394
0.010
0.016
0.419
0.029
0.050
10.00
0.25
0.40
10.65
0.75
1.27
-
e
A1
C
5
B
0.10(0.004)
L
6
0.25(0.010) M
C
A M B S
N
α
24
24
7
0°
8°
0°
8°
-
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
Rev. 1 4/06
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm
(0.006 inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Inter-
lead flash and protrusions shall not exceed 0.25mm (0.010 inch) per
side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN8168.5
April 14, 2011
20
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