XC68HC705B32CFU [ROCHESTER]
Microcontroller, 8-Bit, OTPROM, HCMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, 2.10 MM HEIGHT, PLASTIC, QFP-64;
| 型号： | XC68HC705B32CFU |
| 厂家： | 
Rochester Electronics |
| 描述： | Microcontroller, 8-Bit, OTPROM, HCMOS, PQFP64, 14 X 14 MM, 0.80 MM PITCH, 2.10 MM HEIGHT, PLASTIC, QFP-64 可编程只读存储器 时钟 微控制器 外围集成电路 |
| 文件： | 总305页 (文件大小：3702K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MC68HC05B6/D
Rev. 4
HC05
MC68HC05B4
MC68HC705B5
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC705B16
MC68HC705B16N
MC68HC05B32
MC68HC705B32
TECHNICAL
DATA
1
1
INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
1
2
3
INPUT/OUTPUT PORTS
4
PROGRAMMABLE TIMER
5
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
6
7
8
9
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
10
11
12
13
14
15
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
TPG
INTRODUCTION
1
2
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
3
4
PROGRAMMABLE TIMER
5
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
6
7
8
9
10
11
12
13
14
15
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
TPG
CUSTOMER FEEDBACK QUESTIONNAIRE (MC68HC05B6/D rev. 4)
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SECTION 1 INTRODUCTION
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SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3 MEMORY AND REGISTERS
SECTION 4 INPUT/OUTPUT PORTS
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SECTION 5 PROGRAMMABLE TIMER
SECTION 6 SERIAL COMMUNICATIONS INTERFACE
SECTION 7 PULSE LENGTH D/A CONVERTERS
SECTION 8 ANALOG TO DIGITAL CONVERTER
SECTION 9 RESETS AND INTERRUPTS
SECTION 10 CPU CORE AND INSTRUCTION SET
SECTION 11 ELECTRICAL SPECIFICATIONS
SECTION 12 MECHANICAL DATA
SECTION 13 ORDERING INFORMATION
SECTION 14 APPENDICES
SECTION 15 HIGH SPEED OPERATION
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TPG
Thank you for helping us improve our documentation,
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MC68HC05B6
High-density Complementary
Metal Oxide Semiconductor
(HCMOS) Microcomputer Unit
All Trade Marks recognized. This document contains information on new products. Specifications and information herein are
subject to change without notice.
All products are sold on Motorola’s Terms & Conditions of Supply. In ordering a product covered by this document the
Customer agrees to be bound by those Terms & Conditions and nothing contained in this document constitutes or forms part
of a contract (with the exception of the contents of this Notice). A copy of Motorola’s Terms & Conditions of Supply is available
on request.
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty,
representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any
liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including
without limitation consequential or incidental damages. “Typical” parameters which may be provided in Motorola data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals”, must be validated for each customer application by customer’s technical experts. Motorola
does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or
authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where
personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized
application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Motorola was negligent regarding the design or manufacture of the part. Motorola and
Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
are registered trademarks of
The Customer should ensure that it has the most up to date version of the document by contacting its local Motorola office.
This document supersedes any earlier documentation relating to the products referred to herein. The information contained
in this document is current at the date of publication. It may subsequently be updated, revised or withdrawn.
MOTOROLA LTD., 1999
TPG
Conventions
Where abbreviations are used in the text, an explanation can be found in the
glossary, at the back of this manual. Register and bit mnemonics are defined in the
paragraphs describing them.
An overbar is used to designate an active-low signal, eg: RESET.
Unless otherwise stated, shaded cells in a register diagram indicate that the bit is
either unused or reserved; ‘u’ is used to indicate an undefined state (on reset).
Unless otherwise stated, pins labelled “NU” should be tied to V in an electrically
SS
noisy environment. Pins labelled “NC” can be left floating, since they are not bonded
to any part of the device.
TPG
TABLE OF CONTENTS
Paragraph
Number
Page
Number
TITLE
1
INTRODUCTION
1.1
1.2
Features.............................................................................................................1–2
Mask options for the MC68HC05B6 ..................................................................1–3
2
MODES OF OPERATION AND PIN DESCRIPTIONS
2.1
2.1.1
2.2
2.3
2.4
2.4.1
2.4.2
2.4.2.1
2.4.3
2.4.3.1
2.5
2.5.1
2.5.2
2.5.3
2.5.4
2.5.5
2.5.6
2.5.7
2.5.8
2.5.8.1
2.5.8.2
2.5.8.3
2.5.9
2.5.10
2.5.11
2.5.12
Modes of operation............................................................................................2–1
Single chip mode .........................................................................................2–1
Serial RAM loader .............................................................................................2–2
‘Jump to any address’........................................................................................2–4
Low power modes..............................................................................................2–6
STOP ...........................................................................................................2–6
WAIT ............................................................................................................2–8
Power consumption during WAIT mode .................................................2–8
SLOW mode.................................................................................................2–9
Miscellaneous register...........................................................................2–9
Pin descriptions ..............................................................................................2–10
VDD and VSS ............................................................................................2–10
IRQ ............................................................................................................2–10
RESET.......................................................................................................2–10
TCAP1 .......................................................................................................2–10
TCAP2 .......................................................................................................2–11
TCMP1.......................................................................................................2–11
TCMP2.......................................................................................................2–11
OSC1, OSC2 .............................................................................................2–11
Crystal..................................................................................................2–11
Ceramic resonator................................................................................2–11
External clock.......................................................................................2–12
RDI (Receive data in).................................................................................2–13
TDO (Transmit data out) ............................................................................2–13
SCLK..........................................................................................................2–13
PLMA .........................................................................................................2–13
TPG
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
MOTOROLA
i
Paragraph
Number
Page
Number
TABLE OF CONTENTS
2.5.13
2.5.14
2.5.15
2.5.16
2.5.17
2.5.18
PLMB.........................................................................................................2–13
VPP1..........................................................................................................2–13
VRH ...........................................................................................................2–13
VRL............................................................................................................2–13
PA0 – PA7/PB0 – PB7/PC0 – PC7 ............................................................2–13
PD0/AN0–PD7/AN7...................................................................................2–13
3
MEMORY AND REGISTERS
3.1
3.2
3.3
3.4
Registers ...........................................................................................................3–1
RAM ..................................................................................................................3–1
ROM ..................................................................................................................3–1
Self-check ROM ................................................................................................3–2
EEPROM...........................................................................................................3–3
EEPROM control register.............................................................................3–3
EEPROM read operation .............................................................................3–5
EEPROM erase operation ...........................................................................3–5
EEPROM programming operation ...............................................................3–6
Options register (OPTR)..............................................................................3–6
EEPROM during STOP mode ...........................................................................3–7
EEPROM during WAIT mode ............................................................................3–7
Miscellaneous register......................................................................................3–9
3.5
3.5.1
3.5.2
3.5.3
3.5.4
3.5.5
3.6
3.7
3.8
4
INPUT/OUTPUT PORTS
4.1
4.2
4.3
4.4
Input/output programming .................................................................................4–1
Ports A and B ....................................................................................................4–2
Port C ................................................................................................................4–3
Port D ................................................................................................................4–3
Port registers .....................................................................................................4–4
Port data registers A and B (PORTA and PORTB) ......................................4–4
Port data register C (PORTC)......................................................................4–4
Port data register D (PORTD)......................................................................4–5
A/D status/control register......................................................................4–5
Data direction registers (DDRA, DDRB and DDRC)....................................4–5
Other port considerations..................................................................................4–6
4.5
4.5.1
4.5.2
4.5.3
4.5.3.1
4.5.4
4.6
TPG
MOTOROLA
ii
TABLE OF CONTENTS
MC68HC05B6
Rev. 4
Paragraph
Number
Page
Number
TABLE OF CONTENTS
5
PROGRAMMABLE TIMER
5.1
5.1.1
5.2
5.2.1
5.2.2
5.3
5.3.1
5.3.2
5.4
5.4.1
5.4.2
5.4.3
5.5
5.5.1
5.6
Counter..............................................................................................................5–1
Counter register and alternate counter register ...........................................5–3
Timer control and status....................................................................................5–4
Timer control register (TCR) ........................................................................5–4
Timer status register (TSR)..........................................................................5–6
Input capture......................................................................................................5–7
Input capture register 1 (ICR1) ....................................................................5–7
Input capture register 2 (ICR2) ....................................................................5–8
Output compare.................................................................................................5–9
Output compare register 1 (OCR1)..............................................................5–9
Output compare register 2 (OCR2)............................................................5–10
Software force compare.............................................................................5–11
Pulse Length Modulation (PLM) ......................................................................5–11
Pulse length modulation registers A and B (PLMA/PLMB)........................5–11
Timer during STOP mode................................................................................5–12
Timer during WAIT mode.................................................................................5–12
Timer state diagrams.......................................................................................5–12
5.7
5.8
6
SERIAL COMMUNICATIONS INTERFACE
6.1
6.2
6.3
6.4
6.5
6.6
6.6.1
6.6.2
6.7
SCI two-wire system features............................................................................6–1
SCI receiver features.........................................................................................6–3
SCI transmitter features.....................................................................................6–3
Functional description........................................................................................6–3
Data format........................................................................................................6–5
Receiver wake-up operation ..............................................................................6–5
Idle line wake-up ..........................................................................................6–6
Address mark wake-up ................................................................................6–6
Receive data in (RDI) ........................................................................................6–6
Start bit detection...............................................................................................6–6
Transmit data out (TDO) ....................................................................................6–8
6.8
6.9
6.10 SCI synchronous transmission ..........................................................................6–9
6.11 SCI registers....................................................................................................6–10
6.11.1
6.11.2
6.11.3
6.11.4
6.11.5
Serial communications data register (SCDR) ............................................6–10
Serial communications control register 1 (SCCR1) ...................................6–10
Serial communications control register 2 (SCCR2) ...................................6–14
Serial communications status register (SCSR)..........................................6–16
Baud rate register (BAUD) .........................................................................6–18
6.12 Baud rate selection..........................................................................................6–19
6.13 SCI during STOP mode...................................................................................6–21
6.14 SCI during WAIT mode....................................................................................6–21
TPG
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
MOTOROLA
iii
Paragraph
Number
Page
Number
TABLE OF CONTENTS
7
PULSE LENGTH D/A CONVERTERS
7.1
7.2
7.3
7.4
Miscellaneous register.......................................................................................7–3
PLM clock selection...........................................................................................7–4
PLM during STOP mode ...................................................................................7–4
PLM during WAIT mode ....................................................................................7–4
8
ANALOG TO DIGITAL CONVERTER
8.1
8.2
8.2.1
8.2.2
8.2.3
8.3
A/D converter operation.....................................................................................8–1
A/D registers......................................................................................................8–3
Port D data register (PORTD)......................................................................8–3
A/D result data register (ADDATA)...............................................................8–3
A/D status/control register (ADSTAT)...........................................................8–4
A/D converter during STOP mode.....................................................................8–6
A/D converter during WAIT mode......................................................................8–6
Port D analog input............................................................................................8–6
8.4
8.5
9
RESETS AND INTERRUPTS
9.1
Resets ...............................................................................................................9–1
Power-on reset.............................................................................................9–2
Miscellaneous register................................................................................9–2
RESET pin...................................................................................................9–3
Computer operating properly (COP) watchdog reset ..................................9–3
COP watchdog during STOP mode .......................................................9–4
COP watchdog during WAIT mode ........................................................9–4
Functions affected by reset..........................................................................9–5
Interrupts ...........................................................................................................9–6
Interrupt priorities.........................................................................................9–6
Nonmaskable software interrupt (SWI)........................................................9–6
Maskable hardware interrupts......................................................................9–7
External interrupt (IRQ)..........................................................................9–7
Miscellaneous register ..........................................................................9–9
Timer interrupts....................................................................................9–10
Serial communications interface (SCI) interrupts.................................9–10
Hardware controlled interrupt sequence....................................................9–11
9.1.1
9.1.2
9.1.3
9.1.4
9.1.4.1
9.1.4.2
9.1.5
9.2
9.2.1
9.2.2
9.2.3
9.2.3.1
9.2.3.2
9.2.3.3
9.2.3.4
9.2.4
TPG
MOTOROLA
iv
TABLE OF CONTENTS
MC68HC05B6
Rev. 4
Paragraph
Number
Page
Number
TABLE OF CONTENTS
10
CPU CORE AND INSTRUCTION SET
10.1 Registers .........................................................................................................10–1
10.1.1
10.1.2
10.1.3
10.1.4
10.1.5
Accumulator (A) .........................................................................................10–2
Index register (X)........................................................................................10–2
Program counter (PC)................................................................................10–2
Stack pointer (SP)......................................................................................10–2
Condition code register (CCR)...................................................................10–2
10.2 Instruction set ..................................................................................................10–3
10.2.1
10.2.2
10.2.3
10.2.4
10.2.5
10.2.6
Register/memory Instructions....................................................................10–4
Branch instructions ....................................................................................10–4
Bit manipulation instructions ......................................................................10–4
Read/modify/write instructions...................................................................10–4
Control instructions ....................................................................................10–4
Tables.........................................................................................................10–4
10.3 Addressing modes.........................................................................................10–11
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
Inherent....................................................................................................10–11
Immediate ................................................................................................10–11
Direct........................................................................................................10–11
Extended..................................................................................................10–12
Indexed, no offset.....................................................................................10–12
Indexed, 8-bit offset..................................................................................10–12
Indexed, 16-bit offset................................................................................10–12
Relative ....................................................................................................10–13
Bit set/clear ..............................................................................................10–13
10.3.10 Bit test and branch...................................................................................10–13
11
ELECTRICAL SPECIFICATIONS
11.1 Absolute maximum ratings ..............................................................................11–1
11.2 DC electrical characteristics ............................................................................11–2
11.2.1
11.2.2
I
I
trends for 5V operation ........................................................................11–3
trends for 3.3V operation .....................................................................11–6
DD
DD
11.3 A/D converter characteristics...........................................................................11–8
11.4 Control timing ................................................................................................11–10
12
MECHANICAL DATA
12.1 MC68HC05B family pin configurations............................................................12–1
12.1.1
12.1.2
52-pin plastic leaded chip carrier (PLCC) ..................................................12–1
64-pin quad flat pack (QFP).......................................................................12–2
TPG
MC68HC05B6
Rev. 4
TABLE OF CONTENTS
MOTOROLA
v
Paragraph
Number
Page
Number
TABLE OF CONTENTS
12.1.3
56-pin shrink dual in line package (SDIP)..................................................12–3
12.2 MC68HC05B6 mechanical dimensions...........................................................12–4
12.2.1
12.2.2
12.2.3
52-pin plastic leaded chip carrier (PLCC)..................................................12–4
64-pin quad flat pack (QFP).......................................................................12–5
56-pin shrink dual in line package (SDIP)..................................................12–6
13
ORDERING INFORMATION
13.1 EPROMS.........................................................................................................13–2
13.2 Verification media ............................................................................................13–2
13.3 ROM verification units (RVU)...........................................................................13–2
A
MC68HC05B4
A.1
A.2
Features ........................................................................................................... A–1
Self-check mode............................................................................................... A–5
B
MC68HC05B8
B.1
Features ........................................................................................................... B–1
C
MC68HC705B5
C.1
C.2
C.2.1
C.3
C.3.1
C.4
Features ........................................................................................................... C–1
EPROM ............................................................................................................ C–5
EPROM programming operation................................................................. C–5
EPROM registers.............................................................................................. C–6
EPROM control register.............................................................................. C–6
Options register (OPTR)................................................................................... C–7
Bootstrap mode ................................................................................................ C–8
Erased EPROM verification ...................................................................... C–11
EPROM parallel bootstrap load ................................................................ C–11
EPROM (RAM) serial bootstrap load and execute ................................... C–13
RAM parallel bootstrap load and execute ................................................. C–14
Bootstrap loader timing diagrams ............................................................. C–17
DC electrical characteristics........................................................................... C–19
Control timing ................................................................................................. C–19
C.5
C.5.1
C.5.2
C.5.3
C.5.4
C.5.5
C.6
C.7
TPG
MOTOROLA
vi
TABLE OF CONTENTS
MC68HC05B6
Rev. 4
Paragraph
Number
Page
Number
TABLE OF CONTENTS
D
MC68HC05B16
D.1
D.2
D.3
Features............................................................................................................D–1
Self-check routines ...........................................................................................D–2
External clock ...................................................................................................D–4
E
MC68HC705B16
E.1
E.2
E.3
Features............................................................................................................ E–2
External clock ................................................................................................... E–5
EPROM............................................................................................................. E–5
EPROM read operation............................................................................... E–5
EPROM program operation......................................................................... E–5
EPROM/EEPROM/ECLK control register ................................................... E–6
Mask option register.................................................................................... E–8
EEPROM options register (OPTR).............................................................. E–9
Bootstrap mode .............................................................................................. E–10
Erased EPROM verification ...................................................................... E–13
EPROM/EEPROM parallel bootstrap........................................................ E–13
EEPROM/EPROM/RAM serial bootstrap.................................................. E–16
RAM parallel bootstrap ............................................................................. E–19
Jump to start of RAM ($0050)............................................................. E–20
Absolute maximum ratings ............................................................................. E–21
DC electrical characteristics ........................................................................... E–22
A/D converter characteristics.......................................................................... E–24
Control timing ................................................................................................. E–26
EPROM electrical characteristics ................................................................... E–28
E.3.1
E.3.2
E.3.3
E.3.4
E.3.5
E.4
E.4.1
E.4.2
E.4.3
E.4.4
E.4.4.1
E.5
E.6
E.7
E.8
E.9
F
MC68HC705B16N
F.1
F.2
F.3
F.4
F.4.1
F.4.2
F.4.3
F.4.4
F.4.5
F.5
Features............................................................................................................ F–2
External clock ................................................................................................... F–5
RESET pin........................................................................................................ F–5
EPROM............................................................................................................. F–5
EPROM read operation............................................................................... F–5
EPROM program operation......................................................................... F–6
EPROM/EEPROM/ECLK control register ................................................... F–6
Mask option register.................................................................................... F–8
EEPROM options register (OPTR).............................................................. F–9
Bootstrap mode .............................................................................................. F–10
Erased EPROM verification ...................................................................... F–13
F.5.1
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MC68HC05B6
Rev. 4
TABLE OF CONTENTS
MOTOROLA
vii
Paragraph
Number
Page
Number
TABLE OF CONTENTS
F.5.2
F.5.3
F.5.3.1
F.6
F.7
F.8
EPROM/EEPROM parallel bootstrap.........................................................F–13
Serial RAM loader......................................................................................F–16
Jump to start of RAM ($0051)..............................................................F–16
Absolute maximum ratings ..............................................................................F–19
DC electrical characteristics............................................................................F–20
A/D converter characteristics...........................................................................F–22
Control timing ..................................................................................................F–24
F.9
F.10 EPROM electrical characteristics ....................................................................F–26
G
MC68HC05B32
G.1
G.2
Features ...........................................................................................................G–1
External clock...................................................................................................G–2
H
MC68HC705B32
H.1
H.2
H.3
H.4
Features ........................................................................................................... H–3
External clock................................................................................................... H–7
RESET pin........................................................................................................ H–7
EPROM ............................................................................................................ H–7
EPROM read operation............................................................................... H–8
EPROM program operation ........................................................................ H–8
EPROM/EEPROM control register ............................................................. H–8
Mask option register ................................................................................. H–11
Options register (OPTR)........................................................................... H–12
Bootstrap mode .............................................................................................. H–13
Erased EPROM verification ...................................................................... H–16
EPROM/EEPROM parallel bootstrap........................................................ H–16
Serial RAM loader..................................................................................... H–19
Jump to start of RAM ($0051)............................................................. H–19
Absolute maximum ratings ............................................................................. H–22
DC electrical characteristics........................................................................... H–23
A/D converter characteristics.......................................................................... H–25
Control timing ................................................................................................. H–27
H.4.1
H.4.2
H.4.3
H.4.4
H.4.5
H.5
H.5.1
H.5.2
H.5.3
H.5.3.1
H.6
H.7
H.8
H.9
H.10 EPROM electrical characteristics ................................................................... H–29
I
HIGH SPEED OPERATION
I.1
I.2
I.3
DC electrical characteristics...............................................................................I–2
A/D converter characteristics..............................................................................I–3
Control timing for 5V operation...........................................................................I–4
TPG
MOTOROLA
viii
TABLE OF CONTENTS
MC68HC05B6
Rev. 4
LIST OF FIGURES
Figure
Number
Page
Number
TITLE
1-1
2-1
2-2
2-3
2-4
2-5
3-1
4-1
4-2
4-3
5-1
5-2
5-3
5-4
5-5
6-1
6-2
6-3
6-4
6-5
6-6
6-7
6-8
6-9
6-10
7-1
7-2
7-3
8-1
8-2
9-1
9-2
9-3
MC68HC05B6 block diagram .............................................................................1–3
MC68HC05B6 ‘load program in RAM and execute’ schematic diagram.............2–3
MC68HC05B6 ‘jump to any address’ schematic diagram...................................2–5
STOP and WAIT flowcharts................................................................................2–7
Slow mode divider block diagram.......................................................................2–9
Oscillator connections ......................................................................................2–12
Memory map of the MC68HC05B6 ....................................................................3–2
Standard I/O port structure.................................................................................4–2
ECLK timing diagram..........................................................................................4–3
Port logic levels...................................................................................................4–6
16-bit programmable timer block diagram ..........................................................5–2
Timer state timing diagram for reset.................................................................5–13
Timer state timing diagram for input capture ....................................................5–13
Timer state timing diagram for output compare................................................5–14
Timer state timing diagram for timer overflow...................................................5–14
Serial communications interface block diagram .................................................6–2
SCI rate generator division.................................................................................6–4
Data format.........................................................................................................6–5
SCI examples of start bit sampling technique ....................................................6–7
SCI sampling technique used on all bits.............................................................6–7
Artificial start following a framing error ...............................................................6–8
SCI start bit following a break.............................................................................6–8
SCI example of synchronous and asynchronous transmission..........................6–9
SCI data clock timing diagram (M=0) ...............................................................6–12
SCI data clock timing diagram (M=1) ...............................................................6–13
PLM system block diagram.................................................................................7–1
PLM output waveform examples.........................................................................7–2
PLM clock selection............................................................................................7–4
A/D converter block diagram ..............................................................................8–2
Electrical model of an A/D input pin....................................................................8–6
Reset timing diagram..........................................................................................9–1
Watchdog system block diagram........................................................................9–3
Interrupt flow chart..............................................................................................9–8
TPG
MC68HC05B6
Rev. 4
LIST OF FIGURES
MOTOROLA
ix
Figure
Number
Page
Number
TITLE
10-1
10-2
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
Programming model.........................................................................................10–1
Stacking order ..................................................................................................10–1
Run I vs internal operating frequency (4.5V, 5.5V)......................................11–3
DD
Run I (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–3
DD
Wait I vs internal operating frequency (4.5V, 5.5V)......................................11–3
DD
Wait I (SM = 1) vs internal operating frequency (4.5V, 5.5V).......................11–4
DD
Increase in I vs frequency for A/D, SCI systems active, VDD = 5.5V...........11–4
DD
I
vs mode vs internal operating frequency, V = 5.5V................................11–4
DD
DD
Run I vs internal operating frequency (3 V, 3.6V).........................................11–6
DD
Run I (SM = 1) vs internal operating frequency (3V,3.6V)...........................11–6
DD
Wait I vs internal operating frequency (3V, 3.6V).........................................11–6
DD
11-10 Wait I (SM = 1) vs internal operating frequency (3V, 3.6V)..........................11–7
DD
11-11 Increase in I vs frequency for A/D, SCI systems active, V = 3.6V............11–7
DD
DD
11-12
I
vs mode vs internal operating frequency, V = 3.6V................................11–7
DD DD
11-13 Timer relationship...........................................................................................11–12
12-1
12-2
12-3
12-4
12-5
12-6
A-1
A-2
A-3
B-1
B-2
C-1
C-2
C-3
C-4
C-5
C-6
C-7
C-8
C-9
C-10
D-1
D-2
D-3
E-1
E-2
E-3
52-pin PLCC pinout for the MC68HC05B6.......................................................12–1
64-pin QFP pinout for the MC68HC05B6.........................................................12–2
56-pin SDIP pinout for the MC68HC05B6........................................................12–3
52-pin PLCC mechanical dimensions ..............................................................12–4
64-pin QFP mechanical dimensions.................................................................12–5
56-pin SDIP mechanical dimensions................................................................12–6
MC68HC05B4 block diagram.............................................................................A–2
Memory map of the MC68HC05B4....................................................................A–3
MC68HC05B4 self-check schematic diagram....................................................A–7
MC68HC05B8 block diagram.............................................................................B–2
Memory map of the MC68HC05B8....................................................................B–3
MC68HC705B5 block diagram.......................................................................... C–2
Memory map of the MC68HC705B5................................................................. C–3
Modes of operation flow chart (1 of 2)............................................................... C–9
Modes of operation flow chart (2 of 2)............................................................. C–10
Timing diagram with handshake...................................................................... C–11
EPROM(RAM) parallel bootstrap schematic diagram ..................................... C–12
EPROM (RAM) serial bootstrap schematic diagram ....................................... C–15
RAM parallel bootstrap schematic diagram..................................................... C–16
EPROM parallel bootstrap loader timing diagram ........................................... C–17
RAM parallel loader timing diagram ............................................................... C–18
MC68HC05B16 block diagram.......................................................................... D–3
Oscillator connections ....................................................................................... D–4
Memory map of the MC68HC05B16................................................................. D–5
MC68HC705B16 block diagram.........................................................................E–2
Memory map of the MC68HC705B16................................................................E–3
Modes of operation flow chart (1 of 2)..............................................................E–11
TPG
MOTOROLA
x
LIST OF FIGURES
MC68HC05B6
Rev. 4
Figure
Number
Page
Number
TITLE
E-4
E-5
E-6
E-7
E-8
E-9
E-10
E-11
F-1
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-10
G-1
G-2
H-1
H-2
H-3
H-4
H-5
H-6
H-7
H-8
H-9
H-10
I-1
Modes of operation flow chart (2 of 2)............................................................. E–12
Timing diagram with handshake...................................................................... E–14
Parallel EPROM loader timing diagram........................................................... E–14
EPROM Parallel bootstrap schematic diagram................................................ E–15
RAM/EPROM/EEPROM serial bootstrap schematic diagram ......................... E–17
Parallel RAM loader timing diagram ................................................................ E–19
RAM parallel bootstrap schematic diagram..................................................... E–20
Timer relationship............................................................................................ E–28
MC68HC705B16N block diagram.......................................................................F–2
Memory map of the MC68HC705B16N..............................................................F–3
Modes of operation flow chart (1 of 2)..............................................................F–11
Modes of operation flow chart (2 of 2)..............................................................F–12
Timing diagram with handshake.......................................................................F–14
Parallel EPROM loader timing diagram............................................................F–14
EPROM parallel bootstrap schematic diagram.................................................F–15
RAM load and execute schematic diagram ......................................................F–17
Parallel RAM loader timing diagram .................................................................F–18
Timer relationship.............................................................................................F–26
MC68HC05B32 block diagram ..........................................................................G–2
Memory map of the MC68HC05B32 .................................................................G–3
MC68HC705B32 block diagram ........................................................................ H–4
Memory map of the MC68HC705B32 ............................................................... H–5
Modes of operation flow chart (1 of 2)............................................................. H–14
Modes of operation flow chart (2 of 2)............................................................. H–15
Timing diagram with handshake...................................................................... H–17
Parallel EPROM loader timing diagram........................................................... H–17
EPROM parallel bootstrap schematic diagram................................................ H–18
RAM load and execute schematic diagram ..................................................... H–20
Parallel RAM loader timing diagram ................................................................ H–21
Timer relationship............................................................................................ H–29
Timer relationship................................................................................................I–5
TPG
MC68HC05B6
Rev. 4
LIST OF FIGURES
MOTOROLA
xi
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TPG
MOTOROLA
xii
LIST OF FIGURES
MC68HC05B6
Rev. 4
LIST OF TABLES
Table
Number
Page
Number
TITLE
1-1
2-1
3-1
3-2
3-3
4-1
6-1
6-2
6-3
6-4
6-5
6-6
8-1
8-2
9-1
9-2
Data sheet appendices.......................................................................................1–1
Mode of operation selection ...............................................................................2–1
EEPROM control bits description .......................................................................3–4
Register outline...................................................................................................3–8
IRQ sensitivity.....................................................................................................3–9
I/O pin states ......................................................................................................4–2
Method of receiver wake-up .............................................................................6–11
SCI clock on SCLK pin .....................................................................................6–13
First prescaler stage.........................................................................................6–18
Second prescaler stage (transmitter) ...............................................................6–18
Second prescaler stage (receiver)....................................................................6–19
SCI baud rate selection ....................................................................................6–20
A/D clock selection .............................................................................................8–4
A/D channel assignment.....................................................................................8–5
Effect of RESET, POR, STOP and WAIT............................................................9–5
Interrupt priorities ...............................................................................................9–7
IRQ sensitivity.....................................................................................................9–9
MUL instruction.................................................................................................10–5
Register/memory instructions...........................................................................10–5
Branch instructions...........................................................................................10–6
Bit manipulation instructions.............................................................................10–6
Read/modify/write instructions .........................................................................10–7
Control instructions...........................................................................................10–7
Instruction set (1 of 2).......................................................................................10–8
Instruction set (2 of 2).......................................................................................10–9
M68HC05 opcode map...................................................................................10–10
Absolute maximum ratings ...............................................................................11–1
DC electrical characteristics for 5V operation...................................................11–2
DC electrical characteristics for 3.3V operation................................................11–5
A/D characteristics for 5V operation.................................................................11–8
A/D characteristics for 3.3V operation..............................................................11–9
Control timing for 5V operation.......................................................................11–10
Control timing for 3.3V operation....................................................................11–11
9-3
10-1
10-2
10-3
10-4
10-5
10-6
10-7
10-8
10-9
11-1
11-2
11-3
11-4
11-5
11-6
11-7
TPG
MC68HC05B6
Rev. 4
LIST OF TABLES
MOTOROLA
xiii
Table
Number
Page
Number
TITLE
13-1
13-2
A-1
A-2
A-3
MC order numbers ...........................................................................................13–1
EPROMs for pattern generation.......................................................................13–2
Mode of operation selection ...............................................................................A–1
Register outline ..................................................................................................A–4
MC68HC05B4 self-check results .......................................................................A–6
Register outline ..................................................................................................B–4
Register outline ................................................................................................. C–4
Mode of operation selection .............................................................................. C–8
Bootstrap vector targets in RAM ..................................................................... C–14
Additional DC electrical characteristics for MC68HC705B5............................ C–19
Additional control timing for MC68HC705B5................................................... C–19
Mode of operation selection .............................................................................. D–2
Register outline ................................................................................................. D–6
Register outline ..................................................................................................E–4
EPROM control bits description .........................................................................E–6
EEPROM control bits description.......................................................................E–7
Mode of operation selection .............................................................................E–10
Bootstrap vector targets in RAM ......................................................................E–18
Absolute maximum ratings...............................................................................E–21
DC electrical characteristics for 5V operation ..................................................E–22
DC electrical characteristics for 3.3V operation ...............................................E–23
A/D characteristics for 5V operation.................................................................E–24
A/D characteristics for 3.3V operation..............................................................E–25
Control timing for 5V operation.........................................................................E–26
Control timing for 3.3V operation......................................................................E–27
DC electrical characteristics for 5V operation ..................................................E–28
Control timing for 5V operation.........................................................................E–28
Control timing for 3.3V operation......................................................................E–28
Register outline ..................................................................................................F–4
EPROM control bits description .........................................................................F–7
EEPROM control bits description.......................................................................F–8
Mode of operation selection .............................................................................F–10
Bootstrap vector targets in RAM ......................................................................F–16
Absolute maximum ratings...............................................................................F–19
DC electrical characteristics for 5V operation ..................................................F–20
DC electrical characteristics for 3.3V operation ...............................................F–21
A/D characteristics for 5V operation.................................................................F–22
A/D characteristics for 3.3V operation..............................................................F–23
Control timing for 5V operation.........................................................................F–24
Control timing for 3.3V operation......................................................................F–25
DC electrical characteristics for 5V operation ..................................................F–26
Control timing for 5V operation.........................................................................F–26
B-1
C-1
C-2
C-3
C-4
C-5
D-1
D-2
E-1
E-2
E-3
E-4
E-5
E-6
E-7
E-8
E-9
E-10
E-11
E-12
E-13
E-14
E-15
F-1
F-2
F-3
F-4
F-5
F-6
F-7
F-8
F-9
F-10
F-11
F-12
F-13
F-14
TPG
MOTOROLA
xiv
LIST OF TABLES
MC68HC05B6
Rev. 4
Table
Number
Page
Number
TITLE
F-15
G-1
H-1
H-2
H-3
H-4
H-5
H-6
H-7
H-8
H-9
H-10
H-11
H-12
H-13
H-14
H-15
I-1
Control timing for 3.3V operation......................................................................F–26
Register outline..................................................................................................G–4
Register outline.................................................................................................. H–6
EPROM control bits description......................................................................... H–9
EEPROM control bits description .................................................................... H–10
Mode of operation selection ............................................................................ H–13
Bootstrap vector targets in RAM...................................................................... H–19
Absolute Maximum ratings .............................................................................. H–22
DC electrical characteristics for 5V operation.................................................. H–23
DC electrical characteristics for 3.3V operation............................................... H–24
A/D characteristics for 5V operation................................................................ H–25
A/D characteristics for 3.3V operation............................................................. H–26
Control timing for 5V operation........................................................................ H–27
Control timing for operation at 3.3V................................................................. H–28
DC electrical characteristics for 5V operation.................................................. H–29
Control timing for 5V operation........................................................................ H–29
Control timing for 3.3V operation..................................................................... H–29
Ordering information............................................................................................I–1
DC electrical characteristics for 5V operation......................................................I–2
A/D characteristics for 5V operation....................................................................I–3
I-2
I-3
TPG
MC68HC05B6
Rev. 4
LIST OF TABLES
MOTOROLA
xv
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TPG
MOTOROLA
xvi
LIST OF TABLES
MC68HC05B6
Rev. 4
1
1
INTRODUCTION
The MC68HC05B6 microcomputer (MCU) is a member of Motorola’s MC68HC05 family of
low-cost single chip microcomputers. This 8-bit MCU contains an on-chip oscillator, CPU, RAM,
ROM, EEPROM, A/D converter, pulse length modulated outputs, I/O, serial communications
interface, programmable timer system and watchdog. The fully static design allows operation at
frequencies down to dc to further reduce the already low power consumption to a few micro-amps.
This data sheet is structured such that devices similar to the MC68HC05B6 are described in a set
of appendices (see Table 1-1).
Table 1-1 Data sheet appendices
Device
MC68HC05B4
MC68HC05B8
Appendix
Differences from MC68HC05B6
4K bytes ROM; no EEPROM
A
B
7.25K bytes ROM
6K bytes EPROM; self-check replaced by bootstrap
firmware; no EEPROM
MC68HC705B5
MC68HC05B16
MC68HC705B16
C
D
E
16K bytes ROM; increased RAM and self-check ROM
16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
16K bytes EPROM; increased RAM; self-check replaced
by bootstrap firmware; modified power-on reset routine
MC68HC705B16N
MC68HC05B32
MC68HC705B32
F
G
H
32K bytes ROM; no page zero ROM; increased RAM
32K bytes EPROM;no page zero ROM;increased RAM;
self-check mode replaced by bootstrap firmware
TPG
MC68HC05B6
Rev. 4
INTRODUCTION
MOTOROLA
1-1
1
1.1
Features
Hardware features
•
•
Fully static design featuring the industry standard M68HC05 family CPU core
On chip crystal oscillator with divide by 2 or a software selectable divide by 32 option (SLOW
mode)
•
•
•
•
•
•
•
•
•
•
•
•
•
2.1 MHz internal operating frequency at 5V; 1.0 MHz at 3V
High speed version available
176 bytes of RAM
5936 bytes of user ROM plus 14 bytes of user vectors
256 bytes of byte erasable EEPROM with internal charge pump and security bit
Write/erase protect bit for 224 of the 256 bytes EEPROM
Self test/bootstrap mode
Power saving STOP, WAIT and SLOW modes
Three 8-bit parallel I/O ports and one 8-bit input-only port
Software option available to output the internal E-clock to port pin PC2
16-bit timer with 2 input captures and 2 output compares
Computer operating properly (COP) watchdog timer
Serial communications interface system (SCI) with independent transmitter/receiver baud rate
selection; receiver wake-up function for use in multi-receiver systems
•
•
•
•
8 channel A/D converter
2 pulse length modulation systems which can be used as D/A converters
One interrupt request input plus 4 on-board hardware interrupt sources
Available in 52-pin plastic leaded chip carrier (PLCC), 64-pin quad flat pack (QFP) and 56-pin
shrink dual in line (SDIP) packages
•
•
Complete development system support available using the MMDS05 development station with
the M68HC05B32EM emulation module
Extended operating temperature range of -40 to +125 °C
TPG
MOTOROLA
1-2
INTRODUCTION
MC68HC05B6
Rev. 4
1
1.2
Mask options for the MC68HC05B6
The MC68HC05B6 has three mask options that are programmed during manufacture and must be
specified on the order form.
•
•
•
Power-on-reset delay (t
) = 16 or 4064 cycles
PORL
Automatic watchdog enable/disable following a power-on or external reset
Watchdog enable/disable during WAIT mode
Warning: It is recommended that an external clock is always used if t
is set to 16 cycles.This
PORL
will prevent any problems arising with oscillator stability when the device is put into
STOP mode.
PA0
PA1
PA2
PA3
256 bytes
EEPROM
PA4
PA5
PA6
PA7
5950 bytes
User ROM
VPP1
Charge pump
(including 14 bytes
User vectors)
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESET
IRQ
COP watchdog
OSC2
OSC1
Oscillator
÷ 2 /÷ 32
432 bytes
self check ROM
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
M68HC05
CPU
176 bytes
RAM
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
programmable
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PD7/AN7
VRH
PLMA D/A
PLMB D/A
PLM
VRL
Figure 1-1 MC68HC05B6 block diagram
TPG
MC68HC05B6
Rev. 4
INTRODUCTION
MOTOROLA
1-3
1
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TPG
MOTOROLA
1-4
INTRODUCTION
MC68HC05B6
Rev. 4
2
2
MODES OF OPERATION AND PIN
DESCRIPTIONS
2.1
Modes of operation
The MC68HC05B6 MCU has two modes of operation, namely single chip and self check modes.
Table 2-1 shows the conditions required to enter each mode on the rising edge of RESET.
Table 2-1 Mode of operation selection
IRQ pin
to V
TCAP1 pin
to V
DD
PD3
X
PD4
X
Mode
Single chip
V
V
SS
SS
DD
DD
2V
2V
V
1
0
Serial RAM loader
DD
V
1
1
Jump to any address
DD
DD
2.1.1
Single chip mode
This is the normal operating mode of the MC68HC05B6. In this mode the device functions as a
self-contained microcomputer (MCU) with all on-board peripherals, including the three 8-bit I/O
ports and the 8-bit input-only port, available to the user. All address and data activity occurs within
the MCU.
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-1
2.2
Serial RAM loader
2
The ‘load program in RAM and execute’ mode is entered if the following conditions are satisfied
when the reset pin is released to V . The format used is identical to the format used for the
DD
MC68HC805C4. The SEC bit in the options register must be inactive, i.e. set to ‘1’.
–
–
–
–
IRQ at 2xV
DD
TCAP1 at V
DD
PD3 at V for at least 30 machine cycles after reset
DD
PD4 at V for at least 30 machine cycles after reset
SS
In the ‘load program in RAM and execute’ routine, user programs are loaded into MCU RAM via
the SCI port and then executed. Data is loaded sequentially, starting at RAM location $0050, until
the last byte is loaded. Program control is then transferred to the RAM program starting at location
$0051.The first byte loaded is the count of the total number of bytes in the program plus the count
byte. The program starts at the second byte in RAM. During the firmware initialization stage, the
SCI is configured for the NRZ data format (idle line, start bit, eight data bits and stop bit).The baud
rate is 9600 with a 4 MHz crystal. A program to convert ASCII S-records to the format required by
the RAM loader is available from Motorola.
If immediate execution is not desired after loading the RAM program, it is possible to hold off
execution.This is accomplished by setting the byte count to a value that is greater than the overall
length of the loaded data. When the last byte is loaded, the firmware will halt operation expecting
additional data to arrive.At this point, the reset switch is placed in the reset position which will reset
the MCU, but keep the RAM program intact. All routines can now be entered from this state,
including the one which will execute the program in RAM (see Section 2.3).
To load a program in the EEPROM, the ‘load program in RAM and execute’ function is also used.
In this instance the process involves two distinct steps. Firstly, the RAM is loaded with a program
which will control the loading of the EEPROM, and when the RAM contents are executed, the MCU
is instructed to load the EEPROM.
The erased state of the EEPROM is $FF.
Figure 2-1 shows the schematic diagram of the circuit required for the serial RAM loader.
TPG
MOTOROLA
2-2
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
P1
GND
+5V
2
10 nF
47 µF
2xV
DD
10 kΩ
10
VDD
RESET
16
17
OSC1
OSC2
10 MΩ
18
RESET
0.01 µF
22 pF
22 pF
4 MHz
6
NC
NC
10 kΩ
15
9600 Bd
RS232
19
11
9
IRQ
PD3
50
52
RS232 level translator
suggested:
RDI
TDO
MC145406 or MAX232
PD4
22
8
24
25
26
27
28
29
30
31
TCAP1
VRH
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
7
VRL
40
20
21
51
VPP1
PLMA
PLMB
SCLK
32
33
34
35
36
37
38
39
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
Connect as required
for the application
Connect as required
for the application
1
TCMP2
TCAP2
TCMP1
23
2
42
43
44
45
46
47
48
49
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
3
4
5
12
13
14
PD7
PD6
PD5
PD2
PD1
PD0
VSS
41
Figure 2-1 MC68HC05B6 ‘load program in RAM and execute’ schematic diagram
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-3
2.3
‘Jump to any address’
2
The ‘jump to any address’ mode is entered when the reset pin is released to V , if the following
conditions are satisfied:
DD
–
–
–
–
IRQ at 2xV
DD
TCAP1 at V
DD
PD3 at V for at least 30 machine cycles after reset
DD
PD4 at V for at least 30 machine cycles after reset
DD
This function allows execution of programs previously loaded in RAM or EEPROM using the
methods outlined in Section 2.2.
To execute the ‘jump to any address’ function, data input at port A has to be $CC and data input at
port B and port C should represent the MSB and LSB respectively, of the address to jump to for
execution of the user program. A schematic diagram of the circuit required is shown in Figure 2-2.
TPG
MOTOROLA
2-4
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
P1
GND
+5V
2
10 nF
47 µF
2xV
DD
10 kΩ
10
VDD
RESET
16
17
OSC1
OSC2
10 MΩ
18
RESET
0.01 µF
22 pF
22 pF
4 MHz
6
NC
NC
10 kΩ
15
19
11
9
IRQ
PD3
8 x 10 kΩ optional (see note)
24
25
26
27
28
29
30
31
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PD4
22
8
TCAP1
VRH
7
VRL
40
20
21
VPP1
PLMA
PLMB
8 x 10 kΩ
32
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
33
34
35
36
37
38
39
51
50
52
1
SCLK
RDI
Connect as required
for the application
TDO
TCMP2
TCAP2
TCMP1
8 x 10 kΩ
23
2
42
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
43
44
45
46
47
48
49
3
4
5
12
13
14
PD7
PD6
PD5
PD2
PD1
PD0
VSS
41
Note:
These eight resistors are optional; direct connection is possible if pins PA0-PA7, PB0-PB7 and PC0-PC7 are
kept in input mode during application.
Figure 2-2 MC68HC05B6 ‘jump to any address’ schematic diagram
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-5
2.4
Low power modes
2
The STOP and WAIT instructions have different effects on the programmable timer, the serial
communications interface, the watchdog system, the EEPROM and the A/D converter. These
different effects are described in the following sections.
2.4.1
STOP
The STOP instruction places the MCU in its lowest power consumption mode. In STOP mode, the
internal oscillator is turned off, halting all internal processing including timer, serial
communications interface and the A/D converter (see flowchart in Figure 2-3). The only way for
the MCU to wake-up from the STOP mode is by receipt of an external interrupt or by the detection
of a reset (logic low on RESET pin or a power-on reset).
During STOP mode, the I-bit in the CCR is cleared to enable external interrupts (see
Section 10.1.5).The SM bit is cleared to allow nominal speed operation for the 4064 cycles count
while exiting STOP mode (see Section 2.4.3).
All other registers and memory remain unaltered and all input/output lines remain unchanged.This
continues until an external interrupt (IRQ) or reset is sensed, at which time the internal oscillator
is turned on. The external interrupt or reset causes the program counter to vector to the
corresponding locations ($1FFA, B and $1FFE, F respectively).
When leaving STOP mode, a t
internal cycles delay is provided to give the oscillator time to
PORL
stabilise before releasing CPU operation.This delay is selectable via a mask option to be either 16
or 4064 cycles. The CPU will resume operation by servicing the interrupt that wakes it up, or by
fetching the reset vector, if reset wakes it up.
Warning: If t
is selected to be 16 cycles, it is recommended that an external clock signal is
PORL
used to avoid problems with oscillator stability while the device is in STOP mode.
Note:
The stacking corresponding to an eventual interrupt to go out of STOP mode will only
be executed when going out of STOP mode.
The following list summarizes the effect of STOP mode on the individual modules of the
MC68HC05B6.
–
–
–
–
–
–
–
The watchdog timer is reset; refer to Section 9.1.4.1
The EEPROM acts as read-only memory (ROM); refer to Section 3.6
All SCI activity stopped; refer to Section 6.13
The timer stops counting; refer to Section 5.6
The PLM outputs remain at current level; refer to Section 7.3
The A/D converter is disabled; refer to Section 8.3
The I-bit in the CCR is cleared
TPG
MOTOROLA
2-6
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
STOP
WAIT
2
YES
Watchdog active?
NO
Oscillator active.Timer, SCI,
A/D, EEPROM clocks active.
Processor clocks stopped
Clear I-bit
Stop oscillator and all
clocks.
Clear I bit.
NO
NO
Reset?
YES
Reset?
IRQ
external
interrupt?
IRQ
external
interrupt?
NO
YES
NO
YES
YES
YES
Timer interrupt?
NO
YES
NO
SCI interrupt?
Turn on oscillator.
Wait for time delay to
stabilise
Restart processor clock
Generate
watchdog reset
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
(1) Fetch reset vector or
(2) Service interrupt:
a. stack
b. set I-bit
b. set I-bit
c. vector to interrupt
routine
c. vector to interrupt
routine
Figure 2-3 STOP and WAIT flowcharts
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-7
2.4.2
WAIT
2
The WAIT instruction places the MCU in a low power consumption mode, but WAIT mode
consumes more power than STOP mode. All CPU action is suspended and the watchdog is
disabled, but the timer, A/D and SCI systems remain active and operate as normal (see flowchart
in Figure 2-3). All other memory and registers remain unaltered and all parallel input/output lines
remain unchanged.The programming or erase mechanism of the EEPROM is also unaffected, as
well as the charge pump high voltage generator.
During WAIT mode the I-bit in the CCR is cleared to enable all interrupts. The INTE bit in the
miscellaneous register (Section 2.5) is not affected by WAIT mode. When any interrupt or reset is
sensed, the program counter vectors to the locations containing the start address of the interrupt
or reset service routine.
Any IRQ, timer (overflow, input capture or output compare) or SCI interrupt (in addition to a logic
low on the RESET pin) causes the processor to exit WAIT mode.
If a non-reset exit from WAIT mode is performed (i.e. timer overflow interrupt exit), the state of the
remaining systems will be unchanged.
If a reset exit from WAIT mode is performed the entire system reverts to the disabled reset state.
Note:
The stacking corresponding to an eventual interrupt to leave WAIT mode will only be
executed when leaving WAIT mode.
The following list summarizes the effect of WAIT mode on the modules of the MC68HC05B6.
–
The watchdog timer functions according to the mask option selected; refer
to Section 9.1.4.2
–
–
–
–
–
–
The EEPROM is not affected; refer to Section 3.7
The SCI is not affected; refer to Section 6.14
The timer is not affected; refer to Section 5.7
The PLM is not affected; refer to Section 7.4
The A/D converter is not affected; refer to Section 8.4
The I-bit in the CCR is cleared
2.4.2.1
Power consumption during WAIT mode
Power consumption during WAIT mode depends on how many systems are active. The power
consumption will be highest when all the systems (A/D, timer, EEPROM and SCI) are active, and
lowest when the EEPROM erase and programming mechanism, SCI and A/D are disabled. The
timer cannot be disabled in WAIT mode. It is important that before entering WAIT mode, the
programmer sets the relevant control bits for the individual modules to reflect the desired
functionality during WAIT mode.
Power consumption may be further reduced by the use of SLOW mode.
TPG
MOTOROLA
2-8
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
2.4.3
SLOW mode
2
The SLOW mode function is controlled by the SM bit in the miscellaneous register at location
$000C. It allows the user to insert, under software control, an extra divide-by-16 between the
oscillator and the internal clock driver (see Figure 2-4).This feature permits a slow down of all the
internal operations and thus reduces power consumption.The SLOW mode function should not be
enabled while using the A/D converter or while erasing/programming the EEPROM unless the
internal A/D RC oscillator is turned on.
OSC2
pin
OSC1
pin
fOSC
fOSC/2
Oscillator
÷ 2
÷ 16
fOSC/32
SM–bit
(bit 1, $000C)
Control logic
Main internal clock
Figure 2-4 Slow mode divider block diagram
2.4.3.1
Miscellaneous register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Miscellaneous
$000C POR INTP INTN INTE SFA SFB
SM WDOG ?001 000?
SM — Slow mode
1 (set)
–
The system runs at a bus speed 16 times lower than normal
(f /32). SLOW mode affects all sections of the device, including
OSC
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
/2).
OSC
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-9
2.5
Pin descriptions
VDD and VSS
2
2.5.1
Power is supplied to the microcontroller using these two pins.VDD is the positive supply and VSS
is ground.
It is in the nature of CMOS designs that very fast signal transitions occur on the MCU pins.These
short rise and fall times place very high short-duration current demands on the power supply. To
prevent noise problems, special care must be taken to provide good power supply by-passing at
the MCU. By-pass capacitors should have good high-frequency characteristics and be as close to
the MCU as possible. Bypassing requirements vary, depending on how heavily the MCU pins are
loaded.
2.5.2
IRQ
This is an input-only pin for external interrupt sources. Interrupt triggering is selected using the
INTP and INTN bits in the miscellaneous register, to be one of four options detailed in Table 9-3.
In addition, the external interrupt facility (IRQ) can be disabled using the INTE bit in the
miscellaneous register (see Section 3.8). It is only possible to change the interrupt option bits in
the miscellaneous register while the I-bit is set. Selecting a different interrupt option will
automatically clear any pending interrupts. Further details of the external interrupt procedure can
be found in Section 9.2.3.1.
The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity.
2.5.3
RESET
This active low I/O pin is used to reset the MCU. Applying a logic zero to this pin forces the device
to a known start-up state. An external RC-circuit can be connected to this pin to generate a
power-on-reset (POR) if required. In this case, the time constant must be great enough to allow
the oscillator circuit to stabilize. This input has an internal Schmitt trigger to improve noise
immunity. When a reset condition occurs internally, i.e. from the COP watchdog, the RESET pin
provides an active-low open drain output signal that may be used to reset external hardware.
2.5.4
TCAP1
The TCAP1 input controls the input capture 1 function of the on-chip programmable timer system.
TPG
MOTOROLA
2-10
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
2.5.5
TCAP2
2
The TCAP2 input controls the input capture 2 function of the on-chip programmable timer system.
2.5.6
TCMP1
The TCMP1 pin is the output of the output compare 1 function of the timer system.
2.5.7
TCMP2
The TCMP2 pin is the output of the output compare 2 function of the timer system.
2.5.8
OSC1, OSC2
These pins provide control input for an on-chip oscillator circuit. A crystal, ceramic resonator or
external clock signal connected to these pins supplies the oscillator clock.The oscillator frequency
(f
) is divided by two to give the internal bus frequency (f ). There is also a software option
OP
OSC
which introduces an additional divide by 16 into the oscillator clock, giving an internal bus
frequency of f
/32.
OSC
2.5.8.1
Crystal
The circuit shown in Figure 2-5(a) is recommended when using either a crystal or a ceramic
resonator. Figure 2-5(d) lists the recommended capacitance and feedback resistance values.The
internal oscillator is designed to interface with an AT-cut parallel-resonant quartz crystal resonator
in the frequency range specified for f
(see Section 11.4). Use of an external CMOS oscillator
OSC
is recommended when crystals outside the specified ranges are to be used. The crystal and
associated components should be mounted as close as possible to the input pins to minimise
output distortion and start-up stabilisation time. The manufacturer of the particular crystal being
considered should be consulted for specific information.
2.5.8.2
Ceramic resonator
A ceramic resonator may be used instead of a crystal in cost sensitive applications.The circuit shown
in Figure 2-5(a) is recommended when using either a crystal or a ceramic resonator. Figure 2-5(d) lists
the recommended capacitance and feedback resistance values. The manufacturer of the particular
ceramic resonator being considered should be consulted for specific information.
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-11
2.5.8.3
External clock
2
An external clock should be applied to the OSC1 input, with the OSC2 pin left unconnected, as
shown in Figure 2-5(c). The t or t specifications (see Section 11.4) do not apply when
using an external clock input. The equivalent specification of the external clock source should be
OXOV
ILCH
used in lieu of t
or t
.
OXOV
ILCH
L
C
R
S
1
OSC1
OSC2
MCU
C
0
OSC1
OSC2
R
P
(b) Crystal equivalent circuit
MCU
C
C
OSC2
OSC1
OSC1
OSC2
(a) Crystal/ceramic resonator
oscillator connections
External
clock
NC
(c) External clock source connections
Crystal
Ceramic resonator
2MHz 4MHz
Unit
2 – 4MHz
10
Unit
Ω
R (max)
400
5
75
7
Ω
pF
R (typ)
S
S
C
C
40
pF
0
0
C
8
12
ƒF
pF
C
4.3
pF
1
1
C
C
15 – 40 15 – 30
15 – 30 15 – 25
C
C
30
pF
OSC1
OSC2
P
OSC1
OSC2
P
pF
30
pF
R
10
10
MΩ
—
R
1 – 10
1250
MΩ
—
Q
30 000 40 000
Q
(d) Typical crystal and ceramic resonator parameters
Figure 2-5 Oscillator connections
TPG
MOTOROLA
2-12
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
2.5.9
RDI (Receive data in)
2
The RDI pin is the input pin of the SCI receiver.
2.5.10
TDO (Transmit data out)
The TDO pin is the output pin of the SCI transmitter.
2.5.11
SCLK
The SCLK pin is the clock output pin of the SCI transmitter.
2.5.12
PLMA
The PLMA pin is the output of pulse length modulation converter A.
2.5.13
PLMB
The PLMB pin is the output of pulse length modulation converter B.
2.5.14
VPP1
The VPP1 pin is the output of the charge pump for the EEPROM1 array.
2.5.15
VRH
The VRH pin is the positive reference voltage for the A/D converter.
2.5.16
VRL
The VRL pin is the negative reference voltage for the A/D converter.
2.5.17
PA0 – PA7/PB0 – PB7/PC0 – PC7
These 24 I/O lines comprise ports A, B and C.The state of any pin is software programmable, and
all the pins are configured as inputs during power-on or reset.
Under software control the PC2 pin can output the internal E-clock (see Section 4.2).
2.5.18
PD0/AN0–PD7/AN7
This 8-bit input only port (D) shares its pins with the A/D converter. When enabled, the A/D
converter uses pins PD0/AN0 – PD7/AN7 as its analog inputs. On reset, the A/D converter is
disabled which forces the port D pins to be input only port pins (see Section 8.5).
TPG
MC68HC05B6
Rev. 4
MODES OF OPERATION AND PIN DESCRIPTIONS
MOTOROLA
2-13
2
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
2-14
MODES OF OPERATION AND PIN DESCRIPTIONS
MC68HC05B6
Rev. 4
3
3
MEMORY AND REGISTERS
The MC68HC05B6 MCU is capable of addressing 8192 bytes of memory and registers with its
program counter. The memory map includes 5950 bytes of User ROM (including User vectors),
432 bytes of self check ROM, 176 bytes of RAM and 256 bytes of EEPROM.
3.1
Registers
All the I/O, control and status registers of the MC68HC05B6 are contained within the first 32-byte
block of the memory map, as shown in Figure 3-1. The miscellaneous register is shown in
Section 3.8 as this register contains bits which are relevant to several modules.
3.2
RAM
The user RAM comprises 176 bytes of memory, from $0050 to $00FF.This is shared with a 64 byte
stack area. The stack begins at $00FF and may extend down to $00C0.
Note:
Using the stack area for data storage or temporary work locations requires care to prevent
the data from being overwritten due to stacking from an interrupt or subroutine call.
3.3
ROM
The User ROM consists of 5950 bytes of ROM mapped as follows:
•
•
•
48 bytes of page zero ROM from $0020 to $004F
5888 bytes of User ROM from $0800 to $1EFF
14 bytes of User vectors from $1FF2 to $1FFF
TPG
MC68HC05B6
Rev. 4
MEMORY AND REGISTERS
MOTOROLA
3-1
3.4
Self-check ROM
There are two areas of self-check ROM (ROMI and ROMII) located from $0200 to $02BF (192
bytes) and $1F00 to $1FEF (240 bytes) respectively.
3
MC68HC05B6
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
ROM
(48 bytes)
RAM
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
OPTR (1 byte)
Non protected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
Timer control register
Self-check ROM I
(192 bytes)
Timer status register
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$02C0
$0800
User ROM
(5888 bytes)
Counter low register
$1F00
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Self-check ROM II
(240 bytes)
$1FF0
$1FF2–3
$1FF4–5
SCI
Timer overflow
$1FF6–7 Timer output compare 1& 2
$1FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
$1FFA–B
$1FFC–D
External IRQ
SWI
Options register
$0100
$1FFE–F Reset/power-on reset
Reserved
Figure 3-1 Memory map of the MC68HC05B6
TPG
MOTOROLA
3-2
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4
3.5
EEPROM
The user EEPROM consists of 256 bytes of memory located from address $0100 to $01FF. 255
bytes are general purpose and 1 byte is used by the option register. The non-volatile EEPROM is
byte erasable.
3
An internal charge pump provides the EEPROM voltage (V
), which removes the need to supply
PP1
a high voltage for erase and programming functions.The charge pump is a capacitor/diode ladder
network which will give a very high impedance output of around 20-30 MΩ. The voltage of the
charge pump is visible at the VPP1 pin. During normal operation of the device, where
programming/erasing of the EEPROM array will occur, VPP1 should never be connected to either
VDD or VSS as this could prevent the charge pump reaching the necessary programming voltage.
Where it is considered dangerous to leave VPP1 unconnected for reasons of excessive noise in a
system, it may be tied to V ; this will protect the EEPROM data but will also increase power
DD
consumption, and therefore it is recommended that the protect bit function is used for regular
protection of EEPROM data (see Section 3.5.5).
In order to achieve a higher degree of security for stored data, there is no capability for bulk or row
erase operations.
The EEPROM control register ($0007) provides control of the EEPROM programming and erase
operations.
Warning: The VPP1 pin should never be connected to VSS, as this could cause permanent
damage to the device.
3.5.1
EEPROM control register
State
on reset
Address bit 7
$0007
bit 6
0
bit 5
0
bit 4
0
bit 3
bit 2
bit 1
bit 0
EEPROM/ECLK control
0
ECLK E1ERA E1LAT E1PGM 0000 0000
ECLK
See Section 4.3 for a description of this bit.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
TPG
MC68HC05B6
Rev. 4
MEMORY AND REGISTERS
MOTOROLA
3-3
E1LAT — EEPROM programming latch enable bit
1 (set)
–
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
3
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
erase time or t
programming time, the E1LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) Internal charge pump generator switched on.
–
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are give in Table 3-1.
Table 3-1 EEPROM control bits description
E1ERA E1LAT E1PGM
Description
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
Read condition
Ready to load address/data for program/erase
Byte programming in progress
Ready for byte erase (load address)
Byte erase in progress
Note:
All combinations are not shown in the above table, since the E1PGM and E1ERA bits
are cleared when the E1LAT bit is at zero, and will result in a read condition.
TPG
MOTOROLA
3-4
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4
3.5.2
EEPROM read operation
To be able to read from EEPROM, the E1LAT bit has to be at logic zero, as shown in Table 3-1.
While this bit is at logic zero, the E1PGM bit and the E1ERA bit are permanently reset to zero and
the 256 bytes of EEPROM may be read as if it were a normal ROM area.The internal charge pump
generator is automatically switched off since the E1PGM bit is reset.
3
If a read operation is executed while the E1LAT bit is set (erase or programming sequence), data
resulting from the operation will be $FF.
Note:
When not performing any programming or erase operation, it is recommended that
EEPROM should remain in the read mode (E1LAT = 0)
3.5.3
EEPROM erase operation
To erase the contents of a byte of the EEPROM, the following steps should be taken:
Set the E1LAT bit.
1
1) Set the E1ERA bit (1& 2 may be done simultaneously with the same
instruction).
2) Write address/data to the EEPROM address to be erased.
3) Set the E1PGM bit.
4) Wait for a time t
.
ERA1
5) Reset the E1LAT bit (to logic zero).
While an erase operation is being performed, any access of the EEPROM array will not be
successful.
The erased state of the EEPROM is $FF and the programmed state is $00.
Note:
Data written to the address to be erased is not used, therefore its value is not significant.
If a second word is to be erased, it is important that the E1LAT bit be reset before restarting the
erasing sequence otherwise any write to a new address will have no effect.This condition provides
a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
TPG
MC68HC05B6
Rev. 4
MEMORY AND REGISTERS
MOTOROLA
3-5
3.5.4
EEPROM programming operation
To program a byte of EEPROM, the following steps should be taken:
1
2
3
4
5
Set the E1LAT bit.
Write address/data to the EEPROM address to be programmed.
Set the E1PGM bit.
3
Wait for time t
.
PROG1
Reset the E1LAT bit (to logic zero).
While a programming operation is being performed, any access of the EEPROM array will not be
successful.
Warning: To program a byte correctly, it has to have been previously erased. It is advised that this
is done only for 0→1 transitions, as this saves excessive overwriting of EEPROM.
If a second word is to be programmed, it is important that the E1LAT bit be reset before restarting
the programming sequence otherwise any write to a new address will have no effect.This condition
provides a higher degree of security for the stored data.
User programs must be running from the RAM or ROM as the EEPROM will have its address and
data buses latched.
Note:
224 bytes of EEPROM (address $0120 to $01FF) can be program and erase protected
under the control of bit 1 of the OPTR register detailed in Section 3.5.5.
3.5.5
Options register (OPTR)
This register (OPTR), located at $0100, contains the secure and protect functions for the EEPROM
and allows the user to select options in a non-volatile manner. The contents of the OPTR register
are loaded into data latches with each power-on or external reset.
State
Address bit 7
$0100
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
EE1P SEC Not affected
(1)
Options (OPTR)
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
TPG
MOTOROLA
3-6
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
of the options register.
3
1 (set)
–
Part 2 of the EEPROM array is not protected; all 256 bytes of EEPROM
can be accessed for any read, erase or programming operations
0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful
When this bit is set to 1 (erased), the protection will remain until the next power-on or external
reset. EE1P can only be written to ‘0’ when the ELAT bit in the EEPROM control register is set.
SEC – Security bit
This high security bit allows the user to secure the EEPROM data from external accesses. When
the SEC bit is at ‘0’, the EEPROM contents are secured by preventing any entry to test mode.The
only way to erase the SEC bit to ‘1’ externally is to enter self-check mode, at which time the entire
EEPROM contents will be erased. When the SEC bit is changed, its new value will have no effect
until the next external or power-on reset.
3.6
EEPROM during STOP mode
When entering STOP mode, the EEPROM is automatically set to the read mode and the VPP1
high voltage charge pump generator is automatically disabled.
3.7
EEPROM during WAIT mode
The EEPROM is not affected by WAIT mode. Any program/erase operation will continue as in
normal operating mode.The charge pump is not affected by WAIT mode, therefore it is possible to
wait the t
erase time or t
programming time in WAIT mode.
ERA1
PROG1
Under normal operating conditions, the charge pump generator is driven by the internal CPU
clocks. When the operating frequency is low, e.g. during WAIT mode, the clocking should be done
by the internal A/D RC oscillator. The RC oscillator is enabled by setting the ADRC bit of the A/D
status/control register at $0009.
TPG
MC68HC05B6
Rev. 4
MEMORY AND REGISTERS
MOTOROLA
3-7
Table 3-2 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
3
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
0
0
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA)
0000 0000
CH3 CH2 CH1 CH0 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
TPG
MOTOROLA
3-8
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4
3.8
Miscellaneous register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
3
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
POR — Power-on reset bit (see Section 9.1)
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
–
A power-on reset has occurred.
0 (clear) – No power-on reset has occurred.
INTP, INTN — External interrupt sensitivity options (see Section 9.2)
These two bits allow the user to select which edge the IRQ pin will be sensitive to (see Table 3-3).
Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset,
thus the device is initialised with negative edge and low level sensitivity.
Table 3-3 IRQ sensitivity
INTP
INTN
IRQ sensitivity
Negative edge and low level sensitive
Negative edge only
0
0
1
1
0
1
0
1
Positive edge only
Positive and negative edge sensitive
INTE — External interrupt enable (see Section 9.2)
1 (set) External interrupt function (IRQ) enabled.
–
0 (clear) – External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
TPG
MC68HC05B6
Rev. 4
MEMORY AND REGISTERS
MOTOROLA
3-9
SFA — Slow or fast mode selection for PLMA (see Section 7.1)
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.
1 (set)
–
Slow mode PLMA (4096 x timer clock period).
0 (clear) – Fast mode PLMA (256 x timer clock period).
3
SFB — Slow or fast mode selection for PLMB (see Section 7.1)
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.
1 (set)
–
Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
Note:
The highest speed of the PLM system corresponds to the frequency of the TOF bit
being set, multiplied by 256. The lowest speed of the PLM system corresponds to the
frequency of the TOF bit being set, multiplied by 16.
Warning: Because the SFA bit and SFB bit are not double buffered, it is mandatory to set the SFA
bit and SFB bit to the desired values before writing to the PLM registers; not doing so
could temporarily give incorrect values at the PLM outputs.
SM — Slow mode (see Section 2.4.3)
1 (set)
–
The system runs at a bus speed 16 times lower than normal
(f /32). SLOW mode affects all sections of the device, including
OSC
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
/2).
OSC
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
WDOG — Watchdog enable/disable (see Section 9.1.4)
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
Once the watchdog is enabled, theWDOG bit acts as a reset mechanism for the watchdog counter.
Writing a’1’ to this bit clears the counter to its initial value and prevents a watchdog timeout.
1 (set)
–
Watchdog counter cleared and enabled.
0 (clear) – The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
TPG
MOTOROLA
3-10
MEMORY AND REGISTERS
MC68HC05B6
Rev. 4
4
INPUT/OUTPUT PORTS
4
In single-chip mode, the MC68HC05B6 has a total of 24 I/O lines, arranged as three 8-bit ports (A,
B and C), and eight input-only lines, arranged as one 8-bit port (D). Each I/O line is individually
programmable as either input or output, under the software control of the data direction registers.
The 8-bit input-only port (D) shares its pins with the A/D converter, when the A/D converter is
enabled. To avoid glitches on the output pins, data should be written to the I/O port data register
before writing ones to the corresponding data direction register bits to set the pins to output mode.
4.1
Input/output programming
The bidirectional port lines may be programmed as inputs or outputs under software control. The
direction of each pin is determined by the state of the corresponding bit in the port data direction
register (DDR). Each port has an associated DDR. Any I/O port pin is configured as an output if
its corresponding DDR bit is set to a logic one. A pin is configured as an input if its corresponding
DDR bit is cleared to a logic zero.
At power-on or reset, all DDRs are cleared, thus configuring all port pins as inputs. The data
direction registers can be written to or read by the MCU. During the programmed output state, a
read of the data register actually reads the value of the output data latch and not the I/O pin. The
operation of the standard port hardware is shown schematically in Figure 4-1.
TPG
MC68HC05B6
Rev. 4
INPUT/OUTPUT PORTS
MOTOROLA
4-1
DDRn
DATA
Data direction
register bit
I/O
Pin
Output
buffer
Latched data
register bit
O/P
data
buffer
4
DDRn
DATA
I/O Pin
0
1
1
0
0
0
1
0
1
Output
Input
1
Input
buffer
tristate
tristate
Figure 4-1 Standard I/O port structure
Table 4-1 shows the effect of reading from or writing to an I/O pin in various circumstances. Note
that the read/write signal shown is internal and not available to the user.
Table 4-1 I/O pin states
R/W DDRn
Action of MCU write to/read of data bit
The I/O pin is in input mode. Data is written into the output data latch.
Data is written into the output data latch, and output to the I/O pin.
The state of the I/O pin is read.
0
0
1
1
0
1
0
1
The I/O pin is in output mode. The output data latch is read.
4.2
Ports A and B
These ports are standard M68HC05 bidirectional I/O ports, each comprising a data register and a
data direction register.
Reset does not affect the state of the data register, but clears the data direction register, thereby
returning all port pins to input mode. Writing a ‘1’ to any DDR bit sets the corresponding port pin
to output mode.
TPG
MOTOROLA
4-2
INPUT/OUTPUT PORTS
MC68HC05B6
Rev. 4
4.3
Port C
In addition to the standard port functions described for port A and B, port C pin 2 can be
configured, using the ECLK bit of the EEPROM/ECLK control register, to output the CPU clock. If
this is selected the corresponding DDR bit is automatically set and bit 2 of port C will always read
the output data latch. The other port C pins are not affected by this feature.
State
Address bit 7
$0007
bit 6
0
bit 5
0
bit 4
0
bit 3
bit 2
bit 1
bit 0
on reset
ECLK E1ERA E1LAT E1PGM 0000 0000
4
EEPROM/ECLK control
0
ECLK — External clock output bit
1 (set)
–
–
ECLK CPU clock is output on PC2.
ECLK CPU clock is not output on PC2; port C acts as a normal I/O port.
0 (clear)
The ECLK bit is cleared by power-on or external reset. It is not affected by the execution of a STOP
or WAIT instruction.
The timing diagram of the clock output is shown in Figure 4-2.
Internal clock (PHI2)
External clock (ECLK/PC2)
Output port (if write to output port)
Figure 4-2 ECLK timing diagram
4.4
Port D
This 8-bit input-only port shares its pins with the A/D converter subsystem. When the A/D
converter is enabled, pins PD0-PD7 read the eight analog inputs to the A/D converter. Port D can
be read at any time, however, if it is read during an A/D conversion sequence noise, may be
injected on the analog inputs, resulting in reduced accuracy of the A/D. Furthermore, performing
TPG
MC68HC05B6
Rev. 4
INPUT/OUTPUT PORTS
MOTOROLA
4-3
a digital read of port D with levels other than V or V on the port D pins will result in greater
DD
SS
power dissipation during the read cycle.
As port D is an input-only port there is no DDR associated with it. Also, at power up or external
reset, the A/D converter is disabled, thus the port is configured as a standard input-only port.
Note:
It is recommended that all unused input ports and I/O ports be tied to an appropriate
logic level (i.e. either V or V ).
DD
SS
4
4.5
Port registers
The following sections explain in detail the individual bits in the data and control registers
associated with the ports.
4.5.1
Port data registers A and B (PORTA and PORTB)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
$0000
$0001
Undefined
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
The state of the port data registers following reset is not defined.
4.5.2
Port data register C (PORTC)
State
on reset
Address bit 7
$0002
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
PC2/
ECLK
Port C data (PORTC)
Undefined
Each bit can be configured as input or output via the corresponding data direction bit in the port
data direction register (DDRx).
In addition, bit 2 of port C is used to output the CPU clock if the ECLK bit in the EEPROM
CTL/ECLK register is set (see Section 4.3).
The state of the port data registers following reset is not defined.
TPG
MOTOROLA
4-4
INPUT/OUTPUT PORTS
MC68HC05B6
Rev. 4
4.5.3
Port data register D (PORTD)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port D data (PORTD)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
All the port D bits are input-only and are shared with the A/D converter.The function of each bit is
determined by the ADON bit in the A/D status/control register.
The state of the port data registers following reset is not defined.
4
4.5.3.1
A/D status/control register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A/D status/control
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
ADON — A/D converter on
1 (set)
–
A/D converter is switched on; all port D pins act as analog inputs for
the A/D converter.
0 (clear) – A/D converter is switched off; all port D pins act as input only pins.
Reset clears the ADON bit, thus configuring port D as an input only port.
4.5.4
Data direction registers (DDRA, DDRB and DDRC)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data direction (DDRA)
$0004
$0005
$0006
0000 0000
0000 0000
0000 0000
Port B data direction (DDRB)
Port C data direction (DDRC)
Writing a ‘1’ to any bit configures the corresponding port pin as an output; conversely, writing any
bit to ‘0’ configures the corresponding port pin as an input.
Reset clears these registers, thus configuring all ports as inputs.
TPG
MC68HC05B6
Rev. 4
INPUT/OUTPUT PORTS
MOTOROLA
4-5
4.6
Other port considerations
All output ports can emulate ‘open-drain’ outputs.This is achieved by writing a zero to the relevant
output port latch. By toggling the corresponding data direction bit, the port pin will either be an
output zero or tri-state (an input). This is shown diagrammatically in Figure 4-3.
When using a port pin as an ‘open-drain’ output, certain precautions must be taken in the user
software. If a read-modify-write instruction is used on a port where the‘open-drain’is assigned and
the pin at this time is programmed as an input, it will read it as a ‘one’. The read-modify-write
instruction will then write this ‘one’ into the output data latch on the next cycle. This would cause
the ‘open-drain’ pin not to output a ‘zero’ when desired.
4
Note:
‘Open-drain’ outputs should not be pulled above V
.
DD
Read buffer output
(a)
A
Y
Data direction register bit DDRn
DDRn
A
0
1
0
1
Y
0
1
1
0
0
1
Normal operation – tri state
tri state
tri state
(b)
1
1
0
0
0
1
0
1
low
—
‘Open-drain’
high
high
V
DD
VDD
Px0
‘Open-drain’ output
(c)
DDRx, bit 0 = 0
Portx, bit 0 = 0
DDRx, bit 0 = 0
Portx, bit 0 = 0
Figure 4-3 Port logic levels
TPG
MOTOROLA
4-6
INPUT/OUTPUT PORTS
MC68HC05B6
Rev. 4
5
PROGRAMMABLE TIMER
The programmable timer on the MC68HC05B6 consists of a 16-bit read-only free-running counter,
with a fixed divide-by-four prescaler, plus the input capture/output compare circuitry.The timer can
be used for many purposes including measuring pulse length of two input signals and generating
two output signals. Pulse lengths for both input and output signals can vary from several
microseconds to many seconds. In addition, it works in conjunction with the pulse length
modulation (PLM) system, which can also be referred to as the pulse width modulation system, to
execute two 8-bit D/A PLM (pulse length modulation) conversions, with a choice of two repetition
rates. The timer is also capable of generating periodic interrupts or indicating passage of an
arbitrary multiple of four CPU cycles. A block diagram is shown in Figure 5-1, and timing diagrams
are shown in Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5.
5
The timer has a 16-bit architecture, hence each specific functional segment is represented by two
8-bit registers (except the PLMA and PLMB which use one 8-bit register for each).These registers
contain the high and low byte of that functional segment. Accessing the low byte of a specific timer
function allows full control of that function; however, an access of the high byte inhibits that specific
timer function until the low byte is also accessed.
The 16-bit programmable timer is monitored and controlled by a group of sixteen registers, full
details of which are contained in this section.
Note:
A problem may arise if an interrupt occurs in the time between the high and low bytes
being accessed. To prevent this, the I-bit in the condition code register (CCR) should be
set while manipulating both the high and low byte register of a specific timer function,
ensuring that an interrupt does not occur.
5.1
Counter
The key element in the programmable timer is a 16-bit, free-running counter or counter register,
preceded by a prescaler that divides the internal processor clock by four. The prescaler gives the
timer a resolution of 2µs if the internal bus clock is 2 MHz. The counter is incremented during the
low portion of the internal bus clock. Software can read the counter at any time without affecting
its value.
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-1
Internal bus
8
Internal
processor
clock
8-bit
buffer
High
byte
Low
byte
High
byte
Low
byte
High
byte
Low
byte
High
byte
Low
byte
High
byte
Low
byte
4
÷
16-bit
free-running
counter
Output
compare
register 2
Output
compare
register 1
$0018
$0019
$001C
$001D
$0016
$0017
$001E
$001F
Input capture $0014 Input capture
register 1
register 2
$0015
Counter
alternate
register
$001A
$001B
COP watchdog
counter input
5
To PLM
Internal timer bus
Overflow
detect
circuit
Edge
detect
circuit 1
Edge
detect
circuit 2
Output
compare
circuit 1
Output
compare
circuit 2
TCAP2
pin
TCAP1
pin
TCMP2
pin
D
C
Q
+
+
Latch
TCMP1
pin
D
C
Q
7
6
5
4
3
Latch
Timer status
register
ICF1 OCF1 TOF
ICF2 OCF2
$0013
Timer control
register
$0012
ICIE
OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1
Interrupt circuit
Input capture
interrupt
$1FF8,9
Output compare
interrupt
$1FF6,7
Overflow interrupt
$1FF4,5
Figure 5-1 16-bit programmable timer block diagram
TPG
MOTOROLA
5-2
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
5.1.1
Counter register and alternate counter register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 0
Timer counter high
Timer counter low
$0018
$0019
1111 1111
1111 1100
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
Alternate counter high
Alternate counter low
$001A
$001B
1111 1111
1111 1100
5
The double-byte, free-running counter can be read from either of two locations, $18-$19 (counter
register) or $1A-$1B (alternate counter register). A read from only the less significant byte (LSB)
of the free-running counter ($19 or $1B) receives the count value at the time of the read. If a read
of the free-running counter or alternate counter register first addresses the more significant byte
(MSB) ($18 or $1A), the LSB is transferred to a buffer.This buffer value remains fixed after the first
MSB read, even if the user reads the MSB several times.This buffer is accessed when reading the
free-running counter or alternate counter register LSB and thus completes a read sequence of the
total counter value. In reading either the free-running counter or alternate counter register, if the
MSB is read, the LSB must also be read to complete the sequence. If the timer overflow flag (TOF)
is set when the counter register LSB is read then a read of the timer status register (TSR) will clear
the flag.
The alternate counter register differs from the counter register only in that a read of the LSB does
not clear TOF. Therefore, where it is critical to avoid the possibility of missing timer overflow
interrupts due to clearing of TOF, the alternate counter register should be used.
The free-running counter is set to $FFFC during power-on and external reset and is always a
read-only register. During a power-on reset, the counter begins running after the oscillator start-up
delay. Because the free-running counter is 16 bits preceded by a fixed divide-by-4 prescaler, the
value in the free-running counter repeats every 262,144 internal bus clock cycles.TOF is set when
the counter overflows (from $FFFF to $0000); this will cause an interrupt if TOIE is set.
In some particular timing control applications it may be desirable to reset the 16-bit free running
counter under software control. When the low byte of the counter ($19 or $1B) is written to, the
counter is configured to its reset value ($FFFC).
The divide-by-4 prescaler is also reset and the counter resumes normal counting operation. All of
the flags and enable bits remain unaltered by this operation. If access has previously been made
to the high byte of the free-running counter ($18 or $1A), then the reset counter operation
terminates the access sequence.
Warning: This operation may affect the function of the watchdog system (see Section 9.1.4).The
PLM results will also be affected while resetting the counter.
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-3
5.2
Timer control and status
The various functions of the timer are monitored and controlled using the timer control and status
registers described below.
5.2.1
Timer control register (TCR)
The timer control register ($0012) is used to enable the input captures (ICIE), output compares
(OCIE), and timer overflow (TOIE) functions as well as forcing output compares (FOLV1 and
FOLV2), selecting input edge sensitivity (IEDG1) and levels of output polarity (OLV1 and OLV2).
5
State
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
Timer control (TCR)
ICIE — Input captures interrupt enable
If this bit is set, a timer interrupt is enabled whenever the ICF1 or ICF2 status flag (in the timer
status register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) – Interrupt disabled.
OCIE — Output compares interrupt enable
If this bit is set, a timer interrupt is enabled whenever the OCF1 or OCF2 status flag (in the timer
status register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) – Interrupt disabled.
TOIE — Timer overflow interrupt enable
If this bit is set, a timer interrupt is enabled whenever the TOF status flag (in the timer status
register) is set.
1 (set)
–
Interrupt enabled.
0 (clear) – Interrupt disabled.
TPG
MOTOROLA
5-4
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
FOLV2 — Force output compare 2
This bit always reads as zero, hence writing a zero to this bit has no effect.Writing a one at this position
will force the OLV2 bit to the corresponding output level latch, thus appearing at the TCMP2 pin. Note
that this bit does not affect the OCF2 bit of the status register (see Section 5.4.3).
1 (set)
–
OLV2 bit forced to output level latch.
0 (clear) – No effect.
FOLV1 — Force output compare 1
This bit always reads as zero, hence writing a zero to this bit has no effect.Writing a one at this position
will force the OLV1 bit to the corresponding output level latch, thus appearing at the TCMP1 pin. Note
that this bit does not affect the OCF1 bit of the status register (see Section 5.4.3).
5
1 (set)
–
OLV1 bit forced to output level latch.
0 (clear) – No effect.
OLV2 — Output level 2
When OLV2 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP2 pin. When clear, it will be a low level
which will appear on the TCMP2 pin.
1 (set)
–
A high output level will appear on the TCMP2 pin.
0 (clear) – A low output level will appear on the TCMP2 pin.
IEDG1 — Input edge 1
When IEDG1 is set, a positive-going edge on the TCAP1 pin will trigger a transfer of the
free-running counter value to the input capture register 1. When clear, a negative-going edge
triggers the transfer.
1 (set)
–
TCAP1 is positive-going edge sensitive.
0 (clear) – TCAP1 is negative-going edge sensitive.
Note:
There is no need for an equivalent bit for the input capture register 2 as TCAP2 is
negative-going edge sensitive only.
OLV1 — Output level 1
When OLV1 is set a high output level will be clocked into the output level register by the next
successful output compare, and will appear on the TCMP1 pin. When clear, it will be a low level
which will appear on the TCMP1 pin.
1 (set)
–
A high output level will appear on the TCMP1 pin.
0 (clear) – A low output level will appear on the TCMP1 pin.
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-5
5.2.2
Timer status register (TSR)
The timer status register ($13) is a read only register and contains the status bits corresponding
to the four timer interrupt conditions – ICF1,OCF1, TOF, ICF2 and OCF2.
Accessing the timer status register satisfies the first condition required to clear the status bits.The
remaining step is to access the register corresponding to the status bit.
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Timer status (TSR)
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
ICF1 — Input capture flag 1
5
This bit is set when the selected polarity of edge is detected by the input capture edge detector 1
at TCAP1; an input capture interrupt will be generated, if ICIE is set. ICF1 is cleared by reading
the TSR and then the input capture low register 1 ($15).
1 (set)
–
A valid input capture has occurred.
0 (clear) – No input capture has occurred.
OCF1 — Output compare flag 1
This bit is set when the output compare 1 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF1 is cleared by reading
the TSR and then reading or writing the output compare 1 low register ($17).
1 (set)
–
A valid output compare has occurred.
0 (clear) – No output compare has occurred.
TOF — Timer overflow status flag
This bit is set when the free-running counter overflows from $FFFF to $0000; a timer overflow interrupt
will occur if TOIE is set.TOF is cleared by reading the TSR and the counter low register ($19).
1 (set)
–
Timer overflow has occurred.
0 (clear) – No timer overflow has occurred.
When using the timer overflow function and reading the free-running counter at random times to
measure an elapsed time, a problem may occur whereby the timer overflow flag is unintentionally
cleared if:
1
The timer status register is read or written when TOF is set, and
1) The LSB of the free-running counter is read, but not for the purpose of
servicing the flag.
Reading the alternate counter register instead of the counter register will avoid this potential
problem.
TPG
MOTOROLA
5-6
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
ICF2 — Input capture flag 2
This bit is set when a negative edge is detected by the input capture edge detector 2 at TCAP2;
an input capture interrupt will be generated if ICIE is set. ICF2 is cleared by reading the TSR and
then the input capture low register 2 ($1D).
1 (set)
–
A valid (negative) input capture has occurred.
0 (clear) – No input capture has occurred.
OCF2 — Output compare flag 2
This bit is set when the output compare 2 register contents match those of the free-running
counter; an output compare interrupt will be generated if OCIE is set. OCF2 is cleared by reading
the TSR and then reading or writing the output compare 2 low register ($1F).
5
1 (set)
–
A valid output compare has occurred.
0 (clear) – No output compare has occurred.
5.3
Input capture
‘Input capture’ is a technique whereby an external signal is used to trigger a read of the free
running counter. In this way it is possible to relate the timing of an external signal to the internal
counter value, and hence to elapsed time.
There are two input capture registers:input capture register 1 (ICR1) and input capture register 2 (ICR2).
The same input capture interrupt enable bit (ICIE) is used for the two input captures.
5.3.1
Input capture register 1 (ICR1)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Input capture high 1
Input capture low 1
$0014
$0015
Undefined
Undefined
The two 8-bit registers that make up the 16-bit input capture register 1 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 1 senses
a valid transition at TCAP1. The level transition that triggers the counter transfer is defined by the
input edge bit (IEDG1).When an input capture 1 occurs, the corresponding flag ICF1 inTSR is set.
An interrupt can also accompany an input capture 1 provided the ICIE bit in TCR is set.The 8 most
significant bits are stored in the input capture high 1 register at $14, the 8 least significant bits in
the input capture low 1 register at $15.
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-7
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition.This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 1 on each valid signal transition whether the input capture 1 flag (ICF1) is set or
clear.The input capture register 1 always contains the free-running counter value that corresponds
to the most recent input capture 1. After a read of the input capture 1 register MSB ($14), the
counter transfer is inhibited until the LSB ($15) is also read. This characteristic causes the time
used in the input capture software routine and its interaction with the main program to determine
the minimum pulse period. A read of the input capture 1 register LSB ($15) does not inhibit the
free-running counter transfer since the two actions occur on opposite edges of the internal bus
clock.
5
Reset does not affect the contents of the input capture 1 register, except when exiting STOP mode
(see Section 5.6).
5.3.2
Input capture register 2 (ICR2)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Input capture high 2
Input capture low 2
$001C
$001D
Undefined
Undefined
The two 8-bit registers that make up the 16-bit input capture register 2 are read-only, and are used
to latch the value of the free-running counter after the input capture edge detector circuit 2 senses
a negative transition at pin TCAP2. When an input capture 2 occurs, the corresponding flag ICF2
in TSR is set. An interrupt can also accompany an input capture 2 provided the ICIE bit in TCR is
set.The 8 most significant bits are stored in the input capture 2 high register at $1C, the 8 least
significant bits in the input capture 2 low register at $1D.
The result obtained from an input capture will be one greater than the value of the free-running
counter on the rising edge of the internal bus clock preceding the external transition.This delay is
required for internal synchronization. Resolution is one count of the free-running counter, which is
four internal bus clock cycles. The free-running counter contents are transferred to the input
capture register 2 on each negative signal transition whether the input capture 2 flag (IC2F) is set
or clear. The input capture register 2 always contains the free-running counter value that
corresponds to the most recent input capture 2. After a read of the input capture register 2 MSB
($1C), the counter transfer is inhibited until the LSB ($1D) is also read. This characteristic causes
the time used in the input capture software routine and its interaction with the main program to
determine the minimum pulse period. A read of the input capture register 2 LSB ($1C) does not
inhibit the free-running counter transfer since the two actions occur on opposite edges of the
internal bus clock.
Reset does not affect the contents of the input capture 2 register, except when exiting STOP mode
(see Section 5.6).
TPG
MOTOROLA
5-8
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
5.4
Output compare
‘Output compare’is a technique which may be used, for example, to generate an output waveform,
or to signal when a specific time period has elapsed, by presetting the output compare register to
the appropriate value.
There are two output compare registers: output compare register 1 (OCR1) and output compare
register 2 (OCR2), both of which are read or write registers.
Note:
The same output compare interrupt enable bit (OCIE) is used for the two output
compares.
5
5.4.1
Output compare register 1 (OCR1)
State
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
Undefined
Undefined
Output compare high 1
Output compare low 1
$0016
$0017
The 16-bit output compare register 1 is made up of two 8-bit registers at locations $16 (MSB) and
$17 (LSB). The contents of the output compare register 1 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF1) in the timer status register is set and the output level (OLVL1) is transferred to pin TCMP1.
The output compare register 1 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 1 containing the MSB ($16), the output
compare function is inhibited until the LSB ($17) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($17) will not inhibit the compare
1 function.The processor can write to either byte of the output compare register 1 without affecting
the other byte.The output level (OLVL1) bit is clocked to the output level register and hence to the
TCMP1 pin whether the output compare flag 1 (OCF1) is set or clear.The minimum time required
to update the output compare register 1 is a function of the program rather than the internal
hardware. Because the output compare flag 1 and the output compare register 1 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
–
–
Write to output compare high 1 to inhibit further compares;
Read the timer status register to clear OCF1 (if set);
Write to output compare low 1 to enable the output compare 1 function.
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-9
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.2
Output compare register 2 (OCR2)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Output compare high 2
Output compare low 2
$001E
$001F
Undefined
Undefined
5
The 16-bit output compare register 2 is made up of two 8-bit registers at locations $1E (MSB) and
$1F (LSB). The contents of the output compare register 2 are compared with the contents of the
free-running counter continually and, if a match is found, the corresponding output compare flag
(OCF2) in the timer status register is set and the output level (OLVL2) is transferred to pin TCMP2.
The output compare register 2 values and the output level bit should be changed after each
successful comparison to establish a new elapsed timeout. An interrupt can also accompany a
successful output compare provided the corresponding interrupt enable bit (OCIE) is set. (The
free-running counter is updated every four internal bus clock cycles.)
After a processor write cycle to the output compare register 2 containing the MSB ($1E), the output
compare function is inhibited until the LSB ($1F) is also written. The user must write both bytes
(locations) if the MSB is written first. A write made only to the LSB ($1F) will not inhibit the compare
2 function.The processor can write to either byte of the output compare register 2 without affecting
the other byte.The output level (OLVL2) bit is clocked to the output level register and hence to the
TCMP2 pin whether the output compare flag 2 (OCF2) is set or clear.The minimum time required
to update the output compare register 2 is a function of the program rather than the internal
hardware. Because the output compare flag 2 and the output compare register 2 are not defined
at power on, and not affected by reset, care must be taken when initializing output compare
functions with software. The following procedure is recommended:
–
–
–
Write to output compare high 2 to inhibit further compares;
Read the timer status register to clear OCF2 (if set);
Write to output compare low 2 to enable the output compare 2 function.
TPG
MOTOROLA
5-10
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
The purpose of this procedure is to prevent the OCF1 bit from being set between the time it is read
and the write to the corresponding output compare register.
All bits of the output compare register are readable and writable and are not altered by the timer
hardware or reset. If the compare function is not needed, the two bytes of the output compare
register can be used as storage locations.
5.4.3
Software force compare
A software force compare is required in many applications.To achieve this, bit 3 (FOLV1 for OCR1)
and bit 4 (FOLV2 for OCR2) in the timer control register are used.These bits always read as ‘zero’,
but a write to ‘one’ causes the respective OLVL1 or OLVL2 values to be copied to the respective
output level (TCMP1 and TCMP2 pins).
5
Internal logic is arranged such that in a single instruction, one can change OLVL1 and/or OLVL2,
at the same time causing a forced output compare with the new values of OLVL1 and OLVL2. In
conjunction with normal compare, this function allows a wide range of applications including fixed
frequency generation.
Note:
A software force compare will affect the corresponding output pin TCMP1 and/or
TCMP2, but will not affect the compare flag, thus it will not generate an interrupt.
5.5
Pulse Length Modulation (PLM)
The programmable timer works in conjunction with the PLM system to execute two 8-bit D/A PLM
conversions, with a choice of two repetition rates (see Section 7).
5.5.1
Pulse length modulation registers A and B (PLMA/PLMB)
State
on reset
Address bit 7
Pulse length modulation A (PLMA) $000A
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0000 0000
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Pulse length modulation B (PLMB) $000B
0000 0000
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-11
5.6
Timer during STOP mode
When the MCU enters STOP mode, the timer counter stops counting and remains at that particular
count value until STOP mode is exited by an interrupt. If STOP mode is exited by power-on or
external reset, the counter is forced to $FFFC but if it is exited by external interrupt (IRQ) then the
counter resumes from its stopped value.
Another feature of the programmable timer is that if at least one valid input capture edge occurs at
one of the TCAP pins while in STOP mode, the corresponding input capture detect circuitry is
armed.This action does not wake the MCU or set any timer flags, but when the MCU does wake-up
there will be an active input capture flag (and data) from that first valid edge which occurred during
STOP mode.
If STOP mode is exited by an external reset then no such input capture flag or data action takes
place even if there was a valid input capture edge (at one of the TCAP pins) during STOP mode.
5
5.7
Timer during WAIT mode
The timer system is not affected by WAIT mode and continues normal operation. Any valid timer
interrupt will wake-up the system.
5.8
Timer state diagrams
The relationships between the internal clock signals, the counter contents and the status of the
flag bits are shown in the following figures. It should be noted that the signals labelled ‘internal’
(processor clock, timer clocks and reset) are not available to the user.
TPG
MOTOROLA
5-12
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
Internal
processor clock
Internal
reset
T00
T01
T10
T11
Internal
timer clocks
16-bit
counter
$FFFC
$FFFD
$FFFE
$FFFF
External reset
or end of POR
5
Note:
The counter and timer control registers are the only ones affected by power-on or external reset.
Figure 5-2 Timer state timing diagram for reset
Internal
processor clock
T00
T01
T10
T11
Internal
timer clocks
16-bit
counter
$F123
$F124
$F125
$F126
Input
edge
Internal
capture latch
Input capture
register
$????
$F124
Input capture
flag
Note:
If the input edge occurs in the shaded area from one timer state T10 to the next timer state T10, then
the input capture flag will be set during the next T11 state.
Figure 5-3 Timer state timing diagram for input capture
TPG
MC68HC05B6
Rev. 4
PROGRAMMABLE TIMER
MOTOROLA
5-13
Internal
processor clock
T00
T01
T10
T11
Internal
timer clocks
16-bit
counter
$F456
$F457
$F458
$F459
(Note 1)
Output compare
register
CPU writes $F457
$F457
5
(Note 1)
Compare register
latch
(Note 2)
Output compare
flag and TCMP1,2
Note:
1
The CPU write to the compare registers may take place at any time, but a compare only occurs at timer state
T01.Thus a four cycle difference may exist between the write to the compare register and the actual compare.
1) The output compare flag is set at the timer state T11 that follows the comparison match ($F457 in this example).
Figure 5-4 Timer state timing diagram for output compare
Internal
processor clock
T00
T01
Internal
timer clocks
T10
T11
16-bit
counter
$FFFF
$0000
$0001
$0002
Timer overflow
flag
Note:
The timer overflow flag is set at timer state T11 (transition of counter from $FFFF to $0000). It is cleared
by a read of the timer status register during the internal processor clock high time, followed by a read of the
counter low register.
Figure 5-5 Timer state timing diagram for timer overflow
TPG
MOTOROLA
5-14
PROGRAMMABLE TIMER
MC68HC05B6
Rev. 4
6
SERIAL COMMUNICATIONS INTERFACE
A full-duplex asynchronous serial communications interface (SCI) is provided with a standard
non-return-to-zero (NRZ) format and a variety of baud rates.The SCI transmitter and receiver are
functionally independent and have their own baud rate generator; however they share a common
baud rate prescaler and data format.
The serial data format is standard mark/space (NRZ) and provides one start bit, eight or nine data
bits, and one stop bit.
6
The SCLK pin is the output of the transmitter clock. It outputs the transmitter data clock for
synchronous transmission (no clocks on start bit and stop bit, and a software option to send clock
on last data bit). This allows control of peripherals containing shift registers (e.g. LCD drivers).
Phase and polarity of these clocks are software programmable.
Any SCI bidirectional communication requires a two-wire system: receive data in (RDI) and
transmit data out (TDO).
‘Baud’ and ‘bit rate’ are used synonymously in the following description.
6.1
SCI two-wire system features
•
•
•
•
•
Standard NRZ (mark/space) format
Advanced error detection method with noise detection for noise duration of up to 1/16th bit time
Full-duplex operation (simultaneous transmit and receive)
32 software selectable baud rates
Different baud rates for transmit and receive; for each transmit baud rate, 8 possible receive
baud rates
•
•
•
•
•
Software selectable word length (eight or nine bits)
Separate transmitter and receiver enable bits
Capable of being interrupt driven
Transmitter clocks available without altering the regular transmitter or receiver functions
Four separate enable bits for interrupt control
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-1
Internal bus
SCI interrupt
+
Transmit
data register
$0011
(See note)
$0011
(See note)
Receive
data register
&
&
&
&
$000F
SCCR2
TIE
TCIE
RIE
ILIE
TE
RE
SBK
RWU
7
6
5
4
3
2
1
0
Transmit
data shift
register
Receive
data shift
register
TDO
pin
RDI
pin
+
SCSR
$0010
1
7
6
5
4
3
2
6
TRDE
TC
RDRF IDLE
OR
NF
FE
Wake up
unit
7
TE
SBK
Flag
control
Transmitter
control
Receiver
control
Transmitter
clock
Receiver
clock
Clock extraction
SCLK
pin
phase and
polarity control
7
R8
6
5
4
M
3
2
1
0
SCCR1
$000E
T8
WAKE CPOL CPHA LBCL
Note:
The serial communications data register (SCI SCDR) is controlled by the internal
R/W signal. It is the transmit data register when written to and the receive data
register when read.
Figure 6-1 Serial communications interface block diagram
TPG
MOTOROLA
6-2
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
6.2
SCI receiver features
•
•
•
•
•
•
Receiver wake-up function (idle line or address bit)
Idle line detection
Framing error detection
Noise detection
Overrun detection
Receiver data register full flag
6.3
SCI transmitter features
6
•
•
•
Transmit data register empty flag
Transmit complete flag
Send break
6.4
Functional description
A block diagram of the SCI is shown in Figure 6-1. Option bits in serial control register1 (SCCR1)
select the ‘wake-up’ method (WAKE bit) and data word length (M-bit) of the SCI. SCCR2 provides
control bits that individually enable the transmitter and receiver, enable system interrupts and
provide the wake-up enable bit (RWU) and the send break code bit (SBK). Control bits in the baud
rate register (BAUD) allow the user to select one of 32 different baud rates for the transmitter and
receiver (see Section 6.11.5).
Data transmission is initiated by writing to the serial communications data register (SCDR).
Provided the transmitter is enabled, data stored in the SCDR is transferred to the transmit data
shift register. This transfer of data sets the transmit data register empty flag (TDRE) in the SCI
status register (SCSR) and generates an interrupt (if transmitter interrupts are enabled). The
transfer of data to the transmit data shift register is synchronized with the bit rate clock (see
Figure 6-2). All data is transmitted least significant bit first. Upon completion of data transmission,
the transmission complete flag (TC) in the SCSR is set (provided no pending data, preamble or
break is to be sent) and an interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble or break (in the transmit data shift register) has
been sent, the TC bit will also be set. This will also generate an interrupt if the transmission
complete interrupt enable bit (TCIE) is set. If the transmitter is disabled during a transmission, the
character being transmitted will be completed before the transmitter gives up control of the
TDO pin.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-3
When SCDR is read, it contains the last data byte received, provided that the receiver is enabled.
The receive data register full flag bit (RDRF) in the SCSR is set to indicate that a data byte has
been transferred from the input serial shift register to the SCDR; this will cause an interrupt if the
receiver interrupt is enabled. The data transfer from the input serial shift register to the SCDR is
synchronized by the receiver bit rate clock. The OR (overrun), NF (noise), or FE (framing) error
flags in the SCSR may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and the IDLE bit (which detects
idle line transmission) in SCSR is set. This allows a receiver that is not in the wake-up mode to
detect the end of a message or the preamble of a new message, or to resynchronize with the
transmitter. A valid character must be received before the idle line condition or the IDLE bit will not
be set and idle line interrupt will not be generated.
The SCP0 and SCP1 bits function as a prescaler for SCR0–SCR2 to generate the receiver baud rate
and for SCT0–SCT2 to generate the transmitter baud rate. Together, these eight bits provide multiple
transmitter/receiver rate combinations for a given crystal frequency (see Figure 6-2). This register
should only be written to while both the transmitter and receiver are disabled (TE=0, RE=0).
6
Internal processor clock
SCP0 – SCP1
prescaler
rate control
(÷ NP)
SCT0 – SCT2
transmitter
rate control
(÷ NT)
SCR0 – SCR2
receiver
rate control
(÷ NR)
SCP1 SPC0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0
$000D
÷16
7
6
5
4
3
2
1
0
Baud rate register
Transmitter clock
Receiver clock
Note:
There is a fixed rate divide-by-16 before the transmitter to compensate for the inherent divide-by-16 of the receiver (sampling).
This means that by loading the same value for both the transmitter and receiver baud rate selector, the same baud rates can be
obtained.
Figure 6-2 SCI rate generator division
TPG
MOTOROLA
6-4
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
6.5
Data format
Receive data or transmit data is the serial data that is transferred to the internal data bus from the
receive data input pin (RDI) or from the internal bus to the transmit data output pin (TDO). The
non-return-to-zero (NRZ) data format shown in Figure 6-3 is used and must meet the following
criteria:
–
The idle line is brought to a logic one state prior to transmission/reception of
a character.
–
–
–
A start bit (logic zero) is used to indicate the start of a frame.
The data is transmitted and received least significant bit first.
A stop bit (logic one) is used to indicate the end of a frame. A frame consists
of a start bit, a character of eight or nine data bits, and a stop bit.
–
A break is defined as the transmission or reception of a low (logic zero) for at
least one complete frame time (10 zeros for 8-bit format, 11 zeros for 9-bit).
6
Control bit M selects
8 or 9 bit data
Idle line
0
1
2
3
4
5
6
7
8
0
Start
Stop Start
Figure 6-3 Data format
6.6
Receiver wake-up operation
The receiver logic hardware also supports a receiver wake-up function which is intended for
systems having more than one receiver.With this function a transmitting device directs messages
to an individual receiver or group of receivers by passing addressing information as the initial
byte(s) of each message. The wake-up function allows receivers not addressed to remain in a
dormant state for the remainder of the unwanted message. This eliminates any further software
overhead to service the remaining characters of the unwanted message and thus improves system
performance.
The receiver is placed in wake-up mode by setting the receiver wake-up bit (RWU) in the SCCR2
register. While RWU is set, all of the receiver related status flags (RDRF, IDLE, OR, NF, and FE)
are inhibited (cannot become set). Note that the idle line detect function is inhibited while the RWU
bit is set. Although RWU may be cleared by a software write to SCCR2, it would be unusual to do
so. Normally RWU is set by software and is cleared automatically in hardware by one of the two
methods described below.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-5
6.6.1
Idle line wake-up
In idle line wake-up mode, a dormant receiver wakes up as soon as the RDI line becomes idle. Idle
is defined as a continuous logic high level on the RDI line for ten (or eleven) full bit times. Systems
using this type of wake-up must provide at least one character time of idle between messages to
wake up sleeping receivers, but must not allow any idle time between characters within a message.
6.6.2
Address mark wake-up
In address mark wake-up, the most significant bit (MSB) in a character is used to indicate whether
it is an address (1) or data (0) character. Sleeping receivers will wake up whenever an address
character is received. Systems using this method for wake-up would set the MSB of the first
character of each message and leave it clear for all other characters in the message. Idle periods
may be present within messages and no idle time is required between messages for this wake-up
method.
6
6.7
Receive data in (RDI)
Receive data is the serial data that is applied through the input line and the SCI to the internal bus.
The receiver circuitry clocks the input at a rate equal to 16 times the baud rate.This time is referred
to as the RT rate in Figure 6-4 and as the receiver clock in Figure 6-2.
The receiver clock generator is controlled by the baud rate register, as shown in Figure 6-1 and
Figure 6-2; however, the SCI is synchronized by the start bit, independent of the transmitter.
Once a valid start bit is detected, the start bit, each data bit and the stop bit are sampled three
times at RT intervals 8 RT, 9 RT and 10 RT (1 RT is the position where the bit is expected to start),
as shown in Figure 6-5. The value of the bit is determined by voting logic which takes the value of
the majority of the samples. A noise flag is set when all three samples on a valid start bit or data
bit or the stop bit do not agree.
6.8
Start bit detection
When the input (idle) line is detected low, it is tested for three more sample times (referred to as
the start edge verification samples in Figure 6-4). If at least two of these three verification samples
detect a logic zero, a valid start bit has been detected, otherwise the line is assumed to be idle. A
noise flag is set if one of the three verification samples detect a logic one, thus a valid start bit could
be assumed with a set noise flag present.
TPG
MOTOROLA
6-6
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
16X internal sampling clock
1RT 2RT 3RT 4RT 5RT 6RT 7RT 8RT
RT clock edges for all three examples
Idle
Start
RDI
RDI
RDI
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
Start
Start edge
qualifiers
verification samples
Start
0
Noise
1
1
1
1
1
0
0
Noise
0
Start
0
1
0
0
0
6
Figure 6-4 SCI examples of start bit sampling technique
Previous bit
RDI
Present bit
Samples
Next bit
16RT1RT
8RT 9RT 10RT
16RT1RT
Figure 6-5 SCI sampling technique used on all bits
If there has been a framing error without detection of a break (10 zeros for 8 bit format or 11 zeros
for 9 bit format), the circuit continues to operate as if there actually was a stop bit, and the start
edge will be placed artificially. The last bit received in the data shift register is inverted to a logic
one, and the three logic one start qualifiers (shown in Figure 6-4) are forced into the sample shift
register during the interval when detection of a start bit is anticipated (see Figure 6-6); therefore,
the start bit will be accepted no sooner than it is anticipated.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-7
If the receiver detects that a break (RDRF = 1, FE = 1, receiver data register = $0000) produced
the framing error, the start bit will not be artificially induced and the receiver must actually detect
a logic one before the start bit can be recognised (see Figure 6-7).
Data
Expected stop
Artificial edge
Data
RDI
Start bit
Data samples
a) Case 1: receive line low during artificial edge
Data
Expected stop
Start edge
Data
RDI
Start bit
6
Data samples
b) Case 2: receive line high during expected start edge
Figure 6-6 Artificial start following a framing error
Expected stop
Break
Detected as valid start edge
Start bit
RDI
Start
qualifiers
Start edge
verification
samples
Data samples
Figure 6-7 SCI start bit following a break
6.9
Transmit data out (TDO)
Transmit data is the serial data from the internal data bus that is applied through the SCI to the
output line. Data format is as discussed in Section 6.5 and shown in Figure 6-3. The transmitter
generates a bit time by using a derivative of the RT clock, thus producing a transmission rate equal
to 1/16th that of the receiver sample clock (assuming the same baud rate is selected for both the
receiver and transmitter).
TPG
MOTOROLA
6-8
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
6.10
SCI synchronous transmission
The SCI transmitter allows the user to control a one way synchronous serial transmission. The
SCLK pin is the clock output of the SCI transmitter. No clocks are sent to that pin during start bit
and stop bit. Depending on the state of the LBCL bit (bit 0 of SCCR1), clocks will or will not be
activated during the last valid data bit (address mark). The CPOL bit (bit 2 of SCCR1) allows the
user to select the clock polarity, and the CPHA bit (bit 1 of SCCR1) allows the user to select the
phase of the external clock (see Figure 6-8, Figure 6-9 and Figure 6-10).
During idle, preamble and send break, the external SCLK clock is not activated.
These options allow the user to serially control peripherals which consist of shift registers, without
losing any functions of the SCI transmitter which can still talk to other SCI receivers.These options
do not affect the SCI receiver which is independent of the transmitter.
The SCLK pin works in conjunction with the TDO pin. When the SCI transmitter is disabled
(TE = 0), the SCLK and TDO pins go to the high impedance state.
6
Note:
The LBCL, CPOL and CPHA bits have to be selected before enabling the transmitter to
ensure that the clocks function correctly. These bits should not be changed while the
transmitter is enabled.
RDI
Data out
Data in
Asynchronous
(e.g. Modem)
TDO
SCLK
MC68HC05B6
Data in
Clock
Synchronous
(e.g. shift register,
display driver, etc.)
Output port
Enable
Figure 6-8 SCI example of synchronous and asynchronous transmission
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-9
6.11
SCI registers
The SCI system is configured and controlled by five registers: SCDR, SCCR1, SCCR2, SCSR,
and BAUD.
6.11.1
Serial communications data register (SCDR)
State
on reset
Address bit 7
$0011
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SCI data (SCDR)
0000 0000
The SCDR is controlled by the internal R/W signal and performs two functions in the SCI. It acts
as the receive data register (RDR) when it is read and as the transmit data register (TDR) when it
is written. Figure 6-1 shows this register as two separate registers, RDR and TDR. The RDR
provides the interface from the receive shift register to the internal data bus and the TDR provides
the parallel interface from the internal data bus to the transmit shift register.
6
The receive data register is a read-only register containing the last byte of data received from the
shift register for the internal data bus.The RDR full bit (RDRF) in the serial communications status
register is set to indicate that a byte has been transferred from the input serial shift register to the
SCDR. The transfer is synchronized with the receiver bit rate clock (from the receiver control) as
shown in Figure 6-1. All data is received with the least significant bit first.
The transmit data register (TDR) is a write-only register containing the next byte of data to be
applied to the transmit shift register from the internal data bus. As long as the transmitter is
enabled, data stored in the SCDR is transferred to the transmit shift register (after the current byte
in the shift register has been transmitted).
The transfer is synchronized with the transmitter bit rate clock (from the transmitter control) as
shown in Figure 6-1. All data is received with the least significant bit first.
6.11.2
Serial communications control register 1 (SCCR1)
State
on reset
Address bit 7
$000E R8
bit 6
T8
bit 5
bit 4
M
bit 3
bit 2
bit 1
bit 0
SCI control 1 (SCCR1)
WAKE CPOL CPHA LBCL Undefined
The SCI control register 1 (SCCR1) contains control bits related to the nine data bit character
format, the receiver wake-up feature and the options to output the transmitter clocks for
synchronous transmissions.
TPG
MOTOROLA
6-10
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
R8 — Receive data bit 8
This read-only bit is the ninth serial data bit received when the SCI system is configured for nine
data bit operation (M = 1). The most significant bit (bit 8) of the received character is transferred
into this bit at the same time as the remaining eight bits (bits 0–7) are transferred from the serial
receive shifter to the SCI receive data register.
T8 — Transmit data bit 8
This read/write bit is the ninth data bit to be transmitted when the SCI system is configured for nine
data bit operation (M = 1). When the eight low order bits (bits 0–7) of a transmit character are
transferred from the SCI data register to the serial transmit shift register, this bit (bit 8) is transferred
to the ninth bit position of the shifter.
M — Mode (select character format)
The read/write M-bit controls the character length for both the transmitter and receiver at the same
time.The 9th data bit is most commonly used as an extra stop bit or it can also be used as a parity
bit (see Table 6-1).
6
1 (set)
–
Start bit, 9 data bits, 1 stop bit.
0 (clear) – Start bit, 8 data bits, 1 stop bit.
Table 6-1 Method of receiver wake-up
WAKE
M
Method of receiver wake-up
Detection of an idle line allows the next data type received to cause the receive
data register to fill and produce an RDRF flag.
0
x
Detection of a received one in the eighth data bit allows an RDRF flag and
associated error flags.
1
0
1
Detection of a received one in the ninth data bit allows an RDRF flag and
associated error flags.
1
x = Don’t care
WAKE — Wake-up mode select
This bit allows the user to select the method for receiver wake-up. The WAKE bit can be read or
written to any time. See Table 6-1.
1 (set)
–
Wake-up on address mark; if RWU is set, SCI will wake-up if the 8th
(if M=0) or 9th (if M=1) bit received on the Rx line is set.
0 (clear) – Wake-up on idle line; if RWU is set, SCI will wake-up after 11 (if M=0)
or 12 (if M=1) consecutive ‘1’s on the Rx line.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-11
CPOL – Clock polarity
This bit allows the user to select the polarity of the clocks to be sent to the SCLK pin. It works in
conjunction with the CPHA bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
1 (set)
–
Steady high value at SCLK pin outside transmission window.
0 (clear) – Steady low value at SCLK pin outside transmission window.
This bit should not be manipulated while the transmitter is enabled.
CPHA – Clock phase
This bit allows the user to select the phase of the clocks to be sent to the SCLK pin.This bit works
in conjunction with the CPOL bit to produce the desired clock-data relation (see Figure 6-9 and
Figure 6-10).
1 (set)
–
SCLK clock line activated at beginning of data bit.
6
0 (clear) – SCLK clock line activated in middle of data bit.
This bit should not be manipulated while the transmitter is enabled.
Idle or preceding
Idle or next
transmission
transmission
M = 0 (8 data bits)
Stop
Start
clock
*
*
(CPOL = 0, CPHA = 0)
clock
*
*
(CPOL = 0, CPHA = 1)
clock
(CPOL = 1, CPHA = 0)
clock
(CPOL = 1, CPHA = 1)
data
0
1
2
3
4
5
6
7
Start LSB
MSB Stop
* LBCL bit controls last data clock
Figure 6-9 SCI data clock timing diagram (M=0)
TPG
MOTOROLA
6-12
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
Idle or preceding
transmission
Idle or next
transmission
Stop
M = 1 (9 data bits)
Start
clock
*
*
(CPOL = 0, CPHA = 0)
clock
*
*
(CPOL = 0, CPHA = 1)
clock
(CPOL = 1, CPHA = 0)
clock
(CPOL = 1, CPHA = 1)
data
0
1
2
3
4
5
6
7
8
Start LSB
MSB Stop
* LBCL bit controls last data clock
6
Figure 6-10 SCI data clock timing diagram (M=1)
LBCL – Last bit clock
This bit allows the user to select whether the clock associated with the last data bit transmitted
(MSB) has to be output to the SCLK pin. The clock of the last data bit is output to the SCLK pin if
the LBCL bit is a logic one, and is not output if it is a logic zero.
The last bit is the 8th or 9th data bit transmitted depending on the 8 or 9 bit format selected by M-bit
(seeTable 6-2).
This bit should not be manipulated while the transmitter is enabled.
Table 6-2 SCI clock on SCLK pin
Number of clocks on
Data format M-bit LBCL bit
SCLK pin
8 bit
8 bit
9 bit
9 bit
0
0
1
1
0
1
0
1
7
8
8
9
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-13
6.11.3
Serial communications control register 2 (SCCR2)
The SCI control register 2 (SCCR2) provides the control bits that enable/disable individual SCI
functions.
State
Address bit 7
$000F TIE
bit 6
bit 5
bit 4
ILIE
bit 3
TE
bit 2
bit 1
bit 0
on reset
RE RWU SBK 0000 0000
SCI control (SCCR2)
TCIE RIE
TIE — Transmit interrupt enable
1 (set) TDRE interrupts enabled.
–
0 (clear) – TDRE interrupts disabled.
TCIE — Transmit complete interrupt enable
6
1 (set)
–
TC interrupts enabled.
0 (clear) – TC interrupts disabled.
RIE — Receiver interrupt enable
1 (set)
–
RDRF and OR interrupts enabled.
0 (clear) – RDRF and OR interrupts disabled.
ILIE — Idle line interrupt enable
1 (set)
–
IDLE interrupts enabled.
0 (clear) – IDLE interrupts disabled.
TE — Transmitter enable
When the transmit enable bit is set, the transmit shift register output is applied to the TDO line and
the corresponding clocks are applied to the SCLK pin. Depending on the state of control bit M
(SCCR1), a preamble of 10 (M = 0) or 11 (M = 1) consecutive ones is transmitted when software
sets the TE bit from a cleared state.
If a transmission is in progress and a zero is written to TE, the transmitter will wait until after the
present byte has been transmitted before placing the TDO and the SCLK pin in the idle, high
impedance state.
If the TE bit has been written to a zero and then set to a one before the current byte is transmitted,
the transmitter will wait for that byte to be transmitted and will then initiate transmission of a new
preamble.After this latest transmission, and provided theTDRE bit is set (no new data to transmit),
the line remains idle (driven high while TE = 1); otherwise, normal transmission occurs. This
function allows the user to neatly terminate a transmission sequence.
TPG
MOTOROLA
6-14
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
After loading the last byte in the serial communications data register and receiving the TDRE flag,
the user should clear TE. Transmission of the last byte will then be completed and the line will go
idle.
1 (set)
–
Transmitter enabled.
0 (clear) – Transmitter disabled.
RE — Receiver enable
1 (set) Receiver enabled.
–
0 (clear) – Receiver disabled.
When RE is clear (receiver disabled) all the status bits associated with the receiver (RDRF, IDLE,
OR, NF and FE) are inhibited.
RWU — Receiver wake-up
6
When the receiver wake-up bit is set by the user software, it puts the receiver to sleep and enables
the wake-up function. The type of wake-up mode for the receiver is determined by the WAKE bit
discussed above (in the SCCR1).When the RWU bit is set, no status flags will be set. Flags which
were set previously will not be cleared when RWU is set.
If the WAKE bit is cleared, RWU is cleared by the SCI logic after receiving 10 (M = 0) or 11 (M =1)
consecutive ones. Under these conditions, RWU cannot be set if the line is idle. If the WAKE bit is
set, RWU is cleared after receiving an address bit.The RDRF flag will then be set and the address
byte stored in the receiver data register.
SBK — Send break
If the send break bit is toggled set and cleared, the transmitter sends 10 (M = 0) or 11 (M = 1) zeros
and then reverts to idle sending data. If SBK remains set, the transmitter will continually send
whole blocks of zeros (sets of 10 or 11) until cleared. At the completion of the break code, the
transmitter sends at least one high bit to guarantee recognition of a valid start bit.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-15
6.11.4
Serial communications status register (SCSR)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
OR
bit 2
NF
bit 1
FE
bit 0
SCI status (SCSR)
$0010 TDRE TC RDRF IDLE
1100 000u
The serial communications status register (SCSR) provides inputs to the interrupt logic circuits for
generation of the SCI system interrupt. In addition, a noise flag bit and a framing error bit are also
contained in the SCSR.
TDRE — Transmit data register empty flag
This bit is set when the contents of the transmit data register are transferred to the serial shift
register. New data will not be transmitted unless the SCSR register is read before writing to the
transmit data register to clear the TDRE flag.
If the TDRE bit is clear, this indicates that the transfer has not yet occurred and a write to the serial
communications data register will overwrite the previous value. The TDRE bit is cleared by
accessing the serial communications status register (with TDRE set) followed by writing to the
serial communications data register.
6
TC — Transmit complete flag
This bit is set to indicate that the SCI transmitter has no meaningful information to transmit (no data
in shifter, no preamble, no break). When TC is set the serial line will go idle (continuous MARK).
The TC bit is cleared by accessing the serial communications status register (with TC set) followed
by writing to the serial communications data register. It does not inhibit the transmitter function in
any way.
RDRF — Receive data register full flag
This bit is set when the contents of the receiver serial shift register are transferred to the receiver
data register.
If multiple errors are detected in any one received word, the NF and RDRF bits will be affected as
appropriate during the same clock cycle.The RDRF bit is cleared when the serial communications
status register is accessed (with RDRF set) followed by a read of the serial communications data
register.
IDLE — Idle line detected flag
This bit is set when a receiver idle line is detected (the receipt of a minimum of ten/eleven
consecutive “1”s). This bit will not be set by the idle line condition when the RWU bit is set. This
allows a receiver that is not in the wake-up mode to detect the end of a message, detect the
preamble of a new message or resynchronize with the transmitter. The IDLE bit is cleared by
accessing the serial communications status register (with IDLE set) followed by a read of the serial
communications data register. Once cleared, IDLE will not be set again until after RDRF has been
set, (i.e. until after the line has been active and becomes idle again).
TPG
MOTOROLA
6-16
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
OR — Overrun error flag
This bit is set when a new byte is ready to be transferred from the receiver shift register to the
receiver data register and the receive data register is already full (RDRF bit is set). Data transfer
is inhibited until the RDRF bit is cleared. Data in the serial communications data register is valid in
this case, but additional data received during an overrun condition (including the byte causing the
overrun) will be lost.
The OR bit is cleared when the serial communications status register is accessed (with OR set)
followed by a read of the serial communications data register.
NF — Noise error flag
This bit is set if there is noise on a ‘valid’ start bit, any of the data bits or on the stop bit.The NF bit
is not set by noise on the idle line nor by invalid start bits. If there is noise, the NF bit is not set until
the RDRF flag is set. Each data bit is sampled three times as described in Section 6.7.
The NF bit represents the status of the byte in the serial communications data register.For the byte
being received (shifted in) there will be also a ‘working’ noise flag, the value of which will be
transferred to the NF bit when the serial data is loaded into the serial communications data
register.The NF bit does not generate an interrupt because the RDRF bit gets set with NF and can
be used to generate the interrupt.
6
The NF bit is cleared when the serial communications status register is accessed (with NF set)
followed by a read of the serial communications data register.
FE — Framing error flag
This bit is set when the word boundaries in the bit stream are not synchronized with the receiver
bit counter (generated by the reception of a logic zero bit where a stop bit was expected). The FE
bit reflects the status of the byte in the receive data register and the transfer from the receive shifter
to the receive data register is inhibited by an overrun. The FE bit is set during the same cycle as
the RDRF bit but does not get set in the case of an overrun (OR). The framing error flag inhibits
further transfer of data into the receive data register until it is cleared.
The FE bit is cleared when the serial communications status register is accessed (with FE set)
followed by a read of the serial communications data register.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-17
6.11.5
Baud rate register (BAUD)
The baud rate register provides the means to select two different or equivalent baud rates for the
transmitter and receiver.
State
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
$000D SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 00uu uuuu
SCI baud rate (BAUD)
SCP1, SCP0 — Serial prescaler select bits
These read/write bits determine the prescale factor, NP, by which the internal processor clock is
divided before it is applied to the transmitter and receiver rate control dividers, NT and NR. This
common prescaled output is used as the input to a divider that is controlled by the SCR0–SCR2
bits for the SCI receiver, and by the SCT0–SCT2 bits for the transmitter.
Table 6-3 First prescaler stage
6
Prescaler
SCP1
SCP0
division ratio (NP)
0
0
1
1
0
1
0
1
1
3
4
13
SCT2, SCT1,SCT0 — SCI rate select bits (transmitter)
These three read/write bits select the baud rates for the transmitter.The prescaler output is divided
by the factors shown in Table 6-4.
Table 6-4 Second prescaler stage (transmitter)
Transmitter
division ratio (NT)
SCT2
SCT1
SCT0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
TPG
MOTOROLA
6-18
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
SCR2, SCR1, SCR0 — SCI rate select bits (receiver)
These three read/write bits select the baud rates for the receiver. The prescaler output described
above is divided by the factors shown in Table 6-5.
Table 6-5 Second prescaler stage (receiver)
Receiver
division ratio (NR)
SCR2
SCR1
SCR0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
6
The following equations are used to calculate the receiver and transmitter baud rates:
fop
baudTx =
----------------------------------
16 • NP • NT
fop
baudRx =
-----------------------------------
16 • NP • NR
where:
NP = prescaler divide ratio
NT = transmitter baud rate divide ratio
NR = receiver baud rate divide ratio
baudTx = transmitter baud rate
baudRx = receiver baud rate
f
= oscillator frequency
OSC
6.12
Baud rate selection
The flexibility of the baud rate generator allows many different baud rates to be selected. A
particular baud rate may be generated in several ways by manipulating the various prescaler and
division ratio bits. Table 6-6 shows the baud rates that can be achieved, for five typical crystal
frequencies. These are effectively the highest baud rates which can be achieved using a given
crystal.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-19
Table 6-6 SCI baud rate selection
Crystal frequency – f
(MHz)
OSC
SCP1 SCP0 SCT/R2 SCT/R1 SCT/R0 NP
NT/NR 4.194304
4.00
2.4576
76800
38400
19200
9600
4800
2400
1200
600
2.00
1.8432
57600
28800
14400
7200
3600
1800
900
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
2
131072
65536
32768
16384
8192
4096
2048
1024
43691
21845
10923
5461
2731
1365
683
125000
62500
31250
15625
7813
3906
1953
977
62500
31250
15625
7813
3906
1953
977
1
4
1
8
1
16
32
64
128
1
1
1
1
488
450
3
41667
20833
10417
5208
2604
1302
651
25600
12800
6400
3200
1600
800
20833
10417
5208
2604
1302
651
19200
9600
4800
2400
1200
600
3
2
3
4
3
8
6
3
16
32
64
128
1
3
3
400
326
300
3
341
326
200
163
150
4
32768
16384
8192
4096
2048
1024
512
31250
15625
7813
3906
1953
977
19200
9600
4800
2400
1200
600
15625
7813
3906
1953
977
14400
7200
3600
1800
900
4
2
4
4
4
8
4
16
32
64
128
1
4
488
450
4
488
300
244
225
4
256
244
150
122
113
13
13
13
13
13
13
13
13
10082
5041
2521
1260
630
9615
4808
2404
1202
601
5908
2954
1477
738
4808
2404
1202
601
4431
2215
1108
554
2
4
8
16
32
64
128
369
300
277
315
300
185
150
138
158
150
92
75
69
79
75
46
38
35
Note:
The examples shown above do not apply when the part is operating in slow mode (see
Section 2.4.3).
TPG
MOTOROLA
6-20
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
6.13
SCI during STOP mode
When the MCU enters STOP mode, the baud rate generator driving the receiver and transmitter
is shut down.This stops all SCI activity.Both the receiver and the transmitter are unable to operate.
If the STOP instruction is executed during a transmitter transfer, that transfer is halted.When STOP
mode is exited as a result of an external interrupt, that particular transmission resumes.
If the receiver is receiving data when the STOP instruction is executed, received data sampling is
stopped (baud generator stops) and the rest of the data is lost.
Warning: For the above reasons, all SCI transactions should be in the idle state when the STOP
instruction is executed.
6
6.14
SCI during WAIT mode
The SCI system is not affected by WAIT mode and continues normal operation. Any valid SCI
interrupt will wake-up the system. If required, the SCI system can be disabled prior to entering
WAIT mode by writing a zero to the transmitter and receiver enable bits in the serial communication
control register 2 at $000F.This action will result in a reduction of power consumption during WAIT
mode.
TPG
MC68HC05B6
Rev. 4
SERIAL COMMUNICATIONS INTERFACE
MOTOROLA
6-21
6
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
6-22
SERIAL COMMUNICATIONS INTERFACE
MC68HC05B6
Rev. 4
7
PULSE LENGTH D/A CONVERTERS
The pulse length D/A converter (PLM) system works in conjunction with the timer to execute two
8-bit D/A conversions, with a choice of two repetition rates. (See Figure 7-1.)
Data bus
8
8
PLMA
register
PLMB
register
7
‘A’ register
buffer
‘B’ register
buffer
‘A’
comparator
‘B’
comparator
PLMA
D/A
pin
R
Latch
R
Latch
PLMB
D/A
pin
S
S
Zero detector
Zero detector
8
8
‘A’
multiplexer
SFA
bit
‘B’
multiplexer
SFB
bit
16
16
Timer bus
From timer
Figure 7-1 PLM system block diagram
TPG
MC68HC05B6
Rev. 4
PULSE LENGTH D/A CONVERTERS
MOTOROLA
7-1
The D/A converter has two data registers associated with it, PLMA and PLMB.
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
0000 0000
This is a dual 8-bit resolution D/A converter associated with two output pins (PLMA and PLMB).
The outputs are pulse length modulated signals whose duty cycle ratio may be modified. These
signals can be used directly as PLMs, or the filtered average may be used as general purpose
analog outputs.
The longest repetition period is 4096 times the programmable timer clock period (CPU clock
multiplied by four), and the shortest repetition period is 256 times the programmable timer clock
period (the repetition rate frequencies for a 4 MHz crystal are 122 Hz and 1953 Hz respectively).
Registers PLMA ($0A) and PLMB ($0B) are associated with the pulse length values of the two
counters. A value of $00 loaded into these registers results in a continuously low output on the
corresponding D/A output pin. A value of $80 results in a 50% duty cycle output, and so on, to the
maximum value $FF corresponding to an output which is at ‘1’ for 255/256 of the cycle. When the
MCU makes a write to register PLMA or PLMB the new value will only be picked up by the D/A
converters at the end of a complete cycle of conversion.This results in a monotonic change of the
DC component at the output without overshoots or vicious starts (a vicious start is an output which
gives totally erroneous PLM during the period immediately following an update of the PLM D/A
registers). This feature is achieved by double buffering of the PLM D/A registers. Examples of
PWM output waveforms are shown in Figure 7-2.
7
256 T
$00
255 T
$01
$80
$FF
T
128 T
128 T
255 T
T = 4 CPU clocks in fast mode and 64 CPU clocks in slow mode
T
Figure 7-2 PLM output waveform examples
TPG
MOTOROLA
7-2
PULSE LENGTH D/A CONVERTERS
MC68HC05B6
Rev. 4
Note:
Since the PLM system uses the timer counter, PLM results will be affected while resetting
the timer counter. Both D/A registers are reset to $00 during power-on or external reset.
WAIT mode does not affect the output waveform of the D/A converters.
7.1
Miscellaneous register
State
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
on reset
SM WDOG ?001 000?
Miscellaneous
$000C POR INTP INTN INTE SFA SFB
SFA — Slow or fast mode selection for PLMA
This bit allows the user to select the slow or fast mode of the PLMA pulse length modulation output.
1 (set) Slow mode PLMA (4096 x timer clock period).
–
0 (clear) – Fast mode PLMA (256 x timer clock period).
SFB — Slow or fast mode selection for PLMB
7
This bit allows the user to select the slow or fast mode of the PLMB pulse length modulation output.
1 (set)
–
Slow mode PLMB (4096 x timer clock period).
0 (clear) – Fast mode PLMB (256 x timer clock period).
The highest speed of the PLM system corresponds to the frequency of the TOF bit being set,
multiplied by 256. The lowest speed of the PLM system corresponds to the frequency of the TOF
bit being set, multiplied by 16. Because the SFA bit and SFB bit are not double buffered, it is
mandatory to set them to the desired values before writing to the PLM registers; not doing so could
temporarily give incorrect values at the PLM outputs.
SM — Slow mode
1 (set)
–
The system runs at a bus speed 16 times lower than normal
(f /32). SLOW mode affects all sections of the device, including
OSC
SCI, A/D and timer.
0 (clear) – The system runs at normal bus speed (f
/2).
OSC
The SM bit is cleared by external or power-on reset. The SM bit is automatically cleared when
entering STOP mode.
Note:
The bits that are shown shaded in the above representation are explained individually
in the relevant sections of this manual. The complete register plus an explanation of
each bit can be found in Section 3.8
TPG
MC68HC05B6
Rev. 4
PULSE LENGTH D/A CONVERTERS
MOTOROLA
7-3
7.2
PLM clock selection
The slow/fast mode of the PLM D/A converters is selected by bits 1, 2, and 3 of the miscellaneous
register at address $000C (SFA bit for PLMA and SFB bit for PLMB). The slow/fast mode has no
effect on the D/A converters’ 8-bit resolution (see Figure 7-3).
Bus
Timer
clock
SM bit = 0
SM bit = 1
SF bit = 1
SF bit = 0
frequency (f
)
PLM
clock
OP
f
OSC
÷2
÷4
x4096
x256
÷32
Figure 7-3 PLM clock selection
7.3
PLM during STOP mode
7
On entering STOP mode, the PLM outputs remain at their particular level. When STOP mode is
exited by an interrupt, the PLM systems resume regular operation. If STOP mode is exited by
power-on or external reset the registers values are forced to $00.
7.4
PLM during WAIT mode
The PLM system is not affected by WAIT mode and continues normal operation.
TPG
MOTOROLA
7-4
PULSE LENGTH D/A CONVERTERS
MC68HC05B6
Rev. 4
8
ANALOG TO DIGITAL CONVERTER
The analog to digital converter system consists of a single 8-bit successive approximation
converter and a sixteen channel multiplexer. Eight of the channels are connected to the
PD0/AN0 – PD7/AN7 pins of the MC68HC05B6 and the other eight channels are dedicated to
internal reference points for test functions.The channel input pins do not have any internal output
driver circuitry connected to them because such circuitry would load the analog input signals due
to output buffer leakage current.There is one 8-bit result data register (address $08) and one 8-bit
status/control register (address $09).
The A/D converter is ratiometric and two dedicated pins, VRH and VRL, are used to supply the
reference voltage levels for all analog inputs. These pins are used in preference to the system
power supply lines because any voltage drops in the bonding wires of the heavily loaded supply
pins could degrade the accuracy of the A/D conversion. An input voltage equal to or greater than
V
converts to $FF (full scale) with no overflow indication and an input voltage equal to V
RL
RH
8
converts to $00.
The A/D converter can operate from either the bus clock or an internal RC type oscillator. The
internal RC type oscillator is activated by the ADRC bit in the A/D status/control register (ADSTAT)
and can be used to give a sufficiently high clock rate to the A/D converter when the bus speed is too
low to provide accurate results. When the A/D converter is not being used it can be disconnected,
by clearing the ADON bit in the ADSTAT register, in order to save power (see Section 8.2.3).
For further information on A/D converter operation please refer to the M68HC11 Reference
Manual — M68HC11RM/AD.
8.1
A/D converter operation
The A/D converter consists of an analog multiplexer, an 8-bit digital to analog converter capacitor
array, a comparator and a successive approximation register (SAR) (see Figure 8-1).
There are eleven options that can be selected by the multiplexer; AN0–AN7, VRH, (VRH+VRL)/2
or VRL. Selection is done via the CHx bits in the ADSTAT register (see Section 8.2.3). AN0–AN7
are the only input points for A/D conversion operations; the others are reference points that can be
used for test purposes.
TPG
MC68HC05B6
Rev. 4
ANALOG TO DIGITAL CONVERTER
MOTOROLA
8-1
The A/D reference input (AN0–AN7) is applied to a precision internal D/A converter. Control logic
drives this D/A converter and the analog output is successively compared with the analog input
sampled at the beginning of the conversion. The conversion is monotonic with no missing codes.
VRH
VRL
AN0
8-bit capacitive DAC
with sample and hold
AN1
AN2
Successive approximation
register (SAR) and control
AN3
AN4
Result
AN5
A/D status/control register (ADSTAT)$09
AN6
CH0 CH1 CH2 CH3
0
ADON ADRC
COCO
AN7
VRH
(VRH+VRL)/2
VRL
8
A/D result register (ADDATA) $08
Figure 8-1 A/D converter block diagram
The result of each successive comparison is stored in the SAR and, when the conversion is
complete, the contents of the SAR are transferred to the read-only result data register ($08), and
the conversion complete flag, COCO, is set in the A/D status/control register ($09).
Warning: Any write to the A/D status/control register will abort the current conversion, reset the
conversion complete flag and start a new conversion on the selected channel.
At power-on or external reset, both the ADRC and ADON bits are cleared;thus the A/D is disabled.
TPG
MOTOROLA
8-2
ANALOG TO DIGITAL CONVERTER
MC68HC05B6
Rev. 4
8.2
A/D registers
8.2.1
Port D data register (PORTD)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port D data (PORTD)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
Port D is an input-only port which routes the eight analog inputs to the A/D converter. When the
A/D converter is disabled, the pins are configured as standard input-only port pins, which can be
read via the port D data register.
Note:
When the A/D function is enabled, pins PD0–PD7 will act as analog inputs. Using a pin
or pins as A/D inputs does not affect the ability to read port D as static inputs; however,
reading port D during an A/D conversion sequence may inject noise on the analog
inputs and result in reduced accuracy of the A/D result.
Performing a digital read of port D with levels other than V or V on the pins will
DD
SS
result in greater power dissipation during the read cycle, and may give unpredictable
results on the corresponding port D pins.
8
8.2.2
A/D result data register (ADDATA)
State
on reset
Address bit 7
$0008
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A/D data (ADDATA)
0000 0000
ADDATA is a read-only register which is used to store the results of A/D conversions. Each result
is loaded into the register from the SAR and the conversion complete flag, COCO, in the ADSTAT
register is set.
TPG
MC68HC05B6
Rev. 4
ANALOG TO DIGITAL CONVERTER
MOTOROLA
8-3
8.2.3
A/D status/control register (ADSTAT)
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
COCO — Conversion complete flag
1 (set)
–
COCO is set each time a conversion is complete, allowing the new
result to be read from the A/D result data register ($08). The
converter then starts a new conversion.
0 (clear) – COCO is cleared by reading the result data register or writing to the
status/control register.
Reset clears the COCO flag.
ADRC — A/D RC oscillator control
The ADRC bit allows the user to control the A/D RC oscillator, which is used to provide a
sufficiently high clock rate to the A/D to ensure accuracy when the chip is running at low speeds.
1 (set)
–
When the ADRC bit is set, the A/D RC oscillator is turned on and, if
ADON is set, the A/D runs from the RC oscillator clock. See Table 8-1.
0 (clear) – When the ADRC bit is cleared, the A/D RC oscillator is turned-off
and, if ADON is set, the A/D runs from the CPU clock.
8
When the A/D RC oscillator is turned on, it takes a time tADRC to stabilize (see Table 11-6 and
Table 11-7). During this time A/D conversion results may be inaccurate.
Note:
If the MCU bus clock falls below 1MHz, the A/D RC oscillator should be switched on.
Power-on or external reset clears the ADRC bit.
Table 8-1 A/D clock selection
RC
A/D
ADRC
ADON
Comments
A/D switched off.
oscillator converter
0
0
1
1
0
1
0
1
OFF
OFF
ON
OFF
ON
A/D using CPU clock.
OFF
ON
Allows the RC oscillator to stabilize.
A/D using RC oscillator clock.
ON
TPG
MOTOROLA
8-4
ANALOG TO DIGITAL CONVERTER
MC68HC05B6
Rev. 4
ADON — A/D converter on
The ADON bit allows the user to enable/disable the A/D converter.
1 (set)
–
A/D converter is switched on.
0 (clear) – A/D converter is switched off.
When the A/D converter is switched on, it takes a time tADON for the current sources to stabilize
(see Table 11-6 and Table 11-7). Using the A/D converter before this time has elapsed may result
in the incorrect operation of the A/D, even after t
to be cleared and set again.
has elapsed. In this case ADON would have
ADON
Power-on or external reset will clear the ADON bit, thus disabling the A/D converter.
CH3–CH0 — A/D channels 3, 2, 1 and 0
The CH3–CH0 bits allow the user to determine which channel of the A/D converter multiplexer is
selected. See Table 8-2 for channel selection.
Reset clears the CH0–CH3 bits.
Table 8-2 A/D channel assignment
CH3
0
CH2
0
CH1
0
CH0
0
Channel selected
AN0
8
0
0
0
1
AN1
0
0
1
0
AN2
0
0
1
1
AN3
0
1
0
0
AN4
0
1
0
1
AN5
0
1
1
0
AN6
0
1
1
1
AN7
1
0
0
0
VRH pin (high)
(VRH + VRL) / 2
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
VRL pin (low)
1
0
0
1
1
0
1
0
1
0
1
1
1
1
0
0
1
1
0
1
1
1
1
0
1
1
1
1
TPG
MC68HC05B6
Rev. 4
ANALOG TO DIGITAL CONVERTER
MOTOROLA
8-5
8.3
A/D converter during STOP mode
When the MCU enters STOP mode with the A/D converter turned on, the A/D clocks are stopped
and the A/D converter is disabled for the duration of STOP mode, including the 4064 cycles
start-up time. If the A/D RC oscillator is in operation it will also be disabled.
8.4
A/D converter during WAIT mode
The A/D converter is not affected by WAIT mode and continues normal operation.
In order to reduce power consumption the A/D converter can be disconnected, under software
control using the ADON bit and the ADRC bit in the A/D status/control register at $0009, before
entering WAIT mode.
8.5
Port D analog input
The external analog voltage value to be processed by the A/D converter is sampled on an internal
capacitor through a resistive path, provided by input-selection switches and a sampling aperture
time switch, as shown in Figure 8-2.Sampling time is limited to 12 bus clock cycles.After sampling,
the analog value is stored on the capacitor and held until the end of conversion. During this hold
time, the analog input is disconnected from the internal A/D system and the external voltage
source sees a high impedance input.
8
The equivalent analog input during sampling is an RC low-pass filter with a minimum resistance
of 50 kΩ and a capacitance of at least 10pF. It should be noted that these are typical values
measured at room temperature.
Input protection device
≥ 50kΩ
Analog
input
pin
+ 20V
- 0.7V
< 2pF
1 µA
junction
leakage
≥ 10pF
DAC
capacitance
V
RL
Note:
The analog switch is closed during the 12 cycle sample time only.
Figure 8-2 Electrical model of an A/D input pin
TPG
MOTOROLA
8-6
ANALOG TO DIGITAL CONVERTER
MC68HC05B6
Rev. 4
9
RESETS AND INTERRUPTS
9.1
Resets
The MC68HC05B6 can be reset in three ways: by the initial power-on reset function, by an active
low input to the RESET pin or by a computer operating properly (COP) watchdog reset. Any of
these resets will cause the program to go to its starting address, specified by the contents of
memory locations $1FFE and $1FFF, and cause the interrupt mask bit in the condition code
register to be set.
tVDDR
VDD threshold (1-2V typical)
VDD
tOXOV
OSC1
9
tPORL
tCYC
Internal
processor clock
tRL (or tDOGL
)
RESET
(Internal power-on reset)
(External hardware reset)
Internal
New
PC
address bus
New
PC
1FFE 1FFE 1FFE 1FFE 1FFF
Reset sequence
1FFE 1FFE
1FFE
1FFE
1FFF
Reset sequence
Internal
data bus
New New Op
PCH PCL code
New New Op
PCH PCL code
Program
execution
begins
Program
execution
begins
Figure 9-1 Reset timing diagram
TPG
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
MOTOROLA
9-1
9.1.1
Power-on reset
A power-on reset occurs when a positive transition is detected on VDD. The power-on reset
function is strictly for power turn-on conditions and should not be used to detect drops in the power
supply voltage. The power-on circuitry provides a stabilization delay (tPORL) from when the
oscillator becomes active. If the external RESET pin is low at the end of this delay then the
processor remains in the reset state until RESET goes high.The user must ensure that the voltage
on VDD has risen to a point where the MCU can operate properly by the time tPORL has elapsed.
If there is doubt, the external RESET pin should remain low until the voltage on VDD has reached
the specified minimum operating voltage.This may be accomplished by connecting an external RC
circuit to this pin to generate a power-on reset (POR). In this case, the time constant must be great
enough to allow the oscillator circuit to stabilize.
During power-on reset, the RESET pin is driven low during a t
delay start-up sequence. t
is
PORL
PORL
defined by a user specified mask option to be either 16 cycles or 4064 cycles (see Section 1.2).
A software distinction between a power-on reset and an external reset can be made using the POR
bit in the miscellaneous register (see Section 9.1.2).
9.1.2
Miscellaneous register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG ?001 000?
(1) The POR bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent on the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
9
POR — Power-on reset bit
This bit is set each time the device is powered on. Therefore, the state of the POR bit allows the
user to make a software distinction between a power-on and an external reset. This bit cannot be
set by software and is cleared by writing it to zero.
1 (set)
–
A power-on reset has occurred.
0 (clear) – No power-on reset has occurred.
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
TPG
MOTOROLA
9-2
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
9.1.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 1.5 machine cycles (tCYC). An internal Schmitt Trigger
is used to improve noise immunity on this pin. When the RESET pin goes high, the MCU will
resume operation on the following cycle. When a reset condition occurs internally, i.e. from POR
or the COP watchdog, the RESET pin provides an active-low open drain output signal which may
be used to reset external hardware. Current limitation to protect the pull-down device is provided
in case an RC type external reset circuit is used.
9.1.4
Computer operating properly (COP) watchdog reset
The watchdog counter system consists of a divide-by-8 counter, preceded by a fixed divide-by-4
and a fixed divide-by-256 prescaler, plus control logic as shown in Figure 9-2. The divide-by-8
counter can be reset by software.
Main CPU
clock
Power-on
S
Latch
R
f
/2
Reset
pin
OSC
÷ 256
(Bit 7 of free
running counter)
÷ 8 watchdog
counter
÷ 4
prescaler
f
/32
OSC
9
Schmitt
trigger
Input
protection
WDOG bit
Control logic
Figure 9-2 Watchdog system block diagram
Warning: The input to the watchdog system is derived from the carry output of bit 7 of the free
running timer counter. Therefore, a reset of the timer may affect the period of the
watchdog timeout.
The watchdog system can be automatically enabled, following power-on or external reset, via a
mask option (see Section 1.2), or it can be enabled by software by writing a ‘1’ to the WDOG bit in
the miscellaneous register at $000C (see Section 9.1.2). Once enabled, the watchdog system
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RESETS AND INTERRUPTS
MOTOROLA
9-3
cannot be disabled by software (writing a ‘zero’ to the WDOG bit has no effect at any time). In
addition, the WDOG bit acts as a reset mechanism for the watchdog counter. Writing a ‘1’ to this
bit clears the counter to its initial value and prevents a watchdog timeout.
WDOG — Watchdog enable/disable
The WDOG bit can be used to enable the watchdog timer previously disabled by a mask option.
Following a watchdog reset the state of the WDOG bit is as defined by the mask option specified.
1 (set)
–
Watchdog enabled and counter cleared.
0 (clear) – The watchdog cannot be disabled by software; writing a zero to this
bit has no effect.
The divide-by-8 watchdog counter will generate a main reset of the chip when it reaches its final
state; seven clocks are necessary to bring the watchdog counter from its clear state to its final
state. This reset appears after time t
since the last clear or since the enable of the watchdog
DOG
counter system.The watchdog counter, therefore, has to be cleared periodically, by software, with
a period less than t
.
DOG
The reset generated by the watchdog system is apparent at the RESET pin (see Figure 9-2). The
RESET pin level is re-entered in the control logic, and when it has been maintained at level ‘zero’
for a minimum of t
, the RESET pin is released.
DOGL
9.1.4.1
COP watchdog during STOP mode
The STOP instruction is inhibited when the watchdog system is enabled. If a STOP instruction is
executed while the watchdog system is enabled, then a watchdog reset will occur as if there were
a watchdog timeout. In the case of a watchdog reset due to a STOP instruction, the oscillator will
9
not be affected, thus there will be no t
cycles start-up delay. On start-up, the watchdog will be
PORL
configured according to the user specified mask option.
9.1.4.2
COP watchdog during WAIT mode
The state of the watchdog during WAIT mode is selected via a mask option (see Section 1.2) to
be one of the options below:
Watchdog enabled — the watchdog counter will continue to operate duringWAIT mode and a reset
will occur after time t
.
DOG
Watchdog disabled — on entering WAIT mode, the watchdog counter system is reset and
disabled. On exiting WAIT mode the counter resumes normal operation.
TPG
MOTOROLA
9-4
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
9.1.5
Functions affected by reset
When processing stops within the MCU for any reason, i.e. power-on reset, external reset or the
execution of a STOP or WAIT instruction, various internal functions of the MCU are affected.
Table 9-1 shows the resulting action of any type of system reset, but not necessarily in the order
in which they occur.
Table 9-1 Effect of RESET, POR, STOP and WAIT
Function/effect
Timer prescaler set to zero
RESET POR
WAIT STOP
x
x
–
–
Timer counter set to $FFFC
All timer enable bits cleared (disable)
Data direction registers cleared (inputs)
Stack pointer set to $00FF
x
x
–
–
x
x
–
–
x
x
–
–
x
x
–
–
Force internal address bus to restart
Vector $1FFE, $1FFF
x
x
–
–
x
x
–
–
Interrupt mask bit (I-bit CCR) set to 1
Interrupt mask bit (I-bit CCR) cleared
Set interrupt enable bit (INTE)
Set POR bit in miscellaneous register
Reset STOP latch
x
–
x
–
–
x
–
x
x
x
–
–
–
x
–
–
x
x
–
–
Reset IRQ latch
x
x
–
–
Reset WAIT latch
x
x
–
–
SCI disabled
x
x
x
x
–
–
–
–
9
SCI status bits cleared (except TDRE and TC)
SCI interrupt enable bits cleared
SCI status bits TDRE and TC set
Oscillator disabled for 4064 cycles
Timer clock cleared
x
x
–
–
x
x
–
–
–
x
–
x
–
–
x
x
x
x
–
–
–
x
x
x
SCI clock cleared
A/D disabled
SM bit in the miscellaneous register cleared
Watchdog counter reset
x
x
–
x
x
x
x
–
–
x
WDOG bit in the miscellaneous register reset
EEPROM control bits (see Section 3.5.1)
x
x
x
x
x
x
x = Described action takes place
– = Described action does not take place
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Rev. 4
RESETS AND INTERRUPTS
MOTOROLA
9-5
9.2
Interrupts
The MCU can be interrupted by four different sources: three maskable hardware interrupts and
one non maskable software interrupt:
•
•
•
•
External signal on the IRQ pin
Serial communications interface (SCI)
Programmable timer
Software interrupt instruction (SWI)
Interrupts cause the processor to save the register contents on the stack and to set the interrupt
mask (I-bit) to prevent additional interrupts.The RTI instruction (ReTurn from Interrupt) causes the
register contents to be recovered from the stack and normal processing to resume. While
executing the RTI instruction, the value of the I-bit is replaced by the corresponding I-bit stored on
the stack.
Unlike reset, hardware interrupts do not cause the current instruction execution to be halted, but
are considered pending until the current instruction is complete.The current instruction is the one
already fetched and being operated on. When the current instruction is complete, the processor
checks all pending hardware interrupts. If interrupts are not masked (I-bit clear) and the
corresponding interrupt enable bit is set, the processor proceeds with interrupt processing;
otherwise, the next instruction is fetched and executed.
Note:
Power-on and external reset clear all interrupt enable bits, but set the INTE bit in the
miscellaneous register, thus preventing interrupts during the reset sequence.
9
9.2.1
Interrupt priorities
Each potential interrupt source is assigned a priority level, which means that if more than one
interrupt is pending at the same time, the processor will service the one with the highest priority
first. For example, if both an external interrupt and a timer interrupt are pending after an instruction
execution, the external interrupt is serviced first.
Table 9-2 shows the relative priority of all the possible interrupt sources. Figure 9-3 shows
the interrupt processing flow.
9.2.2
Nonmaskable software interrupt (SWI)
The software interrupt (SWI) is an executable instruction and a nonmaskable interrupt: it is
executed regardless of the state of the I-bit in the CCR. If the I-bit is zero (interrupts enabled), SWI
is executed after interrupts that were pending when the SWI was fetched, but before interrupts
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MOTOROLA
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RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
Table 9-2 Interrupt priorities
Source
Register
—
Flags
—
Vector address
$1FFE, $1FFF
$1FFC, $1FFD
$1FFA, $1FFB
$1FF8, $1FF9
$1FF6, $1FF7
$1FF4, $1FF5
Priority
Reset
highest
Software interrupt (SWI)
External interrupt (IRQ)
Timer input captures
Timer output compares
Timer overflow
—
—
—
—
TSR
TSR
TSR
ICF1, ICF2
OCF1, OCF2
TOF
Serial communications
interface (SCI)
TDRE, TC, OR,
RDRF, IDLE
SCSR
$1FF2, $1FF3
lowest
generated after the SWI was fetched.The SWI interrupt service routine address is specified by the
contents of memory locations $1FFC and $1FFD.
9.2.3
Maskable hardware interrupts
If the interrupt mask bit in the CCR is set, all maskable interrupts (internal and external) are
masked. Clearing the I-bit allows interrupt processing to occur.
Note:
The internal interrupt latch is cleared in the first part of the interrupt service routine;
therefore, one external interrupt pulse could be latched and serviced as soon as the I-bit
is cleared.
9
9.2.3.1
External interrupt (IRQ)
If the interrupt mask in the condition code register has been cleared and the interrupt enable bit
(INTE) is set and the signal on the external interrupt pin (IRQ) satisfies the condition selected by
the option control bits (INTP and INTN), then the external interrupt is recognized. INTE, INTP and
INTN are all bits contained in the miscellaneous register at $000C. When the interrupt is
recognized, the current state of the CPU is pushed onto the stack and the I-bit is set. This masks
further interrupts until the present one is serviced. The external interrupt service routine address
is specified by the content of memory locations $1FFA and $1FFB.
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MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
MOTOROLA
9-7
Reset
Is I-bit set?
IRQ
Clear IRQ request
latch
external interrupt?
Stack
PC, X, A, CC
Timer
internal interrupt?
Set I-bit
SCI
internal interrupt?
9
Load PC from:
IRQ: $1FFA-$1FFB
Timer IC: $1FF8-$1FF9
Timer OC: $1FF6-$1FF7
Timer OVF:$1FF4-$1FF5
Fetch next
instruction
SCI:
$1FF2-$1FF3
Completeinterruptroutine
and execute RTI
Execute instruction
Figure 9-3 Interrupt flow chart
TPG
MOTOROLA
9-8
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
9.2.3.2
Miscellaneous register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Miscellaneous
$000C POR INTP INTN INTE
SFA SFB
SM WDOG ?001 000?
Note:
The bits shown shaded in the above representation are explained individually in the
relevant sections of this manual. The complete register plus an explanation of each bit
can be found in Section 3.8.
INTP, INTN — External interrupt sensitivity options
These two bits allow the user to select which edge the IRQ pin is sensitive to as shown in Table 9-3.
Both bits can be written to only while the I-bit is set, and are cleared by power-on or external reset.
Therefore the device is initialised with negative edge and low level sensitivity.
Table 9-3 IRQ sensitivity
INTP
INTN
IRQ sensitivity
Negative edge and low level sensitive
Negative edge only
0
0
1
1
0
1
0
1
Positive edge only
Positive and negative edge sensitive
INTE — External interrupt enable
1 (set) External interrupt function (IRQ) enabled.
9
–
0 (clear) – External interrupt function (IRQ) disabled.
The INTE bit can be written to only while the I-bit is set, and is set by power-on or external reset,
thus enabling the external interrupt function.
Table 9-3 describes the various triggering options available for the IRQ pin, however it is important
to re-emphasize here that in order to avoid any conflict and spurious interrupt, it is only possible to
change the external interrupt options while the I-bit is set. Any attempt to change the external
interrupt option while the I-bit is clear will be unsuccessful. If an external interrupt is pending, it will
automatically be cleared when selecting a different interrupt option.
Note:
If the external interrupt function is disabled by the INTE bit and an external interrupt is
sensed by the edge detector circuitry, then the interrupt request is latched and the
interrupt stays pending until the INTE bit is set. The internal latch of the external
interrupt is cleared in the first part of the service routine (except for the low level
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MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
MOTOROLA
9-9
interrupt which is not latched); therefore, only one external interrupt pulse can be
latched during t and serviced as soon as the I-bit is cleared.
ILIL
9.2.3.3
Timer interrupts
There are five different timer interrupt flags (ICF1, ICF2, OCF1, OCF2 and TOF) that will cause a
timer interrupt whenever they are set and enabled. These five interrupt flags are found in the five
most significant bits of the timer status register (TSR) at location $0013. ICF1 and ICF2 will vector
to the service routine defined by $1FF8-$1FF9, OCF1 and OCF2 will vector to the service routine
defined by $1FF6–$1FF7 and TOF will vector to the service routine defined by $1FF4–$1FF5 as
shown in Figure 5.1.
There are three corresponding enable bits; ICIE for ICF1 and ICF2, OCIE for OCF1 and OCF2,
and TOIE for TOF. These enable bits are located in the timer control register (TCR) at address
$0012. See Section 5.2.1 and Section 5.2.2 for further information.
9.2.3.4
Serial communications interface (SCI) interrupts
There are five different interrupt flags (TDRE, TC, OR, RDRF and IDLE) that cause SCI interrupts
whenever they are set and enabled.These five interrupt flags are found in the five most significant
bits of the SCI status register (SCSR) at location $0010.
There are four corresponding enable bits: TIE for TDRE, TCIE for TC, RIE for OR and RDRF, and
ILIE for IDLE. These enable bits are located in the serial communications control register 2
(SCCR2) at address $000F. See Section 6.11.3 and Section 6.11.4.
The SCI interrupt causes the program counter to vector to the address pointed to by memory
locations $1FF2 and $1FF3 which contain the starting address of the interrupt service routine.
Software in the SCI interrupt service routine must determine the priority and cause of the interrupt
by examining the interrupt flags and the status bits located in the serial communications status
register SCSR (address $0010).
9
The general sequence for clearing an interrupt is a software sequence of accessing the serial
communications status register while the flag is set followed by a read or write of an associated
register. Refer to Section 6 for a description of the SCI system and its interrupts.
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MOTOROLA
9-10
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
9.2.4
Hardware controlled interrupt sequence
The following three functions:reset, STOP and WAIT, are not in the strictest sense interrupts. However,
they are acted upon in a similar manner. Flowcharts for STOP and WAIT are shown in Figure 2.4.
RESET: A reset condition causes the program to vector to its starting address, which is contained
in memory locations $1FFE (MSB) and $1FFF (LSB). The I-bit in the condition code
register is also set, to disable interrupts.
STOP: The STOP instruction causes the oscillator to be turned off and the processor to ‘sleep’
until an external interrupt (IRQ) or occurs or the device is reset.
WAIT:
The WAIT instruction causes all processor clocks to stop, but leaves the timer clocks
running. This ‘rest’ state of the processor can be cleared by reset, an external interrupt
(IRQ), a timer interrupt or an SCI interrupt. There are no special WAIT vectors for these
individual interrupts.
9
TPG
MC68HC05B6
Rev. 4
RESETS AND INTERRUPTS
MOTOROLA
9-11
THIS PAGE LEFT BLANK INTENTIONALLY
9
TPG
MOTOROLA
9-12
RESETS AND INTERRUPTS
MC68HC05B6
Rev. 4
10
CPU CORE AND INSTRUCTION SET
This section provides a description of the CPU core registers, the instruction set and the
addressing modes of the MC68HC05B6.
10.1
Registers
The MCU contains five registers, as shown in the programming model of Figure 10-1.The interrupt
stacking order is shown in Figure 10-2.
7
7
7
7
0
0
0
0
0
Accumulator
Index register
15
15
Program counter
Stack pointer
0 0 0 0 0 0 0 0 1 1
7
1 1 1 H I N Z C
Condition code register
Carry / borrow
Zero
Negative
Interrupt mask
Half carry
10
Figure 10-1 Programming model
Stack
7
0
Condition code register
Increasing
memory
address
Decreasing
memory
address
Accumulator
Index register
Program counter high
Program counter low
Unstack
Figure 10-2 Stacking order
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-1
10.1.1
Accumulator (A)
The accumulator is a general purpose 8-bit register used to hold operands and results of arithmetic
calculations or data manipulations.
10.1.2
Index register (X)
The index register is an 8-bit register, which can contain the indexed addressing value used to
create an effective address. The index register may also be used as a temporary storage area.
10.1.3
Program counter (PC)
The program counter is a 16-bit register, which contains the address of the next byte to be fetched.
10.1.4
Stack pointer (SP)
The stack pointer is a 16-bit register, which contains the address of the next free location on the
stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to
location $00FF. The stack pointer is then decremented as data is pushed onto the stack and
incremented as data is pulled from the stack.
When accessing memory, the ten most significant bits are permanently set to 0000000011.These
ten bits are appended to the six least significant register bits to produce an address within the
range of $00C0 to $00FF. Subroutines and interrupts may use up to 64 (decimal) locations. If 64
locations are exceeded, the stack pointer wraps around and overwrites the previously stored
information. A subroutine call occupies two locations on the stack; an interrupt uses five locations.
10
10.1.5
Condition code register (CCR)
The CCR is a 5-bit register in which four bits are used to indicate the results of the instruction just
executed, and the fifth bit indicates whether interrupts are masked. These bits can be individually
tested by a program, and specific actions can be taken as a result of their state. Each bit is
explained in the following paragraphs.
TPG
MOTOROLA
10-2
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
Half carry (H)
This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4.
Interrupt (I)
When this bit is set all maskable interrupts are masked. If an interrupt occurs while this bit is set,
the interrupt is latched and remains pending until the interrupt bit is cleared.
Negative (N)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was
negative.
Zero (Z)
When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero.
Carry/borrow (C)
When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred
during the last arithmetic operation.This bit is also affected during bit test and branch instructions
and during shifts and rotates.
10.2
Instruction set
The MCU has a set of 62 basic instructions. They can be grouped into five different types as
follows:
–
–
–
–
–
Register/memory
Read/modify/write
Branch
10
Bit manipulation
Control
The following paragraphs briefly explain each type. All the instructions within a given type are
presented in individual tables.
This MCU uses all the instructions available in the M146805 CMOS family plus one more: the
unsigned multiply (MUL) instruction. This instruction allows unsigned multiplication of the contents
of the accumulator (A) and the index register (X). The high-order product is then stored in the index
register and the low-order product is stored in the accumulator. A detailed definition of the MUL
instruction is shown in Table 10-1.
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-3
10.2.1
Register/memory Instructions
Most of these instructions use two operands. The first operand is either the accumulator or the
index register.The second operand is obtained from memory using one of the addressing modes.
The jump unconditional (JMP) and jump to subroutine (JSR) instructions have no register operand.
Refer to Table 10-2 for a complete list of register/memory instructions.
10.2.2
Branch instructions
These instructions cause the program to branch if a particular condition is met; otherwise, no
operation is performed. Branch instructions are two-byte instructions. Refer to Table 10-3.
10.2.3
Bit manipulation instructions
The MCU can set or clear any writable bit that resides in the first 256 bytes of the memory space
(page 0). All port data and data direction registers, timer and serial interface registers,
control/status registers and a portion of the on-chip RAM reside in page 0. An additional feature
allows the software to test and branch on the state of any bit within these locations.The bit set, bit
clear, bit test and branch functions are all implemented with single instructions. For the test and
branch instructions, the value of the bit tested is also placed in the carry bit of the condition code
register. Refer to Table 10-4.
10.2.4
Read/modify/write instructions
These instructions read a memory location or a register, modify or test its contents, and write the
modified value back to memory or to the register.The test for negative or zero (TST) instruction is
an exception to this sequence of reading, modifying and writing, since it does not modify the value.
Refer to Table 10-5 for a complete list of read/modify/write instructions.
10
10.2.5
Control instructions
These instructions are register reference instructions and are used to control processor operation
during program execution. Refer to Table 10-6 for a complete list of control instructions.
10.2.6
Tables
Tables for all the instruction types listed above follow. In addition there is a complete alphabetical
listing of all the instructions (see Table 10-7 and Table 10-8), and an opcode map for the instruction
set of the M68HC05 MCU family (see Table 10-9).
TPG
MOTOROLA
10-4
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
Table 10-1 MUL instruction
Operation
X:A ← X*A
Multiplies the eight bits in the index register by the eight
Description bits in the accumulator and places the 16-bit result in the
concatenated accumulator and index register.
H : Cleared
I : Not affected
N : Not affected
Z : Not affected
Condition
codes
C : Cleared
Source
Form
MUL
Cycles
11
Addressing mode
Inherent
Bytes Opcode
$42
1
Table 10-2 Register/memory instructions
Addressing modes
Indexed
(no
offset)
Indexed
(8-bit
offset)
Indexed
(16-bit
offset)
Immediate
Direct
Extended
Function
Load A from memory
Load X from memory
Store A in memory
Store X in memory
Add memory to A
LDA A6
LDX AE
STA
2
2
2
2
B6
2
2
2
2
2
2
2
3
3
C6
CE
C7
CF
CB
3
3
4
F6
1
1
3
E6
2
2
4
D6
3
3
5
5
BE
4
FE
3
EE
4
DE
B7
BF
BB
4
3
5
F7
FF
FB
1
4
E7
EF
EB
2
5
D7
DF
DB
3
6
STX
4
3
5
1
4
2
5
3
6
ADD AB
ADC A9
SUB A0
2
2
2
2
2
2
3
3
4
1
3
2
4
3
5
Add memory and carry to A
Subtract memory
B9
B0
3
3
C9
C0
3
3
4
4
F9
F0
1
1
3
3
E9
E0
2
4
D9
D0
3
5
2
4
3
5
10
Subtract memory from A
with borrow
SBC A2
2
2
B2
2
3
C2
3
4
F2
1
3
E2
2
4
D2
3
5
AND memory with A
AND A4
ORA AA
EOR A8
2
2
2
2
2
2
B4
BA
B8
2
2
2
3
3
3
C4
CA
C8
3
3
3
4
4
4
F4
FA
F8
1
1
1
3
3
3
E4
EA
E8
2
2
2
4
4
4
D4
DA
D8
3
3
3
5
5
5
OR memory with A
Exclusive OR memory with A
Arithmetic compare A
with memory
CMP A1
CPX A3
BIT A5
2
2
2
2
2
2
B1
B3
B5
2
2
2
3
3
3
C1
C3
C5
3
3
3
4
4
4
F1
F3
F5
1
1
1
3
3
3
E1
E3
E5
2
2
2
4
4
4
D1
D3
D5
3
3
3
5
5
5
Arithmetic compare X
with memory
Bit test memory with A
(logical compare)
Jump unconditional
Jump to subroutine
JMP
JSR
BC
BD
2
2
2
5
CC
CD
3
3
3
6
FC
FD
1
1
2
5
EC
ED
2
2
3
6
DC
DD
3
3
4
7
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MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-5
Table 10-3 Branch instructions
Relative addressing mode
Mnemonic Opcode # Bytes # Cycles
Function
Branch always
Branch never
Branch if higher
BRA
BRN
BHI
20
21
22
23
24
24
25
25
26
27
28
29
2A
2B
2C
2D
2E
2F
AD
2
2
3
3
2
3
Branch if lower or same
Branch if carry clear
BLS
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
3
3
3
3
3
3
3
3
3
3
BCC
(BHS)
BCS
(BLO)
BNE
BEQ
BHCC
BHCS
BPL
BMI
(Branch if higher or same)
Branch if carry set
(Branch if lower)
Branch if not equal
Branch if equal
Branch if half carry clear
Branch if half carry set
Branch if plus
Branch if minus
Branch if interrupt mask bit is clear
Branch if interrupt mask bit is set
Branch if interrupt line is low
Branch if interrupt line is high
Branch to subroutine
BMC
BMS
BIL
2
3
BIH
2
3
BSR
2
6
Table 10-4 Bit manipulation instructions
Addressing Modes
Bit set/clear Bit test and branch
Opcode # Bytes # Cycles Opcode # Bytes # Cycles
10
Function
Branch if bit n is set
Branch if bit n is clear
Set bit n
Mnemonic
BRSET n (n=0–7)
BRCLR n (n=0–7)
BSET n (n=0–7)
BCLR n (n=0–7)
2•n
3
3
5
5
01+2•n
10+2•n
11+2•n
2
2
5
5
Clear bit n
TPG
MOTOROLA
10-6
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
Table 10-5 Read/modify/write instructions
Addressing modes
Indexed
(no
offset)
Indexed
(8-bit
offset)
Inherent
(A)
Inherent
(X)
Direct
Function
Increment
INC 4C
DEC 4A
CLR 4F
COM 43
NEG 40
ROL 49
ROR 46
LSL 48
LSR 44
ASR 47
TST 4D
MUL 42
1
3
5C
5A
5F
53
50
59
56
58
54
57
5D
1
3
3C
3A
3F
33
30
39
36
38
34
37
3D
2
2
2
2
2
2
2
2
2
2
2
5
5
5
5
5
7C
7A
7F
73
70
79
76
78
74
77
7D
1
1
1
1
1
5
6C
6A
6F
63
60
69
66
68
64
67
6D
2
2
2
2
2
6
Decrement
1
3
1
3
5
6
Clear
1
3
1
3
5
6
Complement
1
3
3
1
3
3
5
5
6
6
Negate (two’s complement)
Rotate left through carry
Rotate right through carry
Logical shift left
1
1
1
3
1
3
5
1
5
2
6
1
3
1
3
5
1
5
2
6
1
3
1
3
5
1
5
2
6
Logical shift right
Arithmetic shift right
Test for negative or zero
Multiply
1
1
3
3
1
1
3
3
5
5
1
1
5
5
2
2
6
6
1
3
1
3
4
1
4
2
5
1
11
Table 10-6 Control instructions
Inherent addressing mode
Function
Transfer A to X
Mnemonic Opcode # Bytes # Cycles
TAX
TXA
SEC
CLC
SEI
97
9F
99
98
9B
9A
83
81
80
9C
9D
8E
8F
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
10
6
9
2
2
2
2
Transfer X to A
Set carry bit
10
Clear carry bit
Set interrupt mask bit
Clear interrupt mask bit
Software interrupt
Return from subroutine
Return from interrupt
Reset stack pointer
No-operation
CLI
SWI
RTS
RTI
RSP
NOP
STOP
WAIT
Stop
Wait
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-7
Table 10-7 Instruction set (1 of 2)
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB
H
I
N
Z
C
ADC
ADD
AND
ASL
ASR
BCC
BCLR
BCS
BEQ
BHCC
BHCS
BHI
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
•
•
◊
◊
◊
◊
◊
•
•
•
•
•
•
•
•
•
•
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
0
◊
◊
◊
◊
◊
◊
•
•
•
•
•
•
•
•
•
•
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
1
◊
◊
◊
•
◊
◊
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
◊
◊
•
•
0
•
•
◊
BHS
BIH
BIL
BIT
BLO
BLS
BMC
BMI
BMS
BNE
BPL
BRA
BRN
BRCLR
BRSET
BSET
BSR
CLC
CLI
10
CLR
CMP
Address mode abbreviations
Condition code symbols
BSC Bit set/clear
BTB Bit test & branch
DIR Direct
IMM Immediate
Tested and set if true,
cleared otherwise
H
Half carry (from bit 3)
◊
IX
IX1
IX2
Indexed (no offset)
I
Interrupt mask
Negate (sign bit)
Zero
•
?
Not affected
Load CCR from stack
Cleared
Indexed, 1 byte offset
Indexed, 2 byte offset
N
Z
C
EXT Extended
INH Inherent
0
1
REL Relative
Carry/borrow
Set
Not implemented
TPG
MOTOROLA
10-8
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
Table 10-8 Instruction set (2 of 2)
Addressing modes
Condition codes
Mnemonic
INH IMM DIR EXT REL IX IX1 IX2 BSC BTB
H
I
N
Z
C
COM
CPX
DEC
EOR
INC
•
•
•
•
•
•
•
•
•
•
•
0
•
•
•
•
•
•
?
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
?
•
•
•
1
•
0
•
•
1
•
•
•
0
◊
◊
◊
◊
◊
•
◊
◊
◊
◊
◊
•
1
◊
•
•
•
•
•
•
•
◊
◊
0
◊
•
•
◊
◊
•
?
•
◊
1
•
•
•
•
◊
•
•
•
•
•
JMP
JSR
LDA
LDX
LSL
LSR
MUL
NEG
NOP
ORA
ROL
ROR
RSP
RTI
•
•
◊
◊
◊
0
•
◊
◊
◊
◊
•
◊
•
◊
•
◊
◊
◊
•
◊
◊
◊
•
?
•
?
•
RTS
SBC
SEC
SEI
◊
•
◊
•
•
•
STA
STOP
STX
SUB
SWI
TAX
TST
TXA
WAIT
◊
•
◊
•
◊
◊
•
◊
◊
•
10
•
•
◊
•
◊
•
•
•
Address mode abbreviations
Condition code symbols
BSC Bit set/clear
BTB Bit test & branch
DIR Direct
IMM Immediate
Tested and set if true,
cleared otherwise
H
Half carry (from bit 3)
◊
IX
IX1
IX2
Indexed (no offset)
I
Interrupt mask
Negate (sign bit)
Zero
•
?
Not affected
Load CCR from stack
Cleared
Indexed, 1 byte offset
Indexed, 2 byte offset
N
Z
C
EXT Extended
INH Inherent
0
1
REL Relative
Carry/borrow
Set
Not implemented
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-9
Bit manipulation
Branch
REL
Read/modify/write
INH
Control
Register/memor y
BTB
BSC
DIR
INH
IX1
IX
INH
INH
IMM
DIR
EXT
IX2
IX1
IX
High
High
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
Low
Low
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
5
3
5
3
3
6
5
9
2
3
4
5
4
3
BRSET0 5 BSET0
BRA
NEG
NEGA
NEGX
NEG
NEG
RTI
SUB
CMP
SBC
CPX
AND
BIT
SUB
CMP
SBC
CPX
AND
BIT
SUB
CMP
SBC
CPX
AND
BIT
SUB
CMP
SBC
CPX
AND
BIT
SUB
CMP
SBC
CPX
AND
BIT
SUB
CMP
SBC
CPX
AND
BIT
0
0
0000
0000
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
BTB
2
BSC
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
REL
3
2
DIR
1
INH
1
INH
2
IX1
1
IX
1
1
INH
6
2
2
2
2
2
2
2
IMM
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
DIR
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
EXT
4
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
IX2
5
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
IX1
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
IX
3
BRCLR0 5 BCLR0
BRN
BHI
RTS
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
1
0001
BTB
2
BSC
5
REL
3
INH
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET1 5 BSET1
MUL
11
2
0010
BTB
2
BSC
5
REL
3
1
1
1
INH
3
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRCLR1 5 BCLR1
BLS
BCC
BCS
BNE
BEQ
COM
LSR
COMA
COMX
COM
LSR
COM
LSR
SWI
5
3
6
5
10
3
0011
BTB
2
BSC
5
REL
3
2
2
DIR
5
INH
3
1
1
INH
3
2
2
IX1
6
1
1
IX
5
1
INH
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET2 5 BSET2
LSRA
LSRX
4
0100
BTB
2
BSC
5
REL
3
DIR
INH
INH
IX1
IX
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRCLR2 5 BCLR2
5
0101
BTB
2
BSC
5
REL
3
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET3 5 BSET3
ROR
ASR
LSL
RORA
RORX
ROR
ASR
LSL
ROR
ASR
LSL
LDA
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
LDA
STA
EOR
ADC
ORA
ADD
JMP
JSR
LDX
STX
5
3
3
6
5
6
0110
BTB
2
BSC
5
REL
3
2
2
2
2
2
DIR
5
1
1
1
1
1
INH
3
1
1
1
1
1
INH
3
2
2
2
2
2
IX1
6
1
1
1
1
1
IX
5
IMM
DIR
4
EXT
5
IX2
6
IX1
5
IX
4
BRCLR3 5 BCLR3
ASRA
ASRX
TAX
CLC
SEC
CLI
2
7
0111
BTB
2
BSC
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
1
1
1
1
1
1
1
INH
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET4 5 BSET4
BHCC
LSLA
LSLX
EOR
ADC
2
8
1000
BTB
2
BSC
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
INH
2
2
2
2
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRCLR4 5 BCLR4
BHCS
ROL
DEC
ROLA
ROLX
ROL
DEC
ROL
DEC
9
1001
BTB
2
BSC
5
REL
3
DIR
5
INH
3
INH
3
IX1
6
IX
5
INH
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET5 5 BSET5
BPL
BMI
BMC
BMS
BIL
DECA
DECX
ORA
ORA
A
1010
BTB
2
BSC
5
REL
3
DIR
INH
INH
IX1
IX
INH
2
IMM
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRCLR5 5 BCLR5
SEI
ADD
ADD
JMP
JSR
LDX
STX
B
1011
BTB
2
BSC
5
REL
3
INH
2
IMM
DIR
2
EXT
3
IX2
4
IX1
3
IX
2
BRSET6 5 BSET6
INC
INCA
INCX
INC
INC
RSP
NOP
5
3
3
6
5
C
1100
BTB
2
BSC
5
REL
3
2
2
DIR
4
1
1
INH
3
1
1
INH
3
2
2
IX1
5
1
1
IX
4
INH
2
DIR
5
EXT
6
IX2
7
IX1
6
IX
5
BRCLR6 5 BCLR6
TST
TSTA
TSTX
TST
TST
BSR
LDX
6
D
1101
BTB
2
BSC
5
REL
3
DIR
INH
INH
IX1
IX
INH
2
2
REL
2
DIR
3
EXT
4
IX2
5
IX1
4
IX
3
BRSET7 5 BSET7
STOP
2
E
1110
BTB
2
BSC
5
REL
3
1
1
INH
2
IMM
DIR
4
EXT
5
IX2
6
IX1
5
IX
4
BRCLR7 5 BCLR7
BIH
CLR
CLRA
CLRX
CLR
CLR
WAIT
TXA
5
3
3
6
5
2
F
1111
BTB
2
BSC
REL
2
DIR
1
INH
1
INH
2
IX1
1
IX
INH
1
INH
DIR
EXT
IX2
IX1
IX
Abbreviations for address modes and register s
Legend
Opcode in hexadecimal
Opcode in binary
BSC
BTB
DIR
EXT
INH
IMM
Bit set/clear
Bit test and branch
Direct
Extended
Inherent
IX
Indexed (no offset)
F
1111
IX1
IX2
REL
A
Indexed, 1 byte (8-bit) offset
Indexed, 2 byte (16-bit) offset
Relative
Accumulator
Index register
Mnemonic
3
0
SUB
0000
1
IX
Bytes
Not implemented
Immediate
X
Cycles
Address mode
10.3
Addressing modes
Ten different addressing modes provide programmers with the flexibility to optimize their code for
all situations. The various indexed addressing modes make it possible to locate data tables, code
conversion tables and scaling tables anywhere in the memory space. Short indexed accesses are
single byte instructions; the longest instructions (three bytes) enable access to tables throughout
memory. Short absolute (direct) and long absolute (extended) addressing are also included. One
or two byte direct addressing instructions access all data bytes in most applications. Extended
addressing permits jump instructions to reach all memory locations.
The term‘effective address’(EA) is used in describing the various addressing modes.The effective
address is defined as the address from which the argument for an instruction is fetched or stored.
The ten addressing modes of the processor are described below.Parentheses are used to indicate
‘contents of’ the location or register referred to. For example, (PC) indicates the contents of the
location pointed to by the PC (program counter). An arrow indicates ‘is replaced by’ and a colon
indicates concatenation of two bytes. For additional details and graphical illustrations, refer to the
M6805 HMOS/M146805 CMOS Family Microcomputer/ Microprocessor User's Manual or to
the M68HC05 Applications Guide.
10.3.1
Inherent
In the inherent addressing mode, all the information necessary to execute the instruction is
contained in the opcode. Operations specifying only the index register or accumulator, as well as
the control instruction, with no other arguments are included in this mode. These instructions are
one byte long.
10.3.2
Immediate
10
In the immediate addressing mode, the operand is contained in the byte immediately following the
opcode. The immediate addressing mode is used to access constants that do not change during
program execution (e.g. a constant used to initialize a loop counter).
EA = PC+1; PC ← PC+2
10.3.3
Direct
In the direct addressing mode, the effective address of the argument is contained in a single byte
following the opcode byte. Direct addressing allows the user to directly address the lowest 256
bytes in memory with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-11
10.3.4
Extended
In the extended addressing mode, the effective address of the argument is contained in the two
bytes following the opcode byte. Instructions with extended addressing mode are capable of
referencing arguments anywhere in memory with a single three-byte instruction. When using the
Motorola assembler, the user need not specify whether an instruction uses direct or extended
addressing. The assembler automatically selects the short form of the instruction.
EA = (PC+1):(PC+2); PC ← PC+3
Address bus high ← (PC+1); Address bus low ← (PC+2)
10.3.5
Indexed, no offset
In the indexed, no offset addressing mode, the effective address of the argument is contained in
the 8-bit index register. This addressing mode can access the first 256 memory locations. These
instructions are only one byte long. This mode is often used to move a pointer through a table or
to hold the address of a frequently referenced RAM or I/O location.
EA = X; PC ← PC+1
Address bus high ← 0; Address bus low ← X
10.3.6
Indexed, 8-bit offset
In the indexed, 8-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the unsigned byte following the opcode. Therefore the
operand can be located anywhere within the lowest 511 memory locations.This addressing mode
is useful for selecting the mth element in an n element table.
EA = X+(PC+1); PC ← PC+2
Address bus high ← K; Address bus low ← X+(PC+1)
where K = the carry from the addition of X and (PC+1)
10
10.3.7
Indexed, 16-bit offset
In the indexed, 16-bit offset addressing mode, the effective address is the sum of the contents of
the unsigned 8-bit index register and the two unsigned bytes following the opcode. This address
mode can be used in a manner similar to indexed, 8-bit offset except that this three-byte instruction
allows tables to be anywhere in memory. As with direct and extended addressing, the Motorola
assembler determines the shortest form of indexed addressing.
EA = X+[(PC+1):(PC+2)]; PC ← PC+3
Address bus high ← (PC+1)+K; Address bus low ← X+(PC+2)
where K = the carry from the addition of X and (PC+2)
TPG
MOTOROLA
10-12
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
10.3.8
Relative
The relative addressing mode is only used in branch instructions. In relative addressing, the
contents of the 8-bit signed byte (the offset) following the opcode are added to the PC if, and only
if, the branch conditions are true. Otherwise, control proceeds to the next instruction. The span of
relative addressing is from –126 to +129 from the opcode address. The programmer need not
calculate the offset when using the Motorola assembler, since it calculates the proper offset and
checks to see that it is within the span of the branch.
EA = PC+2+(PC+1); PC ← EA if branch taken;
otherwise EA = PC ← PC+2
10.3.9
Bit set/clear
In the bit set/clear addressing mode, the bit to be set or cleared is part of the opcode. The byte
following the opcode specifies the address of the byte in which the specified bit is to be set or
cleared. Any read/write bit in the first 256 locations of memory, including I/O, can be selectively set
or cleared with a single two-byte instruction.
EA = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
10.3.10 Bit test and branch
The bit test and branch addressing mode is a combination of direct addressing and relative
addressing. The bit to be tested and its condition (set or clear) is included in the opcode. The
address of the byte to be tested is in the single byte immediately following the opcode byte (EA1).
The signed relative 8-bit offset in the third byte (EA2) is added to the PC if the specified bit is set
or cleared in the specified memory location. This single three-byte instruction allows the program
to branch based on the condition of any readable bit in the first 256 locations of memory.The span
of branch is from –125 to +130 from the opcode address. The state of the tested bit is also
transferred to the carry bit of the condition code register.
10
EA1 = (PC+1); PC ← PC+2
Address bus high ← 0; Address bus low ← (PC+1)
EA2 = PC+3+(PC+2); PC ← EA2 if branch taken;
otherwise PC ← PC+3
TPG
MC68HC05B6
Rev. 4
CPU CORE AND INSTRUCTION SET
MOTOROLA
10-13
THIS PAGE LEFT BLANK INTENTIONALLY
10
TPG
MOTOROLA
10-14
CPU CORE AND INSTRUCTION SET
MC68HC05B6
Rev. 4
11
ELECTRICAL SPECIFICATIONS
This section contains the electrical specifications and associated timing information for the
MC68HC05B6.
11.1
Absolute maximum ratings
Table 11-1 Absolute maximum ratings
Rating
Symbol
Value
Unit
V
(1)
Supply voltage
Input voltage (Except V
V
– 0.5 to +7.0
DD
)
V
V
– 0.5 to V + 0.5
V
PP1
IN
SS
DD
Input voltage
– Self-check mode (IRQ pin only)
V
V
– 0.5 to 2V + 0.5
V
IN
SS
DD
Operating temperature range
– Standard (MC68HC05B6)
– Extended (MC68HC05B6C)
– Automotive (MC68HC05B6M)
T
T to T
0 to +70
–40 to +85
–40 to +125
A
L
H
°C
°C
Storage temperature range
T
– 65 to +150
STG
(2)
Current drain per pin (excluding VDD and VSS)
– Source
– Sink
I
25
45
mA
mA
D
I
S
11
(1) All voltages are with respect to V .
SS
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either V or V
.
SS
DD
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-1
11.2
DC electrical characteristics
Table 11-2 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
(1)
L
H
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.8
V – 0.4
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.8
V
– 0.4
OH
DD
DD
Output low voltage (I = 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
1
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.4
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
V
DD
V
V
IH
DD
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
RESET,TCAP1, TCAP2, RDI
V
V
—
0.2V
6
IL
SS
DD
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
—
—
—
—
3.5
0.5
1
mA
mA
mA
mA
1.5
2
1
0.35
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (extended)
– 40 to 125 (automotive)
—
—
—
—
2
10
20
60
60
µA
µA
µA
µA
—
—
—
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
—
±0.2
±1
µA
IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
±0.2
±0.2
±1
±1
mA
IN
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I
—
—
±5
µA
IN
Capacitance
11
Ports (as input or output), RESET, TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
DD
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I : measured using an external square-wave clock source (f
= 4.2MHz); all inputs 0.2 V from
DD
OSC
rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I : all ports configured as inputs;V = 0.2 V and V = V – 0.2 V: STOP I measured with
DD
IL
IH
DD
DD
OSC1 = V
.
DD
WAIT I is affected linearly by the OSC2 capacitance.
DD
TPG
MOTOROLA
11-2
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
11.2.1
I
trends for 5V operation
DD
For the examples below, typical values are at the mid-point of the voltage range and at a
temperature of 25°C only.
8
7
6
5
I
(mA)
4
3
2
1
0
DD
5.5V
4.5V
0
0.5
1
1.5
2
2.5
3
3.5
4
Internal operating frequency (MHz)
Figure 11-1 Run I vs internal operating frequency (4.5V, 5.5V)
DD
1.2
1
0.8
0.6
0.4
0.2
0
I
(mA)
DD
5.5V
4.5V
0
0.5
1
1.5
2
2.5
3
3.5
4
Internal operating frequency (MHz)
Figure 11-2 Run I (SM = 1) vs internal operating frequency (4.5V, 5.5V)
DD
2.5
2
11
1.5
I
(mA)
DD
1
0.5
0
5.5V
4.5V
0
0.5
1
1.5
2
2.5
3
3.5
4
Internal operating frequency (MHz)
Figure 11-3 Wait I vs internal operating frequency (4.5V, 5.5V)
DD
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-3
0.9
0.8
0.7
0.6
0.5
I
(mA) 0.4
DD
0.3
0.2
0.1
0
5.5V
4.5V
0
0.5
1
1.5
2
2.5
3
3.5
4
Internal operating frequency (MHz)
Figure 11-4 Wait I (SM = 1) vs internal operating frequency (4.5V, 5.5V)
DD
1.6
1.4
1.2
1
0.8
I
(mA) 0.6
A/D + SCI
A/D
SCI
DD
0.4
0.2
0
0
0.5
1
1.5
2
2.5
3
Internal operating frequency (MHz)
Figure 11-5 Increase in I vs frequency for A/D, SCI systems active, VDD = 5.5V
DD
8
7
6
5
4
3
2
1
0
11
Run I
DD
Wait I
DD
I
(mA)
DD
Run I (SM = 1)
DD
Wait I (SM = 1)
DD
0
0.5
1
1.5
2
2.5
3
3.5
4
Internal operating frequency (MHz)
Figure 11-6 I vs mode vs internal operating frequency, V = 5.5V
DD
DD
TPG
MOTOROLA
11-4
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
Table 11-3 DC electrical characteristics for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0Vdc, T = T to T )
DD
SS
A
L
H
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.2mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 0.4mA)
V
V
– 0.3
V – 0.1
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.3
V
– 0.1
OH
DD
DD
Output low voltage (I = 0.4mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.3
0.6
OL
Output low voltage (I
= 0.4mA)
LOAD
V
0.2
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
V
DD
V
V
IH
DD
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
V
V
—
0.2V
DD
IL
SS
RESET, TCAP1, TCAP2, RDI
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
—
—
—
—
1.2
0.2
0.4
3
1
1.5
0.5
mA
mA
mA
mA
0.15
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (extended)
– 40 to 125 (automotive)
—
—
—
—
1
10
10
40
40
µA
µA
µA
µA
—
—
—
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
—
±0.2
±1
µA
µA
IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
±0.2
±0.2
±1
±1
IN
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
I
—
—
±5
µA
IN
Capacitance
Ports (as input or output), RESET,TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
11
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I : measured using an external square-wave clock source (f
= 2.0MHz); all inputs 0.2 V
DD
OSC
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I : all ports configured as inputs;V = 0.2 V and V = V – 0.2 V: STOP I measured with
DD
IL
IH
DD
DD
OSC1 = V
.
DD
WAIT I is affected linearly by the OSC2 capacitance.
DD
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-5
11.2.2
I
trends for 3.3V operation
DD
For the examples below, typical values are at the mid-point of the voltage range and at a
temperature of 25°C only.
2.5
2
1.5
I
(mA)
DD
1
0.5
0
3.6V
3.0V
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-7 Run I vs internal operating frequency (3 V, 3.6V)
DD
0.6
0.5
0.4
0.3
0.2
0.1
0
I
(mA)
DD
3.6V
3.0V
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-8 Run I (SM = 1) vs internal operating frequency (3V,3.6V)
DD
11
1.2
1
0.8
I
(mA)
DD
0.6
0.4
0.2
0
3.6V
3.0V
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-9 Wait I vs internal operating frequency (3V, 3.6V)
DD
TPG
MOTOROLA
11-6
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
0.5
0.4
0.3
0.2
0.1
0
I
(mA)
DD
3.6V
3.0V
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-10 Wait I (SM = 1) vs internal operating frequency (3V, 3.6V)
DD
0.7
0.6
A/D + SCI
0.5
0.4
0.3
0.2
0.1
0
I
(mA)
DD
A/D
SCI
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-11 Increase in I vs frequency for A/D, SCI systems active, V = 3.6V
DD
DD
2.5
2
Run I
DD
11
1.5
1
Wait I
DD
I
(mA)
DD
Run I (SM=1)
DD
Wait I (SM=1)
DD
0.5
0
0
0.5
1
1.5
2
2.5
Internal operating frequency (MHz)
Figure 11-12 I vs mode vs internal operating frequency, V = 3.6V
DD
DD
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-7
11.3
A/D converter characteristics
Table 11-4 A/D characteristics for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 0.5
± 0.5
± 1
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
(1)
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
Conversion time
—
—
32
32
t
CYC
µs
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
IN
RH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
—
—
12
12
t
CYC
(2)
b. Internal RC oscillator
µs
pF
µA
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
12
1
(3)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
11
TPG
MOTOROLA
11-8
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
Table 11-5 A/D characteristics for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 1
± 1
± 2
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
Internal RC oscillator
Conversion time
—
32
µs
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
—
IN
RH
Sample acquisition time Analog input acquisition sampling
(1)
Internal RC oscillator
—
12
12
1
µs
pF
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
(2)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
µA
(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
11
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-9
11.4
Control timing
Table 11-6 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
4.2
4.2
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
dc
dc
2.1
2.1
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
476
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
1.5
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
4064
16
—
—
PORL
t
CYC
t
PORL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
DOGL
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
t
10
10
10
—
—
—
ms
ms
ms
0 to 70 (standard)
ERA
– 40 to 85 (extended)
t
ERA
– 40 to 125 (automotive)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 125 (automotive)
t
10
10
20
—
—
—
ms
ms
ms
PROG
t
PROG
t
PROG
Timer (see Figure 11-13)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
125
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
—
—
—
ns
ILIH
(4)
t
—
t
11
ILIL
CYC
(5)
OSC1 pulse width
t
, t
90
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to execute
TLTL
the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 238ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
TPG
MOTOROLA
11-10
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
Table 11-7 Control timing for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
2.0
2.0
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
—
dc
1.0
1.0
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
1000
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
1.5
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
4064
16
—
—
PORL
t
CYC
t
PORL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
DOGL
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
30
30
30
—
—
—
ms
ms
ms
ERA
– 40 to 85 (extended)
– 40 to 125 (automotive)
t
ERA
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 125 (automotive)
t
30
30
30
—
—
—
ms
ms
ms
PROG
t
PROG
t
PROG
Timer (see Figure 11-13)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
250
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
250
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
200
ns
OH OL
11
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 500ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
TPG
MC68HC05B6
Rev. 4
ELECTRICAL SPECIFICATIONS
MOTOROLA
11-11
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure 11-13 Timer relationship
11
TPG
MOTOROLA
11-12
ELECTRICAL SPECIFICATIONS
MC68HC05B6
Rev. 4
12
MECHANICAL DATA
12.1
MC68HC05B family pin configurations
52-pin plastic leaded chip carrier (PLCC)
12.1.1
VRH
PD4/AN4
8
9
46
45
44
43
42
41
40
39
38
37
36
35
34
PC3
PC4
PC5
PC6
PC7
VSS
VPP1/NU
PB0
PB1
PB2
PB3
PB4
Device
Pin 6 Pin 15 Pin 40
VDD 10
PD3/AN3
11
PD2/AN2 12
PD1/AN1 13
PD0/AN0 14
NC/VPP6 15
OSC1 16
MC68HC05B4
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC05B32
MC68HC705B5
MC68HC705B16
NC
NC
NC
NC
NC
NC
NU
NC
NC
NU
VPP1
VPP1
VPP1
VPP1
NU
NC
NC
NC
VPP6
OSC2 17
VPP6 VPP1
VPP6 VPP1
VPP6 VPP1
RESET 18
IRQ 19
MC68HC705B16N NU
MC68HC705B32 NU
PLMA 20
PB5
NC = Not connected
NU = Non-user pin (Should be tied to V
SS
in an electrically noisy environment)
12
Figure 12-1 52-pin PLCC pinout for the MC68HC05B6
TPG
MC68HC05B6
Rev. 4
MECHANICAL DATA
MOTOROLA
12-1
12.1.2
64-pin quad flat pack (QFP)
PC1
PC0
NC
NC
NC
NC
NC
RDI
SCLK
TDO 10
TCMP2 11
TCMP1 12
PD7/AN7 13
PD6/AN6 14
PD5/AN5 15
NC 16
1
2
3
4
5
6
7
8
9
48 PB6
47 PB7
46 NC
45 NC
44 PA0
43 PA1
42 PA2
41 PA3
40 PA4
39 PA5
38 PA6
37 PA7
36 NC
35 TCAP2
34 TCAP1
33 PLMB D/A
Device
Pin 27
Pin 55
Pin 57
MC68HC05B4
NC
NC
NC
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC05B32
NC
NC
VPP1
MC68HC705B5
MC68HC705B16
Not available in this package
VPP6
NU
NU
NC
VPP1
VPP1
VPP1
MC68HC705B16N VPP6
MC68HC705B32
VPP6
NC = Not connected
12
NU = Non-user pin (Should be tied to V in an electrically noisy environment)
SS
Figure 12-2 64-pin QFP pinout for the MC68HC05B6
TPG
MOTOROLA
12-2
MECHANICAL DATA
MC68HC05B6
Rev. 4
12.1.3
56-pin shrink dual in line package (SDIP)
TCMP1
PD7
TCMP2
TDO
SCLK
RDI
PC0
PC1
NC
PC2
PC3
PC4
PC5
PC6
PC7
VSS
VPP1/NC
PB0
PB1
PB2
PB3
PB4
PB5
NC
1
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
2
PD6
3
PD5
NC
NC/NU
NC
VRL
VRH
PD4
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
VDD
PD3
PD2
PD1
PD0
NC/VPP6
OSC1
OSC2
RESET
IRQ
PLMA
PLMB
TCAP1
TCAP2
PA7
PB6
PB7
PA0
PA6
PA1
PA5
PA2
PA4
PA3
Device
Pin 6
NC
NC
NC
NC
NC
NC
Pin 16
NC
Pin 42
MC68HC05B4
MC68HC05B6
MC68HC05B8
MC68HC05B16
MC68HC05B32
MC68HC705B5
MC68HC705B16
MC68HC705B16N
MC68HC705B32
NC
NC
VPP1
VPP1
VPP1
VPP1
NC
NC
NC
NC
VPP6
Not available in this package
Contact Sales
NU
VPP6
VPP1
NC = Not connected
NU = Non-user pin (Should be tied to V in an electrically noisy environment)
SS
12
Figure 12-3 56-pin SDIP pinout for the MC68HC05B6
TPG
MC68HC05B6
Rev. 4
MECHANICAL DATA
MOTOROLA
12-3
12.2
MC68HC05B6 mechanical dimensions
12.2.1
52-pin plastic leaded chip carrier (PLCC)
B
S
S
S
S
–M
M
0.18
T N
–P
L
–N–
Y BRK
–M–
–L–
Case No. 778-02
52 Lead PLCC
w/o pedestal
G1
W
Z1
pin 52
pin 1
X
–P–
V
U
S
S
S
S
–M
M
0.18
T N
–P
L
A
R
S
S
S
S
S
S
S
S
M
M
0.18
0.18
T L
T L
–M
–M
N
N
–P
–P
Z
C
0.10
G
–T–
SEATING PLANE
J
E
G1
S
S
S
S
S
0.25
T L
–M
N
–P
Dim.
A
B
Min.
Max.
20.19
20.19
4.57
Notes
Dim.
U
Min.
19.05
1.07
1.07
1.07
—
Max.
19.20
1.21
1.21
1.42
0.50
10°
19.94
19.94
4.20
V
1. Datums –L–, –M–, –N– and –P– are determined where top of lead
shoulder exits plastic body at mould parting line.
2. Dimension G1, true position to be measured at datum –T– (seating
plane).
3. Dimensions R and U do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side.
C
W
X
E
2.29
2.79
12
F
0.33
0.48
Y
G
H
J
1.27 BSC
Z
2 °
0.66
0.51
0.81
—
G1
K1
Z1
18.04
1.02
2 °
18.54
—
4. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
5. All dimensions in mm.
K
R
0.64
—
10°
19.05
19.20
Figure 12-4 52-pin PLCC mechanical dimensions
TPG
MOTOROLA
12-4
MECHANICAL DATA
MC68HC05B6
Rev. 4
12.2.2
64-pin quad flat pack (QFP)
L
B
B
48
33
P
49
32
- A, B, D -
- A -
L
- B -
Detail “A”
Case No. 840C
64 lead QFP
B
V
F
Detail “A”
64
17
N
J
1
16
S
- D -
A
Base
Metal
D
0.20
C A – B
D
D
Section B–B
M
S
S
0.05 A – B
0.20
C A – B
D
S S
M
S
U
0.20
H A – B
M
S
T
Detail “C”
M
M
E
R
Q
C
Datum
Plane
-H-
K
X
-C-
G
H
W
Seating
Plane
Dim.
A
B
Min.
Max.
14.10
14.10
2.457
0.45
2.40
—
Notes
Dim.
M
N
Min.
5°
Max.
10°
13.90
13.90
2.067
0.30
1. Datum Plane –H– is located at bottom of lead and is coincident with
the lead where the lead exits the plastic body at the bottom of the
parting line.
0.130
0.170
C
P
0.40 BSC
2. Datums A–B and –D to be determined at Datum Plane –H–.
3. Dimensions S and V to be determined at seating plane –C–.
4. Dimensions A and B do not include mould protrusion. Allowable
mould protrusion is 0.25mm per side. Dimensions A and B do
include mould mismatch and are determined at Datum Plane –H–.
5. Dimension D does not include dambar protrusion. Allowable
dambar protrusion shall be 0.08 total in excess of the D dimension
at maximum material condition. Dambar cannot be located on the
lower radius or the foot.
D
E
Q
2 °
8°
0.30
2.00
R
0.13
F
0.30
S
16.20
16.60
G
H
J
0.80 BSC
T
0.20 REF
0.067
0.250
0.230
0.66
U
9 °
15°
12
0.130
0.50
V
16.20
16.60
K
L
W
X
0.042 NOM
6. Dimensions and tolerancing per ANSI Y 14.5M, 1982.
7. All dimensions in mm.
12.00 REF
1.10
1.30
Figure 12-5 64-pin QFP mechanical dimensions
TPG
MC68HC05B6
Rev. 4
MECHANICAL DATA
MOTOROLA
12-5
12.2.3
56-pin shrink dual in line package (SDIP)
L
- A -
56
1
29
28
H
Case No. 859-01
56 lead SDIP
- B -
M
J
C
S
M
0.25
T B
- T -
K
N
Seating
Plane
G
E
F
D
S
M
0.25
T A
Dim.
A
Min.
Max.
52.45
14.22
5.08
Notes
Dim.
H
Min.
Max.
51.69
13.72
3.94
7.62 BSC
1. Due to space limitations, this case shall be represented by a
general case outline, rather than one showing all the leads.
2. Dimensions and tolerancing per ANSI Y 14.5 1982.
3. All dimensions in mm.
B
J
0.20
2.92
0.38
3.43
C
K
D
0.36
0.56
L
15.24 BSC
4. Dimension L to centre of lead when formed parallel.
5. Dimensions A and B do not include mould flash. Allowable mould
flash is 0.25 mm.
E
0.89 BSC
M
N
0 °
15°
F
0.81
1.17
0.51
1.02
G
1.778 BSC
Figure 12-6 56-pin SDIP mechanical dimensions
12
TPG
MOTOROLA
12-6
MECHANICAL DATA
MC68HC05B6
Rev. 4
13
ORDERING INFORMATION
This section describes the information needed to order the MC68HC05B6 and other family members.
To initiate a ROM pattern for the MCU, it is necessary to contact your local field service office, local
sales person or Motorola representative. Please note that you will need to supply details such as:
mask option selections; temperature range; oscillator frequency; package type; electrical test
requirements; and device marking details so that an order can be processed, and a customer
specific part number allocated. Refer to Table 13-1 for appropriate part numbers.The part number
consists of the device title plus the appropriate suffix. For example, the MC68HC05B6 in 52-pin
PLCC package at –40 to +85°C would be ordered as: MC68HC05B6CFN.
Table 13-1 MC order numbers
Suffix
0 to 70°C
FN
FU
B
FN
FU
B
FN
FU
B
FN
FU
B
FN
FU
B
FN
B
FN
FU
FN
FU
Suffix
Suffix
Suffix
Device Title
Package Type
-40 to +85°C -40 to +105°C -40 to +125°C
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
56-pin SDIP
52-pin PLCC
64-pin QFP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
CFN
CFU
CB
CFN
CFU
CB
CFN
CFU
CB
CFN
CFU
CB
VFN
VFU
VB
VFN
VFU
VB
VFN
VFU
VB
VFN
VFU
VB
N/A
N/A
N/A
VFN
VB
VFN
VFU
VFN
VFU
MFN
MFU
MB
MFN
MFU
MB
MFN
MFU
MB
MFN
MFU
MB
N/A
N/A
N/A
MFN
MB
MC68HC05B6
MC68HC05B4
MC68HC05B8
MC68HC05B16
MC68HC05B32
CFN
CFU
Contact Sales
CFN
CB
MC68HC705B5
MC68HC705B16
CFN
CFU
CFN
CFU
MFN
MFU
MFN
MFU
MC68HC705B16N
MC68HC705B32
13
Contact Sales
FN
FU
B
CFN
CFU
CB
N/A
N/A
N/A
N/A
N/A
N/A
TPG
MC68HC05B6
Rev. 4
ORDERING INFORMATION
MOTOROLA
13-1
13.1
EPROMS
For the MC68HC05B6, an 8 kbyte EPROM programmed with the customer’s software (positive
logic for address and data) should be submitted for pattern generation. All unused bytes should be
programmed to $00. The size of EPROM which should be used for all other family members is
listed in Table 13-2.
The EPROM should be clearly labelled, placed in a conductive IC carrier and securely packed.
Table 13-2 EPROMs for pattern generation
Device
Size of EPROM
8 kbyte
MC68HC05B4
MC68HC05B8
MC68HC05B16
MC68HC05B32
8 kbyte
16 kbyte
32 kbyte
13.2
Verification media
All original pattern media (EPROMs) are filed for contractual purposes and are not returned. A
computer listing of the ROM code will be generated and returned with a listing verification form.
The listing should be thoroughly checked and the verification form completed, signed and returned
to Motorola. The signed verification form constitutes the contractual agreement for creation of the
custom mask. If desired, Motorola will program blank EPROMs (supplied by the customer) from
the data file used to create the custom mask, to aid in the verification process.
13.3
ROM verification units (RVU)
Ten MCUs containing the customer’s ROM pattern will be provided for program verification.These
units will have been made using the custom mask but are for ROM verification only. For
expediency, they are usually unmarked and are tested only at room temperature (25°C) and at
5 Volts. These RVUs are included in the mask charge and are not production parts. They are
neither backed nor guaranteed by Motorola Quality Assurance.
13
TPG
MOTOROLA
13-2
ORDERING INFORMATION
MC68HC05B6
Rev. 4
A
MC68HC05B4
The MC68HC05B4 is a device similar to the MC68HC05B6, but without EEPROM and having a
reduced ROM size of 4 kbytes.The entire MC68HC05B6 data sheet applies to the MC68HC05B4,
with the exceptions outlined in this appendix.
A.1
Features
•
•
•
4158 bytes User ROM (including 14 bytes User vectors)
No EEPROM
High speed version not available
Section 3.5, ‘EEPROM’, therefore, does not apply to the MC68HC05B4, and the register at
address $07 only allows the user to select whether or not the ECLK should appear at PC2, using
bit 3 of $07. All other bits of this register read as ‘0’.
Table A-1 Mode of operation selection
IRQ pin
to V
TCAP1 pin
to V
DD
PD3
X
0
PD4
X
Mode
Single chip
V
V
SS
SS
DD
DD
2V
2V
V
X
Self check
DD
V
1
0
Serial RAM loader
Jump to any address
DD
DD
2V
V
1
1
DD
DD
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B4
MOTOROLA
A-1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
RESET
IRQ
COP watchdog
4158 bytes
User ROM
(including 14 bytes
User vectors)
OSC2
OSC1
Oscillator
÷ 2 /÷32
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
M68HC05
CPU
432 bytes
self check ROM
VDD
VSS
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
176 bytes
RAM
8-bit
A/D converter
PC7
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
programmable
timer
PD7/AN7
VRH
VRL
RDI
SCLK
TDO
PLMA D/A
PLMB D/A
PLM
SCI
Figure A-1 MC68HC05B4 block diagram
14
TPG
MOTOROLA
A-2
MC68HC05B4
MC68HC05B6
Rev. 4
MC68HC05B4
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
ROM
(48 bytes)
RAM
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
$0100
Stack
SCI control register 2
SCI status register
SCI data register
$0200
Timer control register
Self-check ROM I
(192 bytes)
Timer status register
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$02C0
$0F00
User ROM
(4096 bytes)
Counter low register
$1F00
$1FF0
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Self-check ROM II
(240 bytes)
$1FF2–3
$1FF4–5
SCI
Timer overflow
$1FF6–7 Timer output compare 1& 2
$1FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
$1FFA–B
$1FFC–D
External IRQ
SWI
Reserved
$1FFE–F Reset/power-on reset
Figure A-2 Memory map of the MC68HC05B4
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B4
MOTOROLA
A-3
Table A-2 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
$0003 PD7/
AN7
PD6/ PD5/ PD4/ PD3/ PD2/ PD1/ PD0/ Undefined
AN6
AN5
AN4
AN3
AN2
AN1
AN0
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
ECLK control
$0004
$0005
$0006
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
$0007
$0008
0
0
0
0
0
ECLK
0
0
0
A/D data (ADDATA)
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
0000 0000
(1)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG ?001 000?
(2)
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL uuuu uuuu
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
uuuu uuuu
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
14
TPG
MOTOROLA
A-4
MC68HC05B4
MC68HC05B6
Rev. 4
A.2
Self-check mode
The self-check function available on the MC68HC05B4 provides an internal capability to determine
if the device is functional. Self-check is performed using the circuit shown in Figure A-3. Port C
pins PC0–PC3 are monitored for the self-check results (light emitting diodes are shown but other
devices could be used), and are interpreted as described in Table A-3. The self-check mode is
entered by applying 2 x V dc (via a 4.7kΩ resistor) to the IRQ pin and 5V dc input (via a 4.7kΩ
DD
resistor) to the TCAP1 pin and then depressing the reset switch to execute a reset. After reset, the
following tests are performed automatically and once completed they continually repeat. A good
device will exhibit flashing LEDs; a bad device will be indicated by the LEDs holding at one value.
Note:
Self-check code can be obtained from your local Motorola representative.
I/0
—
—
—
—
Functionally exercises ports A, B, C and D
Counter test for each RAM byte
RAM
ROM
Timer
Exclusive OR with odd ones parity result
Tracks counter registers and checks ICF1, ICF2, OCF1, OCF2 andTOF
flags
SCI
A/D
—
—
Transmission test; check for RDRF, TDRE, TC and FE flags
Check A/D functionality on internal channels: VRL, VRH and (VRL +
VRH)/2
PLM
—
Checks the PLM basic functionality
Tests external timer and SCI interrupts
Tests the watchdog
Interrupts —
Watchdog—
Caution: This document includes descriptions of the various self-check and bootstrap
mechanisms that are currently implemented as firmware in the non-user ROM areas of
the MC68HC05B6 and related devices.
As these firmware routines are intended primarily to help Motorola’s engineers test the
devices, they may be changed or removed at any time.
For this reason, Motorola recommends the self-check and bootstrap routines are not
called from the user software. Customers who do call these routines from the user
software do so at their own risk.
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B4
MOTOROLA
A-5
Table A-3 MC68HC05B4 self-check results
PC3
1
PC2
0
PC1
0
PC0
1
Remarks
Bad port
Bad port
0
1
1
0
1
0
1
0
Bad RAM
1
0
1
1
Bad ROM
1
1
0
0
Bad Timer
1
1
0
1
Bad SCI
1
1
1
0
Bad A/D
0
0
0
1
Bad PLM
0
0
1
0
Bad interrupts
Bad watchdog
Good device
Bad device, bad port etc.
0
0
1
1
Flashing
All others
‘0’ indicates LED on;‘1’ indicates LED off
14
TPG
MOTOROLA
A-6
MC68HC05B4
MC68HC05B6
Rev. 4
P1
GND
+5V
10 nF
47 µF
2xV
DD
15
NC
8
10
VDD
RESET
VRH
16
17
OSC1
10 MΩ
18
RESET
OSC2
0.01 µF
4k7 Ω
22 pF
19
22 pF
4 MHz
IRQ
6
40
50
52
20
21
2
BC239
NC
23
1
VPP1
RDI
TCAP2
TCMP2
4k7 Ω
4k7 Ω
22
TCAP1
TDO
EEPROM tested
PLMA
PLMB
TCMP1
SCLK
32
33
34
35
36
37
38
39
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
EEPROM not tested
51
4k7 Ω
3
4
5
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
42
43
44
45
46
47
48
49
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
9
11
12
13
14
24
25
26
27
28
29
30
31
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
680 Ω
680 Ω
680 Ω
680 Ω
VSS VRL
41
7
Note:
For the MC68HC05B4, switches on PB5 and PB6 have no effect
All resistors are 10 kΩ, unless otherwise stated.
Figure A-3 MC68HC05B4 self-check schematic diagram
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B4
MOTOROLA
A-7
THIS PAGE LEFT BLANK INTENTIONALLY
14
TPG
MOTOROLA
A-8
MC68HC05B4
MC68HC05B6
Rev. 4
B
MC68HC05B8
The MC68HC05B8 is a device similar to the MC68HC05B6, but with an increased ROM size of
7.25 kbytes. The entire MC68HC05B6 data sheet applies to the MC68HC05B8, with the
exceptions outlined in this appendix.
B.1
Features
•
•
7230 bytes User ROM (including 14 bytes User vectors)
High speed version available
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B8
MOTOROLA
B-1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
7230 bytes
User ROM
(including 14 bytes
User vectors)
VPP1
Charge pump
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESET
IRQ
COP watchdog
OSC2
OSC1
Oscillator
÷ 2 /÷32
432 bytes
self check ROM
PC0
PC1
PC2/ECLK
PC3
PC4
PC5
PC6
PC7
M68HC05
CPU
176 bytes
RAM
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
programmable
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PD7/AN7
VRH
PLMA D/A
PLMB D/A
PLM
VRL
Figure B-1 MC68HC05B8 block diagram
14
TPG
MOTOROLA
B-2
MC68HC05B8
MC68HC05B6
Rev. 4
MC68HC05B8
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
ROM
(48 bytes)
RAM
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
OPTR (1 byte)
Non protected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
Timer control register
Self-check ROM I
(192 bytes)
Timer status register
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$02C0
$0300
User ROM
(7168 bytes)
Counter low register
$1F00
$1FF0
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Self-check ROM II
(240 bytes)
$1FF2–3
$1FF4–5
SCI
Timer overflow
$1FF6–7 Timer output compare 1& 2
$1FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
$1FFA–B
$1FFC–D
External IRQ
SWI
Options register
$0100
Reserved
$1FFE–F Reset/power-on reset
Figure B-2 Memory map of the MC68HC05B8
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B8
MOTOROLA
B-3
Table B-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
0
0
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA)
0000 0000
CH3 CH2 CH1 CH0 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of theWDOG bit after reset is dependent upon the mask option selected;1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
B-4
MC68HC05B8
MC68HC05B6
Rev. 4
C
MC68HC705B5
The MC68HC705B5 is a device similar to the MC68HC05B6, but with the 6 kbytes ROM and 256
bytes EEPROM replaced by a single EPROM array. In addition, the self-check routines available
on the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B5 is intended to
operate as a one time programmable (OTP) version of the MC68HC05B6 without EEPROM or the
MC68HC05B4, meaning that the application program can never be erased once it has been
loaded into the EPROM.The entire MC68HC05B6 data sheet applies to the MC68HC705B5, with
the exceptions outlined in this appendix.
C.1
Features
•
•
•
•
•
•
•
•
•
6206 bytes EPROM (including 14 bytes User vectors)
No EEPROM
Bootstrap firmware
Simultaneous programming of up to 4 bytes
Data protection for program code
Optional pull-down resistors on port B and port C
MC68HC05B6 mask options are programmable using control bits held in the options register
52-pin PLCC and 56-pin SDIP packages
High speed version not available
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EPROM1
6206 bytes
EPROM
(including 14 bytes
User vectors)
496 bytes
bootstrap ROM
VPP6
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
RESET
IRQ
COP watchdog
OSC2
OSC1
Oscillator
PC0
PC1
÷ 2 /÷32
PC2/ECLK
PC3
PC4
176 bytes
RAM
PC5
M68HC05
CPU
PC6
PC7
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
programmable
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure C-1 MC68HC705B5 block diagram
14
TPG
MOTOROLA
C-2
MC68HC705B5
MC68HC05B6
Rev. 4
MC68HC705B5
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
EPROM
(48 bytes)
RAM
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
$0100
Stack
User EPROM1
(256 bytes)
SCI control register 2
$0200
SCI status register
Bootstrap ROMI
(256 bytes)
SCI data register
Timer control register
Timer status register
$0300
$0800
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
User EPROM
(5888 bytes)
Options register
$1EFE
$1F00
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Bootstrap ROMII
(240 bytes)
$1FF0
$1FF2–3
$1FF2–3
SCI
Timer overflow
$1FF2–3 Timer output compare 1& 2
$1FF2–3 Timer input capture 1 & 2
User vectors
(14 bytes)
$1FF2–3
$1FF2–3
External IRQ
SWI
Options register
$1EFE
Reserved
$1FF2–3 Reset/power-on reset
Figure C-2 Memory map of the MC68HC705B5
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-3
Table C-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
$0000
$0001
Undefined
Undefined
PC2/
ECLK
Port C data (PORTC)
$0002
Undefined
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EPROM/ECLK control
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
u?00 0uuu
0000 0000
(1)
EPPT ELAT EPGM ECLK
A/D data (ADDATA)
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
0000 0000
?001 000?
(2)
(3)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL
uuuu
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
uuuu
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Undefined
Undefined
Undefined
Undefined
1111 1111
1111 1100
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
(4)
Options (OPTR)
$1EFE
EPP
0
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit reflects the state of the EPP bit in the options register ($1EFE) at reset.
(2) This bit is set each time the device is powered-on.
(3) The state of the WDOG bit after reset depends on the mask option selected;‘1’ = watchdog enabled and ‘0’ = watchdog disabled.
(4) Because this register is implemented in EPROM, reset has no effect on the state of the individual bits.
14
TPG
MOTOROLA
C-4
MC68HC705B5
MC68HC05B6
Rev. 4
C.2
EPROM
The MC68HC705B5 has a total of 6206 bytes of EPROM, 256 bytes being reserved for the
EPROM1 array (see Figure C-2). The EPP bit (EPROM protect) is not operative on the EPROM1
array, making it possible to program it after the main EPROM has been programmed and
protected. The reset and interrupt vectors are located at $1FF2-$1FFF and the EPROM control
register described in Section C.3.1 is located at address $0007.
The EPROM array is supplied by the VPP6 pin in both read and programming modes.Typically the
user’s software will be loaded in a programming board where VPP6 is controlled by one of the
bootstrap loader routines (bootloader mode). It will then be placed in an application where no
programming occurs (user mode). In this case the VPP6 pin should be hardwired to V
.
DD
An erased EPROM byte reads as $00.
Warning: A minimum V
voltage must be applied to the VPP6 pin at all times, including
DD
power-on, as a lower voltage could damage the device. Unless otherwise stated,
EPROM programming is guaranteed at ambient (25°C) temperature only
C.2.1
EPROM programming operation
The User program can be used to program some EPROM locations, provided the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
EPROM will not be available for code execution while the ELAT bit is set.The VPP6 switching must
occur externally, after the EPGM bit is set, for example, under the control of a signal generated on
a pin by the programming routine.
Note:
Unless the part has a window for reprogramming, only the cumulative programming of
bits to logic 1 is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to 4 bytes, they must be in the same group of addresses
which share the same most significant address bits; only the two LSBs can change.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-5
C.3
EPROM registers
C.3.1
EPROM control register
State
on reset
Address bit 7
$0007
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
EPROM/ECLK control
EPPT ELAT EPGM ECLK
u?00 0uuu
(1) This bit is a copy of the EPP bit in the options register at $1EFE and therefore its state on reset will be the same as that for the
EPP bit.
Bit 7 — Factory use only
This bit is strictly for factory use only and will always read zero.
EPPT — EPROM protect test bit
This bit is a copy of the EPROM protect bit (EPP) located in the option register.When ELAT is set,
the EPPT bit can be tested by the software to check if the EPROM array is protected or not, since
the EPROM content is not available when ELAT is set.
POR or external reset modifies this bit to reflect the state of the EPP bit in the options register.
ELAT — EPROM programming latch enable bit
1 (set)
–
When set, this bit allows latching of the address and up to 4 data
bytes for further programming, provided EPGM is zero.
0 (clear) – When cleared, program and interrupt routines can be executed and
data can be read in the EPROM or firmware ROM.
STOP, power-on and external reset clear this bit.
EPGM — EPROM programming bit
This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after
ELAT is set and at least one byte is written to the EPROM. It is not possible to clear EPGM by
software, but clearing ELAT will always clear EPGM.
ECLK — External clock option bit
See Section 4.3.
14
TPG
MOTOROLA
C-6
MC68HC705B5
MC68HC05B6
Rev. 4
C.4
Options register (OPTR)
State
on reset
Address bit 7
$1EFE
bit 6
EPP
bit 5
0
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Options (OPTR)
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM, therefore reset has no effect on the state of the individual bits.
Note:
This register can only be written to while the device is in bootloader mode.
Bit 7 — Factory use only
Warning: This bit is strictly for factory use only and will always read zero to avoid accidental
damage to the device. Any attempt to write to this bit could result in physical damage.
EPP — EPROM protect
This bit protects the contents of the main EPROM against accidental modification; it has no effect
on reading or executing code in the EPROM.
1 (set)
–
EPROM contents are protected.
0 (clear) – EPROM contents are not protected.
RTIM — Reset time
This bit can modify t
, i.e. the time that the RESET pin is kept low following a power-on reset.
PORL
This feature is handled in the ROM part via a mask option.
1 (set)
–
t
= 16 cycles.
PORL
PORL
0 (clear) –
t
= 4064 cycles.
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset.
1 (set)
–
The watchdog will be active immediately following power-on or
external reset (except in bootstrap mode).
0 (clear) – The watchdog system will be disabled after power-on or external
reset.
WWAT — Watchdog during WAIT mode
This bit can modify the status of the watchdog counter during WAIT mode.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-7
1 (set)
–
The watchdog will be active during WAIT mode.
0 (clear) – The watchdog system will be disabled during WAIT mode.
PBPD – Port B pull-down resistors
1 (set)
–
Pull-down resistors are connected to all 8 pins of port B; the
pull-down, R , is active only while the pin is an input.
PD
0 (clear) – No pull-down resistors are connected.
PCPD — Port C pull-down resistors
1 (set)
–
Pull-down resistors are connected to all 8 pins of port C; the
pull-down, R , is active only while the pin is an input.
PD
0 (clear) – No pull-down resistors are connected.
The combination of bit 0 and bit 1 allows the option of pull-down resistors on 0, 8 or 16 inputs.This
feature is not available on the MC68HC05B6.
C.5
Bootstrap mode
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced with 496 bytes of
bootstrap firmware.The bootstrap firmware located from $0200 to $02FF and $1F00 to $1FEF can
be used to program the EPROM, to check if the EPROM is erased and to load and execute data
in RAM.
When the MC68HC705B5 is placed in the bootstrap mode, the bootstrap reset vector is fetched
and the bootstrap firmware starts to execute. Table C-2 shows the conditions required to enter
each level of bootstrap mode on the rising edge of RESET. The hold time on the IRQ and TCAP1
pins after the external RESET pin is brought high is two clock cycles.
Table C-2 Mode of operation selection
IRQ pin
to V
TCAP1 pin PD2
PD3
x
PD4
x
Mode
V
V
to V
DD
x
0
x
x
x
Single chip
SS
DD
SS
+ 9 Volts
+ 9 Volts
V
1
0
Erased EPROM verification
DD
V
0
0
EPROM parallel bootstrap load
DD
+ 9 Volts
V
1
1
EPROM (RAM) serial bootstrap load and execute
RAM parallel bootstrap load and execute
DD
+ 9 Volts
V
0
1
DD
x = Don’t care
14
TPG
MOTOROLA
C-8
MC68HC705B5
MC68HC05B6
Rev. 4
The bootstrap program first copies part of itself into RAM, as the program cannot be executed in
ROM during verification/programming of the EPROM. It then sets theTCMP1 output to a logic high
level.
Reset
N
IRQ at 9V?
Y
User mode
N
TCAP1 set?
Y
Non-user mode
Bootstrap mode
Y
PD4 set?
A
N
Y
EPROM
erased?
N
N
PD3 set?
N
PD2 set?
Y
Red LED on
EPROM not erased
Y
Parallel EPROM bootstrap
Program EPROM;
parallel load;
green LED flashes
Non-user mode
Green LED on
Y
Programming OK?
N
Red LED on
Green LED on
Bad EPROM programming
EPROM verified
Figure C-3 Modes of operation flow chart (1 of 2)
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-9
A
Bootstrap RAM
N
N
PD3 set?
Y
Serial EPROM (RAM) bootstrap
PD4 set?
Red LED off
Y
Transmit last four
programmed locations
Load next RAM
byte
N
RAM full?
Y
Receive address
Receive four data
Execute RAM
program at $0050
Bad EPROM
programming
Y
Negative
address?
Green LED on
Red LED on
N
N
Execute RAM
program at $0083
Program EPROM data
at address; green LED
flashes
Y
Programming OK?
Figure C-4 Modes of operation flow chart (2 of 2)
14
TPG
MOTOROLA
C-10
MC68HC705B5
MC68HC05B6
Rev. 4
C.5.1
Erased EPROM verification
The flowchart in Figure C-3 and Figure C-4 shows that the on-chip bootstrap routines can be used
to check if the EPROM is erased (all $00s). If a non $00 byte is detected, the red LED stays on
and the routine will stay in a loop. Only when the whole EPROM content is verified as erased will
the green LED be turned on.
C.5.2
EPROM parallel bootstrap load
When this mode is selected, the EPROM is loaded in increasing address order with non EPROM
segments being skipped by the loader. Simultaneous programming is performed by reading four
bytes of data before actual programming is performed, thus dividing the loading time of the internal
EPROM by four.
When PD2=0, the programming time is set to 5 milliseconds and the program/verify routine takes
approximately 15 seconds.
Parallel data is entered through Port A, while the 13-bit address is output on port B and PC0 to
PC4. If the data comes from an external EPROM, the handshake can be disabled by connecting
together PC5 and PC6. If the data is supplied via a parallel interface, handshaking will be provided
by PC5 and PC6 according to the timing diagram of Figure C-5.
During programming, the green LED flashes at about 3 Hz.
Upon completion of the programming operation, the EPROM content is checked against the
external data source. If programming is verified the green LED stays on, while an error causes the
red LED to be turned on. Figure C-6 shows a circuit that can be used to program the EPROM (or
to load and execute data in the RAM).
Note:
The entire EPROM can be loaded from the external source; if it is desired to leave a
segment undisturbed, the data for this segment should be all zeros.
Address
HDSK out
(PC5)
DATA
HDSK in
(PC6)
F29
Data read
Data read
14
Figure C-5 Timing diagram with handshake
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-11
P1 1
GND
+5V
2
3
RESET
1kΩ
RUN
1N914
+
100µF
V
PP
100kΩ
1N914
TCAP1 VRH VDD
1.0µF
+
47µF
+
IRQ
OSC1
OSC2
10MΩ
RESET
NC
RDI
VRL
TCAP2
PD7
PD6
PD5
red LED
TCMP1
TCMP2
PLMA
PLMB
4.0 MHz
22pF
470Ω
0.01µF
22pF
470Ω
green LED
PD3
red LED — programming failed
green LED — programming OK
PD2
PD1
PD0
MC68HC705B5
+5V
RAM
EPROM
PD4
1 kΩ
1
26 27 28
VPP NC PGM VCC
TDO
10 kΩ
SCLK
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10
A0
A1
A2
A3
A4
A5
VPP6
PC7
9
8
7
6
5
4
3
12 kΩ
4k7Ω
+
BC239C
1nF
4k7Ω
20
A6
CE
A7
27C64
+5V
11
12
13
15
16
17
18
19
D0
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
100 kΩ
D1
D2
D3
D4
D5
HDSK out
Short circuit if
PC5
PC6
handshake not used
25
24
21
23
2
A8
A9
HDSK in
A12
PC4
PC3
PC2
PC1
PC0
D6
A10
D7
A11
A11
A10
A9
A12
A8
VSS
GND
14
OE
22
Note:
This circuit is recommended for programming only at 25°C and not for use in the
end application, or at temperatures other than 25°C. If used in the end application,
VPP6 should be tied to VDD to avoid damaging the device.
14
Figure C-6 EPROM(RAM) parallel bootstrap schematic diagram
TPG
MOTOROLA
C-12
MC68HC705B5
MC68HC05B6
Rev. 4
C.5.3
EPROM (RAM) serial bootstrap load and execute
The serial routine communicates through the SCI with an external host, typically a PC, by means
of an RS232 link at 9600 baud, 8-bit, no parity and full duplex.
Data format is not ASCII, but 8-bit binary, so a complementary program must be run by the host to
supply the required format. Such a program is available for the IBM PC from Motorola.
The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed
of programming, four bytes are programmed in parallel while the data is simultaneously
transmitted and received in full duplex. This implies that while 4 bytes are being programmed, the
next 4 bytes are received and the preceding 4 bytes are echoed.The format accepted by the serial
loader is as follows:
[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]
Address n must have the two LSBs at zero so that n, n+1, n+2 and n+3 have identical MSBs.These
blocks of four bytes do not need to be contiguous, as a new address is transmitted for each new
group.
The protocol is as follows:
1
The MC68HC705B5 sends the last two bytes programmed to the host as a
prompt; this allows verification by the host of proper programming.
1) In response to the first byte prompt, the host sends the first address byte.
2) After receiving the first address byte, the MC68HC705B5 sends the next
byte programmed.
3) The exchange of data continues until the MC68HC705B5 has sent the four
data bytes and the host has sent the 2 address data bytes and 4 data bytes.
4) If the data is non zero, it is programmed at the address provided, while the
next address and bytes are received and the previous data is echoed.
5) Loop to 1.
After reset, the MC68HC705B5 serial bootstrap routine will first echo two blocks of four bytes at
$0000, as no data is programmed yet.
If the data sent in is $00, no programming in the EPROM takes place, and the contents of the
accessed location are returned as a prompt. The entire EPROM memory can be read in this
fashion (serial dump). The red LED will be on if the data read from the EPROM is not $00.
Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if
the address sent by the host in the serial protocol points to the RAM.
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table C-3). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s
service-routine address.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-13
Table C-3 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
$00E4
$00E7
$00EA
$00ED
$00F0
$00F3
SWI
A 10-byte stack is also reserved at the top of the RAM allowing, for example, one interrupt and two
sub-routine levels.
Program execution is triggered by sending a negative (bit 7 set) high address; execution starts at
address XADR ($0083).
The RAM addresses between $0050 and $0082 are used by the loader and are therefore not
available to the user during serial loading/executing.
Refer to Figure C-7 shows a suitable circuit. Figure C-9 shows address and data bus timing.
C.5.4
RAM parallel bootstrap load and execute
The RAM bootstrap program will start loading the RAM with external data (e.g. from a 2564 or
2764 EPROM). Before loading a new byte, the state of the PD4/AN4 pin is checked; if this pin goes
to level ‘0’, or if the RAM is full, then control is given to the loaded program at address $0050.
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to Figure C-10. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6.
Figure C-8 shows a circuit that can be used to load the RAM with short test programs. Up to 8
programs can be loaded in turn from the EPROM. Selection is accomplished by means of the
switches connected to the EPROM higher address lines (A8 through A10).If the user program sets
PC0 to level ‘1’, the external EPROM will be disabled, rendering both port A outputs and port B
inputs available.
The EPROM parallel bootstrap loader circuit (Figure C-6) can also be used, provided VPP is tied
to V . The high order address lines will be at zero. The LEDs will stay off.
DD
14
TPG
MOTOROLA
C-14
MC68HC705B5
MC68HC05B6
Rev. 4
P1
1
2
3
GND
+5V
V
PP
RESET
RUN
10nF
+
100kΩ
1kΩ
1N914
47µF
22
8
10
TCAP1 VRH VDD
1.0µF
1N914
19
+
IRQ
47µF
+
18 RESET
OSC1
OSC2
10MΩ
Red LED
470Ω
470Ω
0.01µF
20
PLMA
4.0 MHz
22pF
22pF
21
PLMB
Green LED
PD3
Erase check
MC68HC705B5
Green — EPROM erased
Red — EPROM not erased
Serial boot
PD4
Erase check
1 kΩ
Serial boot
Green — programming OK
Red — programming error
39
38
37
36
35
34
33
32
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10 kΩ
VPP6
PC7
12 kΩ
4k7Ω
+
BC239C
1nF
4k7Ω
31
PA0
30
PA1
29
PA2
28
PA3
27
PA4
26
PA5
25
43
44
45
46
47
48
49
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PA6
24
PA7
9600 BD
8-bit
14
22µF
+5V
PD0
13
+
no parity
PD1
12
16
1
2 x 3KΩ
PD2
5
8
2
6
+
22µF
PD5
4
5
3
4
22µF
PD6
3
7
3
2
1
+
MAX
232
RS232
Connector
23
2
1
51
40
+
22µF
PD7
TCAP2
TCMP1
TCMP2
SCLK
NC
5
50
13
14
12
11
RDI
52
TDO
15
VSS
41
VRL
7
Note:
A minimum V
voltage must be applied to the VPP6 pin at all times,
DD
including power-on, as a lower voltage could damage the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C)
temperature only
14
Figure C-7 EPROM (RAM) serial bootstrap schematic diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-15
1
2
P1
GND
+5V
+
RESET
1kΩ
RUN
1N914
100µF
100kΩ
1N914
TCAP1
VDD
1.0µF
+
IRQ
OSC1
OSC2
10MΩ
RESET
0.01µF
4.0 MHz
22pF
22pF
PD4
VPP6
+5V
MC68HC705B5
18 x 100 kΩ
NC
+5V
+5V
TCAP2
TCMP2
TCMP1
PLMB
PLMA
SCLK
TDO
RDI
VRH
VRL
PD7
PD6
PD5
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
16 x 100kΩ
1
26 27 28
VPP NC PGM VCC
20
10
CE
A11
A12
A0
A1
A2
A3
A4
A5
A6
A7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB6
PB7
23
2
9
8
7
6
5
4
3
U1
2764
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
+5V
3 x 4.7kΩ
25
24
21
A8
PC3
PC2
A9
PC1
PC0
A10
GND
14
OE
22
VSS
14
Figure C-8 RAM parallel bootstrap schematic diagram
TPG
MOTOROLA
C-16
MC68HC705B5
MC68HC05B6
Rev. 4
C.5.5
Bootstrap loader timing diagrams
t
t
t
t
CDDE
COOE
COOE
COOE
Address
Data
t
t
t
t
ADE
ADE
ADE
ADE
t
t
t
t
DHE
DHE
DHE
DHE
t
max (address to data delay)
min (data hold time)
5 machine cycles
14 machine cycles
117 machine cycles < t
ADE
t
DHA
t
(load cycle time)
< 150 machine cycles
COOE
COOE
t
(programming cycle time)
t
+ t
(5ms nominal)
CDDE
COOE
PROG
1 machine cycle = 1/(2f (Xtal))
0
Figure C-9 EPROM parallel bootstrap loader timing diagram
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-17
t
CR
Address
PC5 out
t
HO
t
ADR
t
DHR
Data
t
max
HI
PC6 in
PD4
t
max
EXR
t
max (address to data delay; PC6=PC5)
min (data hold time)
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
ADR
t
DHR
t
(load cycle time; PC6=PC5)
(PC5 handshake out delay)
CR
t
HO
t
max (PC6 handshake in, data hold time)
HI
t
max (max delay for transition to be
EXR
recognised during this cycle; PC6=PC5
30 machine cycles
1 machine cycle = 1/(2f (Xtal))
0
Figure C-10 RAM parallel loader timing diagram
14
TPG
MOTOROLA
C-18
MC68HC705B5
MC68HC05B6
Rev. 4
C.6
DC electrical characteristics
Note:
The complete table of DC electrical characteristics can be found in Section 11.2. The
values contained in the following table should be used in conjunction with those quoted
in that section.
Table C-4 Additional DC electrical characteristics for MC68HC705B5
(V = 5 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
µA
Input current
I
80
RPD
Port B and port C pull-down (V =V )
IN IH
EPROM absolute maximum voltage
EPROM programming voltage
EPROM programming current
EPROM read voltage
V
max
V
—
15.5
—
18
16
18
V
V
PP6
DD
V
I
15.0
—
PP6
mA
V
PP6
V
V
V
V
DD
PP6R
DD
DD
C.7
Control timing
Note:
The complete table of control timing can be found in Section 11.4.The values contained
in the following table should be used in conjunction with those quoted in that section.
Table C-5 Additional control timing for MC68HC705B5
(V = 5 Vdc ± 10%, V = 0 Vdc, T = 25° C)
DD
SS
A
Characteristic
Symbol
Min
Typ
Max
Unit
EPROM programming time
t
5
—
20
ms
PROG
14
MC68HC05B6
Rev. 4
MC68HC705B5
MOTOROLA
C-19
THIS PAGE LEFT BLANK INTENTIONALLY
14
MOTOROLA
C-20
MC68HC705B5
MC68HC05B6
Rev. 4
D
MC68HC05B16
Maskset errata
This errata section outlines the differences between previously available masksets
(D20J, F62J and G28F) and all other masksets. Unless otherwise stated, the main
body of Appendix D refers to all these other masksets with any differences being noted
in this errata section.
•
Certain MC68HC05B16 masksets contain the same oscillator circuitry as the
MC68HC05B6 (see Section 2.5.8.3).These are denoted by D20J, F62J and G28F.
The MC68HC05B16 is a device similar to the MC68HC05B6, but with increased RAM, ROM and
self-check ROM sizes. The entire MC68HC05B6 data sheet, including the electrical
characteristics, applies to the MC68HC05B16, with the exceptions outlined in this appendix.
D.1
Features
•
•
•
•
•
15 kbytes User ROM
352 bytes of RAM
496 bytes self-check ROM
52-pin PLCC, 56-pin SDIP and 64-pin QFP packages
High speed version available
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B16
MOTOROLA
D-1
Table D-1 Mode of operation selection
IRQ pin
to V
TCAP1 pin
to V
DD
PD3
X
0
PD4
X
Mode
Single chip
V
V
SS
SS
DD
DD
2V
2V
V
X
Self check
DD
V
1
0
Serial RAM loader
Jump to any address
DD
DD
2V
V
1
1
DD
DD
D.2
Self-check routines
The self-check routines for the MC68HC05B16 are identical to those of the MC68HC05B4 with the
following exception.
The count byte on the MC68HC05B16 can be any value up to 256 ($00). The first 176 bytes are
loaded into RAM I and the remainder is loaded into RAM II starting at $0250.
14
TPG
MOTOROLA
D-2
MC68HC05B16
MC68HC05B6
Rev. 4
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
VPP1
Charge pump
496 bytes
self-check ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
15120 bytes
ROM
RESET
IRQ
COP watchdog
PC0
PC1
PC2/ECLK
PC3
PC4
OSC2
OSC1
Oscillator
352 bytes
static RAM
÷ 2 /÷32
PC5
PC6
PC7
M68HC05
CPU
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure D-1 MC68HC05B16 block diagram
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B16
MOTOROLA
D-3
D.3
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase, as shown
in Figure D-2. The t or t specifications (see Section 11.4) do not apply when using an
OXOV
ILCH
external clock input. The equivalent specification of the external clock source should be used in
lieu of t or t
.
ILCH
OXOV
L
C
R
S
1
OSC1
OSC2
MCU
C
0
OSC1
OSC2
(b) Crystal equivalent circuit
MCU
C
C
OSC2
OSC1
OSC1
OSC2
(a) Crystal/ceramic resonator
oscillator connections
External
clock
NC
(c) External clock source connections
Crystal
Ceramic resonator
2MHz 4MHz
Unit
Ω
2 – 4MHz
10
Unit
Ω
R (max)
400
5
75
7
R (typ)
S
S
C
pF
C
40
pF
0
0
C
8
12
ƒF
pF
C
4.3
pF
1
1
C
C
15 – 40 15 – 30
15 – 30 15 – 25
C
C
30
pF
OSC1
OSC2
P
OSC1
OSC2
P
pF
30
pF
R
10
10
MΩ
—
R
1 – 10
1250
MΩ
—
Q
30 000 40 000
Q
(d) Typical crystal and ceramic resonator parameters
Figure D-2 Oscillator connections
14
TPG
MOTOROLA
D-4
MC68HC05B16
MC68HC05B6
Rev. 4
MC68HC05B16
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
ROM
(48 bytes)
RAM1
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
Options register
Unprotected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
$0250
Timer control register
Timer status register
RAM11
(176 bytes)
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$0300
User ROM
(15104 bytes)
$3DFE
$3E00
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Self-check ROM
(496 bytes)
$3FF0
$3FF2–3
$3FF4–5
SCI
Timer overflow
$3FF6–7 Timer output compare 1& 2
$3FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
Options register
$0100
$3FFA–B
$3FFC–D
External IRQ
SWI
Reserved
$3FFE–F Reset/power-on reset
Figure D-3 Memory map of the MC68HC05B16
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B16
MOTOROLA
D-5
Table D-2 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
0
0
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA)
0000 0000
CH3 CH2 CH1 CH0 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
D-6
MC68HC05B16
MC68HC05B6
Rev. 4
E
MC68HC705B16
To ensure correct operation of the MC68HC705B16 after power-on, the device must
be reset a second time after power-on. This can be done in software using the
MC68HC705B16 watchdog.
The following software sub-routine should be used:
RESET2
BSET
0, $0C Start watchdog
STOP STOP causes immediate watchdog
system reset
The interrupt vector at $3FF0 and $3FF1 must be initialised with the RESET2
address value.
The MC68HC705B16 is a device similar to the MC68HC05B6, but with increased RAM and
15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in
the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16 is an OTPROM
(one-time programmable ROM) version of the MC68HC05B16, meaning that once the application
program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data
sheet applies to the MC68HC705B16, with the exceptions outlined in this appendix.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-1
E.1
Features
•
•
•
•
•
•
•
15 kbytes EPROM
352 bytes of RAM
576 bytes bootstrap ROM
Simultaneous programming of up to 8 bytes of EPROM
Optional pull-down resistors available on all port B and port C pins
52-pin PLCC and 64-pin QFP packages
High speed version not available
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
VPP1
VPP6
Charge pump
576 bytes
bootstrap ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
15168 bytes
EPROM
RESET
IRQ
COP watchdog
PC0
PC1
PC2/ECLK
PC3
PC4
OSC2
OSC1
Oscillator
352 bytes
static RAM
÷ 2 /÷ 32
PC5
PC6
PC7
M68HC05
CPU
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure E-1 MC68HC705B16 block diagram
Note:
The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not
apply to the MC68HC705B16.Data specific to the MC68HC705B16 can be found in this
appendix.
14
TPG
MOTOROLA
E-2
MC68HC705B16
MC68HC05B6
Rev. 4
MC68HC705B16
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
E/EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
EPROM
(48 bytes)
RAM1
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
Options register
Unprotected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
$0250
Bootstrap ROM1
(80 bytes)
Timer control register
Timer status register
RAM11
(176 bytes)
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$0300
User EPROM
(15104 bytes)
$3DFE
$3DFF
$3E00
Mask option register
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Bootstrap ROM11
(496 bytes)
$3FF0–1
$3FF2–3
$3FF4–5
SCI
Timer overflow
$3FF6–7 Timer output compare 1& 2
$3FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
Options register
$0100
$3FFA–B
$3FFC–D
External IRQ
SWI
Mask option register
$3DFE
Reserved
$3FFE–F Reset/power-on reset
Figure E-2 Memory map of the MC68HC705B16
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-3
Table E-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EPROM/EEPROM/ECLK control
A/D data (ADDATA)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
0000 0000
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(4)
Mask option register (MOR)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
E-4
MC68HC705B16
MC68HC05B6
Rev. 4
E.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see
Figure D-2). The t or t specifications (see Section E.8) do not apply when using an
OXOV
ILCH
external clock input. The equivalent specification of the external clock source should be used in
lieu of t
or t
.
OXOV
ILCH
E.3
EPROM
The MC68HC705B16 memory map is given in Figure E-2. The device has a total of 15168 bytes
of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.
The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the
user’s software would be loaded into a programming board where V
is controlled by one of the
PP6
bootstrap loader routines. It would then be placed in an application where no programming occurs.
In this case the VPP6 pin should be hardwired to V
.
DD
Warning: A minimum V
voltage must be applied to the VPP6 pin at all times, including
DD
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature
only.
E.3.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read
operations.The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’ which
automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading
the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory
content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,
the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin
must be at the V level. When entering the STOP mode, the EPROM is automatically set to the
DD
read mode.
Note:
An erased byte reads as $00.
E.3.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.
However, the user program can be used to program some EPROM locations if the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-5
EPROM will not be available for code execution while the E6LAT bit is set.TheV
switching must
PP6
occur externally after the E6PGM bit is set, for example under control of a signal generated on a
pin by the programming routine.
Note:
When the part becomes a PROM, only the cumulative programming of bits to logic ‘1’
is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to eight bytes, these bytes must be in the same group
of addresses which share the same most significant address bits; only the three least significant
bits can change.
E.3.3
EPROM/EEPROM/ECLK control register
State
on reset
Address bit 7
$0007
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EPROM/EEPROM/ECLK control
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
E6LAT — EPROM programming latch enable bit
1 (set)
–
Address and up to eight data bytes can be latched into the EPROM
for further programming providing the E6PGM bit is cleared.
0 (clear) – Data can be read from the EPROM or firmware ROM; the E6PGM bit
is reset to zero when E6LAT is ‘0’.
STOP, power-on and external reset clear the E6LAT bit.
Note:
After the t
erase time or t
programming time, the E6LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E6PGM bit.
E6PGM — EPROM program enable bit
This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after
E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using
software but clearing E6LAT will always clear E6PGM.
Table E-2 EPROM control bits description
E6LAT E6PGM
Description
Read/execute in EPROM
0
1
1
0
0
1
Ready to write address/data to EPROM
programming in progress
14
Note:
The E6PGM bit can never be set while the E6LAT bit is at zero.
TPG
MOTOROLA
E-6
MC68HC705B16
MC68HC05B6
Rev. 4
ECLK
See Section 4.3.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
E1LAT — EEPROM programming latch enable bit
1 (set)
–
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
erase time or t
programming time, the E1LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) Internal charge pump generator switched on.
–
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table E-3.
Table E-3 EEPROM control bits description
E1ERA E1LAT E1PGM
Description
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
Read condition
Ready to load address/data for program/erase
Byte programming in progress
Ready for byte erase (load address)
Byte erase in progress
14
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-7
E.3.4
Mask option register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Mask option register (MOR)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
RTIM — Reset time
This bit can modify the time t
, where the RESET pin is kept low after a power-on reset.
PORL
1 (set)
–
t
t
= 16 cycles.
PORL
PORL
0 (clear) –
= 4064 cycles.
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system
is disabled after power-on or external reset but when this bit is set, it will be active immediately
after the following resets (except in bootstrap mode).
WWAT — Watchdog during WAIT mode
This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog
system is disabled inWAIT mode but when this bit is set, the watchdog will be active inWAIT mode.
PBPD — Port B pull-down
This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,
R
, is active on a given pin only while it is an input.
PD
PCPD — Port C pull-down
This bit, when programmed, connects a resistive pull-down on each pin of port C. This pull-down,
R
, is active on a given pin only while it is an input.
PD
14
TPG
MOTOROLA
E-8
MC68HC705B16
MC68HC05B6
Rev. 4
E.3.5
EEPROM options register (OPTR)
State
on reset
Address bit 7
$0100
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Options (OPTR)
EE1P SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
in the options register.
1 (set)
–
Part 2 of the EEPROM array is not protected; all 256 bytes of
EEPROM can be accessed for any read, erase or programming
operations.
0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful.
When this bit is set to 1 (erased), the protection will remain until the next power-on or external
reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.
Note:
The EEPROM1 protect function is disabled while in bootstrap mode.
SEC — Secure bit
This bit allows the EPROM and EEPROM1 to be secured from external access.When this bit is in
the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be
used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1
content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the
EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be
entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its
new value will have no effect until the next power-on or external reset.
1 (set)
–
EEPROM/EPROM not protected.
0 (clear) – EEPROM/EPROM protected.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-9
E.4
Bootstrap mode
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 576 bytes of bootstrap
firmware. A detailed description of the modes of operation within bootstrap mode is given below.
The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can
be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load
and execute data in RAM.
After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the IRQ pin should be at + 9V with the TCAP1 pin ‘high’ during transition of the RESET pin
from low to high. The hold time on the IRQ and TCAP1 pins is two clock cycles after the external
RESET pin is brought high.
When the MC68HC705B16 is placed in the bootstrap mode, the bootstrap reset vector is fetched
and the bootstrap firmware starts to execute. Table E-4 shows the conditions required to enter
each level of bootstrap mode on the rising edge of RESET.
Table E-4 Mode of operation selection
IRQ pin
to V
TCAP1 pin PD1 PD2 PD3 PD4
Mode
V
V
to V
DD
x
0
x
0
x
x
x
0
Single chip
SS
DD
SS
+ 9 Volts
V
Erased EPROM verification (EEV)
DD
Erased EPROM verification;erase EEPROM;EPROM/EEPROM
parallel program/verify
+ 9 Volts
V
1
1
0
0
0
1
0
0
DD
Erased EPROM verification; erase EEPROM;
EPROM/EEPROM/ RAM serial bootstrap load and execute
+ 9 Volts
V
DD
+ 9 Volts
+ 9 Volts
V
x
x
x
x
0
1
1
1
RAM parallel bootstrap load and execute (if SEC bit = 1)
Serial EPROM/EEPROM/RAM bootloader (if SEC = 1)
DD
V
DD
x = Don’t care
The bootstrap program first copies part of itself in RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM. It then sets
the TCMP1 output to a logic high level.
14
TPG
MOTOROLA
E-10
MC68HC705B16
MC68HC05B6
Rev. 4
Reset
N
N
IRQ at 9V?
Y
User mode
Y
N
TCAP1 set?
Y
SEC bit active?
Non-user mode
Bootstrap mode
Erased EPROM verification
Y
N
EPROM
erased?
Y
N
PD4 set?
PD2 set?
Y
A
Green LED on
N
N
Non-user mode
PD1 set?
Y
Red LED on
EPROM not erased
Y
PD3 set?
N
B
Bulk erase EEPROM1
Parallel E/EEPROM bootstrap
Program EPROM;
parallel load;green LED
flashes
Red LED on
N
EEPROM1 erased?
Y
Y
Programming OK?
N
Red LED on
Green LED on
Red LED off
Bad EPROM programming
EPROM verified
14
Figure E-3 Modes of operation flow chart (1 of 2)
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-11
Y
N
A
SEC bit set?
N
Red LED flashes
PD3 set?
Parallel bootstrap RAM
Serial E/EEPROM (RAM) bootstrap
Y
N
B
PD4 set?
Y
Transmit last four
programmed locations
Load next RAM
byte
N
RAM1 full?
Y
Receive address
Receive four data
Execute RAM
program at $0050
Negative
address?
Y
N
Green LED on
Execute RAM
Program E/EEPROM
data at address; green
LED flashes
program at $008B
Figure E-4 Modes of operation flow chart (2 of 2)
14
TPG
MOTOROLA
E-12
MC68HC705B16
MC68HC05B6
Rev. 4
E.4.1
Erased EPROM verification
If a non $00 byte is detected, the red LED is turned on and the routine stops (see Figure E-3 and
Figure E-4). Only when the entire EPROM content is verified as erased does the green LED switch
on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming occurs
until such time as a high level is sensed on PD1. If PD1=1, the bootstrap program proceeds to
erase the EEPROM1 for a nominal 100 ms (4.0 MHz crystal). It is then checked for complete
erasure; if a non $FF byte is detected, the red LED is turned on, and erase is performed a second
time, and so on until total erasure is verified. At this point, both EPROM and EEPROM1 are
completely erased and the security bit is cleared. The programming operation can then be
performed. A schematic diagram of the circuit required for erased EPROM verification is shown in
Figure E-7.
E.4.2
EPROM/EEPROM parallel bootstrap
Before the parallel bootstrap routines begin, the erased EPROM verification program is executed
as described in Section E.4.1. When PD2=0, the programming time is set to 5 milliseconds with
the bootstrap program and verify for the EPROM taking approximately 15 seconds. The EPROM
is loaded in increasing address order with non EPROM segments being skipped by the loader.
Simultaneous programming is performed by reading eight bytes of data before actual
programming is performed, thus the loading time of the internal EPROM is divided by eight.
Parallel data is entered through Port A, while the 14-bit address is output on port B, PC0 to PC4
and TCMP2. If the data comes from an external EPROM, the handshake can be disabled by
connecting together PC5 and PC6. If the data is supplied by a parallel interface, handshaking will
be provided by PC5 and PC6 according to the timing diagram of Figure E-5 (see also Figure E-6).
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the contents of the EPROM and EEPROM1 are
checked against the external data source. If programming is verified the green LED stays on, while
an error will cause the red LED to be turned on. Figure E-7 is a schematic diagram of a circuit that
can be used to program the EPROM or to load and execute data in the RAM.
Note:
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all zeros
for EPROM data and all $FFs for EEPROM1 data.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-13
Address
HDSK out
(PC5)
Data
HDSK in
(PC6)
F29
Data read
Data read
Figure E-5 Timing diagram with handshake
t
t
t
t
CDDE
COOE
COOE
COOE
Address
t
t
t
t
ADE
ADE
ADE
ADE
t
t
t
t
DHE
DHE
DHE
DHE
Data
t
max (address to data delay)
min (data hold time)
5 machine cycles
ADE
t
14 machine cycles
117 machine cycles < t
DHA
t
(load cycle time)
< 150 machine cycles
COOE
COOE
t
(programming cycle time)
t
+ t
(5ms nominal for EPROM; 10ms for EEPROM1))
CDDE
COOE
PROG
1 machine cycle = 1/(2f (Xtal))
0
Figure E-6 Parallel EPROM loader timing diagram
14
TPG
MOTOROLA
E-14
MC68HC705B16
MC68HC05B6
Rev. 4
P1
1
2
3
GND
+5V
RESET
RUN
1N914
+
100µF
V
PP
100kΩ
1N914
1kΩ
TCAP1 VRH VDD
1.0µF
+
47µF
+
IRQ
OSC1
OSC2
RESET
4.0 MHz
22pF
NC
RDI
VRL
TCAP2
PD7
PD6
PD5
red LED
TCMP1
VPP1
PLMA
PLMB
470Ω
22pF
0.01µF
470Ω
green LED
Erase check & boot
Boot
red LED — programming failed
green LED — programming OK
PD3
PD2
EPROM erase
check
PD1
PD0
Erase check
green LED — EPROM erased
red LED — EPROM not erased
MC68HC705B16
MCU
RAM
+5V
28
PD4
EPROM
1 kΩ
1
27
SCLK
TDO
VPP PGM VCC
10k Ω
26
10
A13
TCMP2
VPP6
PC7
12 kΩ
A0
A1
A2
A3
A4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
9
8
7
6
5
4
3
4k7Ω
+
BC239C
1nF
4k7Ω
20
CE
A5
A6
A7
27C128
+5V
100 kΩ
11
12
13
15
16
17
18
19
HDSK out
Short circuit if
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PC6
handshake not used
25
24
21
23
2
A8
A9
A10
A11
A12
HDSK in
A12
PC4
PC3
PC2
PC1
PC0
A11
A10
A9
A8
VSS
GND
14
OE
22
Note:
This circuit is recommended for programming only at 25°C and not for use in the
end application, or at temperatures other than 25°C. If used in the end application,
VPP6 should be tied to VDD to avoid damaging the device.
14
Figure E-7 EPROM Parallel bootstrap schematic diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-15
E.4.3
EEPROM/EPROM/RAM serial bootstrap
For erased EPROM verification, PD4 must be at ‘0’. In this case, erased EPROM verification
executes as described in Section E.4.1 before control is given to the serial routine.
If PD4 is at ‘1’, the program initially checks the state of the security bit. If the security bit is active
(‘0’), the program will not enter serial bootstrap and the red LED will flash. Otherwise the serial
bootstrap program will be executed according to Figure E-3 and Figure E-4.
The serial routine communicates through the SCI with an external host, typically a PC, by means
of an RS232 link at 9600 baud, 8-bit, no parity and full duplex. Refer to Figure E-8 for a schematic
diagram of a suitable circuit.
Note:
Data format is not ASCII, but 8-bit binary, so a complementary program must be run by
the host to supply the required format. Such a program is available for the IBM PC from
Motorola.
The EPROM bootstrap routines are used to customise the OTP EPROM. To increase the speed
of programming the 15 kbytes, four bytes are programmed while the data is simultaneously
transmitted back and forward in full duplex. This implies that while 4 bytes are being programmed
the next 4 bytes are received and the preceding 4 bytes are echoed. The format accepted by the
serial loader is as follows:
1) EPROM locations
[address n high] [address n low] [data(n)] [data (n+1)] [data (n+2)] [data (n+3)]
Address n must have the two least significant bits at zero so that n, n+1, n+2 and n+3
have identical most significant bits. These blocks of four bytes do not need to be
contiguous, as a new address is transmitted for each new group.
2) EEPROM1 locations
[address n high] [address n low] [data(n)] [dummy data 1] [dummy data 2] [dummy data 3]
The same four byte protocol of data exchange is used, but only the first data value is
programmed at address n.The three following dummy data values must be sent to be
in agreement with the protocol, but are not significant.
The protocol is as follows:
1) The MC68HC705B16 sends the last two bytes programmed to the host as a
prompt;this also allows the host to verify that programming has been carried
out correctly.
2) In response to the first byte prompt, the host sends the first address byte.
3) After receiving the first address byte, the MC68HC705B16 sends the next
byte programmed.
14
TPG
MOTOROLA
E-16
MC68HC705B16
MC68HC05B6
Rev. 4
P1
1
2
3
GND
+5V
V
PP
RESET
RUN
10nF
+
100kΩ
1kΩ
1N914
47µF
22
8
10
TCAP1 VRH VDD
1.0µF
1N914
19
+
IRQ
47µF
+
18 RESET
OSC1
OSC2
Red LED
470Ω
470Ω
0.01µF
20
PLMA
4.0 MHz
22pF
22pF
21
PLMB
Green LED
U2MC68HC705B16
MCU (socket)
PD3
Erase check
Green LED — EPROM erased
Red LED — EPROM not erased
Serial boot
PD4
Erase check
&
serial boot
1 kΩ
Serial boot
Flashing green LED — programming
Green LED — programming ended
39
38
37
36
35
34
33
32
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10k Ω
VPP6
12 kΩ
4k7Ω
PC7
+
BC239C
1nF
4k7Ω
31
30
29
28
27
26
25
24
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Erase check and serial boot
EPROM erase check
43
44
45
46
47
48
49
PC6
PC5
PC4
PC3
PC2
PC1
PC0
9600 BD
8-bit
no parity
14
13
12
5
4
3
22µF
+5V
PD0
PD1
PD2
PD5
PD6
PD7
+
16
2 x 3KΩ
22µF
8
5
7
3
2
1
1
2
6
+
22µF
3
VPP1
TCAP2
TCMP1
TCMP2
SCLK
4
+
MAX
232
RS232
connector
23
2
1
51
40
+
22µF
5
50
52
13
14
12
11
RDI
TDO
15
NC
VSS
41
VRL
7
Note:
A minimum V
voltage must be applied to the VPP6 pin at all times,
DD
including power-on, as a lower voltage could damage the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C)
temperature only
14
Figure E-8 RAM/EPROM/EEPROM serial bootstrap schematic diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-17
4) The exchange of data continues until the MC68HC705B16 has sent the four
data bytes and the host has sent the 2 address data bytes and 4 data bytes.
5) If the data is different from $00 for EPROM or $FF for EEPROM, it is
programmed at the address provided, while the next address and bytes are
received and the previous data is echoed.
6) Loop to 1.
After reset, the MC68HC705B16 serial bootstrap routine will first echo two blocks of four bytes at
$00, as no data is programmed yet.
If the data received is $00 for EPROM locations or $FF for EEPROM locations, no programming
in the EPROM and EEPROM1 takes place, and the contents of the accessed location are returned
as a prompt. The entire EPROM/EEPROM memory can be read in this fashion (serial dump).
Warning: When using this function with a programmed device, the device must be placed into
RAM/EPROM/EEPROM serial bootstrap mode without EPROM erase check (PD4 = 1).
Serial RAM loading and execute can be accomplished in this mode. A RAM byte will be written if
the address sent by the host in the serial protocol points to the RAM.
RAM bytes $008B–$00E3 and $0250–$02ED are available for user test programs. A 10-byte stack
resides at the top of RAMI, allowing, for example, one interrupt and two sub-routine levels. The
RAM addresses between $0050 and $008A are used by the loader and are therefore not available
to the user during serial loading/executing.
If the SEC bit is at‘1’, program execution is triggered by sending a negative (bit 7 set) high address;
execution starts at address XADR ($008B).
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table E-5). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the user’s service
routine address.
Table E-5 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
$02EE
$02F1
$02F4
$02F7
$02FA
$02FD
SWI
14
TPG
MOTOROLA
E-18
MC68HC705B16
MC68HC05B6
Rev. 4
E.4.4
RAM parallel bootstrap
The program first checks the state of the security bit. If the SEC bit is active, i.e. ‘0’, the program
will not enter the RAM bootstrap mode and the red LED will flash. Otherwise the RAM bootstrap
program will start loading the RAM with external data (e.g. from a 2564 or 2764 EPROM). Before
loading a new byte the state of the PD4/AN4 pin is checked. If this pin goes to level ‘0’, or if the
RAM is full, then control is given to the loaded program at address $0050. See Figure E-3 and
Figure E-4.
If the data is supplied by a parallel interface, handshaking will be provided by PC5 and PC6
according to Figure E-9. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6.
Figure E-10 provides a schematic diagram of a circuit that can be used to load the RAM with short
test programs. Up to 8 programs can be loaded in turn from the EPROM. Selection is
accomplished by means of the switches connected to the EPROM higher address lines (A8
through A10). If the user program sets PC0 to level ‘1’, this will disable the external EPROM, thus
rendering both port A output and port B input available. The EPROM parallel bootstrap loader
schematic can also be used (Figure E-7), provided VPP is at V level. The high order address
DD
lines will be at zero. The LEDs will stay off.
t
CR
Address
PC5 out
t
HO
t
ADR
t
DHR
Data
t
max
HI
PC6 in
PD4
t
max
EXR
t
max (address to data delay; PC6=PC5)
min (data hold time)
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
ADR
t
DHR
t
(load cycle time; PC6=PC5)
(PC5 handshake out delay)
CR
t
HO
t
max (PC6 handshake in, data hold time)
HI
t
max (max delay for transition to be recognised during this cycle; PC6=PC5
EXR
1 machine cycle = 1/(2f (Xtal))
0
14
Figure E-9 Parallel RAM loader timing diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-19
E.4.4.1
Jump to start of RAM ($0050)
PD4 must be high during the first 49 program cycles and pulled low before the 68th cycle for
immediate jump execution at address $0050.
1
P1
GND
+5V
+
RESET
1kΩ
RUN
2
1N914
100µF
100kΩ
1N914
TCAP1
VDD
1.0µF
+
IRQ
OSC1
RESET
OSC2
0.01µF
4.0 MHz
22pF
22pF
PD4
VPP6
+5V
U2MC68HC705B16
MCU (socket)
18 x 100 kΩ
VPP1
NC
+5V
TCAP2
TCMP2
TCMP1
PLMB
PLMA
SCLK
16 x 100kΩ
1
26 27 28
VPP NC PGM VCC
20
10
CE
A11
A12
A0
A1
A2
A3
A4
A5
A6
A7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB6
PB7
TDO
RDI
23
2
9
8
7
6
5
4
3
VRH
VRL
PD7
PD6
PD5
PD3
PD2
PD1
PD0
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
U1
2764
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
+5V
3 x 4.7kΩ
25
24
21
A8
A9
A10
GND
14
OE
22
VSS
Figure E-10 RAM parallel bootstrap schematic diagram
14
TPG
MOTOROLA
E-20
MC68HC705B16
MC68HC05B6
Rev. 4
E.5
Absolute maximum ratings
Table E-6 Absolute maximum ratings
Rating
Symbol
Value
Unit
V
(1)
Supply voltage
Input voltage (Except V and V
V
– 0.5 to +7.0
DD
)
V
V
– 0.5 to V + 0.5
V
PP1
PP6
IN
SS
DD
Input voltage
– Self-check mode (IRQ pin only)
V
V
– 0.5 to 2V + 0.5
V
IN
SS
DD
Operating temperature range
– Standard (MC68HC705B16)
– Extended (MC68HC705B16C)
– Industrial (MC68HC705B16V)
– Automotive (MC68HC705B16M)
T
T to T
0 to +70
–40 to +85
–40 to +105
–40 to +125
A
L
H
°C
°C
Storage temperature range
T
– 65 to +150
STG
(2)
Current drain per pin (excluding VDD and VSS)
– Source
– Sink
I
25
45
mA
mA
D
I
S
(1) All voltages are with respect to V .
SS
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either V or V
.
SS
DD
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-21
E.6
DC electrical characteristics
Table E-7 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
= +10 µA
V
V
—
—
—
V
LOAD
OH
DD
I
V
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.8
V – 0.4
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.8
V
– 0.4
OH
DD
DD
Output low voltage (I = 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
1
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.4
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
V
DD
V
V
IH
DD
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
V
—
0.2V
6
IL
SS
DD
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
5.0
1.0
1.5
0.9
mA
mA
mA
mA
DD
I
1.5
2
1
DD
I
DD
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
I
—
—
—
—
2
10
20
60
60
µA
µA
µA
µA
DD
I
—
—
—
DD
I
DD
I
DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
±0.2
80
±1
µA
µA
IL
Input current
Port B and port C pull-down (V =V )
I
RPD
IN IH
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
—
±0.2
±1
±5
µA
µA
IN
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
IN
Capacitance
Ports (as input or output), RESET, TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching
currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no
DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs;V = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = V DD
.
IL
WAIT IDD is affected linearly by the OSC2 capacitance.
14
TPG
MOTOROLA
E-22
MC68HC705B16
MC68HC05B6
Rev. 4
Table E-8 DC electrical characteristics for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0Vdc, T = T to T )
DD
SS
A
L
H
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.3
V – 0.1
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
Output low voltage (I = 1.6mA)
V
V
– 0.3
V
– 0.1
OH
DD
DD
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
0.6
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.2
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
Input low voltage
V
0.7V
V
DD
V
V
IH
DD
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
V
V
—
0.2V
DD
IL
SS
RESET, TCAP1, TCAP2, RDI
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
2.0
0.8
1.0
0.4
3
1
1.5
0.5
mA
mA
mA
mA
DD
I
DD
I
DD
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
I
—
—
—
—
1
10
10
40
40
µA
µA
µA
µA
DD
I
—
—
—
DD
I
DD
– 40 to 125 (automotive)
High-Z leakage current
I
DD
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
Input current
I
—
±0.2
80
±1
µA
µA
IL
Port B and port C pull-down (V =V )
I
RPD
IN IH
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
I
—
—
±0.2
±1
±5
µA
µA
IN
I
—
IN
Ports (as input or output), RESET,TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching
currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no
DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs;V = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = V DD
WAIT IDD is affected linearly by the OSC2 capacitance.
.
IL
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-23
E.7
A/D converter characteristics
Table E-9 A/D characteristics for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 0.5
± 0.5
± 1
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
(1)
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
Conversion time
—
—
32
32
t
CYC
µs
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
IN
RH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
—
—
12
12
t
CYC
(2)
b. Internal RC oscillator
µs
pF
µA
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
12
1
(3)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MOTOROLA
E-24
MC68HC705B16
MC68HC05B6
Rev. 4
Table E-10 A/D characteristics for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 1
± 1
± 2
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
Internal RC oscillator
Conversion time
—
32
µs
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
—
IN
RH
Sample acquisition time Analog input acquisition sampling
(1)
Internal RC oscillator
—
12
12
1
µs
pF
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
(2)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
µA
(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-25
E.8
Control timing
Table E-11 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
4.2
4.2
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
Cycle time (see Figure 9-1)
f
f
OP
dc
dc
2.1
2.1
—
MHz
MHz
ns
OP
t
480
—
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
A/D converter stabilization time
External RESET input pulse width
Power-on RESET output pulse width
4064 cycle
t
100
100
5
ms
OXOV
t
ms
ILCH
t
µs
ADRC
t
500
—
µs
ADON
t
1.5
t
RL
CYC
t
CYC
t
t
4064
16
—
—
PORL
t
CYC
16 cycle
PORL
DOGL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
10
10
10
10
—
—
—
—
ms
ms
ms
ms
ERA
– 40 to 85 (extended)
– 40 to 105 (industrial)
t
ERA
t
ERA
– 40 to 125 (automotive)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
t
10
10
15
20
—
—
—
—
ms
ms
ms
ms
PROG
t
PROG
– 40 to 105 (industrial)
– 40 to 125 (automotive)
Timer (see Figure E-11)
t
PROG
t
PROG
(2)
Resolution
t
4
—
—
—
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
TH TL
(3)
t
—
TLTL
t
125
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
90
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to
ILIL
execute the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 238ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MOTOROLA
E-26
MC68HC705B16
MC68HC05B6
Rev. 4
Table E-12 Control timing for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
2.0
2.0
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
—
dc
1.0
1.0
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
1000
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
1.5
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
4064
16
—
—
PORL
t
CYC
t
PORL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
DOGL
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
30
30
30
30
—
—
—
—
ms
ms
ms
ms
ERA
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
t
ERA
t
ERA
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
t
30
30
30
30
—
—
—
—
ms
ms
ms
ms
PROG
t
PROG
t
PROG
t
PROG
Timer (see Figure E-11)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
250
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
250
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
200
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 500ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16
MOTOROLA
E-27
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure E-11 Timer relationship
E.9
EPROM electrical characteristics
Table E-13 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
(1)
(2)
Characteristic
Symbol
max
Min
Typ
Max
Unit
EPROM
Absolute maximum voltage
Programming voltage
Programming current
Read voltage
V
V
—
15.5
50
18
16
64
V
V
mA
V
PP6
DD
V
15
—
PP6
I
PP6
V
V
V
V
PP6R
DD
DD
DD
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
Table E-14 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
Table E-15 Control timing for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
14
TPG
MOTOROLA
E-28
MC68HC705B16
MC68HC05B6
Rev. 4
F
MC68HC705B16N
The MC68HC705B16N is a new device identical to the MC68HC705B16 in its memory
map and functionality, except for the following:
•
•
•
•
Bootloader
Reset pulse width
Reset twice issue
Electrical characteristics
On the MC68HC705B16 there was a requirement to reset the device a second time
after power-on. On the MC68HC705B16N this reset twice action is now not required.
The interrupt service routine for the vector at address $3FF0–$3FF1 is no longer
required, as the vector will never be fetched. However, the interrupt service routine and
vector contents required for the MC68HC705B16 (see Section E, page E–1) can also
be kept on the MC68HC705B16N with no detrimental effect, although they will never
be used.
The MC68HC705B16N is a device similar to the MC68HC05B6, but with increased RAM and
15 kbytes of EPROM instead of 6 kbytes of ROM. In addition, the self-check routines available in
the MC68HC05B6 are replaced by bootstrap firmware. The MC68HC705B16N is an OTPROM
(one-time programmable ROM) version of the MC68HC05B16, meaning that once the application
program has been loaded in the EPROM it can never be erased. The entire MC68HC05B6 data
sheet applies to the MC68HC705B16N, with the exceptions outlined in this appendix.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-1
F.1
Features
•
•
•
•
•
•
15 kbytes EPROM
352 bytes of RAM
576 bytes bootstrap ROM
Simultaneous programming of up to 8 bytes of EPROM
Optional pull-down resistors available on all port B and port C pins
52-pin PLCC and 64-pin QFP packages
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
VPP1
VPP6
Charge pump
576 bytes
bootstrap ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
15168 bytes
EPROM
RESET
IRQ
COP watchdog
PC0
PC1
PC2/ECLK
PC3
PC4
OSC2
OSC1
Oscillator
352 bytes
static RAM
÷ 2 /÷ 32
PC5
PC6
PC7
M68HC05
CPU
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure F-1 MC68HC705B16N block diagram
Note:
The electrical characteristics of the MC68HC05B6 as provided in Section 11 do not
apply to the MC68HC705B16N. Data specific to the MC68HC705B16N can be found in
this appendix.
14
TPG
MOTOROLA
F-2
MC68HC705B16N
MC68HC05B6
Rev. 4
MC68HC705B16
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
E/EEPROM/ECLK control register
A/D data register
$0020
$0050
Page 0 User
EPROM
(48 bytes)
RAM1
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
Options register
Unprotected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
$0250
Bootstrap ROM1
(80 bytes)
Timer control register
Timer status register
RAM11
(176 bytes)
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$0300
User EPROM
(15104 bytes)
$3DFE
$3DFF
$3E00
Mask option register
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
Bootstrap ROM11
(496 bytes)
$3FF0–1
$3FF2–3
$3FF4–5
SCI
Timer overflow
$3FF6–7 Timer output compare 1& 2
$3FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
Options register
$0100
$3FFA–B
$3FFC–D
External IRQ
SWI
Mask option register
$3DFE
Reserved
$3FFE–F Reset/power-on reset
Figure F-2 Memory map of the MC68HC705B16N
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-3
Table F-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EPROM/EEPROM/ECLK control
A/D data (ADDATA)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
0000 0000
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(4)
Mask option register (MOR)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
F-4
MC68HC705B16N
MC68HC05B6
Rev. 4
F.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see
Figure D-2). The t or t specifications (see Section F.9) do not apply when using an
OXOV
ILCH
external clock input. The equivalent specification of the external clock source should be used in
lieu of t
or t
.
OXOV
ILCH
F.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 3.0 machine cycles (tCYC). For more information see
Section 9.1.3.
F.4
EPROM
The MC68HC705B16N memory map is given in Figure F-2.The device has a total of 15168 bytes
of EPROM (including 14 bytes for User vectors) and 256 bytes of EEPROM.
The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the
user’s software would be loaded into a programming board where V
is controlled by one of the
PP6
bootstrap loader routines. It would then be placed in an application where no programming occurs.
In this case the VPP6 pin should be hardwired to V
.
DD
Warning: A minimum V
voltage must be applied to the VPP6 pin at all times, including
DD
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature
only.
F.4.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read
operations.The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’ which
automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading
the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory
content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,
the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin
must be at the V level. When entering the STOP mode, the EPROM is automatically set to the
DD
read mode.
14
Note:
An erased byte reads as $00.
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-5
F.4.2
EPROM program operation
Typically the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.
However, the user program can be used to program some EPROM locations if the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
EPROM will not be available for code execution while the E6LAT bit is set.TheV
switching must
PP6
occur externally after the E6PGM bit is set, for example under control of a signal generated on a
pin by the programming routine.
Note:
When the part becomes a PROM, only the cumulative programming of bits to logic ‘1’
is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to eight bytes, these bytes must be in the same group
of addresses which share the same most significant address bits; only the three least significant
bits can change.
F.4.3
EPROM/EEPROM/ECLK control register
State
on reset
Address bit 7
$0007
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EPROM/EEPROM/ECLK control
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM 0000 0000
E6LAT — EPROM programming latch enable bit
1 (set)
–
Address and up to eight data bytes can be latched into the EPROM
for further programming providing the E6PGM bit is cleared.
0 (clear) – Data can be read from the EPROM or firmware ROM; the E6PGM bit
is reset to zero when E6LAT is ‘0’.
STOP, power-on and external reset clear the E6LAT bit.
Note:
After the t
erase time or t
programming time, the E6LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E6PGM bit.
E6PGM — EPROM program enable bit
This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after
E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using
software but clearing E6LAT will always clear E6PGM.
Note:
The E6PGM bit can never be set while the E6LAT bit is at zero.
14
TPG
MOTOROLA
F-6
MC68HC705B16N
MC68HC05B6
Rev. 4
Table F-2 EPROM control bits description
E6LAT E6PGM
Description
Read/execute in EPROM
0
1
1
0
0
1
Ready to write address/data to EPROM
programming in progress
ECLK
See Section 4.3.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
E1LAT — EEPROM programming latch enable bit
1 (set)
–
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
erase time or t
programming time, the E1LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) Internal charge pump generator switched on.
–
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table F-3.
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-7
Table F-3 EEPROM control bits description
E1ERA E1LAT E1PGM
Description
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
Read condition
Ready to load address/data for program/erase
Byte programming in progress
Ready for byte erase (load address)
Byte erase in progress
F.4.4
Mask option register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Mask option register (MOR)
$3DFE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
RTIM — Reset time
This bit can modify the time t
, where the RESET pin is kept low after a power-on reset.
PORL
1 (set)
–
t
t
= 16 cycles.
PORL
PORL
0 (clear) –
= 4064 cycles.
RWAT — Watchdog after reset
This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system
is disabled after power-on or external reset but when this bit is set, it will be active immediately
after the following resets (except in bootstrap mode).
WWAT — Watchdog during WAIT mode
This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog
system is disabled inWAIT mode but when this bit is set, the watchdog will be active inWAIT mode.
PBPD — Port B pull-down
This bit, when programmed, connects a resistive pull-down on each pin of port B. This pull-down,
R
, is active on a given pin only while it is an input.
PD
14
TPG
MOTOROLA
F-8
MC68HC705B16N
MC68HC05B6
Rev. 4
PCPD — Port C pull-down
This bit, when programmed, connects a resistive pull-down on each pin of port C.This pull-down,
R
, is active on a given pin only while it is an input.
PD
F.4.5
EEPROM options register (OPTR)
State
on reset
Address bit 7
$0100
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Options (OPTR)
EE1P SEC Not affected
(1) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
in the options register.
1 (set)
–
Part 2 of the EEPROM array is not protected; all 256 bytes of
EEPROM can be accessed for any read, erase or programming
operations.
0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful.
When this bit is set to 1 (erased), the protection will remain until the next power-on or external
reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.
Note:
The EEPROM1 protect function is disabled while in bootstrap mode.
SEC — Secure bit
This bit allows the EPROM and EEPROM1 to be secured from external access.When this bit is in
the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be
used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1
content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the
EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be
entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its
new value will have no effect until the next power-on or external reset.
1 (set)
–
EEPROM/EPROM not protected.
0 (clear) – EEPROM/EPROM protected.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-9
F.5
Bootstrap mode
Oscillator divide-by-two is forced in bootstrap mode.
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 576 bytes of bootstrap
firmware. A detailed description of the modes of operation within bootstrap mode is given below.
The bootstrap program in mask ROM address locations $0200 to $024F and $3E00 to $3FEF can
be used to program the EPROM and the EEPROM, to check if the EPROM is erased or to load
and execute data in RAM.
After reset, while going to the bootstrap mode, the vector located at address $3FEE and $3FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the IRQ pin should be at 2xV with the TCAP1 pin ‘high’ during transition of the RESET
DD
pin from low to high.The hold time on the IRQ andTCAP1 pins is two clock cycles after the external
RESET pin is brought high.
When the MC68HC705B16N is placed in the bootstrap mode, the bootstrap reset vector will be
fetched and the bootstrap firmware will start to execute. Table F-4 shows the conditions required
to enter each level of bootstrap mode on the rising edge of RESET.
Table F-4 Mode of operation selection
IRQ pin
to V
TCAP1 pin PD1 PD2 PD3 PD4
Mode
V
V
to V
DD
x
0
0
x
0
0
x
0
1
x
0
0
Single chip
SS
DD
SS
2xV
V
Erased EPROM verification
EPROMverification;
DD
DD
2xV
V
DD
DD
EPROM verification; erase EEPROM;
EPROM/EEPROM parallel program/verify
2xV
V
1
0
0
0
DD
DD
Erased EPROM verification; erase EEPROM;
EPROM parallel program/verify (no E )
2xV
V
1
1
x
0
0
0
1
0
1
0
1
1
2
DD
DD
2xV
V
Jump to start of RAM ($0051); SEC bit = NON ACTIVE
DD
DD
Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I
and II
2xV
V
DD
DD
x = Don’t care
The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM. It will then
set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low.This
can be used to distinguish between the two circuits and, in particular, for selection of the VPP level
and current capability.
14
TPG
MOTOROLA
F-10
MC68HC705B16N
MC68HC05B6
Rev. 4
Reset
N
N
Y
IRQ at 2xV
?
?
User mode
DD
Y
Y
N
TCAP1=V
Y
SEC bit active?
Non-user mode
DD
PD4 set?
N
Y
Y
Y
Y
PD2 set?
N
SEC bit active?
N
Non-user mode
Red LED on
N
Y
Non-user mode
PD3 set?
Y
PD2 set?
N
Erased EPROM
verification
Serial RAM
load/execute
PD1 set?
N
PD3 set?
N
Y
Jump to RAM
($0051)
SEC bit active?
N
Red LED on
N
EPROM verify
Verify EPROM
EPROM erased?
Y
Red LED on
Erased EPROM verification
N
Green LED on
Y
EPROM
verified?
Red LED on
Y
N
PD1 set?
Green LED on
Y
D
14
Figure F-3 Modes of operation flow chart (1 of 2)
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-11
D
EEPROM byte
erase and verify
N
EEPROM erased?
Y
Parallel program
and verify
N
PD3 set?
Y
Go to $300
Go to $100
(EPROM only)
(EPROMandEEPROM)
Parallel program
N
Data verified?
Y
Red LED on
Green LED on
14
Figure F-4 Modes of operation flow chart (2 of 2)
TPG
MOTOROLA
F-12
MC68HC705B16N
MC68HC05B6
Rev. 4
F.5.1
Erased EPROM verification
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure F-3
and Figure F-4). Only when the whole EPROM content is verified as erased will the green LED be
turned on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming
occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program
proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked
for complete erasure; if any EEPROM byte is not erased, the program will stop before erasing the
SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is
cleared the programming operation can be performed. A schematic diagram of the circuit required
for erased EPROM verification is shown in Figure F-8.
F.5.2
EPROM/EEPROM parallel bootstrap
Within this mode there are various subsections which can be utilised by correctly configuring the
port pins shown in Table F-4.
The erased EPROM verification program will be executed first as described in Section F.5.1. The
EPROM programming time is set to 10 milliseconds with the bootstrap program and verify for the
EPROM taking approximately 15 seconds.The EPROM will be loaded in increasing address order
with non EPROM segments being skipped by the loader. Simultaneous programming is performed
by reading eight bytes of data before actual programming is performed, thus dividing the loading
time of the internal EPROM by 8. If any block of 8 EPROM bytes or 1 EEPROM byte of data is in
the erased state, no programming takes place, thus speeding up the execution time.
Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4
and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,
handshake will be provided by PC5 and PC6 according to the timing diagram of Figure F-6 (see
also Figure F-7).
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the EPROM and EEPROM1 content will be
checked against the external data source. If programming is verified the green LED will stay on,
while an error will cause the red LED to be turned on. Figure F-7 is a schematic diagram of a circuit
which can be used to program the EPROM or to load and execute data in the RAM.
Note:
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all $00s
for EPROM data and all $FFs for EEPROM1 data.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-13
Address
HDSK out
(PC5)
Data
HDSK in
(PC6)
F29
Data read
Data read
Figure F-5 Timing diagram with handshake
t
t
t
t
CDDE
COOE
COOE
COOE
Address
t
t
t
t
ADE
ADE
ADE
ADE
t
t
t
t
DHE
DHE
DHE
DHE
Data
t
max (address to data delay)
min (data hold time)
5 machine cycles
14 machine cycles
ADE
t
DHA
t
(load cycle time)
117 machine cycles < t
< 150 machine cycles
COOE
COOE
t
(programming cycle time)
t
+ t (10 ms nominal for EPROM; 10ms for EEPROM1))
CDDE
COOE PROG
1 machine cycle = 1/(2f (Xtal))
0
Figure F-6 Parallel EPROM loader timing diagram
14
TPG
MOTOROLA
F-14
MC68HC705B16N
MC68HC05B6
Rev. 4
P1
1
2
3
GND
+5V
RESET
RUN
1N914
+
100µF
V
PP
100kΩ
1N914
1kΩ
TCAP1 VRH VDD
47µF
+
1.0µF
+
IRQ
OSC1
OSC2
RESET
EPROM verify
4.0 MHz
22pF
NC
RDI
VRL
TCAP2
PD7
PD6
PD5
red LED
Erase check
& boot
(EPROM only)
TCMP1
VPP1
PLMA
PLMB
470Ω
22pF
0.01µF
470Ω
green LED
Erase verify & boot
Boot
Erase check &
boot (EPROM
& EEPROM)
red LED — programming failed
green LED — programming OK
PD3
PD2
PD1
PD0
EPROM
check
Erase check
green LED — EPROM erased
red LED — EPROM not erased
MC68HC705B16N
MCU
+5V
28
PD4
EPROM
1 kΩ
1
27
VPP PGM VCC
SCLK
TDO
TCMP2
A14
10k Ω
26
10
A13
VPP6
12 kΩ
A0
A1
A2
A3
A4
PB0
PB1
9
8
7
6
5
4
3
4k7Ω
PB2
PB3
PB4
PB5
PB6
PB7
PC7
+
BC239C
1nF
4k7Ω
20
CE
A5
A6
A7
27C256
+5V
100 kΩ
11
12
13
15
16
17
18
19
HDSK out
Short circuit if
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PC6
handshake not used
25
24
21
23
2
A8
A9
A10
A11
A12
HDSK in
A12
PC4
PC3
PC2
PC1
PC0
A11
A10
A9
A8
VSS
GND
14
OE
22
Note:
This circuit is recommended for programming only at 25°C and not for use in the
end application, or at temperatures other than 25°C. If used in the end application,
VPP6 should be tied to VDD to avoid damaging the device.
14
Figure F-7 EPROM parallel bootstrap schematic diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-15
F.5.3
Serial RAM loader
This mode is similar to the RAM load/execute program for the MC68HC05B6 described in
Section 2.2, with the additional features listed below. Table F-4 shows the entry conditions
required for this mode.
If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count
byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)
then the code continues to fill RAM II. In this case the count byte is ignored and the program
execution begins at $0051 once the total RAM area is filled or if no data is received for 5
milliseconds.
The user must take care when using branches or jumps as his code will be relocated in RAM I and
II. If the user intends to use the stack in his program, he should send NOP’s to fill the desired stack
area.
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table F-5). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the users
service-routine address.
Table F-5 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
$0063
$0060
$005D
$005A
$0057
$0054
SWI
F.5.3.1
Jump to start of RAM ($0051)
The Jump to start of RAM program will be executed when the device is brought out of reset with
PD1 and PD4 at ‘1’ and PD2 and PD3 at ‘0’.
14
TPG
MOTOROLA
F-16
MC68HC705B16N
MC68HC05B6
Rev. 4
P1
1
2
3
GND
+5V
V
PP
RESET
RUN
10nF
+
100kΩ
1kΩ
1N914
47µF
22
8
10
TCAP1 VRH VDD
1.0µF
1N914
19
+
IRQ
47µF
+
18 RESET
OSC1
OSC2
Red LED
470Ω
470Ω
0.01µF
20
PLMA
4.0 MHz
22pF
22pF
21
PLMB
Green LED
RAM load
& execute
PD3
Jump to $51
Erase check
Green LED — EPROM erased
Red LED — EPROM not erased
MC68HC705B16N
MCU (socket)
Serial boot
PD4
1 kΩ
Serial boot
Flashing green LED — programming
Green LED — programming ended
39
38
37
36
35
34
33
32
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10k Ω
VPP6
12 kΩ
4k7Ω
PC7
+
BC239C
1nF
4k7Ω
31
30
29
28
27
26
25
24
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Serial RAM
load & execute
43
44
45
46
47
48
49
PC6
PC5
PC4
PC3
PC2
PC1
PC0
9600 BD
8-bit
no parity
14
13
12
5
4
3
22µF
+5V
PD0
PD1
PD2
PD5
PD6
PD7
+
16
2 x 3KΩ
22µF
8
5
7
3
2
1
1
2
+
22µF
3
VPP1
TCAP2
TCMP1
TCMP2
SCLK
4
+
MAX
232
RS232
Connector
23
2
1
51
40
6
+
22µF
5
50
52
13
14
12
11
RDI
TDO
15
NC
VSS
41
VRL
7
Note:
A minimum V
voltage must be applied to the VPP6 pin at all times,
DD
including power-on, as a lower voltage could damage the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C)
temperature only
14
Figure F-8 RAM load and execute schematic diagram
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-17
t
CR
Address
PC5 out
t
HO
t
ADR
t
DHR
Data
t
max
HI
PC6 in
PD4
t
max
EXR
t
max (address to data delay; PC6=PC5)
min (data hold time)
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
ADR
t
DHR
t
(load cycle time; PC6=PC5)
(PC5 handshake out delay)
CR
t
HO
t
max (PC6 handshake in, data hold time)
HI
t
max (max delay for transition to be recognised during this cycle; PC6=PC5
EXR
1 machine cycle = 1/(2f (Xtal))
0
Figure F-9 Parallel RAM loader timing diagram
14
TPG
MOTOROLA
F-18
MC68HC705B16N
MC68HC05B6
Rev. 4
F.6
Absolute maximum ratings
Table F-6 Absolute maximum ratings
Rating
Symbol
Value
Unit
V
(1)
Supply voltage
Input voltage (Except V and V
V
– 0.5 to +7.0
DD
)
V
V
– 0.5 to V + 0.5
V
PP1
PP6
IN
SS
DD
Input voltage
– Self-check mode (IRQ pin only)
V
V
– 0.5 to 2V + 0.5
V
IN
SS
DD
Operating temperature range
T
T to T
A
L
H
– Standard (MC68HC705B16N)
– Extended (MC68HC705B16NC)
– Industrial (MC68HC705B16NV)
0 to +70
–40 to +85
–40 to +105
–40 to +125
°C
°C
– Automotive (MC68HC705B16NM)
Storage temperature range
T
– 65 to +150
STG
(2)
Current drain per pin (excluding VDD and VSS)
– Source
– Sink
I
25
45
mA
mA
D
I
S
(1) All voltages are with respect to V .
SS
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either V or V
.
SS
DD
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-19
F.7
DC electrical characteristics
Table F-7 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
= +10 µA
V
V
—
—
—
V
LOAD
OH
DD
I
V
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.8
V – 0.4
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.8
V
– 0.4
OH
DD
DD
Output low voltage (I = 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
1
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.4
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
V
DD
V
V
IH
DD
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
V
—
0.2V
6
IL
SS
DD
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11.2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
5.0
1.0
1.5
0.9
mA
mA
mA
mA
DD
I
1.5
2
1
DD
I
DD
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
I
—
—
—
—
2
10
20
60
µA
µA
µA
µA
DD
I
—
—
—
DD
I
DD
I
100
DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
±0.2
80
±1
µA
µA
IL
Input current
Port B and port C pull-down (V =V )
I
RPD
IN IH
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
—
±0.2
±1
±5
µA
µA
IN
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
IN
Capacitance
Ports (as input or output), RESET, TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching
currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 4.2MHz); all inputs 0.2 V from rail; no
DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs;V = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = V DD
.
IL
WAIT IDD is affected linearly by the OSC2 capacitance.
14
TPG
MOTOROLA
F-20
MC68HC705B16N
MC68HC05B6
Rev. 4
Table F-8 DC electrical characteristics for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0Vdc, T = T to T )
DD
SS
A
L
H
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.3
V – 0.1
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
Output low voltage (I = 1.6mA)
V
V
– 0.3
V
– 0.1
OH
DD
DD
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
0.6
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.2
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
Input low voltage
V
0.7V
V
DD
V
V
IH
DD
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
V
V
—
0.2V
DD
IL
SS
RESET, TCAP1, TCAP2, RDI
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
2.0
0.8
1.0
0.4
3
1
1.5
0.5
mA
mA
mA
mA
DD
I
DD
I
DD
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
I
—
—
—
—
1
10
10
40
60
µA
µA
µA
µA
DD
I
—
—
—
DD
I
DD
– 40 to 125 (automotive)
High-Z leakage current
I
DD
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
Input current
I
—
±0.2
80
±1
µA
µA
IL
Port B and port C pull-down (V =V )
I
RPD
IN IH
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Capacitance
I
—
—
±0.2
±1
±5
µA
µA
IN
I
—
IN
Ports (as input or output), RESET,TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching
currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0MHz); all inputs 0.2 V from rail; no
DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT IDD: all ports configured as inputs;V = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = V DD
WAIT IDD is affected linearly by the OSC2 capacitance.
.
IL
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-21
F.8
A/D converter characteristics
Table F-9 A/D characteristics for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 0.5
± 0.5
± 1
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
(1)
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
Conversion time
—
—
32
32
t
CYC
µs
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
IN
RH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
—
—
12
12
t
CYC
(2)
b. Internal RC oscillator
µs
pF
µA
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
12
1
(3)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MOTOROLA
F-22
MC68HC705B16N
MC68HC05B6
Rev. 4
Table F-10 A/D characteristics for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 1
± 1
± 2
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
Internal RC oscillator
Conversion time
—
32
µs
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
—
IN
RH
Sample acquisition time Analog input acquisition sampling
(1)
Internal RC oscillator
—
12
12
1
µs
pF
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
(2)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
µA
(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-23
F.9
Control timing
Table F-11 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
4.2
4.2
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
Cycle time (see Figure 9-1)
f
f
OP
dc
dc
2.1
2.1
—
MHz
MHz
ns
OP
t
480
—
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
A/D converter stabilization time
External RESET input pulse width
Power-on RESET output pulse width
4064 cycle
t
100
100
5
ms
OXOV
t
ms
ILCH
t
µs
ADRC
t
500
—
µs
ADON
t
3.0
t
RL
CYC
t
CYC
t
t
4064
16
—
—
PORL
t
CYC
16 cycle
PORL
DOGL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
10
10
10
10
—
—
—
—
ms
ms
ms
ms
ERA
– 40 to 85 (extended)
– 40 to 105 (industrial)
t
ERA
t
ERA
– 40 to 125 (automotive)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
t
10
10
15
20
—
—
—
—
ms
ms
ms
ms
PROG
t
PROG
– 40 to 105 (industrial)
– 40 to 125 (automotive)
Timer (see Figure F-10)
t
PROG
t
PROG
(2)
Resolution
t
4
—
—
—
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
TH TL
(3)
t
—
TLTL
t
125
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
90
ns
OH OL
(6)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 238ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MOTOROLA
F-24
MC68HC705B16N
MC68HC05B6
Rev. 4
Table F-12 Control timing for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0 Vdc, T = T to T )
DD
SS
A
L
H
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
2.0
2.0
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
—
dc
1.0
1.0
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
1000
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
3.0
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
4064
16
—
—
PORL
t
CYC
t
PORL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
DOGL
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
30
30
30
30
—
—
—
—
ms
ms
ms
ms
ERA
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
t
ERA
t
ERA
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
– 40 to 105 (industrial)
– 40 to 125 (automotive)
t
30
30
30
30
—
—
—
—
ms
ms
ms
ms
PROG
t
PROG
t
PROG
t
PROG
Timer (see Figure F-10)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
250
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
250
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
200
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 500ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B16N
MOTOROLA
F-25
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure F-10 Timer relationship
F.10
EPROM electrical characteristics
Table F-13 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
(1)
(2)
Characteristic
Symbol
max
Min
Typ
Max
Unit
EPROM
Absolute maximum voltage
Programming voltage
Programming current
Read voltage
V
V
—
15.5
50
18
16
64
V
V
mA
V
PP6
DD
V
15
—
PP6
I
PP6
V
V
V
V
PP6R
DD
DD
DD
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
Table F-14 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
Table F-15 Control timing for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
14
TPG
MOTOROLA
F-26
MC68HC705B16N
MC68HC05B6
Rev. 4
G
MC68HC05B32
The MC68HC05B32 is a device similar to the MC68HC05B6, but with increased RAM and ROM
sizes. The entire MC68HC05B6 data sheet applies to the MC68HC05B32, with the exceptions
outlined in this appendix.
G.1
Features
•
•
•
•
31248 bytes User ROM
No page zero ROM
528 bytes of RAM
52-pin PLCC and 64-pin QFP packages for -40 to +85°C operating temperature range
(extended)
•
•
56-pin SDIP package for 0 to 70°C operating temperature range
High speed version not available
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B32
MOTOROLA
G-1
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
VPP1
VPP6
Charge pump
638 bytes
self-check ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
32 kbytes
ROM
RESET
IRQ
COP watchdog
PC0
PC1
PC2/ECLK
PC3
PC4
OSC2
OSC1
Oscillator
528 bytes
static RAM
÷ 2 /÷32
PC5
PC6
PC7
M68HC05
CPU
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure G-1 MC68HC05B32 block diagram
Note:
Preliminary electrical specifications for the MC68HC05B32 should be taken as being
similar to those for the MC68HC705B32. When silicon is fully available, the part will be
re-characterised and new data made available.
G.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see
Figure D-2). The t or t specifications (see Section H.9) do not apply when using an
OXOV
ILCH
external clock input. The equivalent specification of the external clock source should be used in
lieu of t or t
.
ILCH
OXOV
14
TPG
MOTOROLA
G-2
MC68HC05B32
MC68HC05B6
Rev. 4
MC68HC05B32
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
EEPROM/ECLK control register
A/D data register
$0020
$0050
RAMI
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
Options register
Unprotected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
$0250
$03B0
$0400
Timer control register
Bootloader ROMI
(80 bytes)
Timer status register
RAMII
(352 bytes)
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
Bootloader ROMII
(80 bytes)
User ROM
(31232 bytes)
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
$7E00
$7FDE
Bootloader ROMIII
(478 bytes)
$7FE0
$7FF0
Bootloader ROM vectors
(16 bytes)
Options register
$0100
$7FF2–3
$7FF4–5
SCI
Timer overflow
$7FF6–7 Timer output compare 1& 2
$7FF8–9 Timer input capture 1 & 2
User vectors
(14 bytes)
$7FFA–B
$7FFC–D
External IRQ
SWI
Reserved
$7FFE–F Reset/power-on reset
Figure G-2 Memory map of the MC68HC05B32
14
TPG
MC68HC05B6
Rev. 4
MC68HC05B32
MOTOROLA
G-3
Table G-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EEPROM/ECLK control
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
0
0
0
0
ECLK E1ERA E1LAT E1PGM 0000 0000
A/D data (ADDATA)
0000 0000
CH3 CH2 CH1 CH0 0000 0000
0000 0000
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(4)
Mask option register (MOR)
$7FDE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1 = watchdog enabled, 0 = watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in ROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
G-4
MC68HC05B32
MC68HC05B6
Rev. 4
H
MC68HC705B32
Maskset errata
This errata section outlines the differences between two previously available masksets
(D59J and D40J) and all other masksets. Unless otherwise stated, the main body of
Appendix G refers to all these other masksets with any differences being noted in this
errata section.
•
For the D59J and D40J masksets, the MCU only requires that a logic zero is
applied to the RESET input for 1.5 t
.
CYC
•
•
For D59J, 16 cycle POR delay option (t
) is not available
PORL
For the D59J maskset, oscillator divide ratio DIV10 is forced in Bootstrap mode.On
all other revisions DIV2 is forced.
For the D59J:
The STOP Idd is greater than the expected value of 120µA at 5 volts Vdd at a
temperature of 20°C with the CAN module enabled and in SLEEP mode.Typically the
STOP Idd is in the region of 2.0 milliamps at 20°C.
The fault lies with the design of the EPROM array. When the STOP instruction is
executed, the next opcode in memory is present on the data bus. A fault in the EPROM
write data latch circuitry causes a latch to be driven to logic 0 on both sides when the
data bus for that bit is logic 1. This results in increasing STOP Idd of 450µA per data
bus bit set to a logic 1. If all data bus bits are set to logic 1 (i.e. next opcode is $FF, STX
0,X) the STOP Idd shall be in the region of 3.6mA.
The minimum STOP Idd is achieved by ensuring the opcode immediately following the
STOP instruction is data $00. This corresponds to BRSET 0,ADDRESS,LABEL. If the
label points to the next sequential instruction in memory then this has the effect of a 5
cycle NOP but note that the carry bit in the condition code register may be altered by
the BRSET instruction.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-1
Example
STOP
BRSET 0,$00,NEXT
NEXT any CPU instruction
The address compared may be any address in the page zero memory and the only
restriction is that it should not be a register with flags cleared by reading the register.
The example shows the address compared to be port A data register and this should
not cause any problems in any applications.
High STOP Idd will be variable dependant upon the opcode following the STOP
instruction. The more bits set in the following opcode, the higher the STOP Idd. The
work around described above may be used on any 68HC05B32 or corrected version of
the 68HC705B32 without problem. It simply adds a 5 cycle delay to the recovery from
STOP and 3 bytes of additional code per STOP instruction but may alter the state of the
carry bit in the CCR.
Also for the D59J:
The EEPROM programming circuit only fully supports 16-byte simultaneous
programming mode and does not support single byte programming correctly.
The fault lies with the design of the EPROM array. A fault in the EPROM write data latch
circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that
bit is logic 1.When the ELAT signal is removed, there is a race condition with the EPBS
signal which results in the data bus value being copied to all the EPROM latches.
Since 16-byte simultaneous programming functions correctly, it is a relatively simple
matter to emulate single byte programming by first initialising all 16 data latches to $00
and then writing the data to be written to the appropriate address.
This problem does not affect user application software in normally circumstances since
it only applies to programming the EPROM array. The serial programming software
should always simulate 16-byte programming. The Motorola software for programming
the 705B32 from an IBM compatible PC functions in 16 byte programming mode. This
program therefore correctly programs the EPROM.
In normal circumstances this errata does not affect the user application software. This
only affects software that programs the EPROM array. The parallel programming
bootloader software within the 705B32 ROM performs 16-byte programming and so
functions correctly.
14
TPG
MOTOROLA
H-2
MC68HC705B32
MC68HC05B6
Rev. 4
The MC68HC705B32 is an EPROM version of the MC68HC05B32, with the ROM replaced by a
similar amount of EPROM. The entire MC68HC05B6 data sheet applies to the MC68HC705B32,
with the exceptions outlined in this appendix.
H.1
Features
•
•
•
•
•
•
•
•
31246 bytes user EPROM
No page zero EPROM at $20–$4F
528 bytes of RAM
638 bytes bootstrap ROM instead of 432 bytes of self-check ROM
Simultaneous programming of EPROM with up to 16 bytes of different data
-40 to +85°C operating temperature range (extended)
52-pin PLCC, 56-pin SDIP and 64-pin QFP packages
High speed version not available
Note:
The electrical characteristics from the MC68HC05B6 data sheet should not be used for
the MC68HC705B32. Data specific to this device can be found in Section H.7 and
Section H.9.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-3
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
256 bytes
EEPROM
VPP1
VPP6
Charge pump
638 bytes
bootstrap ROM
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
32 kbytes
EPROM
RESET
IRQ
COP watchdog
PC0
PC1
PC2/ECLK
PC3
PC4
OSC2
OSC1
Oscillator
528 bytes
static RAM
÷ 2 /÷32
PC5
PC6
PC7
M68HC05
CPU
VDD
VSS
TCMP1
TCMP2
TCAP1
TCAP2
16-bit
timer
PD0/AN0
PD1/AN1
PD2/AN2
PD3/AN3
PD4/AN4
PD5/AN5
PD6/AN6
PD7/AN7
VRH
RDI
SCLK
TDO
8-bit
A/D converter
SCI
PLMA D/A
PLMB D/A
PLM
VRL
Figure H-1 MC68HC705B32 block diagram
14
TPG
MOTOROLA
H-4
MC68HC705B32
MC68HC05B6
Rev. 4
MC68HC705B32
Registers
$0000
$0000
$0001
$0002
$0003
$0004
$0005
$0006
$0007
$0008
$0009
$000A
$000B
$000C
$000D
$000E
$000F
$0010
$0011
$0012
$0013
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
Port A data register
Port B data register
I/O
(32 bytes)
Port C data register
Port D input data register
Port A data direction register
Port B data direction register
Port C data direction register
E/EEPROM/ECLK control register
A/D data register
$0020
$0050
RAM1
(176 bytes)
A/D status/control register
Pulse length modulation A
Pulse length modulation B
Miscellaneous register
SCI baud rate register
SCI control register 1
$00C0
Stack
$0100
$0101
Options register
Unprotected (31 bytes)
$0120
EEPROM
(256 bytes)
SCI control register 2
SCI status register
Protected (224 bytes)
SCI data register
$0200
$0250
Bootstrap ROMI
(80 bytes)
Timer control register
Timer status register
RAM11
(352 bytes)
Capture high register 1
Capture low register 1
Compare high register 1
Compare low register 1
Counter high register
$03B0
$0400
Bootstrap ROMII
(80 bytes)
User EPROM
(31232 bytes)
Counter low register
Alternate counter high register
Alternate counter low register
Capture high register 2
Capture low register 2
Compare high register 2
Compare low register 2
$7E00
Bootstrap ROMIII
(478 bytes)
Mask option register
$7FDE
$7FDF
$7FE0
Bootstrap ROM vectors
(16 bytes)
$7FF0–1
$7FF2–3
$7FF4–5
SCI
Timer overflow
Options register
$0100
Mask option register
$7FDE
$7FF6–7 Timer output compare 1& 2
$7FF8–9 Timer input capture 1 & 2
$7FFA–B
$7FFC–D
User vectors
(14 bytes)
External IRQ
SWI
$7FFE–F Reset/power-on reset
Reserved
Figure H-2 Memory map of the MC68HC705B32
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-5
Table H-1 Register outline
State on
reset
Register name
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Port A data (PORTA)
Port B data (PORTB)
Port C data (PORTC)
$0000
$0001
$0002
Undefined
Undefined
Undefined
PC2/
ECLK
Port D data (PORTD)
Port A data direction (DDRA)
Port B data direction (DDRB)
Port C data direction (DDRC)
EPROM/EEPROM/ECLK control
A/D data (ADDATA)
$0003 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Undefined
$0004
$0005
$0006
$0007
$0008
0000 0000
0000 0000
0000 0000
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000
0000 0000
0
A/D status/control (ADSTAT)
$0009 COCO ADRC ADON
0
CH3 CH2 CH1 CH0 0000 0000
0000 0000
Pulse length modulation A (PLMA) $000A
Pulse length modulation B (PLMB) $000B
0000 0000
(1)
(2)
Miscellaneous
$000C POR
INTP INTN INTE SFA SFB
SM WDOG
?001 000?
SCI baud rate (BAUD)
SCI control 1 (SCCR1)
SCI control 2 (SCCR2)
SCI status (SCSR)
SCI data (SCDR)
$000D SPC1 SPC0 SCT1 SCT0 SCT0 SCR2 SCR1 SCR0 00uu uuuu
$000E
$000F
R8
T8
M
WAKE CPOL CPHA LBCL Undefined
TIE
TCIE RIE
ILIE
TE
RE RWU SBK 0000 0000
$0010 TDRE TC RDRF IDLE
$0011
OR
NF
FE
1100 000u
0000 0000
Timer control (TCR)
Timer status (TSR)
Input capture high 1
Input capture low 1
Output compare high 1
Output compare low 1
Timer counter high
Timer counter low
$0012 ICIE OCIE TOIE FOLV2 FOLV1 OLV2 IEDG1 OLVL1 0000 00u0
$0013 ICF1 OCF1 TOF ICF2 OCF2
Undefined
Undefined
$0014
$0015
$0016
$0017
$0018
$0019
$001A
$001B
$001C
$001D
$001E
$001F
$0100
Undefined
Undefined
Undefined
1111 1111
1111 1100
Alternate counter high
Alternate counter low
Input capture high 2
Input capture low 2
Output compare high 2
Output compare low 2
1111 1111
1111 1100
Undefined
Undefined
Undefined
Undefined
(3)
Options (OPTR)
EE1P SEC Not affected
(4)
Mask option register (MOR)
$7FDE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) This bit is set each time there is a power-on reset.
(2) The state of the WDOG bit after reset is dependent upon the mask option selected; 1=watchdog enabled, 0=watchdog disabled.
(3) This register is implemented in EEPROM; therefore reset has no effect on the individual bits.
(4) This register is implemented in EPROM; therefore reset has no effect on the individual bits.
14
TPG
MOTOROLA
H-6
MC68HC705B32
MC68HC05B6
Rev. 4
H.2
External clock
When using an external clock the OSC1 and OSC2 pins should be driven in antiphase (see
Figure D-2). The t or t specifications (see Section H.9) do not apply when using an
OXOV
ILCH
external clock input. The equivalent specification of the external clock source should be used in
lieu of t
or t
.
OXOV
ILCH
H.3
RESET pin
When the oscillator is running in a stable condition, the MCU is reset when a logic zero is applied
to the RESET input for a minimum period of 3.0 machine cycles (tCYC).This differs from the 05B6,
05B4, 705B5, 05B8, 05B16, 705B16 and the 05B32, which require 1.5 t
see Section 9.1.3.
. For more information
CYC
H.4
EPROM
The MC68HC705B32 memory map is given in Figure H-2. The device has a total of 31246 bytes
of EPROM. 14 bytes are used for the reset and interrupt vectors from address $7FF2 to $7FFF.
The main EPROM block of 31232 bytes is located from $0400 to $7DFF. One byte of EPROM is
used as an options register and is located at address $7FDE.
The EPROM array is supplied by the VPP6 pin in both read and program modes. Typically the
user’s software will be loaded into a programming board where V
is controlled by one of the
PP6
bootstrap loader routines. It will then be placed in an application where no programming occurs.
In this case the VPP6 pin should be hardwired to V
.
DD
Warning: A minimum V
voltage must be applied to the VPP6 pin at all times, including
DD
power-on. Failure to do so could result in permanent damage to the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C) temperature
only.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-7
H.4.1
EPROM read operation
The execution of a program in the EPROM address range or a load from the EPROM are both read
operations.The E6LAT bit in the EPROM/EEPROM control register should be cleared to ‘0’ which
automatically resets the E6PGM bit. In this way the EPROM is read like a normal ROM. Reading
the EPROM with the E6LAT bit set will give data that does not correspond to the actual memory
content. As interrupt vectors are in EPROM, they will not be loaded when E6LAT is set. Similarly,
the bootstrap ROM routines cannot be executed when E6LAT is set. In read mode, the VPP6 pin
must be at the V level. When entering the STOP mode, the EPROM is automatically set to the
DD
read mode.
Note:
An erased byte reads as $00.
H.4.2
EPROM program operation
Typically, the EPROM will be programmed by the bootstrap routines resident in the on-chip ROM.
However, the user program can be used to program some EPROM locations if the proper
procedure is followed. In particular, the programming sequence must be running in RAM, as the
EPROM will not be available for code execution while the E6LAT bit is set.TheV
switching must
PP6
occur externally after EPGM is set, for example under control of a signal generated on a pin by the
programming routine.
Note:
Unless the part has a window for reprogramming, only the cumulative programming of
bits to logic ‘1’ is possible if multiple programming is made on the same byte.
To allow simultaneous programming of up to sixteen bytes, these bytes must be in the same group
of addresses which share the same most significant address bits; only the four LSBs can change.
H.4.3
EPROM/EEPROM control register
State
on reset
Address bit 7
$0007
bit 6
0
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
EPROM/EEPROM/ECLK control
E6LAT E6PGM ECLK E1ERA E1LAT E1PGM u000 0000
14
TPG
MOTOROLA
H-8
MC68HC705B32
MC68HC05B6
Rev. 4
E6LAT — EPROM programming latch enable bit
1 (set)
–
Address and up to sixteen data bytes can be latched into the EPROM
for further programming providing the E6PGM bit is cleared. When
programming the EPROM, all other 15 addresses must be latched
with the erased state ($00) or corruption may occur.
0 (clear) – Data can be read from the EPROM or firmware ROM; the E6PGM bit
is reset to zero when E6LAT is ‘0’.
STOP, power-on and external reset clear the E6LAT bit.
Note:
After the t
erase time or t
programming time, the E6LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E6PGM bit.
E6PGM — EPROM program enable bit
This bit is the EPROM program enable bit. It can be set to ‘1’ to enable programming only after
E6LAT is set and at least one byte is written to the EPROM. It is not possible to clear this bit using
software but clearing E6LAT will always clear E6PGM.
Table H-2 EPROM control bits description
E6LAT E6PGM
Description
Read/execute in EPROM
0
1
1
0
0
1
Ready to write address/data to EPROM
programming in progress
Note:
All combinations are not shown in the above table, since the E6PGM bit is cleared when
the E6LAT bit is at zero, and will result in a read condition.
ECLK
See Section 4.3.
E1ERA — EEPROM erase/programming bit
Providing the E1LAT and E1PGM bits are at logic one, this bit indicates whether the access to the
EEPROM is for erasing or programming purposes.
1 (set)
–
An erase operation will take place.
0 (clear) – A programming operation will take place.
Once the program/erase EEPROM address has been selected, E1ERA cannot be changed.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-9
E1LAT — EEPROM programming latch enable bit
1 (set)
–
Address and data can be latched into the EEPROM for further
program or erase operations, providing the E1PGM bit is cleared.
0 (clear) – Data can be read from the EEPROM.The E1ERA bit and the E1PGM
bit are reset to zero when E1LAT is ‘0’.
STOP, power-on and external reset clear the E1LAT bit.
Note:
After the t
erase time or t
programming time, the E1LAT bit has to be reset
ERA1
PROG1
to zero in order to clear the E1ERA bit and the E1PGM bit.
E1PGM — EEPROM charge pump enable/disable
1 (set) Internal charge pump generator switched on.
–
0 (clear) – Internal charge pump generator switched off.
When the charge pump generator is on, the resulting high voltage is applied to the EEPROM array.
This bit cannot be set before the data is selected, and once this bit has been set it can only be
cleared by clearing the E1LAT bit.
A summary of the effects of setting/clearing bits 0, 1 and 2 of the control register are given in Table H-3.
Table H-3 EEPROM control bits description
E1ERA E1LAT E1PGM
Description
0
0
0
1
1
0
1
1
1
1
0
0
1
0
1
Read condition
Ready to load address/data for program/erase
Byte programming in progress
Ready for byte erase (load address)
Byte erase in progress
Note:
The E1PGM and E1ERA bits are cleared when the E1LAT bit is at zero.
14
TPG
MOTOROLA
H-10
MC68HC705B32
MC68HC05B6
Rev. 4
H.4.4
Mask option register
State
on reset
Address bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Mask option register (MOR)
$7FDE
RTIM RWAT WWAT PBPD PCPD Not affected
(1) Because this register is implemented in EPROM, reset has no effect on the individual bits.
RTIM
This bit can modify the time t
, where the RESET pin is kept low after a power-on reset.
PORL
1 (set)
–
t
t
= 16 cycles.
PORL
PORL
0 (clear) –
= 4064 cycles.
RWAT
This bit can modify the status of the watchdog counter after reset. Usually, the watchdog system
is disabled after power-on or external reset but when this bit is set, it will be active immediately
after the following resets (except in bootstrap mode).
WWAT
This bit can modify the status of the watchdog counter in WAIT mode. Normally, the watchdog
system is disabled inWAIT mode but when this bit is set, the watchdog will be active inWAIT mode.
PBPD
This bit, when programmed, connects a resistive pull-down on all 8 pins of port B.This pull-down,
R
, is active on a given pin only while it is an input.
PD
PCPD
This bit, when programmed, connects a resistive pull-down on all 8 pins of port C.This pull-down,
R
, is active on a given pin only while it is an input.
PD
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-11
H.4.5
Options register (OPTR)
State
on reset
Address bit 7
$0100
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(1)
Options (OPTR)
EE1P SEC Not affected
(1) Because this register is implemented in EEPROM, reset has no effect on the individual bits.
EE1P – EEPROM protect bit
In order to achieve a higher degree of protection, the EEPROM is effectively split into two parts,
both working from the VPP1 charge pump. Part 1 of the EEPROM array (32 bytes from $0100 to
$011F) cannot be protected; part 2 (224 bytes from $0120 to $01FF) is protected by the EE1P bit
of the options register.
1 (set)
–
Part 2 of the EEPROM array is not protected; all 256 bytes of
EEPROM can be accessed for any read, erase or programming
operations.
0 (clear) – Part 2 of the EEPROM array is protected; any attempt to erase or
program a location will be unsuccessful.
When this bit is set to 1 (erased), the protection will remain until the next power-on or external
reset. EE1P can only be written to ‘0’ when the E1LAT bit in the EEPROM control register is set.
Note:
The EEPROM1 protect function is disabled while in bootstrap mode.
SEC — Secure bit
This bit allows the EPROM and EEPROM1 to be secured from external access.When this bit is in
the erased state (set), the EPROM and EEPROM1 content is not secured and the device may be
used in non user mode. When the SEC bit is programmed to ‘zero’, the EPROM and EEPROM1
content is secured by prohibiting entry to the non user mode. To deactivate the secure bit, the
EPROM has to be erased by exposure to a high density ultraviolet light, and the device has to be
entered into the EPROM erase verification mode with PD1 set. When the SEC bit is changed, its
new value will have no effect until the next power-on or external reset.
1 (set)
–
EEPROM/EPROM not protected.
0 (clear) – EEPROM/EPROM protected.
14
TPG
MOTOROLA
H-12
MC68HC705B32
MC68HC05B6
Rev. 4
H.5
Bootstrap mode
Oscillator divide-by-two is forced in bootstrap mode.
The 432 bytes of self-check firmware on the MC68HC05B6 are replaced by 654 bytes of bootstrap
firmware. A detailed description of the modes of operation within bootstrap mode is given below.
The bootstrap program in mask ROM address locations $0200 to $024F, $03B0 to $3FFF, $7E00
to $7FDD and $7FE0 to $7FEF can be used to program the EPROM and the EEPROM, to check
if the EPROM is erased or to load and execute data in RAM.
After reset, while going to the bootstrap mode, the vector located at address $7FEE and $7FEF
(RESET) is fetched to start execution of the bootstrap program. To place the part in bootstrap
mode, the IRQ pin should be at 2xV with the TCAP1 pin ‘high’ during transition of the RESET
DD
pin from low to high.The hold time on the IRQ andTCAP1 pins is two clock cycles after the external
RESET pin is brought high.
When the MC68HC705B32 is placed in the bootstrap mode, the bootstrap reset vector will be
fetched and the bootstrap firmware will start to execute. Table H-4 shows the conditions required
to enter each level of bootstrap mode on the rising edge of RESET.
Table H-4 Mode of operation selection
IRQ pin
to V
TCAP1 pin PD1 PD2 PD3 PD4
Mode
V
V
to V
DD
x
0
x
0
x
0
x
x
Single chip
SS
DD
SS
2xV
V
Erased EPROM verification
DD
DD
EPROM verification; erase EEPROM;
EPROM/EEPROM parallel program/verify
2xV
V
1
0
1
0
1
1
0
0
0
0
0
0
DD
DD
Erased EPROM verification;
no EEPROM erase if SEC is zero (parallel mode)
2xV
V
DD
DD
Erased EPROM verification; erase EEPROM;
2xV
V
DD
2
DD
EPROM parallel program/verify (no E )
2xV
V
x
0
1
1
1
0
0
1
Jump to start of RAM ($0051); SEC bit = ACTIVE
DD
DD
2xV
V
EPROM and EEPROM verification; SEC bit = ACTIVE (parallel mode)
DD
DD
Serial RAM load/execute – similar to MC68HC05B6 but can fill RAM I,
II and III
2xV
V
x
x
1
1
DD
DD
x = Don’t care
The bootstrap program will first copy part of itself in RAM (except ‘RAM parallel load’), as the
program cannot be executed in ROM during verification/programming of the EPROM. It will then
set the TCMP1 output to a logic high level, unlike the MC68HC05B6 which keeps TCMP1 low.This
can be used to distinguish between the two circuits and, in particular, for selection of the VPP level
and current capability.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-13
Reset
N
N
IRQ at 2xV
?
?
User mode
DD
Y
Y
N
TCAP1=V
Y
SEC bit active?
Non-user mode
DD
Parallel E/EEPROM bootstrap
Bootstrap mode
Erased EPROM verification
Y
Y
Y
Y
PD3 set?
SEC bit active?
N
Red LED on
N
Serial RAM
load/execute
N
PD2 set?
PD4 set?
N
Y
N
PD1 set?
Y
PD2 set?
N
Non-user mode
N
Jump to RAM
($0051)
EPROM erased?
Red LED on
Y
Green LED on
Y
SEC bit active?
N
Red LED on
A
N
PD1 set?
Y
PD4 set?
Erase EEPROM1
B
Red LED off
N
C
14
Figure H-3 Modes of operation flow chart (1 of 2)
TPG
MOTOROLA
H-14
MC68HC705B32
MC68HC05B6
Rev. 4
C
Y
N
PD2 set?
Base address = $400
(EPROM only)
Base address = $400
(EPROM only)
Y
Base address = $400
(EPROM only)
A
B
PD2 set?
N
Base address = $100
(EPROMandEEPROM)
N
Data verified?
Red LED on
Y
Green LED on
Figure H-4 Modes of operation flow chart (2 of 2)
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-15
H.5.1
Erased EPROM verification
If a non $00 byte is detected, the red LED will be turned on and the routine will stop (see Figure H-3
and Figure H-4). Only when the whole EPROM content is verified as erased will the green LED be
turned on. PD1 is then checked. If PD1=0, the bootstrap program stops here and no programming
occurs until such time as a high level is sensed on PD1. If PD1 = 1, the bootstrap program
proceeds to erase the EEPROM1 for a nominal 2.5 seconds (4.0 MHz crystal). It is then checked
for complete erasure; if any EEPROM byte is not erased, the program will stop before erasing the
SEC byte. When both EPROM and EEPROM1 are completely erased and the security bit is
cleared the programming operation can be performed. A schematic diagram of the circuit required
for erased EPROM verification is shown in Figure H-7.
H.5.2
EPROM/EEPROM parallel bootstrap
Within this mode there are various subsections which can be utilised by correctly configuring the
port pins shown in Table H-4.
The erased EPROM verification program will be executed first as described in Section H.5.1.
When PD2=0, the programming time is set to 5 milliseconds with the bootstrap program and verify
for the EPROM taking approximately 15 seconds. The EPROM will be loaded in increasing
address order with non EPROM segments being skipped by the loader. Simultaneous
programming is performed by reading sixteen bytes of data before actual programming is
performed, thus dividing the loading time of the internal EPROM by 16. If any block of 16 EPROM
bytes or 1 EEPROM byte of data is in the erased state, no programming takes place, thus speeding
up the execution time.
Parallel data is entered through Port A, while the 15-bit address is output on port B, PC0 to PC4
and TCMP1 and TCMP2. If the data comes from an external EPROM, the handshake can be
disabled by connecting together PC5 and PC6. If the data is supplied by a parallel interface,
handshake will be provided by PC5 and PC6 according to the timing diagram of Figure H-5 (see
also Figure H-6).
During programming, the green LED will flash at about 3 Hz.
Upon completion of the programming operation, the EPROM and EEPROM1 content will be
checked against the external data source. If programming is verified the green LED will stay on,
while an error will cause the red LED to be turned on.Figure H-7 is a schematic diagram of a circuit
which can be used to program the EPROM or to load and execute data in the RAM.
Note:
The entire EPROM and EEPROM1 can be loaded from the external source; if it is
desired to leave a segment undisturbed, the data for this segment should be all $00s
for EPROM data and all $FFs for EEPROM1 data.
14
TPG
MOTOROLA
H-16
MC68HC705B32
MC68HC05B6
Rev. 4
Address
HDSK out
(PC5)
Data
HDSK in
(PC6)
F29
Data read
Data read
Figure H-5 Timing diagram with handshake
t
t
t
t
CDDE
COOE
COOE
COOE
Address
t
t
t
t
ADE
ADE
ADE
ADE
t
t
t
t
DHE
DHE
DHE
DHE
Data
t
max (address to data delay)
min (data hold time)
5 machine cycles
14 machine cycles
ADE
t
DHA
t
(load cycle time)
117 machine cycles < t
< 150 machine cycles
COOE
COOE
t
(programming cycle time)
t
+ t (5ms nominal for EPROM; 10ms for EEPROM1))
PROG
CDDE
COOE
1 machine cycle = 1/(2f (Xtal))
0
Figure H-6 Parallel EPROM loader timing diagram
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-17
P1
1
2
3
GND
+5V
RESET
RUN
1N914
+
100µF
V
PP
100kΩ
1N914
1kΩ
TCAP1 VRH VDD
1.0µF
+
47µF
+
IRQ
OSC1
OSC2
RESET
4.0 MHz
22pF
NC
RDI
VRL
TCAP2
PD7
PD6
PD5
red LED
TCMP1
VPP1
PLMA
PLMB
470Ω
22pF
0.01µF
Verify
EPROM
470Ω
green LED
Erase check & boot
Boot
red LED — programming failed
green LED — programming OK
PD3
PD2
PD1
PD0
Program
EPROM
EPROM erase
check
Erase check
green LED — EPROM erased
red LED — EPROM not erased
MC68HC705B32
MCU
RAM
+5V
28
PD4
EPROM
1 kΩ
1
27
VPP PGM VCC
SCLK
TDO
TCMP2
A14
10k Ω
26
10
A13
VPP6
PC7
12 kΩ
A0
A1
A2
A3
A4
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
9
8
7
6
5
4
3
4k7Ω
+
BC239C
1nF
4k7Ω
20
CE
A5
A6
A7
27C256
+5V
100 kΩ
11
12
13
15
16
17
18
19
HDSK out
Short circuit if
D0
D1
D2
D3
D4
D5
D6
D7
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
PC5
PC6
handshake not used
25
24
21
23
2
A8
A9
A10
A11
A12
HDSK in
A12
PC4
PC3
PC2
PC1
PC0
A11
A10
A9
A8
VSS
GND
14
OE
22
Note:
This circuit is recommended for programming only at 25°C and not for use in the
end application, or at temperatures other than 25°C. If used in the end application,
VPP6 should be tied to VDD to avoid damaging the device.
14
Figure H-7 EPROM parallel bootstrap schematic diagram
TPG
MOTOROLA
H-18
MC68HC705B32
MC68HC05B6
Rev. 4
H.5.3
Serial RAM loader
This mode is similar to the RAM load/execute program for the MC68HC05B6 described in
Section 2.2, with the additional features listed below. Table H-4 shows the entry conditions
required for this mode.
If the first byte is less than $B0, the bootloader behaves exactly as the MC68HC05B6, i.e. count
byte followed by data stored in $0050 to $00FF. If the count byte is larger than RAM I (176 bytes)
then the code continues to fill RAM II then RAM III. In this case the count byte is ignored and the
program execution begins at $0051 once the total RAM area is filled or if no data is received for 5
milliseconds.
The user must take care when using branches or jumps as his code will be relocated in RAM I, II
and III. If the user intends to use the stack in his program, he should send NOP’s to fill the desired
stack area.
In the RAM bootloader mode, all interrupt vectors are mapped to pseudo-vectors in RAM (see
Table H-5). This allows programmers to use their own service-routine addresses. Each
pseudo-vector is allowed three bytes of space rather than the two bytes for normal vectors,
because an explicit jump (JMP) opcode is needed to cause the desired jump to the users
service-routine address.
Table H-5 Bootstrap vector targets in RAM
Vector targets in RAM
SCI interrupt
Timer overflow
Timer output compare
Timer input capture
IRQ
$0063
$0060
$005D
$005A
$0057
$0054
SWI
H.5.3.1
Jump to start of RAM ($0051)
The Jump to start of RAM program will be executed when bring the device out of reset with PD2
and PD3 at ‘1’ and PD4 at ‘0’.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-19
P1
1
2
3
GND
+5V
V
PP
RESET
RUN
10nF
+
100kΩ
1kΩ
1N914
47µF
22
8
10
TCAP1 VRH VDD
1.0µF
1N914
19
+
IRQ
47µF
+
18 RESET
OSC1
OSC2
Red LED
470Ω
470Ω
0.01µF
20
PLMA
4.0 MHz
22pF
22pF
21
PLMB
Green LED
PD3
Erase check
Green LED — EPROM erased
Red LED — EPROM not erased
MC68HC705B32
MCU (socket)
Serial boot
PD4
Erase check
&
serial boot
1 kΩ
Serial boot
Flashing green LED — programming
Green LED — programming ended
39
38
37
36
35
34
33
32
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
10k Ω
VPP6
PC7
12 kΩ
4k7Ω
+
BC239C
1nF
4k7Ω
31
30
29
28
27
26
25
24
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
Erase check and serial boot
EPROM erase check
43
44
45
46
47
48
49
PC6
PC5
PC4
PC3
PC2
PC1
PC0
9600 BD
8-bit
no parity
14
13
12
5
4
3
22µF
+5V
PD0
PD1
PD2
PD5
PD6
PD7
+
16
2 x 3KΩ
22µF
8
5
7
3
2
1
1
2
6
+
22µF
3
VPP1
TCAP2
TCMP1
TCMP2
SCLK
4
+
MAX
232
RS232
Connector
23
2
1
51
40
+
22µF
5
50
52
13
14
12
11
RDI
TDO
15
NC
VSS
41
VRL
7
Note:
A minimum V
voltage must be applied to the VPP6 pin at all times,
DD
including power-on, as a lower voltage could damage the device. Unless
otherwise stated, EPROM programming is guaranteed at ambient (25°C)
temperature only
14
Figure H-8 RAM load and execute schematic diagram
TPG
MOTOROLA
H-20
MC68HC705B32
MC68HC05B6
Rev. 4
t
CR
Address
PC5 out
t
HO
t
ADR
t
DHR
Data
t
max
HI
PC6 in
PD4
t
max
EXR
t
max (address to data delay; PC6=PC5)
min (data hold time)
16 machine cycles
4 machine cycles
49 machine cycles
5 machine cycles
10 machine cycles
30 machine cycles
ADR
t
DHR
t
(load cycle time; PC6=PC5)
(PC5 handshake out delay)
CR
t
HO
t
max (PC6 handshake in, data hold time)
HI
t
max (max delay for transition to be recognised during this cycle; PC6=PC5
EXR
1 machine cycle = 1/(2f (Xtal))
0
Figure H-9 Parallel RAM loader timing diagram
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-21
H.6
Absolute maximum ratings
Table H-6 Absolute Maximum ratings
Rating
Symbol
Value
Unit
V
(1)
Supply voltage
Input voltage (Except V and V
V
– 0.5 to +7.0
DD
)
V
V
– 0.5 to V + 0.5
V
PP1
PP6
IN
SS
DD
Input voltage
– Self-check mode (IRQ pin only)
V
V
– 0.5 to 2V + 0.5
V
IN
SS
DD
Operating temperature range
– Standard (MC68HC705B32)
– Extended (MC68HC705B32C)
T
T to T
0 to +70
–40 to +85
A
L
H
°C
°C
Storage temperature range
T
– 65 to +150
STG
(2)
Current drain per pin (excluding VDD and VSS)
– Source
– Sink
I
25
45
mA
mA
D
I
S
(1) All voltages are with respect to V .
SS
(2) Maximum current drain per pin is for one pin at a time, limited by an external resistor.
Note:
This device contains circuitry designed to protect against damage due to high
electrostatic voltages or electric fields. However, it is recommended that normal
precautions be taken to avoid the application of any voltages higher than those given in
the maximum ratings table to this high impedance circuit. For maximum reliability all
unused inputs should be tied to either V or V
.
SS
DD
14
TPG
MOTOROLA
H-22
MC68HC705B32
MC68HC05B6
Rev. 4
H.7
DC electrical characteristics
Table H-7 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, –40 to +85°C)
DD
SS
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.8
V – 0.4
DD
—
—
—
OH
DD
LOAD
V
V
TDO, SCLK, PLMA, PLMB
V
V
– 0.8
– 0.8
V
DD
– 0.4
– 0.3
OH
DD
Output high voltage (I
= -300µA)
LOAD
OSC2
V
V
V
DD
OH
DD
Output low voltage (I
= 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.4
1
OL
Output low voltage (I
= 1.6mA)
LOAD
RESET
Output low voltage (I
V
—
—
0.4
OL
= -100µA)
LOAD
OSC2
V
TBD
—
OL
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
Input low voltage
V
0.7V
—
—
V
DD
V
V
IH
DD
PA0–7, PB0–7, PC0–7, PD0–7,OSC1, IRQ ,
RESET, TCAP1, TCAP2, RDI
V
V
0.2V
DD
IL
SS
(3)
Supply current (For Guidance Only)
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
6
1.5
2
TBD
mA
mA
mA
mA
DD
I
TBD
TBD
TBD
DD
I
DD
I
1
DD
0 to 70 (standard)
– 40 to 85 (extended)
I
—
—
10
10
TBD
TBD
µA
µA
DD
I
DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
Input current
I
—
±0.2
80
±1
µA
µA
IL
Port B and port C pull-down (V =V )
I
RPD
IN IH
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
Input current (– 40 to 85)
I
—
—
±0.2
±1
±5
µA
µA
IN
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
IN
Capacitance
Ports (as input or output), RESET,TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
OUT
IN
IN
C
(1) All IDD measurements taken with suitable decoupling capacitors across the power supply to suppress the transient switching
currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT IDD: measured using an external square-wave clock source (fOSC = 2.0 MHz); all inputs 0.2 V from rail; no
DC loads; maximum load on outputs 50pF (20pF on OSC2).
14
STOP /WAIT IDD: all ports configured as inputs;V = 0.2 V and VIH = VDD – 0.2 V: STOP IDD measured with OSC1 = V DD
.
IL
WAIT IDD is affected linearly by the OSC2 capacitance.
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-23
Table H-8 DC electrical characteristics for 3.3V operation
(V = 3.3Vdc ± 10%, V = 0Vdc, T = –40 to +85°C)
DD
SS
A
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.3
V – 0.1
DD
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.3
V
– 0.1
OH
DD
DD
Output low voltage (I = 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
0.1
0.3
0.6
OL
Output low voltage (I
= 1.6mA)
LOAD
V
0.2
—
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
V
DD
V
V
IH
DD
Input low voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
RESET, TCAP1, TCAP2, RDI
V
V
—
0.2V
DD
IL
SS
(3)
Supply current (For Guidance Only)
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
I
—
—
—
—
3
1
1.5
0.5
TBD
mA
mA
mA
mA
DD
I
TBD
TBD
TBD
DD
I
DD
I
DD
0 to 70 (standard)
– 40 to 85 (extended)
I
—
—
10
10
TBD
TBD
µA
µA
DD
I
DD
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
—
±0.2
±0.2
±1
±1
µA
µA
IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
IN
Input current (– 40 to 125)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
—
±5
µA
IN
Capacitance
Ports (as input or output), RESET,TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
OUT
IN
IN
C
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I : measured using an external square-wave clock source (f
= 2.0 MHz); all inputs 0.2 V
DD
OSC
from rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I : all ports configured as inputs;V = 0.2 V and V = V – 0.2 V: STOP I measured with
DD
IL
IH
DD
DD
OSC1 = V
.
DD
WAIT I is affected linearly by the OSC2 capacitance.
DD
14
TPG
MOTOROLA
H-24
MC68HC705B32
MC68HC05B6
Rev. 4
H.8
A/D converter characteristics
Table H-9 A/D characteristics for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 0.5
± 0.5
± 1
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
a. External clock (OSC1, OSC2)
Conversion time
—
—
32
32
t
CYC
µs
b. Internal RC oscillator
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
IN
RH
Sample acquisition time Analog input acquisition sampling
a. External clock (OSC1, OSC2)
—
—
12
12
t
CYC
(1)
b. Internal RC oscillator
µs
pF
µA
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
12
1
(2)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-25
Table H-10 A/D characteristics for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Non-linearity
Max deviation from the best straight line through the A/D
transfer characteristics
—
—
—
± 1
± 1
± 2
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error
Absolute accuracy
Uncertainty due to converter resolution
Difference between the actual input voltage and the
full-scale equivalent of the binary code output code for all
errors
Conversion range
Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital conversion
Internal RC oscillator
Conversion time
—
32
µs
Monotonicity
Conversion result never decreases with an increase in
input voltage and has no missing codes
GUARANTEED
Zero input reading
Full scale reading
Conversion result when V = V
00
—
FF
Hex
Hex
IN
RL
Conversion result when V = V
—
IN
RH
Sample acquisition time Analog input acquisition sampling
(1)
Internal RC oscillator
—
12
12
1
µs
pF
Sample/holdcapacitance Input capacitance on PD0/AN0–PD7/AN7
—
(2)
Input leakage
InputleakageonA/Dpins PD0/AN0–PD7/AN7,VRL,VRH
—
µA
(1) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(2) The external system error caused by input leakage current is approximately equal to the product of R source and input
current. Input current to A/D channel will be dependent on external source impedance (see Figure 8-2).
14
TPG
MOTOROLA
H-26
MC68HC705B32
MC68HC05B6
Rev. 4
H.9
Control timing
Table H-11 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
4.2
4.2
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
—
dc
2.1
2.1
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
476
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
3.0
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
t
4064
16
—
—
PORL
t
CYC
PORL
DOGL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
10
10
—
—
ms
ms
ERA
– 40 to 85 (extended)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
t
10
10
—
—
ms
ms
PROG
t
PROG
Timer (see Figure H-10)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
125
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
90
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting factor
CYC
in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to execute
TLTL
the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to execute
ILIL
the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 238ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-27
Table H-12 Control timing for operation at 3.3V
(V = 3.3Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
2.0
2.0
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Using crystal
Using external clock
f
f
OP
—
dc
1.0
1.0
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
1000
—
—
100
100
5
ns
ms
ms
µs
µs
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
RC oscillator stabilization time
t
OXOV
t
ILCH
t
ADRC
A/D converter stabilization time
t
500
—
ADON
External RESET input pulse width
t
3.0
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
4064
16
—
—
PORL
t
CYC
t
PORL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
DOGL
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
30
30
—
—
ms
ms
ERA
– 40 to 85 (extended)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
t
30
30
—
—
ms
ms
PROG
t
PROG
Timer (see Figure H-10)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
250
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
250
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
(5)
OSC1 pulse width
t
, t
100
ns
OH OL
(6)(7)
Write/Erase endurance
—
10000
10
cycles
years
(6)(7)
Data retention
—
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to
ILIL
execute the interrupt service routine plus 21 t
.
CYC
(5) t and t should not total less than 500ns.
OH
OL
(6) At a temperature of 85°C
(7) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate information.
14
TPG
MOTOROLA
H-28
MC68HC705B32
MC68HC05B6
Rev. 4
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure H-10 Timer relationship
H.10
EPROM electrical characteristics
Table H-13 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
(1)
(2)
Characteristic
Symbol
max
Min
Typ
Max
Unit
EPROM
Absolute maximum voltage
Programming voltage
Programming current
Read voltage
V
V
—
15.5
50
18
16
64
V
V
mA
V
PP6
DD
V
15
—
PP6
I
PP6
V
V
V
V
PP6R
DD
DD
DD
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the
DD
transient switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
Table H-14 Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
Table H-15 Control timing for 3.3V operation
(V = 3.3 Vdc ± 10%, V = 0 Vdc, T = 25°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
EPROM programming time
t
5
20
ms
PROG
14
MC68HC05B6
Rev. 4
MC68HC705B32
MOTOROLA
H-29
THIS PAGE LEFT BLANK INTENTIONALLY
14
MOTOROLA
H-30
MC68HC705B32
MC68HC05B6
Rev. 4
I
HIGH SPEED OPERATION
This section contains the electrical specifications and associated timing information for high speed
versions of the MC68HC05B6, MC68HC05B8 and MC68HC05B16 (f
ordering information for these devices is contained in Table I-1.
max = 8 MHz). The
OSC
Table I-1 Ordering information
Suffix
Suffix
Device title
Package
0 to 70°C -40 to +85°C
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
52-pin PLCC
64-pin QFP
56-pin SDIP
FN
FU
B
CFN
CFU
CB
MC68HC05B6
FN
FU
B
CFN
CFU
CB
MC68HC05B8
MC68HC05B16
FN
FU
B
CFN
CFU
CB
Note:
The high speed version has the same device title as the standard version. High speed
operation is selected via a check-box on the order form and will be confirmed on the
listing verification form.
TPG
15
MC68HC05B6
Rev. 4
HIGH SPEED OPERATION
MOTOROLA
I-1
I.1
DC electrical characteristics
Table I-2 DC electrical characteristics for 5V operation
(V = 5 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
(1)
(2)
Characteristic
Symbol
Min
– 0.1
Typ
Max
Unit
Output voltage
I
= – 10 µA
V
V
—
—
V
LOAD
OH
DD
I
= +10 µA
V
—
—
0.1
LOAD
OL
Output high voltage (I
= 0.8mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2
Output high voltage (I = 1.6mA)
V
V
– 0.8
—
—
—
—
—
OH
DD
V
V
LOAD
TDO, SCLK, PLMA, PLMB
V
V
– 0.8
OH
DD
Output low voltage (I = 1.6mA)
LOAD
PA0–7, PB0–7, PC0–7, TCMP1, TCMP2,
TDO, SCLK, PLMA, PLMB
V
—
—
—
—
—
—
0.4
1
OL
Output low voltage (I
= 1.6mA)
LOAD
V
OL
RESET
Input high voltage
PA0–7, PB0–7, PC0–7, PD0–7, OSC1,
IRQ, RESET, TCAP1, TCAP2, RDI
V
0.7V
—
—
V
DD
V
V
IH
DD
Input low voltage
V
V
0.2V
DD
PA0–7, PB0–7, PC0–7, PD0–7, OSC1, IRQ ,
IL
SS
RESET, TCAP1, TCAP2, RDI
(3)
Supply current
RUN (SM = 0) (See Figure 11-1)
RUN (SM = 1) (See Figure 11-2)
WAIT (SM = 0) (See Figure 11-3)
WAIT (SM = 1) (See Figure 11-4)
STOP
—
—
—
—
—
—
—
—
12
3
4
mA
mA
mA
mA
I
DD
2
0 to 70 (standard)
– 40 to 85 (extended)
—
—
—
—
10
20
µA
µA
High-Z leakage current
PA0–7, PB0–7, PC0–7, TDO, RESET , SCLK
I
—
—
—
±1
µA
µA
IL
Input current (0 to 70)
IRQ, OSC1, TCAP1, TCAP2, RDI,
PD0/AN0-PD7/AN7 (channel not selected)
I
—
—
±5
±1
IN
Capacitance
Ports (as input or output), RESET, TDO, SCLK
IRQ, TCAP1, TCAP2, OSC1, RDI
PD0/AN0–PD7/AN7 (A/D off)
PD0/AN0–PD7/AN7 (A/D on)
C
C
C
C
—
—
—
—
—
—
12
22
12
8
—
—
pF
pF
pF
pF
OUT
IN
IN
IN
(1) All I measurements taken with suitable decoupling capacitors across the power supply to suppress the transient
DD
switching currents inherent in CMOS designs (see Section 2).
(2) Typical values are at mid point of voltage range and at 25°C only.
(3) RUN and WAIT I : measured using an external square-wave clock source (f
= 8.0MHz); all inputs 0.2 V from
DD
OSC
rail; no DC loads; maximum load on outputs 50pF (20pF on OSC2).
STOP /WAIT I : all ports configured as inputs;V = 0.2 V and V = V – 0.2 V: STOP I measured with
DD
IL
IH
DD
DD
OSC1 = V
.
DD
WAIT I is affected linearly by the OSC2 capacitance.
DD
TPG
15
MOTOROLA
I-2
HIGH SPEED OPERATION
MC68HC05B6
Rev. 4
I.2
A/D converter characteristics
Table I-3 A/D characteristics for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Parameter
Min
Max
Unit
Resolution
Number of bits resolved by the A/D
8
—
Bit
Max deviation from the best straight line through
the A/D transfer characteristics
Non-linearity
—
—
—
± 0.5
± 0.5
± 1
LSB
LSB
LSB
(V = V and V = 0V)
RH
DD
RL
Quantization error Uncertainty due to converter resolution
Difference between the actual input voltage and
Absolute accuracy the full-scale equivalent of the binary code
output code for all errors
Conversion range Analog input voltage range
V
V
V
V
V
V
RL
RH
V
Maximum analog reference voltage
Minimum analog reference voltage
V
V
+ 0.1
RH
RL
DD
V
V
– 0.1
V
RH
RL
SS
(1)
∆V
Minimum difference between V and V
RL
3
—
R
RH
Total time to perform a single analog to digital
conversion
Conversion time
Monotonicity
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
—
—
32
32
t
CYC
µs
Conversion result never decreases with an
increase in input voltage and has no missing
codes
GUARANTEED
Zero input reading Conversion result when V = V
00
—
—
FF
Hex
Hex
IN
RL
Full scale reading Conversion result when V = V
IN
RH
Analog input acquisition sampling
a. External clock (OSC1, OSC2)
b. Internal RC oscillator
Sample acquisition
time
—
—
12
12
t
CYC
µs
(2)
Sample/hold
capacitance
Input capacitance on PD0/AN0–PD7/AN7
—
12
pF
Input leakage on A/D pins PD0/AN0–PD7/AN7
VRL, VRH
—
—
1
1
µA
µA
(3)
Input leakage
(1) Performance verified down to 2.5V ∆VR, but accuracy is tested and guaranteed at∆VR = 5V±10%.
(2) Source impedances greater than 10kΩ will adversely affect internal charging time during input sampling.
(3) The external system error caused by input leakage current is approximately equal to the product of R
source and input current. Input current to A/D channel will be dependent on external source impedance
(see Figure 8-2).
TPG
15
MC68HC05B6
Rev. 4
HIGH SPEED OPERATION
MOTOROLA
I-3
I.3
Control timing for 5V operation
(V = 5.0 Vdc ± 10%, V = 0 Vdc, T = –40 to +85°C)
DD
SS
A
Characteristic
Symbol
Min
Max
Unit
Frequency of operation
Crystal option
f
—
dc
8.0
8.0
MHz
MHz
OSC
External clock option
f
OSC
Internal operating frequency (f /2)
OSC
Crystal
External clock
f
f
OP
—
dc
4.0
4.0
MHz
MHz
OP
Cycle time (see Figure 9-1)
t
250
—
—
100
100
—
ns
ms
ms
CYC
Crystal oscillator start-up time (see Figure 9-1)
Stop recovery start-up time (crystal oscillator)
External RESET input pulse width
t
OXOV
t
ILCH
t
1.5
t
RL
CYC
Power-on RESET output pulse width
t
CYC
4064 cycle
16 cycle
t
t
4064
16
—
—
PORL
t
CYC
PORL
DOGL
Watchdog RESET output pulse width
Watchdog time-out
t
1.5
—
t
t
CYC
CYC
t
6144
7168
DOG
EEPROM byte erase time
0 to 70 (standard)
t
10
10
—
—
ms
ms
ERA
– 40 to 85 (extended)
t
ERA
(1)
EEPROM byte program time
0 to 70 (standard)
– 40 to 85 (extended)
t
10
10
—
—
ms
ms
PROG
t
PROG
Timer (see Figure I-1)
(2)
Resolution
t
4
—
—
—
t
CYC
ns
t
CYC
RESL
, t
Input capture pulse width
Input capture pulse period
t
125
TH TL
(3)
t
—
TLTL
Interrupt pulse width (edge-triggered)
Interrupt pulse period
t
125
—
—
—
ns
ILIH
(4)
t
—
t
ILIL
CYC
OSC1 pulse width
t
, t
90
ns
OH OL
(5)(6)
Write/Erase endurance
—
—
10000
10
cycles
years
(5)(6)
Data retention
(1) For bus frequencies less than 2 MHz, the internal RC oscillator should be used when
programming the EEPROM.
(2) Since a 2-bit prescaler in the timer must count four external cycles (t ), this is the limiting
CYC
factor in determining the timer resolution.
(3) The minimum period t
should not be less than the number of cycle times it takes to
TLTL
execute the capture interrupt service routine plus 24 t
.
CYC
(4) The minimum period t should not be less than the number of cycle times it takes to
ILIL
execute the interrupt service routine plus 21 t
.
CYC
(5) At a temperature of 85°C
(6) Refer to Reliability Monitor Report (current quarterly issue) for current failure rate
information.
TPG
15
MOTOROLA
I-4
HIGH SPEED OPERATION
MC68HC05B6
Rev. 4
tTLTL
tTH
tTL
External
signal
(TCAP1,
TCAP2)
Figure I-1 Timer relationship
TPG
15
MC68HC05B6
Rev. 4
HIGH SPEED OPERATION
MOTOROLA
I-5
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
15
MOTOROLA
I-6
HIGH SPEED OPERATION
MC68HC05B6
Rev. 4
GLOSSARY
This section contains abbreviations and specialist words used in this data
sheet and throughout the industry. Further information on many of the terms
may be gleaned from Motorola’s M68HC11 Reference Manual,
M68HC11RM/AD, or from a variety of standard electronics text books.
$xxxx
The digits following the ‘$’ are in hexadecimal format.
The digits following the ‘%’ are in binary format.
Analog-to-digital (converter).
%xxxx
A/D, ADC
Bootstrap mode
In this mode the device automatically loads its internal memory from an
external source on reset and then allows this program to be executed.
Byte
Eight bits.
CCR
Condition codes register; an integral part of the CPU.
CERQUAD
A ceramic package type, principally used for EPROM and high temperature
devices.
Clear
‘0’ — the logic zero state; the opposite of ‘set’.
CMOS
Complementary metal oxide semiconductor. A semiconductor technology
chosen for its low power consumption and good noise immunity.
COP
Computer operating properly. aka ‘watchdog’. This circuit is used to detect
device runaway and provide a means for restoring correct operation.
CPU
Central processing unit.
D/A, DAC
EEPROM
EPROM
Digital-to-analog (converter).
Electrically erasable programmable read only memory. aka ‘EEROM’.
Erasable programmable read only memory. This type of memory requires
exposure to ultra-violet wavelengths in order to erase previous data. aka
‘PROM’.
ESD
Electrostatic discharge.
Expanded mode
In this mode the internal address and data bus lines are connected to
external pins. This enables the device to be used in much more complex
systems, where there is a need for external memory for example.
TPG
MC68HC05B6
GLOSSARY
MOTOROLA
i
EVS
Evaluation system. One of the range of platforms provided by Motorola for
evaluation and emulation of their devices.
HCMOS
High-density complementary metal oxide semiconductor. A semiconductor
technology chosen for its low power consumption and good noise immunity.
I/O
Input/output; used to describe a bidirectional pin or function.
Input capture
(IC) This is a function provided by the timing system, whereby an external
event is ‘captured’ by storing the value of a counter at the instant the event
is detected.
Interrupt
IRQ
This refers to an asynchronous external event and the handling of it by the
MCU. The external event is detected by the MCU and causes a
predetermined action to occur.
Interrupt request. The overline indicates that this is an active-low signal
format.
K byte
LCD
A kilo-byte (of memory); 1024 bytes.
Liquid crystal display.
LSB
Least significant byte.
M68HC05
MCU
Motorola’s family of 8-bit MCUs.
Microcontroller unit.
MI BUS
Motorola interconnect bus. A single wire, medium speed serial
communications protocol.
MSB
Most significant byte.
Half a byte; four bits.
Non-return to zero.
Nibble
NRZ
Opcode
The opcode is a byte which identifies the particular instruction and operating
mode to the CPU. See also: prebyte, operand.
Operand
The operand is a byte containing information the CPU needs to execute a
particular instruction.There may be from 0 to 3 operands associated with an
opcode. See also: opcode, prebyte.
Output compare
(OC) This is a function provided by the timing system, whereby an external
event is generated when an internal counter value matches a predefined
value.
PLCC
PLL
Plastic leaded chip carrier package.
Phase-locked loop circuit. This provides a method of frequency
multiplication, to enable the use of a low frequency crystal in a high
frequency circuit.
Prebyte
This byte is sometimes required to qualify an opcode, in order to fully specify
a particular instruction. See also: opcode, operand.
TPG
MOTOROLA
ii
GLOSSARY
MC68HC05B6
Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
permanently connected to either ground or V
.
DD
PWM
Pulse width modulation.This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.
QFP
Quad flat pack package.
RAM
Random access memory.Fast read and write, but contents are lost when the
power is removed.
RFI
Radio frequency interference.
Real-time interrupt.
RTI
ROM
Read-only memory. This type of memory is programmed during device
manufacture and cannot subsequently be altered.
RS-232C
SAR
A standard serial communications protocol.
Successive approximation register.
SCI
Serial communications interface.
Set
‘1’ — the logic one state; the opposite of ‘clear’.
Silicon glen
An area in the central belt of Scotland, so called because of the
concentration of semiconductor manufacturers and users found there.
Single chip mode In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.
SPI
Serial peripheral interface.
Test mode
TTL
This mode is intended for factory testing.
Transistor-transistor logic.
UART
Universal asynchronous receiver transmitter.
Voltage controlled oscillator.
see ‘COP’.
VCO
Watchdog
Wired-OR
A means of connecting outputs together such that the resulting composite
output state is the logical OR of the state of the individual outputs.
Word
XIRQ
Two bytes; 16 bits.
Non-maskable interrupt request. The overline indicates that this has an
active-low signal format.
TPG
MC68HC05B6
GLOSSARY
MOTOROLA
iii
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
iv
GLOSSARY
MC68HC05B6
INDEX
In this index numeric entries are placed first; page references in italics indicate that the reference
is to a figure.
MC68HC705B32 H–4
MC68HC705B5 C–2
PLM system 7–1
A
A/D converter
programmable timer 5–2
block diagram 8–2
SCI 6–2
watchdog system 9–3
,
6–2
during STOP mode 8–6
during WAIT mode 8–6
operation 8–1
bootstrap mode C–8
,
E–10 H–12
,
registers
ADDATA 8–3
ADSTAT 8–4
PORTD 8–3
A/D converter characteristics 11–8
C
,
11–9
,
E–24
,
E–25
,
ceramic resonator 2–11
F–22
,
F–23
,
H–25
,
H–26 I–3
,
CH3-CH0 – A/D channels 3, 2, 1 and 0 8–5
COCO – Conversion complete flag 8–4
control timing 11–10
F–25 H–27
COP watchdog 9–3
A/D status/control register
ADON 4–5
,
11–11
,
C–19
,
E–26
,
E–27
,
F–24
,
absolute maximum ratings 11–1
,
,
H–28
,
I–4
ADDATA – A/D result data register 8–3
ADON – A/D converter on 8–5
ADON – A/D converter on bit 4–5
ADRC – A/D RC oscillator control 8–4
ADSTAT
during STOP mode 9–4
during WAIT mode 9–4
counter 5–1
counter register 5–3
CPHA – Clock phase 6–12
CPOL – Clock polarity 6–12
crystal 2–11
ADON 8–5
ADRC 8–4
CH3-CH0 8–5
COCO 8–4
ADSTAT – A/D status/control register 8–4
alternate counter register 5–3
analog input 8–6
D
data direction registers
DDRA, DDRB, DDRC 4–5
data format 6–5
B
DC electrical characteristics 11–2
E–23 F–20 F–21
,
11–5
,
C–19
,
E–22
I–2
,
Baud rate register
,
,
,
H–23
,
H–24
,
SCP1, SCP0 6–18
SCR2, SCR1, SCR0 6–19
SCT2, SCT1, SCT0 6–18
block diagrams
E
MC68HC05B16 D–3
MC68HC05B32 G–2
MC68HC05B4 A–2
MC68HC05B8 B–2
MC68HC705B16 E–2
MC68HC705B16N F–2
E1ERA – EEPROM erase/programming bit 3–3
F–7 H–9
E1LAT – EEPROM programming latch enable 3–4
E1LAT – EEPROM programming latch enable bit E–7
F–7 H–10
,
E–7
,
,
,
,
TPG
MC68HC05B6
INDEX
MOTOROLA
v
E1PGM – EEPROM charge pump enable/disable 3–4
E–7 F–7 H–10
,
I
,
,
E6LAT – EPROM programming latch enable bit E–6
H–9
,
F–6
,
I/O pin states 4–2
I/O port structure 4–2 4–2
,
E6PGM – EPROM program enable bit E–6
ECLK – External clock output bit 4–3
,
F–6 H–9
,
ICF1 – Input capture flag 1 5–6
ICF2 – Input capture flag 2 5–7
IDLE – Idle line detect flag 6–16
IEDG1 – Input edge 1 5–5
ILIE – Idle line interrupt enable 6–14
Input capture registers
ICR1 5–7
EE1P – EEPROM protect bit E–9
EE1P – EEPROM protection bit H–12
EEPROM 3–1 3–3
,
F–9
,
erase operation 3–5
programming operation 3–6
read operation 3–5
STOP mode 3–7
WAIT mode 3–7
EEPROM control register
E1ERA 3–3
ICR2 5–8
input/output programming 4–1
INTE – External interrupt enable 3–9
interrupts
,
9–9
priorities 9–6
SCI 9–10
SWI 9–6
E1LAT 3–4
E1PGM 3–4
ECLK 3–3
INTP, INTN – External interrupt sensitivity options 3–9 9–9
IRQ 9–7
IRQ sensitivity 9–9
,
EEPROM options register
EE1P E–9
SEC E–9
EEPROM/ECLK control
ECLK 4–3
,
F–9
F–9
,
ELAT – EPROM programming latch enable bit C–6
EPGM – EPROM programming bit C–6
EPP – EPROM protect C–7
L
LBCL – Last bit clock 6–13
low power modes
SLOW 2–9
EPPT – EPROM protect test bit C–6
EPROM 13–2
control register C–6
options register C–7
program operation E–5
programming operation C–5
,
C–5
,
E–5
,
,
F–5
STOP 2–6
WAIT 2–8
E–6
,
F–6
H–8
H–8
,
F–6
,
read operation E–5
EPROM control register
ELAT C–6
,
F–5
,
M
M – Mode 6–11
Mask option register
EPGM C–6
EPPT C–6
PBPD E–8
PCPD E–8
RTIM E–8
RWAT E–8
WWAT E–8
mask options
MC68HC05B6 1–3
maskable hardware interrupts 9–7
maskset errata D–1 H–1
MC68HC05B16 D–1
block diagram D–3
memory map D–5
MC68HC05B32 G–1
block diagram G–2
memory map G–3
MC68HC05B4
,
F–8
F–9
F–8
,
H–11
H–11
H–11
,
,
EPROM electrical characteristics E–28
EPROM registers C–6
,
F–26 H–29
,
,
,
,
F–8
,
H–11
H–11
EPROM/EEPROM/ECLK control register
,
F–8
,
E1ERA E–7
E1LAT E–7
E1PGM E–7
E6LAT E–6
E6PGM E–6
,
F–7
F–7
F–7
F–6
F–6
,
,
,
,
,
external clock 2–12
external interrupt 9–7
,
D–4
,
E–5
,
F–5 G–2
,
F
FE – Framing error flag 6–17
block diagram A–2
memory map A–3
MC68HC05B6
block diagram 1–3
mask options 1–3
memory map 3–2
H
high speed operation I–1
pinouts 12–1
,
12–2 12–3
,
TPG
MOTOROLA
vi
INDEX
MC68HC05B6
MC68HC05B8 B–1
block diagram B–2
memory map B–3
PCPD C–8
RTIM C–7
RWAT C–7
MC68HC705B16 E–1
block diagram E–2
memory map E–3
MC68HC705B16N F–1
block diagram F–2
memory map F–3
MC68HC705B32 H–3
block diagram H–4
memory map H–5
WWAT C–7
OPTR – options register 3–6 C–7
EE1P – EEPROM protection bit 3–7
SEC – Security bit 3–7
OR – Overrun error flag 6–17
oscillator connections 2–12
Output compare registers
OCR1 5–9
,
,
D–4
OCR2 5–10
MC68HC705B5 C–1
block diagram C–2
memory map C–3
mechanical dimensions 12–4
memory map
P
,
12–5 12–6
,
parallel bootstrap E–13
,
E–19
,
F–13
F–8
,
H–16
MC68HC05B16 D–5
MC68HC05B32 G–3
MC68HC05B4 A–3
MC68HC05B6 3–2
MC68HC05B8 B–3
MC68HC705B16 E–3
MC68HC705B16N F–3
MC68HC705B32 H–5
MC68HC705B5 C–3
Miscellaneous register
PBPD – Port B pull-down E–8
,
PBPD – Port B pull-down resistors C–8
PCPD – Port C pull-down E–8 F–9
PCPD – Port C pull-down resistors C–8
pin configurations 12–1
pins
,
IRQ 2–10
OSC1, OSC2 2–11
PA0–PA7, PB0–PB7, PC0–PC7 2–13
PD0/AN0–PD7/AN7 2–13
PLMA, PLMB 2–13
INTE 3–9
INTP, INTN 3–9
,
9–9
,
9–9
RDI, TDO 2–13
POR 3–9
SFA 3–10
SFB 3–10
,
9–2
7–3
7–3
RESET 2–10
SCLK 2–13
TCAP1 2–10
TCAP2 2–11
,
9–3
,
,
SM 2–9
WDOG 3–10
modes of operation
,
3–10
,
7–3
9–4
,
TCMP1, TCMP2 2–11
VDD, VSS 2–10
VPP1 2–13
jump to any address 2–4
low power modes 2–6
single chip mode 2–1
VRH, VRL 2–13
PLCC 12–1
PLM 5–11
block diagram 7–1
clock selection 7–4
PLMA, PLMB 7–2
POR – Power-on reset bit 3–9
port registers
N
NF – Noise error flag 6–17
,
9–2
nonmaskable software interrupt 9–6
PORTA, PORTB 4–4
PORTC 4–4
PORTD 4–5
PORTD – Port D data register 8–3
ports
O
OCF1 – Output compare flag 2 5–6
OCF2 – Output compare flag 2 5–7
A and B 4–2
C
D
4–3
4–3
OCIE – Output compares interrupt enable 5–4
OLV1 – Output level 1 5–5
OLV2 – Output level 2 5–5
Options register
SEC H–12
options register
power-on reset 9–2
programmable timer
block diagram 5–2
Pulse 5–11
pulse length modulation 5–11
registers
EE1P H–12
EPP C–7
PBPD C–8
PLMA, PLMB 5–11
TPG
MC68HC05B6
INDEX
MOTOROLA
vii
pulse length modulation registers
PLMA, PLMB 5–11
LBCL 6–13
6–11
M
R8 6–11
T8 6–11
WAKE 6–11
Serial communications control register 2
Q
ILIE 6–14
RE 6–15
QFP 12–2
RIE 6–14
RWU 6–15
SBK 6–15
TCIE 6–14
TE 6–14
TIE 6–14
R
R8 – Receive data bit 8 6–11
RAM 3–1
RDI 6–6
Serial communications data register 6–10
Serial communications status register
FE 6–17
RDRF – Receive data register full flag 6–16
RE – receiver enable 6–15
receive data in 6–6
receiver 6–3
register outline 3–8
registers 3–1
IDLE 6–16
NF 6–17
OR 6–17
RDRF 6–16
TC 6–16
TDRE 6–16
RESET 9–3
reset timing diagram 9–1
resets 9–1
,
E–5 F–5
,
serial RAM loader 2–2
,
F–16 H–19
,
RIE – receiver interrupt enable 6–14
ROM 3–1
SFA – Slow or fast mode selection for PLMA 3–10
SFB – Slow or fast mode selection for PLMB 3–10
single chip mode 2–1
,
7–3
7–3
,
RTIM – Reset time C–7
RVU 13–2
,
E–8 F–8
,
SLOW 2–9
RWAT – Watchdog after reset C–7
RWU – receiver wake-up 6–15
,
E–8 F–8
,
SM – Slow mode 3–10 7–3
,
SM – slow mode selection bit 2–9
start bit detection 6–6
STOP 2–6
,
3–7
,
5–12
,
6–21
,
7–4
,
8–6 9–4
,
S
SBK – Send break 6–15
SCI
T
block diagram 6–2
receiver 6–3
sampling technique 6–7
T8 – transmit data bit 8 6–11
TC – Transmit complete flag 6–16
TCIE – Transmit complete interrupt enable 6–14
TDO 6–8
TDRE – Transmit data register empty flag 6–16
TE – Transmitter enable 6–14
TIE – Transmit interrupt enable 6–14
Timer control register
IEDG1 5–5
synchronous transmission 6–9
transmitter 6–3
two-wire system 6–1
SCI interrupts 9–10
SCI registers
BAUD 6–18
SCCR1 6–10
SCCR2 6–14
SCDR 6–10
OCIE 5–4
OLV1 5–5
OLV2 5–5
TOIE 5–4
SCSR 6–16
SCP1, SCP0 – Serial prescaler select bits 6–18
SCR2, SCR1, SCR0 – SCI rate select bits 6–19
SCT2, SCT1, SCT0 – SCI rate select bits 6–18
SDIP 12–3
timer interrupts 9–10
timer state diagrams 5–12
Timer status register
ICF1 5–6
SEC – Secure bit E–9
self-check mode A–5
self-check ROM 3–2
serial bootstrap E–16
,
F–9 H–12
,
ICF2 5–7
OCF1 5–6
OCF2 5–7
TOF 5–6
Serial communications control register 1 6–10
TOF – Timer overflow status flag 5–6
TOIE – Timer overflow interrupt enable 5–4
transmit data out 6–8
CPHA 6–12
CPOL 6–12
TPG
MOTOROLA
viii
INDEX
MC68HC05B6
transmitter 6–3
TSR – Timer status register 5–6
V
verification media 13–2
W
WAIT 2–8
,
3–7
,
5–12
,
6–21
,
7–4
,
8–6
,
9–4
9–4
WAKE – Wake-up mode select 6–11
wake-up
address mark 6–6
idle line 6–6
receiver 6–5
WDOG – Watchdog enable/disable 3–10
WWAT – Watchdog during WAIT mode C–7
,
,
E–8 F–8
,
TPG
MC68HC05B6
INDEX
MOTOROLA
ix
THIS PAGE LEFT BLANK INTENTIONALLY
TPG
MOTOROLA
x
INDEX
MC68HC05B6
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SECTION 2 MODES OF OPERATION AND PIN DESCRIPTIONS
SECTION 3 MEMORY AND REGISTERS
SECTION 4 INPUT/OUTPUT PORTS
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SECTION 5 PROGRAMMABLE TIMER
SECTION 6 SERIAL COMMUNICATIONS INTERFACE
SECTION 7 PULSE LENGTH D/A CONVERTERS
SECTION 8 ANALOG TO DIGITAL CONVERTER
SECTION 9 RESETS AND INTERRUPTS
SECTION 10 CPU CORE AND INSTRUCTION SET
SECTION 11 ELECTRICAL SPECIFICATIONS
SECTION 12 MECHANICAL DATA
SECTION 13 ORDERING INFORMATION
SECTION 14 APPENDICES
SECTION 15 HIGH SPEED OPERATION
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INTRODUCTION
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
1
2
3
INPUT/OUTPUT PORTS
4
PROGRAMMABLE TIMER
5
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
6
7
8
9
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
10
11
12
13
14
15
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
TPG
INTRODUCTION
1
2
MODES OF OPERATION AND PIN DESCRIPTIONS
MEMORY AND REGISTERS
INPUT/OUTPUT PORTS
3
4
PROGRAMMABLE TIMER
5
SERIAL COMMUNICATIONS INTERFACE
PULSE LENGTH D/A CONVERTERS
ANALOG TO DIGITAL CONVERTER
RESETS AND INTERRUPTS
CPU CORE AND INSTRUCTION SET
ELECTRICAL SPECIFICATIONS
MECHANICAL DATA
6
7
8
9
10
11
12
13
14
15
ORDERING INFORMATION
APPENDICES
HIGH SPEED OPERATION
TPG
1
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3
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Motorola > Semiconductors >
68HC705B32 : Microcontroller
Page Contents:
The 68HC705B32 offers EEPROM memory and more I/O including Analog to Digital Convertors (ADC),
Pulse Width Modulators (PWM), and Serial Communications (SCI+).
Features
Documentation
Tools
Block Diagram
Orderable Parts
Related Links
68HC705B32 Features
Other Info:
●
68HC05 CPU
FAQs
❍
❍
❍
32K bytes EPROM
528 bytes RAM
256 bytes of Byte Eraseable EEPROM
3rd Party Design Help
3rd Party Tool
Vendors
●
Timer System
❍
❍
❍
16-bit Timer with Two Input Captures and Two Output Compare
Two Pulse Width Modulation Channels can be used as D/A Converters
Computer Operating Properly Watchdog Timer
3rd Party Trainers
Rate this Page
●
●
●
●
●
8 Channel Analog to Digital Converter (ADC)
24 Bidirectional I/O Lines and 8 Input Only Lines
On-Chip Oscillator with Crystal/Ceramic Resonator
Serial Communications
Asynchronous Serial Communications Interface with Synchronous Master Transmit Capability
(SCI+)
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68HC705B32 Documentation
Documentation
Application Note
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
AN-HK-22
AN-HK-23
AN-HK-24
AN1050_D
AN1055/D
AN1067/D
AN1120/D
MC68HC05SR3 and MC68HC705SR3 Design Notes
MC6805R3 and MC68HC05SR3 Technical Comparison
Software Emulation of DDC1 Hardware Using HC05BD3
0
0
1/01/1994
MOTOROLA
pdf
0
0
0
0
0
0
1
1
1/01/1994
1/01/1994
MOTOROLA
pdf
Designing for Electromagnetic Compatibility (EMC) with
HCMOS Microcontrollers
MOTOROLA
pdf
82
1/01/2000
1/01/1990
-
MOTOROLA
pdf
1048
M6805 16-Bit Support Macros
MOTOROLA
pdf
Pulse Generation and Detection with Microcontroller Units
242
613
5/31/2002
Basic Servo Loop Motor Control Using the MC68HC05B6 MOTOROLA
MCU
11/06/2001
pdf
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
AN1222/D
AN1222SW
AN1259/D
AN1262/D
AN1262SW
AN1263/D
AN1292/D
AN1292SW
AN1516/D
AN1667/D
AN1667SW
AN1688/D
AN1705/D
AN1723/D
AN1734/D
AN1734SW
AN1744/D
AN1752/D
AN1757/D
AN1758/D
AN1771/D
AN1775/D
AN1818/D
AN1820/D
AN1820SW
AN2103/D
AN2159/D
AN2159SW
AN4006/D
Arithmetic Waveform Synthesis with the HC05/08 MCUs
Software Files for AN1222 zipped
pdf
zip
pdf
pdf
zip
pdf
pdf
zip
pdf
pdf
zip
pdf
pdf
pdf
pdf
zip
pdf
pdf
pdf
pdf
pdf
pdf
pdf
pdf
zip
pdf
pdf
zip
pdf
24
20
0
0
0
0
0
0
0
0
2
0
1/01/1993
1/01/1995
1/01/1995
1/01/1995
1/01/1995
1/01/1995
1/01/1996
1/01/1996
1/24/2003
7/10/2002
-
-
-
-
System Design and Layout Techniques for Noise
Reduction in MCU-Based Systems
78
Simple Real-Time Kernels for M68HC05 Microcontrollers
Software files for AN1262
84
11
Designing for Electromagnetic Compatibility with Single-
Chip Microcontrollers
104
155
215
77
Adding a Voice User Interface to M68HC05 Applications
Software files for AN1292 zipped
Liquid Level Control Using a Motorola Pressure Sensor
Software SCI Implementation to the MISC Communication MOTOROLA
Protocol
112
MOTOROLA
Software for AN1667, zip format
93 1.0 7/31/2002
MOTOROLA
MISC Bus Slave Switch Node
243
67
0
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
1
0
7/11/2002
1/01/1999
1/01/1997
1/01/1998
1/01/1997
1/01/1998
5/07/2001
1/01/1998
1/01/1998
1/01/1998
1/01/1998
1/01/1999
1/01/1999
Noise Reduction Techniques for Microcontroller-Based
Systems
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
Interfacing MC68HC05 Microcontrollers to the IBM AT
Keyboard Interface
274
102
2
Pulse Width Modulation Using the 16-Bit Timer
Software files for AN1734 zipped
-
Resetting Microcontrollers During Power Transitions
Data Structures for 8-Bit Microcontrollers
Add a Unique Silicon Serial Number to the HC05
Add Addressable Switches to the HC05
80
213
105
111
250
86
Precision Sine-Wave Tone Synthesis Using 8-Bit MCUs
Expanding Digital Input with an A/D Converter
Software SCI Routines with the 16-Bit Timer Module
Software I2C Communications
84
55
Software files for AN1820 zipped
2
1/01/1998
-
-
12/01/2000
Local Interconnect Network (LIN) Demonstration
953
129
182
61
Digital Direct Current Ignition System Using HC08
Microcontrollers
11/20/2001
AN2159SW
3/08/2002
3/27/2000
Digital Captive Discharge Ignition System Using
HC05/HC08 8-Bit Microcontrollers
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
1134
AN442/D
AN463/D
AN464/D
AN477/D
AN499/D
AN991/D
ANE416/D
Driving LCDs with M6805 Microprocessors
68HC05K0 Infra-red Remote Control
pdf
pdf
pdf
pdf
pdf
pdf
pdf
0
0
0
0
0
1
0
1/01/1991
1/01/1992
1/01/1993
1/01/1993
7/01/1996
1/28/2002
1/01/1988
111
Software Driver Routines for the Motorola MC68HC05
CAN Module
2859
Simple A/D for MCUs without Built-In A/D Converters
Let the MC68HC705 Program Itself
224
154
Using the Serial Peripheral Interface to Communicate
Between Multiple Microcomputers
251
1958
MC68HC05B4 Radio Synthesizer
Brochure
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
5/21/2003
BR68HC08FAMAM/D
FLYREMBEDFLASH/D
68HC08 Family: High Performance and Flexibility
57
2
Embedded Flash: Changing the Technology World for MOTOROLA
the Better
5/21/2003
pdf
68
2
Data Sheets
Date
Size Rev
Order
ID
Name
Vendor ID Format
Last
K
#
Availability
Modified
MC68HC05B4/705B5/05B6/05B8/(7)05B16/705B16N/(7)05B32 MOTOROLA
Technical Data
1/01/1999
MC68HC05B6
pdf
0
4
Engineering Bulletin
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
System Design Considerations: Converting from the
MC68HC805B6 to the MC68HC705B16 Microcontroller
MOTOROLA
pdf
757
1/01/1993
EB166/D
EB180/D
EB181/D
EB349/D
EB396/D
EB413/D
EB421/D
0
Differences between the MC68HC705B16 and the
MC68HC705B16N
MOTOROLA
pdf
1/01/1996
1/01/1997
6/22/2000
6/19/2002
1/01/2000
2/23/2000
20
0
0
1
0
0
0
Frequently Asked Questions and Answers for the
M68HC05 Family MCAN Module
MOTOROLA
pdf
181
RAM Data Retention Considerations for Motorola
Microcontrollers
MOTOROLA
pdf
45
49
62
78
Use of OSC2/XTAL as a Clock Output on Motorola
Microcontrollers
MOTOROLA
pdf
MOTOROLA
pdf
Resetting MCUs
MOTOROLA
pdf
The Motorola MCAN Module
Fact Sheets
Date Last
Modified
ID
Name
Vendor ID
Format Size K Rev #
Order Availability
CWDEVSTUDFACTHC08
Development Studio
MOTOROLA
pdf
48
2
5/13/2002
-
Product Change Notices
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
14X14 QFP ASSY MOVE FROM SHC TO KLM, PT 1 OF 2 MOTOROLA
8/05/2002
-
PCN7855
htm
24
0
Reference Manual
ID
Size Rev Date Last
Order
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
2866
1/01/1998
M68HC05TB/D
HC05 Family - Understanding Small Microcontrollers
2
MC68HC05C4, C8, C9, MC68HC705C8,
MC68HC805C4, MC68HCL05C4, C8, MC68HSC05C4,
C8 Programming Reference
MC68HC05CXRG/D
MOTOROLA
pdf
3150
2/23/2000
-
1
Selector Guide
Size Rev Date Last
Order
ID
Name
Vendor ID Format
K
#
Modified Availability
MOTOROLA
pdf
579
10/24/2003
SG1002
SG1006
SG1010
SG1011
SG2000CR
SG2039
Analog Selector Guide - Quarter 4, 2003
Microcontrollers Selector Guide - Quarter 4, 2003
Sensors Selector Guide - Quarter 4, 2003
0
MOTOROLA
pdf
826
219
287
10/24/2003
10/24/2003
10/24/2003
11/11/2003
0
0
0
3
0
MOTOROLA
pdf
Software and Development Tools Selector Guide - Quarter MOTOROLA
4, 2003
pdf
pdf
pdf
MOTOROLA
Application Selector Guide Index and Cross-Reference.
95
0
Application Selector Guide - Vacuum Cleaners Vacuum
Cleaners
MOTOROLA
6/17/2003
Return to Top
68HC705B32 Tools
Hardware Tools
Emulators/Probes/Wigglers
ID
Name
Vendor ID
HITEX
ISYS
Format
Size K Rev #
Order Availability
AX-6811
IC10000
IC20000
IC40000
AX-6811
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
iC1000 PowerEmulator
iC2000 PowerEmulator
iC4000 ActiveEmulator
ISYS
ISYS
Evaluation/Development Boards and Systems
ID
Name
Vendor ID
Format Size K Rev # Order Availability
KITMMDS05B
Modular Development System (MMDS) Kits
MOTOROLA
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
KITMMEVS05B
M68CBL05B
M68CBL05C
M68ICS05B
Modular Evaluation System (MMEVS)
Low-noise Flex Cable
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
METROWERKS
Low-noise Flex Cable
In-Circuit Simulator for 68HC05B and 68HC705B
Emulation Module
M68EM05B32
Programmers
ID
Name
Vendor ID
SYSGEN
Format
Size K Rev #
Order Availability
POWERLAB
Universal Programmer
-
-
-
-
Software
Application Software
Code Examples
Size Rev
Order
Availability
ID
Name
Vendor ID Format
K
#
HC05 Software Example: Home Thermostat example using the MOTOROLA
705C8 with indoor/outdoor temperature and time of day
C8THERMSW
FLOAT05COD
HC05DELAYSW
zip
zip
zip
zip
zip
11
-
-
-
-
-
-
MOTOROLA
Floating Point routines
13
2
-
-
-
-
HC05 Software Example: Subroutine that delays for a whole
number of milliseconds
MOTOROLA
Library containing software examples in assembly for 68HC05 MOTOROLA
HC05EXSW
45
7
HC05KEYINTSW
HC05 Software Examples: Using keyboard interrupts and
decoding a matrix keypad
MOTOROLA
MOTOROLA
HC05 Software Example: Keypad debounce and decode.
When a key is found, it is changed to ASCII and displayed on
an LCD
HC05KEYPADSW
zip
2
-
-
HC05 Software Example: Initializes an LCD and displays
ABCDEF...S
MOTOROLA
MOTOROLA
MOTOROLA
HC05LCDSW
HC05SCISW
zip
zip
zip
1
1
1
-
-
-
-
-
-
HC05 Software Example: Serial Communications Interface
example
HC05SPISW
HC05 Software Example: Serial Peripheral Interface example
HC05 Software Example: Simple program that reads the state
of a switch on a general-purpose I/O pin and lights an LED
based on the state of the switch
HC05SWITCHSW
MOTOROLA
MOTOROLA
MOTOROLA
zip
zip
zip
1
1
1
-
-
-
-
-
-
HC05TIMERSW
J1APWMSW
HC05 Software Example: Using the 68HC05 16-bit Timer
HC05 Software Example: Low frequency PWM example using
the 68HC705J1A real-time interrupt and timer overflow
interrupt
HC05 Software example: Software UART example that
transmits and receives data on the 68HC705J1A
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
MOTOROLA
J1AUARTSW
K1THERMSW
MATH16ACOD
zip
zip
2
5
-
-
-
-
-
-
-
-
-
-
-
-
HC05 Software Example: Thermometer project using the
68HC705K1
General Math routines
General Math routines
Example routines
asm
asm
exe
zip
4
MATHAGBCOD
6
SAMPPROGCOD
35
11
THERM-CCOD
Thermometer example in C
Software Tools
Assemblers
Order
Availability
ID
Name
Vendor ID Format Size K Rev #
ASHC5ASM
AX6805
DOS based freeware assembler
MOTOROLA
COSMIC
arc
-
55
-
0
-
-
-
AX6805 relocatable/absolute macro assembler for HC05
Compilers
ID
Name
Vendor ID
Format Size K Rev # Order Availability
CWHC05
CX6805
METROWERKS
COSMIC
CodeWarrior Development Tools for HC05
CX6805 C Cross Compiler for HC05
-
-
-
-
-
-
-
Debuggers
ID
Name
Vendor ID
Format Size K Rev # Order Availability
CWHC05
METROWERKS
CodeWarrior Development Tools for HC05
-
-
-
ZAP 6805 MMDS
COSMIC
COSMIC
HITEX
ZAP 6805 MMDS Debugger
ZAP 6805 Simulator Debugger
AX-6811
-
-
-
-
-
-
-
-
-
-
-
-
ZAP 6805 SIM
AX-6811
IDE (Integrated Development Environment)
Order
Availability
ID
Name
Vendor ID
Format Size K Rev #
CWHC05
METROWERKS
CodeWarrior Development Tools for HC05
-
-
-
IDEA05
COSMIC
ISYS
IDEA05 integrated development environment for HC05
winIDEA
-
-
-
-
-
-
-
-
IC-SW-OPR
Models
Instruction Set Simulator
Size Rev
Order
Availability
ID
Name
Vendor ID Format
PEMICRO
K
#
PE68HC05SIM
Windows upgrades for P&E's simulator software for 68HC05
html
0
-
-
Performance and Testing
ID
Name
Vendor ID
Format
Size K
Rev #
Order Availability
AX-6811
HITEX
AX-6811
-
-
-
-
Return to Top
Orderable Parts Information
Budgetary
Price
QTY 1000+
($US)
Tape
and
Reel
Additional
Info
Order
Availability
Life Cycle Description (code)
PartNumber
Package Info
PRODUCT
MATURITY/SATURATION(4)
PSDIP 56
PSDIP 56
PLCC 52
more
more
more
XC68HC705B32B
XC68HC705B32CB
XC68HC705B32CFN
No
No
No
$10.95
$10.95
$10.95
PRODUCT
MATURITY/SATURATION(4)
PRODUCT
MATURITY/SATURATION(4)
QFP 64
14*14*2.1P0.8
PRODUCT
MATURITY/SATURATION(4)
more
XC68HC705B32CFU
No
$10.95
NOTE: Are you looking for an obsolete orderable part? Click HERE to check our distributors' inventory.
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