BD12801MUF-M [ROHM]
BD12801MUF-M是一款16通道恒流驱动器，具有13bit PWM调光和8bit局部DC调光通道。可通过SPI与微控制器通信。;
| 型号： | BD12801MUF-M |
| 厂家： | 
ROHM |
| 描述： | BD12801MUF-M是一款16通道恒流驱动器，具有13bit PWM调光和8bit局部DC调光通道。可通过SPI与微控制器通信。 通信 驱动 控制器 微控制器 驱动器 |
| 文件： | 总68页 (文件大小：1435K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Automotive LED Driver Series
16-channel Constant Current Driver
Embedded Automotive Backlight LED Driver
BD12801MUF-M
General Description
Key Specifications
BD12801MUF-M is 16-channel constant current driver
with 13 bit PWM dimming and 8 bit local DC dimming
individual channels. Communication with µController via
SPI is feasible.
◼Power Supply Voltage Range:
◼LED Output Current Range:
◼Operating Temperature Range:
3.0 V to 5.5 V
20 mA to 130 mA
-40 °C to +125 °C
Package
VQFN48FAV070
W (Typ) x D (Typ) x H (Max)
7.0 mm x 7.0 mm x 1.0 mm
Features
◼AEC-Q100 Qualified(Note 1)
◼Integrated 16-channel 20 V LED Constant Current
Driver
◼SPI Interface
◼Independent 13 bit PWM Dimming Function
◼Independent 8 bit Local DC Dimming Function
◼Independent 8 bit Phase Shift Function
◼LSI Protection Function (UVLO, TSD, ISETSCP)
◼LED Abnormality Detection Function (Open/Short)
◼Integrated Abnormality Output FAIL Pin
◼Cascade Connection Feasible
(Note 1) Grade 1
Applications
◼Cluster, Center Infotainment Display
◼Other Automotive Backlights
Typical Application Circuit
・・・
Buck
Buck-Boost DC/DC
Converter
VCC
LED1
LED2
LED3
LED4
LED5
EN
VREG33
LED6
LED7
SDI
LED8
LED9
SCLK
LED10
LED11
SCSB
BD12801MUF-M
SDO
LED12
LED13
LED14
VREG33
FAIL
LED15
LED16
VSYNC
EXTCLK
LGND
ISET
TEST1 TEST2
GND
〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.
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BD12801MUF-M
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Contents .........................................................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Block Diagram ................................................................................................................................................................................5
Description of Blocks ......................................................................................................................................................................6
Absolute Maximum Ratings ............................................................................................................................................................9
Thermal Resistance........................................................................................................................................................................9
Recommended Operating Conditions...........................................................................................................................................10
Electrical Characteristics...............................................................................................................................................................10
Typical Performance Curves.........................................................................................................................................................12
Functions of Logic Blocks .............................................................................................................................................................14
Timing Chart .................................................................................................................................................................................40
Application Examples ...................................................................................................................................................................59
I/O Equivalence Circuit .................................................................................................................................................................60
Operational Notes.........................................................................................................................................................................61
Ordering Information.....................................................................................................................................................................63
Marking Diagram ..........................................................................................................................................................................63
Physical Dimension and Packing Information...............................................................................................................................64
Revision History............................................................................................................................................................................65
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Pin Configuration
(TOP VIEW)
EXP-PAD (Note 1)
EXP-PAD (Note 1)
N.C.
N.C.
LED10
LED9
37
38
39
40
41
42
43
44
24
23
N.C.
22 N.C.
ISET
21 LGND
VREG33
VCC
N.C.
20
19
18
17
16
15
14
13
TEST2
TEST1
SDO
EN
GND
LGND
N.C.
FAIL 45
SCSB
SDI
46
47
48
LED8
LED7
EXP-PAD
SCLK
EXP-PAD (Note 1)
EXP-PAD (Note 1)
(Note 1) EXP-PAD on the corner is comprised of three electrodes and is short-circuited inside.
Pin Descriptions
Pin No.
1
Pin Name
EXTCLK
Function
EXTCLK signal pin. Input the frequency 8,192 times of VSYNC (PWMFREQ[1:0] = 0).
2
3
VSYNC
N.C.
VSYNC signal pin
-
4
LED1
LED2
LED3
LED4
N.C.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
-
5
6
7
8
9
LGND
N.C.
Analog GND for constant current driver block
-
10
11
12
13
14
15
16
LED5
LED6
LED7
LED8
N.C.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
-
LGND
Analog GND for constant current driver block
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Pin Descriptions - continued
Pin No.
17
Pin Name
SDO
Function
Data output pin.
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
TEST1
TEST2
N.C.
TEST mode output pin. Set this pin open.
TEST mode input pin. Connect to GND.
-
LGND
N.C.
Analog GND for constant current driver block
-
LED9
LED10
LED11
LED12
N.C.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
-
LGND
N.C.
Analog GND for constant current driver block
-
LED13
LED14
LED15
LED16
N.C.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
Constant current output pin. Connect to LED cathode.
-
N.C.
-
N.C.
-
N.C.
-
N.C.
-
N.C.
-
ISET
LED current setting pin. LED current is set by resistor connected to GND.
VREG33
VCC
Output 3.3 V constant voltage
Power supply pin
EN
Engage Standby-mode with VEN = Low. Operation mode with VEN = High.
GND
Small signal GND
Abnormal detection output pin
Chip select setting pin
Data input pin
FAIL
SCSB
SDI
SCLK
CLK input pin
Exposed Pad. Connect center EXP-PAD to the internal PCB ground plane using multiple via, it
will provide excellent heat dissipation characteristics.
-
EXP-PAD
(Note) LED1 to LED16 are defined as LEDn (n = 1 to 16) from this page.
If there is no use LEDn channel, set open for the pin. If LEDn pin connects to GND, standby current isn’t 0 µA (Typ) because there is a current path.
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Block Diagram
VCC
EN
VCCUVLO
＋
－
Band
Gap
Voltage
3.3 V
REG
VREG33UVLO
TSD
ISET
ISET SHORT DET
VREG33
VCC
Constant Current Driver
DTY01[12:0]
13
LED1
LED OPEN DET
LED SHORT DET
Thermal Warning
LCDAC1[7:0]
SDI
8
ERLOP[0]
ERLSH[0]
・
・
・
WARTSD[0]
SCLK
・
・
・
DTY13[12:0]
13
SCSB
SDO
LED13
LED14
LED15
LED16
LED OPEN DET
LED SHORT DET
Thermal Warning
LCDAC13[7:0]
8
Level
Shifter
ERLOP[12]
ERLSH[12]
WARTSD[12]
DTY14[12:0]
13
LOGIC
Control
LED OPEN DET
LED SHORT DET
Thermal Warning
LCDAC14[7:0]
VSYNC
8
ERLOP[13]
ERLSH[13]
WARTSD[13]
EXTCLK
DTY15[12:0]
13
LED OPEN DET
LED SHORT DET
Thermal Warning
LCDAC15[7:0]
8
ERLOP[14]
PROTECT
LOGIC
ERLSH[14]
FAIL
WARTSD[14]
DTY16[12:0]
13
LED OPEN DET
LED SHORT DET
Thermal Warning
LCDAC16[7:0]
TEST1
TEST2
TEST
MODE
LOGIC
8
ERLOP[15]
ERLSH[15]
WARTSD[15]
LGND
GND
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Description of Blocks
If there is no description, the mentioned values are typical value.
1. Reference Voltage (3.3V REG)
3.3V REG Block generates 3.3 V at EN = High, and outputs to the VREG33 pin. This voltage (VVREG33) is used as I/O
interface power supply for internal circuit. The VREG33 pin has UVLO function, and it starts operation at VCC ≥ 2.8 V and
VVREG33 ≥ 2.7 V and stops when at VCC ≤ 2.7 V or VVREG33 ≤ 2.6 V. About the condition to release/detect VVREG33 voltage,
refer to Table 1. Protection Table. Connect a ceramic capacitor (CVREG33) to the VREG33 pin for phase margin. CVREG33
range is 1.0 µF to 4.7 µF and recommended value is 2.2 µF. If the CVREG33 is not connected, it might occur unstable
operation e.g. oscillation. In addition, VREG33 pin has the over current protection function. If the load current of
VREG33 pin exceeds 15 mA, the voltage drops. The following diagram shows the power supply system of MCU and
LED Driver. Select the suitable connection in accord with application structure.
Case 1: A power supply of MCU and LED Driver are different.
Case 2: A power supply of MCU and LED Driver are same.
3.3 V
MCU
5.0 V
VCC
3.3 V
5.0 V
MCU
VCC
VCC
SPI
SPI
SPI
VREG33
BD12801MUF-M
MCU
BD12801MUF-M
BD12801MUF-M
VREG33
VREG33
OCP in VREG33 is not activated.
Figure 1. VCC Pin and VREG33 Pin Connection
2. Constant Current Driver
This device integrates 16-channel constant current driver. Constant current drivers capability is defined by supply
voltage thus with VCC ≥ 4.2 V will be 130 mA/ch and with 3.0 V ≤ VCC < 4.2 V will be 100 mA/ch. Also 13 bit PWM
dimming function, 8 bit DC dimming function, 8 bit phase shift function are built in for independent channel.
(1) Maximum LED Output Current Setting (RISET
)
1000
100
LED
Driver
LEDn
(n=1 to 16)
10
1
10
100
ISET
RISET [kΩ]
RISET
Figure 2. ILEDMAX vs RISET
Figure 3. ISET Block Diagram
The Maximum LED Output Current ILEDMAX can be obtained by the following equation.
퐼퐿퐸퐷푀퐴푋 = 757/푅ꢀ푆퐸푇
[A]
The operating range of the RISET value is from 6.3 kΩ to 30 kΩ. Additionally, the RISET value could not be changed
during operation. In this IC, ISET SHORT protection is built-in to protect an LED element from excess current when
the ISET pin and GND are shorted. If the RISETSCP is 2.2 kΩ (Typ) or less, the IC detects ISET SHORT protection
and LED current is turned off.
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2. Constant Current Driver - continued
(2) Local DC Dimming Control
Integrates 8 bit DC dimming function LCDACn[7:0], which controls LED current of each channel by SPI input from
the defined LED current by RISET. LED current under DC dimming can be calculated in below equation.
{( }
[
]
)
퐼퐿퐸퐷푛 = 퐼퐿퐸퐷푀퐴푋 × ꢁ퐶ꢂꢃ퐶ꢄ 7: 0 + 1 /256
>
0.02 [A] (ꢄ = 1 푡표 16)
In instance when RISET = 6.3 kΩ and LCDACn[7:0] = 0xFF, LED current will be 120 mA. As minimum LED current of
the device is minimum 20 mA, LCDACn[7:0] should be set from 0x2A to 0xFF. Note that LCDACn[7:0] minimum bit
cannot be set due to minimum current 20 mA. Step width will be 0.47 mA ( = 120 mA / 256 ). On the other hand RISET
= 19 kΩ and LCDACn[7:0] = 0xFF will set LED current as 40 mA, LCDACn[7:0] should be set from 0x80 to 0xFF.
Step width will be 0.156 mA ( = 40 mA / 256). LCDACn[7:0] setting range will differ by RISET
.
(3) Local PWM Dimming Control
PWM dimming frequency, pulse width, and phase shift can be controlled by SPI input. Constant current driver can be
controlled synchronized to PWM for independent channel set by SPI.
However constant current driver’s minimum pulse width depends on LED current value. When LED current value is
80 mA or more, set the minimum pulse width to more than 0.6 µs. If LED current value is less than 80 mA, set the
minimum pulse width to more than 2 µs. For example with PWM frequency 200 Hz at LED current of 100 mA setting,
it’s possible to set with 13 bit full range of PWM duty. Average LED current under PWM dimming can be calculated in
below equation.
{( }
[
]
)
퐼퐿퐸퐷푛_퐴푉퐸 = 퐼퐿퐸퐷푛 × ꢂꢅ푌ꢄ 12: 0 + 1 / 8,192
[A] (ꢄ = 1 푡표 16)
(4) Local Phase Shift Control
This device integrates 8 bit Phase Shift function. Control by independent channel based on set PWM cycle is
feasible. In case PWM frequency is 200 Hz, shift rate per channel can be set by about 20 µs steps. Refer to Figure 4.
To summarize (1) to (3), the LED current setting, PWM dimming, DC dimming are schematically shown as Figure 5.
LED Current
1 ms/div
ILED1 (50 mA/div)
Maximum setting
130 mA
(A)
ILEDMAX
ILED2(50 mA/div)
(B)
ILEDn
ILED3 (50 mA/div)
Minimum Setting
20 mA
t
(C)
Figure 4. Local Phase Shift Control
Figure 5. Setting Range by Dimming Method
(A) ILEDMAX is set to the maximum LED current value
from 20 mA to 130 mA by RISET
.
(B) When ILEDMAX is set to 80 mA by RISET, DC dimming
range is limited from 64 to 256 because of
minimum LED current setting 20 mA.
(C) PWM dimming can be controlled by 13 bit range.
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Description of Blocks - continued
3. Protection Feature
Table 1. Protection Table
Error Setting(Note 4)
Error
Protection
Error Flag
FAIL(Note 6)
Protection Name
Recommend Operation
Detection
Condition
Release
Condition
Pin
SSMASK
ERRMASK
ERRLAT
Error Register
Clear Condition
Enable
DTYENn = 1
and
LEDOPEN = 1
and
DTYENn = 0
or
LEDOPEN = 0
or
Protection released
(ERRLAT = 0)
or
target LEDn(Note 3) OFF
(DTYENn(Note 3) = 0)
LEDn(Note 3)
LED OPEN
LEDOPEN
O
O
O
ERLOP[15:0]
Low
[ PWMn = High
[ PWMn = High
ERRCLR
and
(Note 3)
and
(ERRLAT = 1)
(Note 3)
VLEDn
≤ 0.2 V]
VLEDn
> 0.2 V]
ꢀ
DTYENn = 1
and
LEDSHEN = 1
and
DTYENn = 0
or
LEDSHEN = 0
or
[ PWMn = High
and
VLEDn(Note 3) < register
setting ]
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
target LEDn(Note 3) OFF
(DTYENn(Note 3) = 0)
LEDn(Note 3)
LEDn(Note 3)
ISET
LED SHORT
LEDSHEN
LEDOPEN
-
O
O
O
O
O
O
ERLSH[15:0]
Low
[ PWMn = High
and
(Note 3)
VLEDn
≥ register
setting ]
DTYENn = 0
and
LEDOPEN = 1
TSD detect
or
EN detect
or
TSD detect
or
EN detect
or
and
LED SCP(Note 1)
(Note 3)
All LEDn(Note 3) OFF
-
-
WARSCP
VSYNC
VLEDn
≤ 0.2 Vduring
VCCUVLO detect
or
VREG33UVLO detect
VCCUVLO detect
or
VREG33UVLO detect
SCP setting time
(after detecting LED Open
Error)
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
LED1 to 16 OFF
(automaticaly)
RSETSCP ≤ 2.2 kΩ
ISET SHORT
RSETSCP > 2.2 kΩ
-
O
WARISET
Low
Protection released
(ERRLAT = 0)
or
ERRCLR
(ERRLAT = 1)
WARTSD[15:0]
(Note 2)
target LEDn OFF
(DTYENn(Note 3) = 0)
Tj ≥ 135 °C
Tj ≤ 125 °C
Thermal Warning
-
TSDWEN
-
O
Low
Low
All block initialized
(automaticaly)
TSD(Note 5)
-
Tj ≥ 175 °C
VCC ≤ 2.7 V
Tj ≤ 150 °C
VCC ≥ 2.8 V
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Protection released
High
(Hi-z)
High
(Hi-z)
All block initialized
(automaticaly)
All block initialized
(automaticaly)
VCCUVLO(Note 5)
VREG33UVLO(Note 5)
VCC
-
-
VREG33
VVREG33 ≤ 2.6 V
VVREG33 ≥ 2.7 V
(Note 1) It can’t detect “SCP error” if LEDn (n = 1 to 16) pin shorts GND before setting DTYEN = 1 and detecting “LED open error”. This function is available after
detecting “LED open error”.
(Note 2) WARTSD[n-1]: monitor LEDn
(Note 3) n = 1 to 16
(Note 4) O: It has this function. -: It doesn’t have this function.
(Note 5) When it detects “VREG33UVLO” or “VCCUVLO” or “TSD” or “EN”, it can’t detect other protection.
(Note 6) The FAIL pin is recommended to pull up to VVREG33. Recommended value for pull up resistance is 20 kΩ to 100 kΩ.
When above failure is detected, the FAIL pin voltage becomes Low. If the FAIL pin is not used pin, it shall be kept open or short to GND.
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BD12801MUF-M
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
VCC
Rating
Unit
V
Power Supply Voltage
EN Pin Voltage
-0.3 to +7.0
-0.2 to +7.0
-0.2 to +20.0
-0.3 to +7.0
VEN
V
LED1 to LED16 Pin Voltage
VLED1 to VLED16
VFAIL
V
FAIL Pin Voltage
V
VREG33, SCSB, SCLK, SDI, SDO,
VSYNC, EXTCLK, TEST1, TEST2,
ISET Pin Voltage
VVREG33, VSCSB, VSCLK, VSDI, VSDO, VVSYNC, VEXTCLK
VTEST1, VTEST2, VISET
,
-0.2 to +7.0
V
Storage Temperature Range
Tstg
-55 to +150
150
°C
°C
Maximum Junction Temperature
Tjmax
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
VQFN48FAV070
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
71.4
6.0
24.2
3.0
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A (Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-5, 7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70 μm
Footprints and Traces
Layer Number of
Measurement Board
Thermal Via(Note 5)
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
Footprints and Traces
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 5) This thermal via connects with the copper pattern of all layers.
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Recommended Operating Conditions
Parameter
Symbol
Min
3.0
1.0
6.3
20
Typ
Max
5.5
Unit
V
Condition
Power Supply Voltage
VCC
CVREG33
RISET
5.0
2.2
4.7
µF
kΩ
kΩ
kHz
%
VREG33 Pin Connect Capacitance
ISET Pin Connection Resistance
-
30.0
100
5,000.0
60
FAIL Pin Connection Resistance
EXTCLK Frequency
RFAIL
fEXTCLK
-
409.6
40
-
-
EXTCLK Duty
DEXTCLK
fVSYNCCLK
tVSYNCMIN
ILEDMAX1
ILEDMAX2
Topr
VSYNC Frequency
50
-
600
-
Hz
µs
VSYNC Minimum Pulse Width
LEDn Output Current 1
LEDn Output Current 2
Operating Temperature
50
-
20
-
-
100
130
+125
mA
mA
°C
3.0 V ≤ VCC < 4.2 V
VCC ≥ 4.2 V
20
-40
+25
(Note) Above operation range is referring to IC independently. Thorough verification of the coefficient setting in actual application shall be practiced.
Electrical Characteristics
(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Parameter
[Device Overview]
Symbol
Min
Typ
Max
Unit
Condition
VEN = High,
All Current drivers are OFF
Circuit Current
ICC
-
-
5.5
0
15.0
300
mA
µA
Standby Current
ISTB
VEN = Low
[VREG33 Block]
VCC = 3.5 V to 5.5 V,
IVREG33 = 0 mA
VCC = 3.5 V to 5.5 V,
IVREG33 = -5 mA
VREG33 Pin Output Voltage
VVREG33
ΔVVREG33
IVREG33OCP
3.1
-
3.3
30
-
3.5
80
-
V
VREG33 Pin
Load Regulation Voltage
VREG33 Pin
mV
mA
10
VCC = 5.0 V
Over Current Protection
[PROTECT LOGIC Block]
VCCUVLO Detection Voltage
VCCUVLO Hysteresis Voltage
VREG33UVLO Detection Voltage
VREG33UVLO Hysteresis Voltage
LED OPEN Detection Voltage
LED SHORT Detection Voltage
VVCCUVLO
VVCCUHYS
VVREG33UVLO
VVREG33UHYS
VOPDET
2.55
-
2.70
100
2.60
100
0.2
2.85
-
V
mV
V
VCC: SWEEP DOWN
2.40
-
2.80
-
VVREG33: SWEEP DOWN
mV
V
0.1
4.5
0.3
5.1
VLEDn: SWEEP UP
LEDSH = 0xF
VSHDET
4.8
V
ISET GND Short Detection
Resistance
Thermal Warning Monitor Detection
Temperature
Thermal Warning Monitor
Hysteresis Width
RSETSCP
tMON
0.7
2.2
135
10
4.3
kΩ
°C
°C
-
-
-
-
tMONHYS
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Electrical Characteristics - continued
(Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Parameter
Symbol
Min
Typ
Max
Unit
Condition
[Constant Current Driver Block]
ISET Pin Reference Voltage
LEDn Pin ON Resistance
VISET
RLED1
IOUT1
-
-
0.606
-
V
Ω
-
6.5
106
+4
LEDn Pin Output Current1(Note 1)
94
-4
100
mA
%
-
-
Ta = 25 °C, VCC = 5 V
Ta = 25 °C, VCC = 5 V
LEDn Pin Output Current
Absolute Error1(Note 1)
ΔIOUTA1
-6
+6
%
-4
-
+4
%
LEDn Pin Output Current
Relative Error1(Note 1)
ΔIOUTR1
IOUT2
-6
-
+6
%
LEDn Pin Output Current2(Note 2)
45
-6
50
-
55
mA
%
+6
Ta = 25 °C, VCC = 5 V
Ta = 25 °C, VCC = 5 V
LEDn Pin Output Current
Absolute Error2(Note 2)
ΔIOUTA2
-7.5
-6
-
+7.5
+6
%
-
%
LEDn Pin Output Current
Relative Error2(Note 3)
ΔIOUTR2
-7.5
-
+7.5
%
[EN Input Pin]
EN Pin Input Current
IEN
18
30
-
50
µA
V
VEN = 3.0 V
0.8 x
VVREG33
VVREG33
+ 0.2
+0.2 x
VVREG33
EN Pin Input High Voltage
EN Pin Input Low Voltage
VENH
VENL
-0.2
-
V
[LOGIC Input (SCSB, SCLK, SDI, EXTCLK, VSYNC)]
LOGIC Pin Input Current
IIN
-1
0
-
+1
µA
V
VIN = VCC
0.8 x
VVREG33
VVREG33
+ 0.2
LOGIC Pin Input High Voltage
VINH
+0.2 x
VVREG33
LOGIC Pin Input Low Voltage
[LOGIC Output Block (SDO)]
SDO Pin Output High Voltage
VINL
-0.2
-
V
VVREG33
-0.2
VVREG33
+0.2
VSDOH
VSDOL
-
-
V
V
ISDO = -1 mA
ISDO = +1 mA
SDO Pin Output Low Voltage
[FAIL Output Block]
-
0.2
FAIL Pin ON Resistance
FAIL Pin Leak Current
RFAIL
0.5
-
1.0
-
2.0
0.1
kΩ
µA
IFAIL = +1 mA
VFAIL = 5.0 V
ILEAKFAIL
(Note 1) RISET = 7.5 kΩ, VLEDn = 0.65 V, SDI = w(0x18,0xFF), w(0x19,0x3F)
(Note 2) RISET = 15 kΩ, VLEDn = 0.65 V, SDI = w(0x18,0xFF), w(0x19,0x3F)
(Note 3) VLEDn describes either pin of LED1 to LED16 voltage.
ILEDn describes either pin of LED1 to LED16 current.
ΔIOUTA1 = (ILEDn/0.1 - 1) x 100
ΔIOUTR1 = (ILEDn/ILED_AVE - 1) x 100
ILED_AVE describes the average current of LED1 to LED16.
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BD12801MUF-M
Typical Performance Curves
200
175
150
125
100
75
12
10
8
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
6
4
50
2
25
0
0
0
1
2
3
4
5
0
1
2
3
4
5
Power Supply Voltage: VCC [V]
Power Supply Voltage: VCC [V]
Figure 6. Standby Current
vs Power Supply Voltage
Figure 7. Circuit Current vs Power Supply Voltage
(VEN = High)
0.30
3.50
3.45
3.40
3.35
3.30
3.25
3.20
3.15
3.10
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
0.28
0.26
0.24
0.22
0.20
0.18
0.16
0.14
0.12
0.10
-40 -20 +0 +20 +40 +60 +80 +100+120
-40 -20 +0 +20 +40 +60 +80 +100 +120
Temperature [°C]
Temperature [°C]
Figure 8. VREG33 Pin Output Voltage
vs Temperature
Figure 9. LED OPEN Detection Voltage
vs Temperature
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Typical Performance Curves - continued
5.1
105
104
103
102
101
100
99
VCC = 3.3 V
VCC = 3.3 V
VCC = 5.0 V
VCC = 5.5 V
VCC = 5.0 V
VCC = 5.5 V
5.0
4.9
4.8
4.7
4.6
4.5
98
RISET = 7.5 kΩ
97
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
96
95
-40 -20 +0 +20 +40 +60 +80 +100 +120
-40 -20 +0 +20 +40 +60 +80 +100 +120
Temperature [°C]
Temperature [°C]
Figure 10. LED SHORT Detection Voltage
vs Temperature
Figure 11. LEDn Pin Output Current1 vs Temperature
120
100
80
60
40
20
0
120
100
80
Ta = -40 °C
Ta = +25 °C
Ta = +125 °C
Ta = -40 °C
60
40
20
0
Ta = +25 °C
Ta = +125 °C
RISET = 7.5 kΩ
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
RISET = 7.5 kΩ
VLED1 = 0.65 V
SDI = w(0x18,0xFF)
w(0x19,0x3F)
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8
LEDn Pin Voltage [V]
LED Pin Voltage [V]
Figure 12. LEDn Pin Output Current1 vs LED Pin Voltage
(VCC = 3.3 V)
Figure 13. LEDn Pin Output Current1 vs LED Pin Voltage
(VCC = 5.0 V)
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Functions of Logic Blocks
1. Serial Interface and AC Electrical Characteristics
Serial Peripheral Interface (SPI) controls the IC with SCSB, SCLK, SDI, and SDO signals.
Start the SPI communication with the initial value of SCSB is ‘High’, and that of SCLK and SDI is ‘Low’.
When using several devices, connect the SDO pin to the SDI pin of the next device to make cascade connection.
SDO signal is output after SDI input from 8 datas. Example of the n byte Write is shown in the following.
SDO is in the state of output the signals. (initial value is ‘Low’)
SCSB
･･････････
1st 2nd 3rd 4th 5th 6th 7th 8th
SCLK
SDI
･･････････
･･････････
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
RA RA RA RA RA RA RA DT DT DT DT DT DT DT DT
[6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
B
S
RW
DevAddr[5:0]
8 bits
NumOfData[6:0]
8 bits
RegAddr[6:0]
8 bits
Data1[7:0]
8 bits
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
RA RA RA RA RA RA RA DT
[6] [5] [4] [3] [2] [1] [0] [7]
B
S
Lowꢀ
RW
SDO
･･････････
･･････････
･･････････
B:
S:
Broadcast
Single
DT DT DT DT DT DT DT DT DT DT DT
[2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
RW:
Read / Write
Device Address
Number Of Data
Register Address
Data
･･････････
DA[5:0]:
ND[7:0]:
RA[6:0]:
DT[7:0]:
Data[7:0]
DT DT DT DT DT DT DT DT
[6] [5] [4] [3] [2] [1] [0] [7]
Lowꢀ
･･････････
Figure 14. SPI Protocol (Write)
SCSB
SCLK
SDI
･･････････
･･････････
1st 2nd 3rd 4th 5th 6th 7th 8th
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
RA RA RA RA RA RA RA
[6] [5] [4] [3] [2] [1] [0]
B
S
0
RW
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
･･････････
DevAddr[5:0]
8 bits
NumOfData[6:0]
8 bits
RegAddr[6:0]
8 bits
DA DA DA DA DA DA ND ND ND ND ND ND ND ND
[5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]
RA RA RA RA RA RA RA RD
[6] [5] [4] [3] [2] [1] [0] [7]
B
S
Lowꢀ
RW
SDO
･･････････
･･････････
･･････････
B:
S:
RW:
DA[5:0]:
ND[6:0]:
RA[6:0]:
DT[7:0]:
RD[7:0]:
Broadcast
Single
0
･･････････
Read / Write
Device Address
Number Of Data
Register Address
Data
8 bits
RD RD RD RD RD RD RD RD RD RD
[6] [5] [4] [3] [2] [1] [0] [7] [6] [5]
RD
[0]
Read Data
･･････････
Figure 15. SPI Protocol (Read)
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Functions of Logic Blocks - continued
2. SPI AC Timing
VSYNC
tSCSBHP
tSCSBVS
tSCSBVH
high Vth
low Vth
SCSB
tSCSBS
fSCLK
tSCLKH
tSCSBH
SCLK
SDI
tSDIH
tSDIS
tSDIH
tSDIS
tSCLKL
tSDOD
tSDOD
SDO
High Vth
Low Vth
Figure 16. SPI AC Timing
Table 2. SPI AC Timing
Recommended Operation Condition (Unless otherwise specified, Ta = -40 °C to +125 °C, VCC = 3.0 V to 5.5 V)
Rating
Parameter
Symbol
Unit
Comments
Min
0.1
40
Typ
Max
SCLK Frequency
fSCLK
DSCLK
tSCLKH
tSCLKL
tSDIS
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5
MHz
%
SCLK Duty
60
SCLK High Level Range
SCLK Low Level Range
SDI Input Setup Time
SDI Input Hold Time
SCSB Input Setup Time
SCSB Input Hold Time
70
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
µs
70
-
40
-
tSDIH
25
-
tSCSBS
tSCSBH
100
100
25
-
-
140
100
140
-
VCC = VVREG33: 3.0 V to 3.6 V
VCC = VVREG33: 4.5 V to 5.5 V
VCC = VVREG33: 3.0 V to 5.5 V
SDO Output Delay Time
tSDOD
15
15
SCSB High Pulse Width
tSCSBHP
tSCSBVS
tSCSBVH
1000
10
SCSB Setup Time for VSYNC
SCSB Hold Time for VSYNC
-
10
-
(Output load capacitance: 15 pF)
(Note) It is not available to input VSYNC during SCSB = L.
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Functions of Logic Blocks - continued
3. Cascade Connection
Each device can be controlled by connecting the SCLK and SCSB pins to all devices in parallel, and by connecting
each SDO to the SDI of the next device in series. The maximum number of devices that can be cascaded is 16.
MCU
Device #1
SDI SDO
SCSB
Device #2
SDI SDO
SCSB
Device #n
SDI SDO
SCSB
DO
SCLK
SCLK
SCLK
CS
*n = Max 16
CLK
DI
Figure 17. Image of Cascade Connection
4. SPI Data Flow
MCU Write and Read as following flow. This IC has 3 timing for update analog control data.
Type A (immediately):
Type B (VSYNC):
Type C (PWM):
It updates data after SPI access.
It updates data after SPI access and VSYNC rising edge.
It updates data after SPI access and VSYNC and PWM rising edge.
(PWM is internal signal set by SPI)
So, there is mismatch between “Read data” and “Control data”.
register
A
SPI Write
(update timing
"Immediately")
VSYNC rising edge
Control
Data
B
Analog
Circuit
MCU
(update timing
"VSYNC")
SPI Read
PWM rising
Control
Data
buffer
C
(update timing
"PWM")
Figure 18. SPI Data Flow
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Functions of Logic Blocks - continued
5. SPI Protocol
(1) Device Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
DevAddr [5:0]
B
S
Bit
B
Parameter
Broadcast
Function
B = 1: All chips receive the data (Write only/No Read)
B = 0: Write/Read to the chip that assigned by DevAddr [5:0]
S = 1: 1 byte Write/Read mode
S
Single byte
S = 0: block Write/Read mode
0x00: Write the same data to the same RegAddr of all devices (Provided, B = 1)
0x01 to 0x3E: Each Device Address
0x3F: Write the different data to the same RegAddr of all devices (Provided, B = 1)
Device
Address
DevAddr [5:0]
DevAddr of each device will be calculated by counting the number of byte of 0x00 data after the fall-edge of SCSB.
When matching the received DevAddr and calculated DevAddr of the device, Write/Read function will occur.
When unmatching the received DevAddr and calculated DevAddr of the chip, not taking in the data and output to
SDO. Refer to the each protocol for the details.
(2) Number of transferred byte when block Write/Read
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
0
NumOfData [6:0]
Bit
Parameter
Function
Number of transferred byte for one
device
NumOfData [6:0]
0x02 to 0x48
When S = 0 (Block Write/Read) of DevAddr, set the number of transferred byte (NumOfData) after DevAddr.
When S = 1, it skip this packet. (“Device Address” ->“Register Address” ->….)
Transferred byte number = NumOfData
Table 3. Access Table for Write (RW = 0)
SPI setting
DevAddr
Access to devices
For All device
For single
device
Acceptable(Note 1)
B
0
S
0
1
0
1
NumOfData
0x02 to 0x48
Same
Different
data
data
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
-
O
-
-
O
-
-
-
-
-
-
-
-
-
X
O
X
X
O
X
O
X
O
O
X
O
-
-
-
-
Not sending
this data
-
-
-
-
O
-
-
-
0x02 to 0x48
-
O
-
O
-
-
1
Not sending
this data
-
-
-
O
(Note 1) X: This setting isn’t acceptable. Don’t set this condition.
Table 4. Access Table for Read (RW = 1)
Access to devices
SPI setting
DevAddr
For All device
Same
data
For single
device
Acceptable(Note 1)
B
0
1
S
0
NumOfData
0x02 to 0x48
Different
data
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
0x00
0x01 to 0x3E
0x3F
-
O
-
-
O
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
X
O
X
X
O
X
X
X
X
Not sending
this data
1
0/1
0x02 to 0x48
(Note 1) X: This setting isn’t acceptable. Don’t set this condition.
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5. SPI Protocol - continued
(3) Register Address
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
RW RegAddr [6:0]
Bit
Parameter
Function
RW = 0: Write the registers
RW = 1: Read the registers
0x00 to 0x4F
RW
Read/Write
RegAddr [6:0]
Register Address
(4) Data
bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0
Data [7:0]
Bit
Parameter
Value
Data [7:0]
Data
0x00 to 0xFF
(5) Single device, 1 byte Write (Write to Device #1)
B:
0
Target Device receives the data
S:
1
Single byte
DevAddr[5:0]:
NumOfData[6:0]:
RW:
0x01
-
0
Target Device Address
1 byte Write mode
Write
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, RegAddr, and Data.
SDO : The data input to SDI is output with a 1 byte shift.
SCSB
SCSB = H stop the output
of this data.
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
01 0x01
0
0x02
1 byte shift
01 0x01
Data1 [7:0]
SDI
SDO
0x01
0
0x02
Ex) Detail of Timing Chart
SCSB
SCLK
B
S
DevAddr[5:0]
RW
RegAddr[6:0]
Data1[7:0]
SDI
8 bit shift every Device
SDO
Device #1
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data1
Figure 19. SPI Protocol of the 1 Byte Write to Device #1
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5. SPI Protocol - continued
(6) Single device, 1 byte Write (Write to Device #3)
B:
S:
0
1
Target Device receives the data
Single byte
DevAddr[5:0]:
NumOfData[6:0]:
RW:
0x03
-
0
Target Device Address
1 byte Write mode
Write
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
DevAddr of each device will be calculated by counting the number of byte of 0x00 data after the fall-edge of
SCSB.
DevAddr = (Number of byte of 0x00 data) + 1
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
0 1
0x03
0
0x02
Data1 [7:0]
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
0 1 0x03
0x00
0
0x02
Data1 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0 1 0x03
0x00
0
0x02
Data1 [7:0]
0x00
0 1 0x03
0
0x02
Device #3 SDO
2 byte 00h after SCSB↓
⇒DevAddr of Device#3 = 2 + 1 = 0x03
Match to the DevAddr
of Device#3
This data will be written to
RegAddr02h, Device#3
Device #1
Register
Device #2
Register
Device #3
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data1
Figure 20. SPI Protocol of the 1 Byte Write to Device #3
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5. SPI Protocol - continued
(7) Single device, “n byte” Write (Write to the consecutive register of Device #1)
B:
S:
0
0
Target Device receives the data
Single byte
DevAddr[5:0]:
NumOfData[6:0]: 0x03
RW:
0x01
Target Device Address
3 byte Write mode
Write
0
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0] RW RegAddr[6:0]
0 1
0x01
0
0x03
0
0x02
Data1 [7:0] Data2 [7:0] Data3 [7:0]
0x02
Data1 [7:0] Data2 [7:0]
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0
0x00
0 0 0x01
0x00
0
0x03
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0 0 0x01
0x00
0
0x03
0
0x02
Data1 [7:0]
0x00
0 0 0x01
0
0x03
0
0x02
Device #3 SDO
2byte 00h after SCSB↓
⇒DevAddr of Device#3=2+1=0x03
Match to the DevAddr
of Device#3
This data will be written to
RegAddr02h, Device#3
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x04
Data3
0x03
Data2
0x02
Data1
0x01
0x00
Figure 21. SPI Protocol of the n Byte Write to Device #1
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5. SPI Protocol - continued
(8) All device, different “1 byte” Write (Write the same 1 byte data to the same RegAddr of all Devices)
B:
S:
1
1
All device receive data
Single byte
DevAddr[5:0]:
NumOfData[6:0]:
RW:
0x3F
-
0
All device different data
1 byte Write mode
Write
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
1 1
0x3F
0
0x02
Data1 [7:0]
0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
1 1
0x3F
0
Data3 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0x00
0x00
1 1
0x3F
0
0x02
Data1 [7:0]
0 0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
0x00
1 1
0x3F
Device #3 SDO
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
0x07
0x06
0x05
0x04
0x03
0x02
Data1
Data2
Data3
0x01
0x00
0x01
0x00
Figure 22. SPI Protocol of the 1 Byte Distinct Data Write to All Devices
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5. SPI Protocol - continued
(9) All device, same “1 byte” Write (Write the same 1 byte data to the same RegAddr of all Devices)
B:
S:
1
1
All device receive data
Single byte
DevAddr[5:0]:
NumOfData[6:0]:
RW:
0x00
-
0
All device same data
1 byte Write mode
Write
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
0 1
0x00
0
0x02
Data1 [7:0]
0x02
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
1 1 0x00
0x00
0
Data1 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
1 1 0x00
0x00
0
0x02
Data1 [7:0]
0x00
1 1
0x00
0
0x02
Device #3 SDO
Device #1
Device #2
Device #3
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Register
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x03
0x02
Data1
Data1
Data1
0x01
0x00
Figure 23. SPI Protocol of the 1 Byte Distinct Data Write to All Devices
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5. SPI Protocol - continued
(10) All device, different “n byte” Write (Write the different n byte data to the same RegAddr of all Devices)
B:
S:
1
0
All device receive data
multi byte
DevAddr[5:0]:
NumOfData[6:0]: 0x02
RW:
0x3F
All device different data
2 byte Write mode
Write
0
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0] RW RegAddr[6:0]
1 1
0x3F
0
0x02
0
0x02
Data1 [7:0]
0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
Data4 [7:0]
Data3 [7:0]
Data5 [7:0]
Data4 [7:0]
Data6 [7:0]
Data5 [7:0]
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
1 0
0x3F
0
0x02
0
0
Data6 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0x00
0x00
1 0
0x3F
0x02
0
0
0x02
0x02
Data1 [7:0]
0 0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
Data4 [7:0]
Data3 [7:0]
Data5 [7:0]
Data4 [7:0]
Data6 [7:0]
Data5 [7:0]
Device #3 SDO
0x00
1 0
0x3F
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x04
0x03
0x07
0x06
0x05
0x04
0x03
0x07
0x06
0x05
0x04
0x03
Data2
Data4
Data3
Data6
Data5
0x02
0x01
0x00
0x02
0x01
0x00
0x02
0x01
0x00
Data1
Figure 24. SPI Protocol of the n Byte Distinct Data Write to All Devices
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5. SPI Protocol - continued
(11) All device, same “n byte” Write (Write the same n byte data to the same RegAddr of all Devices)
B:
S:
1
0
All device receive data
multi byte
DevAddr[5:0]:
NumOfData[6:0]: 0x03
RW:
0x00
All device same data
3 byte Write mode
Write
0
RegAddr[6:0]:
0x02
Address
SDI
: Transfer in the order of DevAddr, NumOfData, RegAddr, and Data.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0] RW RegAddr[6:0]
1 0
0x00
0
0x03
0
0x02
Data1 [7:0]
0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
1 0
0x00
0
0x03
0
0
Data3 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0x00
0x00
1 0
0x00
0x00
0x03
0
0
0x02
0x03
Data1 [7:0]
0 0x02
Data2 [7:0]
Data1 [7:0]
Data3 [7:0]
Data2 [7:0]
1 0
0x00
Device #3 SDO
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x04
0x07
0x06
0x05
0x04
0x07
0x06
0x05
0x04
Data3
Data2
Data1
Data3
Data2
Data1
Data3
Data2
Data1
0x03
0x02
0x01
0x00
0x03
0x02
0x01
0x00
0x03
0x02
0x01
0x00
Figure 25. SPI Protocol of the n Byte Same Data Write to All Devices
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5. SPI Protocol - continued
(12) Single device, “1 byte” Read (Read the 1 byte data from Device #2)
B:
S:
0
1
Target device receive each data
single byte
DevAddr[5:0]:
NumOfData[6:0]:
RW:
0x02
-
1
Target Device Address
1 byte Read mode
Read
RegAddr[6:0]:
0x03
Address
SDI
: Transfer in the order of DevAddr and RegAddr.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] RW RegAddr[6:0]
01
0x02
1
0x03
0x00
0x03
0x00
0x00
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
0 1
0x02
1
0x00
Read Data[7:0]
Data1 [7:0]
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0x00
0x00
0 1
0x02
0x00
1
0x03
0x02
0x00
0 1
1
0x03
Data1 [7:0]
Device #3 SDO
Device #1
Register
0x07
Device #2
Register
0x07
Device #3
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x06
0x05
0x04
0x03
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data1
0x02
0x01
0x00
Figure 26. SPI Protocol of the 1 Byte Read from Device #2
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5. SPI Protocol - continued
(13) Single device, “n byte” Read (Read the n byte data from Device #2)
B:
S:
0
0
Target device receive each data
multi byte
DevAddr[5:0]:
NumOfData:
RW:
0x02
0x02
1
Target Device Address
1 byte Read mode
Read
RegAddr[6:0]:
0x03
Address
SDI
: Transfer in the order of DevAddr, NumOfData, and RegAddr.
SDO : Output the transferred data to the next device after SDI input by 1 byte.
SCSB
SCLK
B S DevAddr[5:0] NumOfData[6:0]
RW RegAddr[6:0]
0 0
0x02
0
0x02
1
0x03
0x00
0x03
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Device #1 SDI
Device #1 SDO
(Device #2 SDI)
0x00
0 0
0x02
0
0x02
1
0
Device #2 SDO
(Device #3 SDI)
0x00
0x00
0x00
0x00
0 0
0x02
0x00
0x02
0x02
1
0
0x03
0x02
Data1 [7:0]
0x03
Data2 [7:0]
Data1 [7:0]
0x00
0 0
1
Data2 [7:0]
Device #3 SDO
SCSB = H stop the output
of this data
Device #1
Device #2
Device #3
Register
Register
Register
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
0x07
0x06
0x05
0x04
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
Data2
Data1
0x03
0x02
0x01
0x00
Figure 27. SPI Protocol of the n Byte Read from Device #2
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5. SPI Protocol - continued
(14) Example of n byte Write (Write the n byte data to Device #1 and #2)
Example of the transfer of 2 device Cascade Connection.
DevAddr
1 byte
Transfer setting
Number of transferred byte
RegAddr
1 byte
1 byte
2 byte x 16 channel x 2 device
= 64 byte
Data
Data for the duty setting of Duty
Dummy clock
for multi device transfer
SUM
1 byte
68 byte
DevAddr[5:0]
1 0 0x3F
NumOfData[6:0] RegAddr[6:0]
Date[7:0] x 2 x 16 ch
device #1
device #1
device #1
device #1
DTYCNT01L
0
0x20
0
0x18
DTYCNT01U
DTYCNT16L
DTYCNT16U
Number of
RegAddr of
transferred byte
for each device
DTYCNT01L
Dummy byte
Date[7:0] x 2 x 16 ch
device #2
device #2
DTYCNT16U
device #2
DTYCNT01L
device #2
DTYCNT01U
0x00
Dummy Clocks
DTYCNT16L
Figure 28. Transfer Byte Number for Multi Access
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Functions of Logic Blocks - continued
6. Register Map
Each registers is updated at the 3 timings.
Provided for Type B and Type C, the registers are not updated when the update timing and SCSB = ‘Low’ are the same, and
wait for the next update timing when SCSB = ‘High’.
Reset Condition: “UVLO” condition = VREG33UVLO or VCCUVLO or TSD or EN is detected.
Register Update timing for control data
Type A : Updated to the newest data immediately when the data is written.
Type B : Updated to the newest data when the next VSYNC timing.
(rise-edge trigger) after the data is written.)
Type C : Updated to the newest data when the next VSYNC and PWM (PWM is internal signal) timing.
(rise-edge trigger of VSYNC, then rise-edge trigger of PWM (first PWM pulse when PWMFREQ[1:0] = 01h to 11h)
after the data is written.
Note: Don’t access (Write) register except for following register and write ‘0’ in ‘-’.
register
A
SPI Write
(update timing
"Immediately")
VSYNC rising edge
Control
Data
B
Analog
Circuit
MCU
(update timing
"VSYNC")
SPI Read
PWM rising
Control
Data
buffer
C
(update timing
"PWM")
Figure 29. SPI Data Flow
Address 0x01 to 0x16 (1/3)
Register
Access
Reset
Condition
Update
Timing
Register Name
Address
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[2]
Bit[1]
-
Bit[0]
-
Initial
0x00
0x00
0x0F
0x3C
0x29
0x07
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Comments
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UVLO
Type A Blank
PWMFREQ[1:0]
PWMFREQ
ERRSET1
SSMASK
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
Type A PWM output frequency setting
Type A LED short voltage setting
SCPTIME[1:0]
LEDSH[3:0]
SSMASK[7:0]
ERRMASK[7:0]
Type B SS mask time
ERRMASK
ERREN
Type B error mask time
-
-
-
-
-
-
-
TSDWEN
-
LEDSHEN
-
LEDOPEN
Type B error enable setting
ERRLAT
(Note 1)
ERRSET2
DLYCNT01
DLYCNT02
DLYCNT03
DLYCNT04
DLYCNT05
DLYCNT06
DLYCNT07
DLYCNT08
DLYCNT09
DLYCNT10
DLYCNT11
DLYCNT12
DLYCNT13
DLYCNT14
DLYCNT15
DLYCNT16
FAILTEST
FAILCNT
ERRCLR
DLY01[7:0]
Type A Error controlling
Type B LED1 PWM Delay setting upper 8bit
Type B LED2 PWM Delay setting upper 8bit
Type B LED3 PWM Delay setting upper 8bit
Type B LED4 PWM Delay setting upper 8bit
Type B LED5 PWM Delay setting upper 8bit
Type B LED6 PWM Delay setting upper 8bit
Type B LED7 PWM Delay setting upper 8bit
Type B LED8 PWM Delay setting upper 8bit
Type B LED9 PWM Delay setting upper 8bit
Type B LED10 PWM Delay setting upper 8bit
Type B LED11 PWM Delay setting upper 8bit
Type B LED12 PWM Delay setting upper 8bit
Type B LED13 PWM Delay setting upper 8bit
Type B LED14 PWM Delay setting upper 8bit
Type B LED15 PWM Delay setting upper 8bit
Type B LED16 PWM Delay setting upper 8bit
DLY02[7:0]
DLY03[7:0]
DLY04[7:0]
DLY05[7:0]
DLY06[7:0]
DLY07[7:0]
DLY08[7:0]
DLY09[7:0]
DLY10[7:0]
DLY11[7:0]
DLY12[7:0]
DLY13[7:0]
DLY14[7:0]
DLY15[7:0]
DLY16[7:0]
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
(Note 1) Update timing of ERRLAT is Type B.
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6. Register Map – continued
Address 0x17 to 0x47 (2/3)
Register
Access
Reset
Condition
Update
Timing
Register Name
Address
0x17
0x18
0x19
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
0x20
0x21
0x22
0x23
0x24
0x25
0x26
0x27
0x28
0x29
0x2A
0x2B
0x2C
0x2D
0x2E
0x2F
0x30
0x31
0x32
0x33
0x34
0x35
0x36
0x37
0x38
0x39
0x3A
0x3B
0x3C
0x3D
0x3E
0x3F
0x40
0x41
0x42
0x43
0x44
0x45
0x46
0x47
Bit[7]
Bit[6]
Bit[5]
-
Bit[4]
Bit[3]
-
Bit[2]
-
Bit[1]
Bit[0]
Initial
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
0xFF
Comments
PWMPLS
-
-
PLSSET
PLSNUM[1:0]
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
Type C PWM pulse number setting
Type C LED1 PWM ON duty Lower 8bit
Type C LED1 PWM ON duty Upper 5bit
Type C LED2 PWM ON duty Lower 8bit
Type C LED2 PWM ON duty Upper 5bit
Type C LED3 PWM ON duty Lower 8bit
Type C LED3 PWM ON duty Upper 5bit
Type C LED4 PWM ON duty Lower 8bit
Type C LED4 PWM ON duty Upper 5bit
Type C LED5 PWM ON duty Lower 8bit
Type C LED5 PWM ON duty Upper 5bit
Type C LED6 PWM ON duty Lower 8bit
Type C LED6 PWM ON duty Upper 5bit
Type C LED7 PWM ON duty Lower 8bit
Type C LED7 PWM ON duty Upper 5bit
Type C LED8 PWM ON duty Lower 8bit
Type C LED8 PWM ON duty Upper 5bit
Type C LED9 PWM ON duty Lower 8bit
Type C LED9 PWM ON duty Upper 5bit
Type C LED10 PWM ON duty Lower 8bit
Type C LED10 PWM ON duty Upper 5bit
Type C LED11 PWM ON duty Lower 8bit
Type C LED11 PWM ON duty Upper 5bit
Type C LED12 PWM ON duty Lower 8bit
Type C LED12 PWM ON duty Upper 5bit
Type C LED13 PWM ON duty Lower 8bit
Type C LED13 PWM ON duty Upper 5bit
Type C LED14 PWM ON duty Lower 8bit
Type C LED14 PWM ON duty Upper 5bit
Type C LED15 PWM ON duty Lower 8bit
Type C LED15 PWM ON duty Upper 5bit
Type C LED16 PWM ON duty Lower 8bit
Type C LED16 PWM ON duty Upper 5bit
Type C LED1 local DAC setting
DTYCNT01L
DTYCNT01U
DTYCNT02L
DTYCNT02U
DTYCNT03L
DTYCNT03U
DTYCNT04L
DTYCNT04U
DTYCNT05L
DTYCNT05U
DTYCNT06L
DTYCNT06U
DTYCNT07L
DTYCNT07U
DTYCNT08L
DTYCNT08U
DTYCNT09L
DTYCNT09U
DTYCNT10L
DTYCNT10U
DTYCNT11L
DTYCNT11U
DTYCNT12L
DTYCNT12U
DTYCNT13L
DTYCNT13U
DTYCNT14L
DTYCNT14U
DTYCNT15L
DTYCNT15U
DTYCNT16L
DTYCNT16U
LCDAC1
DTY01[7:0]
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
DTYEN01
DTYEN02
DTYEN03
DTYEN04
DTYEN05
DTYEN06
DTYEN07
DTYEN08
DTYEN09
DTYEN10
DTYEN11
DTYEN12
DTYEN13
DTYEN14
DTYEN15
DTYEN16
DTY01[12:8]
DTY02[12:8]
DTY03[12:8]
DTY04[12:8]
DTY05[12:8]
DTY06[12:8]
DTY07[12:8]
DTY08[12:8]
DTY09[12:8]
DTY10[12:8]
DTY11[12:8]
DTY12[12:8]
DTY13[12:8]
DTY14[12:8]
DTY15[12:8]
DTY16[12:8]
DTY02[7:0]
DTY03[7:0]
DTY04[7:0]
DTY05[7:0]
DTY06[7:0]
DTY07[7:0]
DTY08[7:0]
DTY09[7:0]
DTY10[7:0]
DTY11[7:0]
DTY12[7:0]
DTY13[7:0]
DTY14[7:0]
DTY15[7:0]
DTY16[7:0]
LCDAC1[7:0]
LCDAC2[7:0]
LCDAC3[7:0]
LCDAC4[7:0]
LCDAC5[7:0]
LCDAC6[7:0]
LCDAC7[7:0]
LCDAC8[7:0]
LCDAC9[7:0]
LCDAC2
Type C LED2 local DAC setting
LCDAC3
Type C LED3 local DAC setting
LCDAC4
Type C LED4 local DAC setting
LCDAC5
Type C LED5 local DAC setting
LCDAC6
Type C LED6 local DAC setting
LCDAC7
Type C LED7 local DAC setting
LCDAC8
Type C LED8 local DAC setting
LCDAC9
Type C LED9 local DAC setting
LCDAC10
LCDAC10[7:0]
LCDAC11[7:0]
LCDAC12[7:0]
LCDAC13[7:0]
LCDAC14[7:0]
LCDAC15[7:0]
LCDAC16[7:0]
Type C LED10 local DAC setting
LCDAC11
Type C LED11 local DAC setting
LCDAC12
Type C LED12 local DAC setting
LCDAC13
Type C LED13 local DAC setting
LCDAC14
Type C LED14 local DAC setting
LCDAC15
Type C LED15 local DAC setting
LCDAC16
Type C LED16 local DAC setting
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
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6. Register Map - continued
Address 0x48 to 0x4F (3/3)
Register
Access
Reset
Condition
Update
Timing
Register Name
Address
Bit[7]
Bit[6]
Bit[5]
-
Bit[4]
-
Bit[3]
-
Bit[2]
-
Bit[1]
-
Bit[0]
-
Initial
-
Comments
-
0x48
-
-
-
-
-
blank
error flag LEDn open
(n = 1 to 8)
ERLOP[7:0]
ERRLEDOPA
ERRLEDOPB
ERRLEDSHA
ERRLEDSHB
ERRISETSCP
ERRTSDA
0x49
RO
RO
RO
RO
RO
RO
RO
0x00
0x00
0x00
0x00
0x00
0x00
0x00
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
UVLO
Type A
Type A
Type A
Type A
(Note 2)
error flag LEDn open
(n = 9 to 16)
ERLOP[15:8]
(Note 2)
0x4A
0x4B
0x4C
0x4D
0x4E
0x4F
error flag LEDn short
(n = 1 to 8)
ERLSH[7:0]
(Note 2)
error flag LEDn short
(n = 9 to 16)
ERLSH[15:8]
(Note 2)
WARSCP
(Note 3)
WARISET
(Note 2)
-
-
-
-
-
-
Type A error flag ISET short and SCP
error flag TSD warning
(n = 1 to 8)
WARTSD[7:0]
(Note 2)
Type A
error flag TSD warning
Type A
WARTSD[15:8]
(Note 2)
ERRTSDB
(n = 9 to 16)
(Note) WO: Write Only, RO: Read Only, R/W: Read and Write
(Note 2) Released condition is referred in description of register.
(Note 3) Released condition is only reset.
7. Description of Registers
Address 0x01: PWMFREQ
Output PWM frequency setting [Read/Write]
Initial value 0x00
Bit No
Name
Bit[7]
-
Bit[6]
-
Bit[5]
-
Bit[4]
-
Bit[3]
-
Bit[2]
-
Bit[1]
PWMFREQ[1:0]
Bit[0]
Initial value
0
0
0
0
0
0
0
0
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
Regarding EXTCLK frequency, refer to the following list.
If it is different from relation of PWMFREQ and EXTCLK frequency, it can’t control LED normally.
Don’t change value during dimming. (only initial setting before PWM setting)
PWMFREQ[1:0]
PWM Frequency
VSYNC x 1
VSYNC x 2
VSYNC x 4
VSYNC x 8
EXTCLK Frequency
VSYNC x 8,192
VSYNC x 16,384
VSYNC x 32,768
VSYNC x 65,536
0
1
2
3
Example of EXTCLK setting is referred. This IC can be acceptable to input EXTCLK under 5 MHz.
(Refer to frequency range of electric characteristics)
(Example) EXTCLK frequency and PWM frequency
VSYNC Frequency [Hz]
PWMFREQ[1:0]
60
491,520
60
983,040
120
1,966,080
240
3,932,160
480
120
983,040
120
240
1,966,080
480
3,932,160
0
1
2
3
240
480
-
-
-
-
-
-
1,966,080
240
3,932,160
480
3,932,160
480
-
-
-
-
-
-
[Hz]
Upper: EXTCLK frequency
Lower: PWM frequency
‘-’ is not acceptable to set this value in PWMFREQ register.
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7. Description of Registers - continued
PWMFREQ[1:0] = 0
VSYNC
EXTCLK
EXTCLK = VSYNC x 8,192(213)[Hz]
PWM:VSYNCx1[Hz]
PWMn
resolution:213
PWMFREQ[1:0] = 1
VSYNC
EXTCLK
PWMn
EXTCLK = VSYNC x 16,384(214)[Hz]
PWM:VSYNCx2[Hz]
resolution:213
PWMFREQ[1:0] = 2
VSYNC
EXTCLK = VSYNC x 32,768(215)[Hz]
EXTCLK
PWM:VSYNCx4[Hz]
PWMn
resolution:213
PWMFREQ[1:0] = 3
VSYNC
EXTCLK = VSYNC x 65,536(216)[Hz]
EXTCLK
PWM:VSYNCx8[Hz]
PWMn
resolution:213
Figure 30. PWMFREQ Setting
LED short detection voltage setting
Address 0x02: ERRSET1
[Read/Write]
Bit[2]
Initial value 0x0F
Bit No
Name
Bit[7]
-
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[1]
Bit[0]
-
SCPTIME[1:0]
LEDSH[3:0]
Initial value
0
0
0
0
1
1
1
1
Update: Immediately
The data in register is updated to the newest data immediately when the new data is written.
Bit[5:4]
SCPTIME
This register controls MASK time for SCP detected.
SCPTIME[1:0]
MASK Time
0
1
2
3
1 VSYNC cycle
2 VSYNC cycle
4 VSYNC cycle
8 VSYNC cycle
Bit[3:0] LEDSH[3:0]
This register controls detection voltage LED short protection.
LEDSH[3:0]
0x0 to 0x8
0x9
Detection Voltage [V]
Not available
3.00
0xA
3.30
0xB
3.60
0xC
3.90
0xD
4.20
0xE
4.50
0xF
4.80
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7. Description of Registers – continued
Address 0x03: SSMASK
Soft start mask register
[Read/Write]
Bit[3]
SSMASK[7:0]
Initial value 0x3C
Bit[1]
Bit No
Name
Bit[7]
0
Bit[6]
0
Bit[5]
Bit[4]
1
Bit[2]
1
Bit[0]
0
Initial value
1
1
0
Update: VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
Set value more than 0x02.
It controls protect function (LED open protection, LED short protection, SCP, ISET short warning, TSD warning) after
SSMASK time. So, it is not available to operate protection function during SSMASK time.
The time of mask of ERROR detection is set by counting the number of VSYNC.
Time of mask = SSMASK x VSYNC
(except for waiting time until 1st VSYNC pulse)
VSYNC [Hz]
60
120
240
480
Max Mask time [ms]
4,250
2,125
1,062.5
531.3
Address 0x04: ERRMASK
ERROR output mask time setting register
[Read/Write]
Bit[2]
Initial value 0x29
Bit No
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
Bit[1]
Bit[0]
ERRMASK[7:0]
Initial value
0
0
1
0
1
0
0
1
Update: VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
When 0 to 2 is written to this register, the register value becomes 3.
When over 3 is written to this register, writing value becomes register value.
This IC has mask function for “LED open protection” and “LED short protection”. It can’t detect these errors during this time.
ERROR mask time is set by counting the number of EXTCLK.
Mask time = ERRMASK x EXTCLK
Example) ERRMASK = 3: mask 3 clock to 4 clock (PWM = H and error signal (after synchronizing))
‘-’ column is not acceptable setting.
VSYNC/EXTCLK condition vs “Maximum Mask time” (Default 0x29 (41))
VSYNC [Hz]
PWMFREQ[1:0]
60
519
259
130
65
120
259
130
65
240
130
65
-
480
65
-
-
-
0
1
2
3
-
-
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7. Description of Registers – continued
Address 0x05: ERREN
Error enable setting
[Read/Write]
Initial value 0x07
Bit No
Name
Initial value
Bit[7]
-
0
Bit[6]
-
0
Bit[5]
-
0
Bit[4]
-
0
Bit[3]
-
0
Bit[2]
TSDWEN
1
Bit[1]
LEDSHEN
1
Bit[0]
LEDOPEN
1
Update: VSYNC
This register is updated to the newest data when the next VSYNC signal rises up after the data is written.
Bit[2]:
0:
1:
TSDWEN
disable (error register and error output (FAIL) is initial condition if “TSD warning” is occurred
enable (135 deg (Typ))
Bit[1]
0:
1:
LEDSHEN
disable (error register and error output (FAIL) is initial condition if “LED short protection” is occurred
enable
Bit[0]
0:
1:
LEDOPEN
disable (error register and error output (FAIL) is initial condition if “LED open protection” is occurred
enable
“LED open function” effects SCP detection. So, it is not available to change this enable during operation.
Address 0x06: ERRSET2
Error Latch mode setting
[Read/Write]
Bit[3]
Initial value 0x00
Bit[1]
Bit No
Name
Bit[7]
FAILTEST
0
Bit[6]
FAILCNT
0
Bit[5]
-
0
Bit[4]
ERRCLR
0
Bit[2]
-
0
Bit[0]
ERRLAT
0
-
0
Initial value
0
Update: FAILTEST, FAILCNT, ERRCLR: Immediately, ERRLAT: VSYNC
The data (ERRCLR) in register is updated to the newest data immediately when the new data is written.
The register data (ERRLAT) is updated to the newest data when the next VSYNC signal rises up after the data is written.
Bit[7]
0:
FAILTEST
normal operation
1:
It available to control the FAIL pin output by FAILCNT register.
Bit[4]
0:
1:
FAILCNT
It outputs Low from the FAIL pin when FAILTEST = 1
It outputs High from the FAIL pin when FAILTEST = 1
Bit[4]
0:
ERRCLR
no operation
1:
clear error register and return Hi-Z in FAIL output when ERRLAT = 1
ERRCLR return ‘0’ automatically. So, it can’t read ‘1’.
Bit[0]
0:
1:
ERRLAT
error register and FAIL output are returned to initial condition when error is released.
error register and FAIL output are kept until writing ‘1’ in ERRCLR.
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7. Description of Registers - continued
Address 0x07: DLYCNT01 (LED1 PWM Delay setting register) [Read/Write]
Initial value 0x00
Bit[2]
Bit No
Name
Bit[7]
0
Bit[6]
0
Bit[5]
Bit[4]
Bit[3]
Bit[1]
0
Bit[0]
DLY01[7:0]
Initial value
0
0
0
0
0
Update: VSYNC
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
This register is used to make setting of delay width for PWM light modulation in a total of 8 bits,
i.e., Bit[7:0] when Address = 0x07.
LED Delay Width (clock width@EXTCLK)
DLY01[7:0]
PWMFREQ[1:0]
= 0
PWMFREQ[1:0]
= 1
PWMFREQ[1:0]
= 2
PWMFREQ[1:0]
= 3
0x00
0x01
0x02
0x03
…
0xXX
…
0xFC
0xFD
0xFE
0xFF
4 clock to 5 clock width@EXTCLK from posedge of VSYNC (*)
(*) + 0x01 x 25
(*) + 0x02 x 25
(*) + 0x03 x 25
...
(*) + 0x01 x 26
(*) + 0x02 x 26
(*) + 0x03 x 26
...
(*) + 0x01 x 27
(*) + 0x02 x 27
(*) + 0x03 x 27
...
(*) + 0x01 x 28
(*) + 0x02 x 28
(*) + 0x03 x 28
...
(*) + 0xXX x 25
...
(*) + 0xXX x 26
...
(*) + 0xXX x 27
...
(*) + 0xXX x 28
...
(*) + 0xFC x 25
(*) + 0xFD x 25
(*) + 0xFE x 25
(*) + 0xFF x 25
(*) + 0xFC x 26
(*) + 0xFD x 26
(*) + 0xFE x 26
(*) + 0xFF x 26
(*) + 0xFC x 27
(*) + 0xFD x 27
(*) + 0xFE x 27
(*) + 0xFF x 27
(*) + 0xFC x 28
(*) + 0xFD x 28
(*) + 0xFE x 28
(*) + 0xFF x 28
Decide “DLY01 setting” in VSYNC and EXTCLK jitter of MCU. Refer to “PWM behavior at close VSYNC interval”.
Address 0x08 to 0x16: DLYCNTn (n = 2 to 16)
This register is used to make PWM delay width setting for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x07.
The register data is updated to the newest data when the next VSYNC signal rises up after the data is written.
Address 0x17: PWMPLS (PWM pulse number setting)
[Read/Write]
Initial value 0x00
Bit No
Name
Initial value
Bit[7]
-
0
Bit[6]
-
0
Bit[5]
-
0
Bit[4]
PLSSET
0
Bit[3]
-
0
Bit[2]
-
0
Bit[1]
PLSNUM[1:0]
0
Bit[0]
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
PLSNUM (PWM pulse number)
PWMFREQ[1:0]
0
1
2
3
0
1
2
3
1
2
1
4
8
3
6
2
4
1
2
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7. Description of Registers - continued
It outputs PWM pulse in Head position When PLSSET = 0
Example) PWMFREQ[1:0] = 3, PLSSET = 0
PLSNUM[1:0] = 0
VSYNC
PWMn
PLSNUM[1:0] = 1
VSYNC
OFF
PWMn
PLSNUM[1:0] = 2
VSYNC
OFF
PWMn
PLSNUM[1:0] = 3
VSYNC
OFF
OFF
PWMn
Figure 31. PWM Pulse Number Setting (Tail OFF)
It outputs PWM pulse in Tail position When PLSSET = 1.
Example) PWMFREQ[1:0] = 3, PLSSET = 1
PLSNUM[1:0] = 0
VSYNC
PWMn
PLSNUM[1:0] = 1
VSYNC
OFF
OFF
PWMn
PLSNUM[1:0] = 2
VSYNC
OFF
OFF
PWMn
PLSNUM[1:0] = 3
VSYNC
OFF
OFF
PWMn
Figure 32. PWM Pulse Number Setting (Head OFF)
DLY = 0x7F, PWMFREQ = 3, PLSNUM[1:0] = 2, PLSSET = 0
VSYNC
EXTCLK = VSYNC x 65,536[Hz]
EXTCLK
SPI
delay
OFF
PWMn
update
LCDAC setting
analog signal(image)
Figure 33. PWM Pulse Number Setting
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7. Description of Registers - continued
Address 0x18: DTYCNT01L (LED1 PWM duty setting register - lower 8 bits)
[Read/Write]
Bit[2]
Initial value 0x00
Bit No
Name
Bit[7]
0
Bit[6]
0
Bit[5]
Bit[4]
Bit[3]
0
Bit[1]
Bit[0]
DTY01[7:0]
Initial value
0
0
0
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
Address 0x19: DTYCNT01U (LED1 PWM duty setting register - upper 5 bits)
[Read/Write]
Bit[2]
DTY01[12:8]
0
Initial value 0x00
Bit No
Name
Bit[7]
-
Bit[6]
-
Bit[5]
DTYEN01
0
Bit[4]
Bit[3]
Bit[1]
Bit[0]
Initial value
0
0
0
0
0
0
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
This register is used to make setting of pulse duty for PWM light modulation in a total of 13 bits,
i.e., Bit[7:0] when Address = 0x18 and Bit[4:0] when Address = 0x19.
DTYEN01
DTY01[12:0]
0x000 to 0x1FFF
0x0000
LED Pulse Width
0 clock width@EXTCLK
1 clock width@EXTCLK
2 clock width@EXTCLK
3 clock width@EXTCLK
4 clock width@EXTCLK
...
0
1
1
1
1
1
1
1
1
1
0x0001
0x0002
0x0003
...
0x1FFC
0x1FFD
0x1FFE
0x1FFF
8189 clock width@EXTCLK
8190 clock width@EXTCLK
8191 clock width@EXTCLK
Normally set to High (Duty 100 %)
If DTYEN01 = 0 is set when it detects LED open/LED short in channel 1, Error register (ERLOP[0]/ERLSH[0]) and FAIL turn
normal condition.
Address 0x1A to 0x37: DTYCNTn (n = 2 to 16)
This register is used to make setting of PWM pulse width for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x1A and 0x37.
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7. Description of Registers - continued
Address 0x38: LCDAC1 (Analog light modulation setting for LED1)
[Read/Write]
Bit[3]
Initial value 0xFF
Bit[1]
Bit No
Name
Bit[7]
1
Bit[6]
1
Bit[5]
Bit[4]
Bit[2]
1
Bit[0]
LCDAC1[7:0]
Initial value
1
1
1
1
1
Update: PWM
The register data is updated to the newest data when the next PWM signal rises up after the data is written.
Address 0x39 to 0x47: LCDACn (n = 2 to 16)
This register is used to make setting of PWM pulse width for LED2 to LED16. The setting procedure is the same as that for
LED1 with Address set to 0x38.
This register can be written 0x00 to 0xFF value.
The DAC setting is possible, but the guarantee levels become more than 20 mA.
LCDACn[7:0]
ILEDn
(Write value)
0x00
0x01
...
ILEDMAX x 1/256
ILEDMAX x 2/256
…
0xXX
...
ILEDMAX x (LCDACn +1)/256
…
0xFF
ILEDMAX x 256/256
(n = 1 to 16)
퐼퐿퐸퐷푀퐴푋 = 757/푅ꢀ푆퐸푇
{(
[A]
[
]
)
}
퐼퐿퐸퐷푛 = 퐼퐿퐸퐷푀퐴푋 × ꢁ퐶ꢂꢃ퐶ꢄ 7: 0 + 1 /256
>
0.02
[A] (ꢄ = 1 푡표 16)
[A] (ꢄ = 1 푡표 16)
{(
[
]
)
}
퐼퐿퐸퐷푛_퐴푉퐸 = 퐼퐿퐸퐷푛 × ꢂꢅ푌ꢄ 12: 0 + 1 / 8,192
LED Current
Maximum setting
130 mA
ILEDMAX
Variable Range
ILEDn
ILEDn_AVE
Minimum Setting
20 mA
t
PWM Duty
Figure 34. Current Setting Image
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7. Description of Registers - continued
Address 0x49: ERRLEDOPA (LED1 to LED8 pin open ERROR monitor)
[Read]
Bit[2]
Initial value 0x00
Bit[1]
Bit No
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0
Bit[0]
0
ERLOP[7:0]
Initial value
0
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED open protection”) is detected.
Address 0x4A: ERRLEDOPB (LED8 to LED16 pin open ERROR monitor)
[Read]
Bit[2]
Initial value 0x00
Bit[1]
Bit No
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0
Bit[0]
0
ERLOP[15:8]
Initial value
0
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED open protection”) is detected.
ERLOP[n-1]
Status
Normal
0
1
Detect protection(Note 1)
(n = 1 to 16 channel)
(Note 1) ERRLAT = 0: ERLOP[n-1] turns 0, if Error is released or “DTYENn = 0” is set or “LEDOPEN = 0” is set.
ERRLAT = 1: ERLOP[n-1] turns 0, if “ERRCLR = 1” is set.
Address 0x4B: ERRLEDSHA (LED1 to LED8 short ERROR monitor)
[Read]
Bit[2]
Initial value 0x00
Bit No
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0
Bit[1]
Bit[0]
ERLSH[7:0]
Initial value
0
0
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED short protection”) is detected.
Address 0x4C: ERRLEDSHB (LED8 to LED16 short ERROR monitor)
[Read]
Bit[2]
Initial value 0x00
Bit No
Name
Bit[7]
Bit[6]
Bit[5]
Bit[4]
Bit[3]
0
Bit[1]
Bit[0]
ERLSH[15:8]
Initial value
0
0
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“LED short protection”) is detected.
ERLSH[n-1]
Status
Normal
0
1
Detect protection(Note 2)
(n = 1 to 16 channel)
(Note 2) ERRLAT = 0: ERLSH[n-1] turns 0, if Error is released or “DTYENn = 0” is set or “LEDSHEN = 0” is set.
ERRLAT = 1: ERLSH[n-1] turns 0, if “ERRCLR = 1” is set.
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7. Description of Registers - continued
Address 0x4D: ERRISETSCP (ISET short warning and SCP)
[Read]
Initial value 0x00
Bit No
Name
Initial value
Bit[7]
-
0
Bit[6]
-
0
Bit[5]
-
0
Bit[4]
-
0
Bit[3]
-
0
Bit[2]
-
0
Bit[1]
WARSCP
0
Bit[0]
WARISET
0
Update: Immediately
Bit[1]
The register data is updated to the newest data immediately when the data (“SCP”) are detected.
WARSCP
Status
Normal
0
1
Detect SCP(Note 1)
(Note 1) WARSCP turns 0 by only reset. It operates SCP circuit using “LED open circuit”.
Don’t change LEDOPEN = 0.
Bit[0]
The register data is updated to the newest data immediately when the data (“ISET short warning”) are detected.
WARISET
0
Status
Normal
Detect ISET short
1
(ISET resistor is under 2.5 kΩ)(Note 2)
(Note 2) ERRLAT = 0: WARISET turns 0, if Error is released.
ERRLAT = 1: WARISET turns 0, if “ERRCLR = 1” is set.
Address 0x4E: ERRTSDA (TSD warning)
[Read]
Initial value 0x00
Bit No
Name
Initial value
Bit[7]
Bit[6]
Bit[5]
0
Bit[4]
WARTSD[7:0]
0
Bit[3]
Bit[2]
Bit[1]
0
Bit[0]
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“TSD warning”) are detected.
Address 0x4F: ERRTSDB (TSD warning)
[Read]
Initial value 0x00
Bit No
Name
Initial value
Bit[7]
Bit[6]
Bit[5]
0
Bit[4]
WARTSD[15:8]
0
Bit[3]
Bit[2]
Bit[1]
0
Bit[0]
0
0
0
0
0
Update: Immediately
The register data is updated to the newest data immediately when the data (“TSD warning”) are detected.
WARTSD[n-1]
Status
Normal
0
1
Detect protection(Note 3)
(n = 1 to 16 channel)
(Note 3) ERRLAT = 0: WARTSD[n-1] turns 0, if Error is released or “TSDWEN = 0” is set.
ERRLAT = 1: WARTSD[n-1] turns 0, if “ERRCLR = 1” is set.
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Timing Chart
1. PWM Delay and ON Duty Setting Procedure Each Dimming Mode
Available to access register for next frame
SPI
VSYNC
register
DLYn
DTYn
update at next VSYNC
DLYCNTn
DTYn_buf
update at next PWM output
DTYCNTn
DLYCNTn
DTYCNTn
DLYCNTn
PWMn
Figure 35. Head Control(PWMFREQ[1:0] = 0)
ex) DLY01[7:0] = 0x01,DTY01[12:0] = 0x05
VSYNC
1st 2nd 3rd 4th 5th
EXTCLK
r_vsync_ext_q
(internal signal)
r_vsync_ext_qq
(internal signal)
w_vsync_pls
(internal signal)
0 x 020
dly counter
0
1
2
3
4
5
6
0
1
2
3
(internal signal)
dly counter1
0
1
2
3
4
5
6
7
(internal signal)
dly complh
(internal signal)
dly comphl
(internal signal)
PWM1 L->H : 0
H->L : DTY01+1
(when max value : 0)
DLY01[7:0]x32
DTY01[11:0]+1
PWM1
(internal signal)
Figure 36. Setting for PWM Delay and ON Duty for Head Control
By making register setting, PWM output delay and ON duty time counts of LED1 to LED16 can be controlled.
The above timing chart shows an example for LED1.
(Example) To make delay time count setting, write “delay time” in Address 0x07.
To make ON duty time count setting, write “duty time” in Address 0x18 and 0x19.
The delay counter starts counting after 4 to 5 EXTCLKs from the rise-edge of VSYNC signal due to internal signal’s timing.
When the counter reaches the set delay value (0x07), the duty counter starts counting, also PWM1 signal is set to ‘High’.
Subsequently, when the duty counter reaches the set duty value (0x18 and 0x19), PWM1 signal is set to ‘Low’.
The sequence is continuously repeated. The procedure for LED2 to LED16 is the same as LED1.
It can set delay of 256 resolution of VSYNC period.
ntn frrame
(n+1)th frame
PWMFREQ[1:0] = 3
VSYNC
EXTCLK = VSYNC × 65,536 (216) [Hz]
EXTCLK
SPI
setting for (n+1)th frame
256 clock (28)/bit
delay
ntn frrame
PWMn
Figure 37. PWM Delay (PWMFREQ[1:0] = 3)
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Timing Chart - continued
2. PWM Behavior at Close VSYNC Interval
Basically, the frequency of EXTCLK pulse is 8,192(PWMFREQ[1:0] = 0) times of that of VSYNC.
Close-interval VSYNC up to 8,192 can make the stick to ‘High’/‘Low’ of PWM signals.
Example of PWM behavior for LED1 is shown as follows.
(1) Stick to High of PWM
Example: Delay = 0, Duty = 75 %
VSYNC: 8,192 divided
VSYNC: under 8,192 divided
VSYNC
EXTCLK
main counter
compdly
Duty counter
(each LED
Channel)
compdly
PWMn
PMW is stick to High
Figure 38. Waveform Function when PWM is Fixed to High
PWM is sets to ‘High’ at the trigger of compdly (internal signal that shows the arrival of Delay set value) = ‘High’, also is set
to ‘Low’ at the trigger of compdty (internal signal that shows the arrival of Duty set value) = ‘Low’.
“Main counter” is reset and starts counting up at the rise-edge of VSYNC. If it counts up until 8,191, it keeps 8,191 until
VSYNC pulse.
“duty counter” is reset and starts counting up at trigger of compdly. If trigger of compdty is generated, it keeps counter
value until next trigger of compdly.
For this example, compdly just after the rise-edge of VSYNC sets PWM = ‘High’ because Delay = 0 %.
“Duty counter” is reset and starts counting up at the pulse of compdly. For this example, as long as VSYNC is divided by
8,192 EXTCLK, PWM is set to ‘Low’ at the trigger of compdty after the arrival of Duty set value. While, If VSYNC is less
than 8,192 EXTCLK, PWM is stick to ‘High’. Because the counter is reset since VSYNC is input before the arrival of Duty
set value, and the trigger compdty to set PWM to ‘Low’ is not provided.
(2) Stick to Low of PWM
Example: Delay = 75 %, Duty = 50 %
VSYNC: 8,192 divided
VSYNC: under 8,192 divided
VSYNC
EXTCLK
main counter
compdly
no compdly pulse
duty counter
(each LED
Channel)
compdly
PWMn
PMW is stick to Low
Figure 39. Waveform Function when PWM is Fixed to Low
When the setting of Delay is not 0, PWM is also set to ‘High’ at the trigger of compdly and is set to L at the trigger of
compdty. When VSYNC is divided by up to 8,192 EXTCLK, PWM is also set to L after the arrival of Duty set value. But
when the interval of VSYNC is less than the setting of Delay, PWM is stick to ‘Low’. Because the counter is reset since
VSYNC is input before the arrival of Delay set value, and the trigger compdly to set PWM to ‘High’ is not provided.
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2. PWM Behavior at Close VSYNC Interval - continued
(3) Lower PWM duty
Example: Delay = 0, Duty = 75 %
VSYNC: 8,192 divided
VSYNC: over 8,192 divided
VSYNC
EXTCLK
main counter
compdly
duty counter
(each LED
channel)
compdly
PWMn
lower PWM duty
Figure 40. Waveform Function when PWM Duty is Low
For this example, compdly just after the rise-edge of VSYNC sets PWM = ‘High’ because Delay = 0 %.
“Duty counter” is reset and starts counting up at the pulse of compdly. For this example, If VSYNC is more than 8,192
EXTCLK, PWM is set to ‘Low’ at the trigger of compdty after the arrival of Duty set value. Counter keep 8,191 after count =
8,191 until next rise-edge of VSYNC. So PWM is lower than target duty in this case.
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Timing Chart - continued
3. ERROR Control
There are the following internal signals on timing chart:
PWM_OH[n-1] (n = 1 to 16)
LOPDET_ID[n-1] (n = 1 to 16)
LSPDET_ID[n-1] (n = 1 to 16)
WARTSD_ID[n-1] (n = 1 to 16)
WARISET_IL
PWM signal for LEDn (high: LED ON, low: LED OFF)
LED open error signal (low: error)
LED short error signal (low: error)
TSD warning signal (low: error)
ISET short warning (low: error)
Soft start mask signal (low: mask)
retiming signal
SSEND
r_lopdet, r_lspdet, r_vsync
r_wartsd, r_wariset
err_mskcnt
retiming signal
error mask counter
Timing chart of each ERROR detection is as follows
(1) LED Short Protection
It operates as following when it detects (The LED pin voltage is over setting value) or released “LED short Error“.
(Example) Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
PWM_OH[1]
LED2
VSHDET
VSHDET
LSPDET_ID[1]
r_lspdet[1]
SSEND
err_mskcnt[7:0]
ERRMASK register
Error register
FAIL
0 x 00
0 x 03
All '0'
0 x 00
LED2 : 1 , other : 0
Figure 41. LED Short Protection
(a) Enlarged chart (A)
VSYNC
EXTCLK
PWM_OH[1]
LED2
VSHDET
LSPDET_ID[1]
mask
2clock delay
(synchronize)
r_lspdet[1]
SSEND
0 x 02 0 x 03 0 x 00
0 x 01
0 x 00
0 x 03
All '0'
err_mskcnt[7:0]
ERRMASK register
LED2 : '1' , other : '0'
Error register
FAIL
Figure 42. LED Short Protection (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
EXTCLK
PWM_OH[1]
Highꢀ
VSHDET
LED2
LSPDET_ID[1]
Highꢀ
mask
r_lspdet[1]
SSEND
Highꢀ
0 x 02 0 x 03
0 x 01
0 x 00
All '0'
0 x 00
0 x 03
err_mskcnt[7:0]
ERRMASK register
LED2 : '1' , other : '0'
Error register
FAIL
Figure 43. LED Short Protection (Enlarged View B)
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3. ERROR Control – continued
(2) LED Open Protection
It operates as following when it detects (The LED pin voltage is under 0.2 V) or released “LED open Error“.
(Example) Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
PWM_OH[1]
LED2
VOPDET
VOPDET
LOPDET_ID[1]
r_lopdet[1]
SSEND
err_mskcnt[7:0]
ERRMASK register
Error register
FAIL
0 x 00
0 x 03
All '0'
0 x 00
LED2 : 1ꢀ , other : 0ꢀ
Figure 44. LED Open Protection
(a) Detail of Enlarged chart (A)
VSYNC
EXTCLK
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
mask
2 clock delay
(synchronize)
r_lopdet[1]
SSEND
0 x 02 0 x 03 0 x 00
0 x 01
0 x 00
0 x 03
All '0'
err_mskcnt[7:0]
ERRMASK register
LED2 : '1' , other : '0'
Error register
FAIL
Figure 45. LED Open Protection (Enlarged View A)
(b) Detail of Enlarged chart (B)
VSYNC
EXTCLK
LED2
VOPDET
PWM_OH[1]
Highꢀ
LOPDET_ID[1]
Highꢀ
mask
r_lopdet[1]
SSEND
Highꢀ
0 x 02 0 x 03
0 x 01
0 x 00
All '0'
0 x 00
err_mskcnt[7:0]
0 x 03
ERRMASK register
LED2 : '1' , other : '0'
Error register
FAIL
Figure 46. LED Open Protection (Enlarged View B)
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(2) LED Open Protection – continued
[Operation]
When PWM_OH[1] = ‘High’ and LOPDET_ID[1] = ‘Low’ with SSEND = ‘High’ (Soft Start end), ERRMASK starts counting
with EXTCLK (err_mskcnt_r) from the rise-edge of PWM_OH[1]. At the arriving to the set value (0x03), FAIL is set to
‘Low’, i.e. ERROR is started to be detected. When ERROR is detected and PWM_OH[1] = ‘High’ and LOPDET_ID[1] =
High, ERRMASK starts counting with EXTCLK (err_mskcnt_r) from the rise-edge of PWM_OH[1]. At the arriving to the
set value (0x03), FAIL is set to ‘High’, i.e. It released ERROR condition.
(Example) low width error case,
Register setting: DLY02[7:0] = 0x00, ERRMASK[7:0] = 0x03, ERRLAT = 0
Enlarged view B
Enlarged view A
VSYNC
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
VOPDET
LOPDET_ID[1]
r_lopdet[1]
SSEND
err_mskcnt[7:0]
ERRMASK register
Error register
FAIL
0 x 00
0 x 00
0 x 03
Figure 47. LED Open Protection Mask Function
(a) Enlarged chart (A)
VSYNC
1st
2nd
3rd
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
2clock delay
(synchronize)
mask(3 to 4 clock)
r_lopdet[1]
SSEND
0 x 02 0 x 03 0 x 00
0 x 01
0 x 00
0 x 03
err_mskcnt[7:0]
ERRMASK register
All '0'
Error register
FAIL
highꢀ
Figure 48. LED Open Protection Masked (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
1st 2nd 3rd 4th 1st 2nd 3rd 4th
EXTCLK
r_vsync
PWM_OH[1]
LED2
VOPDET
LOPDET_ID[1]
Highꢀ
Highꢀ
mask
r_lopdet[1]
SSEND
Highꢀ
0 x 02 0 x 03 0 x 00
0 x 01
0 x 02 0 x 03
0 x 00
0 x 01
0 x 00
All '0'
err_mskcnt[7:0]
0 x 03
All '0'
ERRMASK register
LED2 : '1' , other : '0'
Error register
FAIL
Figure 49. “LED Open Protection” (Enlarged View B)
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3. ERROR Control – continued
(3) TSD Warning
If It heats over 135 deg, it detects “TSD warning” (WARTSD_ID[1] = Low).
It update error register (WARTSD[1] = 1) and FAIL = Low after detection.
If it releases error condition, it updates error register (WARTSD[1] = 0) and FAIL = High.
This function has enabled (TSDWEN). If TSDWEN = 0, it doesn’t detect “TSD warning protection”
PWM_OH[n-1] signal don’t effect “TSD warning protection”.
Enlarged view A
Enlarged view B
VSYNC
EXTCLK
PWM_OH[1]
Temp.
tMON
tMON - tMONHYS
WARTSD_ID[1]
r_wartsd[1]
WARTSD[1] register
FAIL
Figure 50. “TSD Warning”
(a) Enlarged chart (A)
VSYNC
EXTCLK
PWM_OH[1]
Temp.
High
High
tMON
WARTSD_ID[1]
r_wartsd[1]
2 clock delay
(synchronize)
WARTSD[1] register
FAIL
Figure 51. “TSD Warning” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
Low
EXTCLK
PWM_OH[1]
Temp.
Low
tMON - tMONHYS
WARTSD_ID[1]
r_wartsd[1]
2 clock delay
(synchronize)
WARTSD[1] register
FAIL
Figure 52. “TSD Warning” Released (Enlarged View B)
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3. ERROR Control – continued
(4) ISET Short Warning
If It set ISET resistor under 2.5 kΩ, it detect “ISET short warning” (WARISET_IL = Low).
It update error register (WARISET = 1) and FAIL = Low after detection.
If it release error condition, it update error register (WARISET = 0) and FAIL = High.
ERRMASK doesn’t effect this protection.
Enlarged view A
Enlarged view B
VSYNC
EXTCLK
PWM_OH[1]
RSETSCP
ISET resistor value
WARISET_IL
r_wariset
WARISET[0] register
FAIL
Figure 53. “ISET Short Warning”
(a) Enlarged chart (A)
VSYNC
High
EXTCLK
PWM_OH[1]
High
RSETSCP
ISET resistor value
WARISET_IL
r_wariset
2 clock delay
(synchronize)
WARISET[0] register
FAIL
Figure 54. “ISET Short Warning” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
Low
EXTCLK
PWM_OH[1]
ISET resistor value
WARISET_IL
r_wariset
Low
RSETSCP
2 clock delay
(synchronize)
WARISET[0] register
FAIL
Figure 55. “ISET Short Warning” Released (Enlarged View B)
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3. ERROR Control – continued
(5) TSD
If It heat over 175 deg, it detect “TSD” (TSD_IL = Low).
It update FAIL = Low and initialized all circuit after detection.
It update FAIL = High after released.
ERRMASK and SSMASK don’t effect this protection.
Enlarged view (A)
Enlarged view (B)
VSYNC
EXTCLK
TSD_IL
PWM_OH[1]
SSEND
FAIL
Figure 56. TSD
(a) Enlarged chart (A)
VSYNC
EXTCLK
TSD_IL
PWM_OH[1]
SSEND
FAIL
High
High
asynchronous reset
Figure 57. “TSD” Detected (Enlarged View A)
(b) Enlarged chart (B)
VSYNC
EXTCLK
TSD_IL
PWM_OH[1]
SSEND
FAIL
Low
reset released
Low
Low
Figure 58. “TSD” Released (Enlarged View B)
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3. ERROR Control – continued
(6) Soft-Start Masking Function
The time of mask of ERROR detection at starting of IC is set by counting the number of VSYNC.
Time of mask = set value x VSYNC
(Example) Address = 0x03(SSMASK), DATA = 0x3C:
internal reset
VSYNC
EXTCLK
PWM
LOPDET_ID[0]
SSMASK[7:0]
r_sscnt[7:0]
0x3C
0x00 0x01 0x02 0x03 0x04 0x05 0x06
0x3A 0x3B 0x3C
0xFF
0x00
released "soft start mask"
SSEND
FAIL
mask
Figure 59. Setting for Soft Start Mask
(7) LED SCP
LED SCP is operated after detecting “LED open error” and writing DTYENn = 0.
MASK time can be controlled by SCPTIME register.
FAIL outputs VSYNC pulse after the MASK time.
SPI
VSYNC
EXTCLK
LED1
LOPDET_ID[0]
DTYEN01 register
ledscp_det (internal signal)
SCPTIME register
'1'
PWM
FAIL
MASK time
2VSYNC cycle
Figure 60. SCP Function
(Note) It can’t detect “SCP error” if LEDn (n = 1 to 16) pin shorts GND before setting DTYEN = 1 and detecting LED open error”. This function is available
after detecting “LED open error”.
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Timing Chart - continued
4. Boot Sequence
(1) Normal Boot
(1)
VCC
(2)
EN
VREG33
VSYNC
EXTCLK
SPI
UVLO
(3)
(4)
PWM
standby
dimming
IC condition
OFF
OFF
Enlarged view
Enlarged view
#all device
address
#device 1
address
#device N
address
#device1
address
#device N
address
SPI
SPI
Register
PWMFREQ
DLYCNTn
PWMPLS
DTYCNTn
LCDACn
DLYCNTn
PWMPLS
DTYCNTn
LCDACn
Register
DTYCTn
LCDACn
(n = 1 to 16)
DTYCTn
LCDACn
(n = 1 to 16)
ERRSET1
SSMASK
ERRMASK
ERREN
(n = 1 to16)
(n = 1 to 16)
ERRSET2
Figure 61. Starting Sequence for Normal Operation
When you light the LED by general SPI control, follow the sequence below.
(1) Input the power supply of VCC.
(2) Launch the EN from ‘Low’ to ‘High’.
(3) Write the data to the register by SPI control, then set the LED driver.
(4) Input the VSYNC, EXTCLK signal and set register for PWM dimming.
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Timing Chart - continued
5. PWM Dimming Sequence
It has “register”, “buffer” and “control data” for DTYCNTn and LCDACn. 1st “register” are updated by SPI. 2nd “buffer” are
updated at VSYNC pulse, 3rd “control data” are updated at PWM timing as following for keeping data until finishing output.
(1) PWM Duty (DTYCNTn)/Local DAC (LCDACn) Control
VCC
EN
VREG33
Current VSYNC
Next VSYNC cycle
cycle
VSYNC
EXTCLK
(1)
SCSB
SPI
dimming
(2)
register
Update data at VSYNC
buffer
(3)
Update data at PWM timing
control data
output
PWM
Enlarged view
#device 1
address
#device N
address
SPI
……
DTYCNTn
LCDACn
(n = 1 to 16)
DTYCNTn
LCDACn
(n = 1 to 16)
Register
Figure 62. Dimming Sequence for Normal Operation
When the LEDs are controlled by general SPI control, the sequence is the following.
(1) “SPI write sequence” should be finished in “current VSYNC cycle” until next VSYNC pulse.
(2) The buffer value is updated at VSYNC timing.
(3) The control data (DTYCNTn, LCDACn) are updated and PWM is updated at the same time.
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5. PWM Dimming Sequence – continued
(2) PWM Duty (DTYCNTn)/Local DAC (LCDACn) Control (Wrong SPI Access)
If MCU access at VSYNC pulse, it don’t update buffer data for any register (update timing VSYNC, PWM)
VCC
EN
VREG33
Current VSYNC
Next VSYNC cycle
cycle
VSYNC
EXTCLK
(1)
SCSB
SPI
dimming
(2)
register
not update data at VSYNC
Update data at VSYNC
(3)
buffer
update data at PWM timing
(same data)
Update data at PWM timing
control data
PWM
output
Enlarged view
#device 1
address
#device N
address
SPI
……
DTYCNTn
LCDACn
( n =1 to 16)
DTYCNTn
LCDACn
(n = 1 to 16)
Register
Figure 63. Dimming Sequence for Normal Operation (Wrong SPI Access)
When the LEDs are controlled by general SPI control, the sequence is the following.
(1) “SPI write sequence” is not finished in “current VSYNC cycle” until next VSYNC pulse.
(2) The buffer value is not updated at VSYNC timing. (because it occurred SCSB = Low and VSYNC pulse condition)
(3) The control data (DTYCNTn, LCDACn) are not updated, because buffer value is not updated.
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Timing Chart - continued
6. Error Sequence
(1) Error Sequence for “LED Open Protection” without ERRLAT
Example) It detects “LED open error” in LED1
VSYNC
(5)
LED1
Error
condition
nomal
LED1;LED open
(3)
(4)
SPI
ERRLAT(register)
ERRCLR(register)
Lowꢀ
Lowꢀ
Highꢀ
LEDOPEN(register)
SCPTIME(register)
0
ERRLEDOPA(register)
ERRLEDOPB(register)
ERRLEDSHA(register)
0×00
0×00
0×00
0×00
0×01
0×00
ERRLEDSHB(register)
WARSCP(register)
DTYEN01(register)
DTYENn(other)
Highꢀ
leden[0](LED1)
(internal signal)
PWM OFF
(6)
(7)
PWMn
FAIL
(1)
(2)
Enlarged view
Enlarged view
SPI
Register
SPI
Register
Read:
Write:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
DTYEN01
Figure 64. Error Sequence for “LED OPEN Error” without ERRLAT
(1) If it detects “LED OPEN error”, it outputs Low from FAIL after ERRMASK time.
(2) If Error condition is released in this timing, it outputs high from FAIL after ERRMASK.
(3) MCU read “Error register” after MCU receiving FAIL = Low condition.
(4) MCU write “DTYEN01 = 0” of “Error Channel” for protection.
(5) It pulls up the LED1 pin after DTYEN01 = 0. So LED1 voltage is over 0.2 V for LED1 open.
(6) PWM output is OFF after next VSYNC and PWM timing.
(7) “Error register” and FAIL return normal condition after next VSYNC and PWM timing.
MCU can’t detect Error condition if “error condition” is cleared before reading “error register”.
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6. Error Sequence – continued
(2) Error Sequence for SCP without ERRLAT
Example) It detects “SCP Error” in LED1.
VSYNC
(5)
LED1
(2)
Error
condition
nomal
LED1;LED pin GND short
(3)
(4)
SPI
ERRLAT(register)
ERRCLR(register)
Lowꢀ
Lowꢀ
Highꢀ
LEDOPEN(register)
SCPTIME(register)
0
ERRLEDOPA(register)
ERRLEDOPB(register)
ERRLEDSHA(register)
0×00
0×00
0×00
0×00
0×01
0×00
ERRLEDSHB(register)
WARSCP(register)
DTYEN01(register)
DTYENn(other)
Highꢀ
leden[0](LED1)
(internal signal)
(6)
(7)
PWM OFF
PWMn
FAIL
(1)
(8)
Enlarged view
Enlarged view
SPI
SPI
Register
Register
Read:
Write:
DTYEN01
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Figure 65. Error Sequence for SCP without ERRLAT
(1) If it detecs “LED OPEN error” after ERRMASK time, it outputs Low from FAIL.
(2) If Error condition is released in this timing, it outputs high from FAIL after ERRMASK.
(3) MCU read “Error register” after MCU receiving FAIL = Low condition.
(4) MCU write “DTYEN01 = 0” of “Error Channel” for protection.
(5) It pulls up the LED1 pin after DTYEN01 = 0. But it can’t be over 0.3 V because LED1 shorts to GND.
(6) It doesn’t outputs PWM after next VSYNC and PWM timing.
(7) It releases “Error register” and FAIL after next VSYNC and PWM timing.
(8) It outputs VSYNC pulse from the FAIL pin after detecting SCP.
MCU can’t detect Error condition if “error condition” is cleared before reading “error register”.
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6. Error Sequence – continued
(3) Error Sequence for “LED Open Protection” with ERRLAT
Example) It detects “LED open error” in LED1
VSYNC
LED1
(2)
Error
Error
condition
nomal
nomal
(3)
(4)
(5)
SPI
ERRLAT(register)
ERRCLR(register)
Lowꢀ
Lowꢀ
Highꢀ
LEDOPEN(register)
SCPTIME(register)
0
ERRLEDOPA(register)
ERRLEDOPB(register)
ERRLEDSHA(register)
0×00
0×00
0×00
0×01
0×00
ERRLEDSHB(register)
WARSCP(register)
DTYEN01(register)
0×00
Lowꢀ
DTYENn(other)
Highꢀ
leden[0](LED1)
(internal signal)
(7)
PWMn
FAIL
(1)
(6)
Enlarged view
Enlarged view
SPI
Register
SPI
Register
Read:
Write:
DTYEN01
Write:
ERRCLR
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
Figure 66. Error Sequence for “LED Open Protection” with ERRLAT
(1) If it detects “LED open error”, it outputs Low from FAIL after ERRMASK time.
(2) If Error condition is released in this timing, it keeps Low in FAIL and “Error register”.
(3) MCU read “Error register” after MCU receiving FAIL = Low condition.
(4) MCU write “DTYEN01 = 0” of “Error Channel” for protection condition released.
(5) MCU write “ERRCLR = 1” for releasing “Latch condition”.
(6) “Error register” and FAIL return normal condition after ERRCLR = 1.
(7) PWM is OFF after next VSYNC and PWM timing.
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6. Error Sequence – continued
(4) Error Sequence SCP with ERRLAT
Example) It detects “SCP Error” in LED1.
VSYNC
(7)
LED1
Error
nomal
LED1:LED pin GND short
condition
(2)
(3)
(4)
SPI
ERRLAT(register)
ERRCLR(register)
Highꢀ
Lowꢀ
Highꢀ
LEDOPEN(register)
SCPTIME(register)
0
ERRLEDOPA(register)
ERRLEDOPB(register)
ERRLEDSHA(register)
0×00
0×00
0×00
0×01
0×00
ERRLEDSHB(register)
WARSCP(register)
DTYEN01(register)
0×00
Lowꢀ
DTYENn(other)
Highꢀ
leden[0](LED1)
(internal signal)
(6)
PWMn
FAIL
(5)
(1)
(8)
Enlarged view
Enlarged view
SPI
Register
SPI
Register
Read:
Write:
Write:
ERRLEDOPA,B
ERRLEDSHA,B
ERRISETSCP
ERRTSD
DTYEN01
ERRCLR
Figure 67. Error Sequence for SCP with ERRLAT
(1) If it detects “LED open error”, it outputs Low from FAIL after ERRMASK time.
(2) MCU read “Error register” after MCU receiving FAIL = Low condition.
(3) MCU write “DTYEN01 = 0” of “Error Channel” for protection condition released.
(4) MCU write “ERRCLR = 1” for releasing “Latch condition”.
(5) “Error register” and FAIL return normal condition after ERRCLR = 1
(6) PWM is OFF after next VSYNC and PWM timing.
(7) It pulls up LED1 pin. But it can’t be over 0.3 V because LED1 shorts to GND.
(8) It detects SCP. So output VSYNC input from the FAIL pin.
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Timing Chart - continued
7. FAIL Control Sequence
FAIL output can be controlled by register setting.
(1)
(2)
(3)
SPI
FAILTEST(register)
FAILCNT(register)
Highꢀ
Lowꢀ
FAIL
Enlarged view
Enlarged view
Enlarged view
SPI
Register
SPI
Register
SPI
Register
Write
Write
Write
FAILTEST
FAILCNT
FAILCNT
Figure 68. FAIL Control Sequence
(1) It is available to control FAIL output by FAILTEST = 1
(2) FAILCNT = High, so it outputs High from the FAIL pin.
(3) FAILCNT = Low, so it outputs Low from the FAIL pin.
(1) LED Open Protection
When PWMn = high, If the LEDn pin becomes 0.1 V (Typ) or lower, FAIL = ‘Low’ is outputted and “LED open error” will
be detected. (n = 1 to 16)
VSYNC
EXTCLK
PWMn
(internal)
LEDn
0.2 V
(1)
(2)
(3)
(4)
(5)
(6)
FAIL
ERRMASK time
Figure 69. LED Open Protection
(1) When PWMn = ‘High’, “LED open error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
(2) If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
(3) If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (High).
(4) When PWMn = ‘High’, “LED open error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
(5) If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (Low).
(6) If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
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7. FAIL Control Sequence – continued
(2) LED Short Protection
If LEDn pin becomes LEDSH[3:0](Address 0x02) when PWMn = high, FAIL = ‘Low’ is outputted and “LED short error”
will be detected. (n = 1 to 16)
VSYNC
EXTCLK
PWMn
(internal)
4.8 V (default)
LEDn
(1)
(2)
(3)
(4)
(5)
(6)
FAIL
ERRMASK time
Figure 70. LED Short Protection
(1) When PWMn = ‘High’, “LED short error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
(2) If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
(3) If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (High).
(4) When PWMn = ‘High’, “LED short error” is detected. FAIL outputs ‘Low’ after ERRMASK time.
(5) If LEDn pin voltage is release condition when PWMn = ‘Low’, it keeps FAIL condition (Low).
(6) If LEDn pin voltage is release condition, FAIL outputs ‘High’ after ERRMASK.
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Application Examples
1. External Component Setting Example
CVOUT
10 μF
DC/DC
CVCC
2.2 μF
VCC
5 V
VCC
LED1
LED2
VREG33
CVREG33
LED3
2.2 μF
LED4
LED5
RFAIL
100 kΩ
LED6
FAIL
LED7
SCSB
SDI
LED8
BD12801MUF- M
LED9
LED10
LED11
LED12
LED13
LED14
LED15
LED16
SCLK
SDO
MCU
VSYNC
EXTCLK
EN
TEST1
TEST2
GND ISET
LGND
RISET
7.5 kΩ
Figure 71. External Component Setting Example
2. Cascade Connection Application
DC/DC
Backlight
LED101 LED102 LED103
LED115 LED116 LED201 LED202 LED203
LED215 LED216
LED1 to LED24
LED1 to LED24
VCC
EN
VSYNC
EXTCLK
SCSB
SCLK
MOSI
VCC
VCC
EN
EN
VSYNC
VSYNC
EXTCLK
VREG33
VREG3 3
MCU
EXTCLK
BD12801MUF-M
BD12801MUF-M
SCSB
SCSB
(#2)
(#1)
SCLK
SCLK
SDI
SDO
FAIL
SDI
SDO
FAIL
FAIL
MISO
Figure 72. Cascade Connection Application
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I/O Equivalence Circuit
VCC
EXTCLK, VSYNC, SCLK, SDI, SCSB
FAIL
VREG33
EXTCLK
VSYNC
SCLK
SDI
VCC
FAIL
SCSB
GND
GND
GND
GND
GND
GND
LED1 to LED16
TEST1
SDO
VCC
LED1
to LED16
VREG33
TEST1
＋
－
SDO
ꢀꢀꢀ
LGND
GND
GND
LGND
LGND
GND
GND
EN
TEST2
GND,LGND
VCC
VCC
GND
EN
TEST2
200 kΩ
100 kΩ
100 kΩ
100 kΩ
30 kΩ
70 kΩ
LGND
GND
GND
GND
GND
GND
GND
ISET
VREG33
VCC
＋
－
ꢀꢀꢀ
＋
ꢀꢀꢀ
－
GND
VREG33
GND
GND
ISET
GND
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
6.
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8.
9.
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10.
Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 73. Example of Monolithic IC Structure
11.
12.
Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
Thermal Shutdown Circuit(TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF all output pins. When the Tj falls
below the TSD threshold, the circuits are automatically restored to normal operation.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13.
Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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Ordering Information
B D 1 2 8 0 1 M U F
-
ME2
Package
MUF: VQFN48FAV070
Product Rank
M: for Automotive
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagram
VQFN48FAV070 (TOP VIEW)
Part Number Marking
D 1 2 8 0 1
LOT Number
Pin 1 Mark
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BD12801MUF-M
Physical Dimension and Packing Information
Package Name
VQFN48FAV070
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Revision History
Date
Revision
001
Changes
10.May.2021
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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