BD18397RUV-M_技术文档

Datasheet

Buck LED Driver

2 ch/3 ch Current LED Driver with

SPI for Automotive

BD18397RUV-M BD18398RUV-M BD18397EUV-M BD18398EUV-M

General Description

Key Specifications

The BD18397/98xxx-M are 2 ch/3 ch synchronous buck

DC/DC LED drivers with using on-time topology

supporting near fixed switching frequency and fast

switching duty regulation and with using average LED

current feed buck topology for more accreted LED current

regulation system over wide input, LED output range.

The BD18397/98xxx-M can support individual 10-bit

analog dimming and 10-bit PWM dimming for LED current

by programing the 10-bit register via SPI.

The BD18397/98xxx-M will support LIMP-HOME mode, if

SPI communication has an error. In the LIMP-HOME

mode, individual LED current can be set by the external

pins and can keep LED current sourcing during applying

input power without SPI communication.

◼ Continuous Input Voltage Range

VIN:

PIN:

5VEXT:

5 V to 45 V

5 V to 65 V

4.5 V to 5.5 V

2.5 V to 60 V

2.0 A

±3 %

5 % to 100 %

◼ LED Output Voltage Range:

◼ Maximum Output LED Current/Channel:

◼ LED Average Current Accuracy:

◼ 10-bit Analog Dimming Range:

◼ Programmable Switching Frequency Range:

200 kHz to 2.25 MHz

◼ Junction Temperature Range: -40 °C to +150 °C

Applications

◼ Automotive Exterior Lamps

Rear, Turn, DRL/Position, Fog, High/Low Beam etc.

Features

◼ AEC-Q100 Qualified^{(Note 1)}

Packages

W (Typ) x D (Typ) x H (Max)

12.5 mm x 8.1 mm x 1.0 mm

◼ ISO 26262 Process Compliant to Support ASIL-B

◼ On-time Topology for Near Fixed Frequency Switching

◼ Average LED Current Regulation

◼ Protection Diodes Less for Current Sense Pins

◼ Cycle-by-cycle Switch Over Current Protection

◼ Thermal Shutdown (TSD)

HTSSOP-C48R

HTSSOP-C48

◼ Thermal Sensor Reading

◼ Serial Peripheral Interface (SPI)

◼ LIMP-HOME Mode

(Note 1) Grade1.

Typical Application Circuit

CPINx

VPIN

Boost

DC/DC

PGND

+B

VIN

CVIN

GND

RISN1

GND

SNSN1

RISP1

C5VEXT

C5VREG

SNSP1

RBT1

COUT1

Optional

External

5 V

CBT1

5VREG

5VEXT

BOOT1

SW1

・・・

L1

RSNS1

RSNS2

RSNS3

LED1+

RTON

ROUT1

GND

TON

COMP1

RISN2

CCOMP1 RCOMP1

CCOMP2 RCOMP2

CCOMP3 RCOMP3

SNSN2

RISP2

COMP2

COMP3

SNSP2

RBT2

COUT2

CBT2

BOOT2

V5VREG

SW2

RIS12

RIS22

LED2+

ROUT2

GND

RIS11

L2

ISET/PWM1

ISET/PWM2

ISET/PWM3

RIS21

RSO

RISN3

RIS31

RIS32

SNSN3

RISP3

SNSP3

RBT3

5 V

COUT3

CBT3

BOOT3

SW3

SO/FAULT_B

LED3+

ROUT3

L3

D3

CSB

SCK

MCU

SI

EXP_PAD

Figure 1. Typical Application Circuit

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Pin Configurations

(TOP VIEW)

GND

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

SNSN2

SNSP2

SO/FAULT_B

CSB

PGND

3

4

SCK

SI

SW1

5

SW2

SW1

COMP1

6

BD18397RUV-M

HTSSOP-C48R

BD18397EUV-M

HTSSOP-C48

BOOT2

BOOT1

7

SNSN1

SNSP1

8

COMP2

9

5VEXT

PGND

ISET/PWM 1

10

11

12

13

14

15

16

17

18

19

20

10

11

12

13

14

15

16

17

18

19

20

GND

ISET/PWM2

VIN

5VREG

TON

TOP-EXP-PAD

(GND)

BOTTOM-EXP-PAD

TON

VIN

5VREG

ISET/PWM2

GND

PGND

5VEXT

ISET/PWM 1

COMP2

SNSP1

SNSN1

BOOT1

SW1

BOOT2

SW2

COMP1

SW1

SI

21

22

21

22

SCK

PGND

CSB

SO/FAULT_B

GND

23

24

23

24

SNSP2

SNSN2

Figure 2. BD18397RUV/EUV-M Pin Configuration

(TOP VIEW)

GND

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

1

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

SNSN2

SNSP2

2

SO/FAULT_B

CSB

PGND

3

4

SCK

SI

SNSN3

SNSP3

SW1

5

SW2

SW1

COMP1

6

BD18398RUV-M

HTSSOP-C48R

BD18398EUV-M

HTSSOP-C48

BOOT2

BOOT1

7

SNSN1

SNSP1

COMP3

COMP2

8

BOOT3

SW3

9

5VEXT

PGND

ISET/PWM 1

10

11

12

13

14

15

16

17

18

19

20

10

11

12

13

14

15

16

17

18

19

20

ISET/PWM3

ISET/PWM2

GND

SW3

5VREG

TON

VIN

TOP-EXP-PAD

(GND)

BOTTOM-EXP-PAD

TON

VIN

5VREG

SW3

ISET/PWM2

ISET/PWM 3

SW3

GND

PGND

5VEXT

BOOT3

ISET/PWM1

COMP2

SNSP1

SNSN1

COMP3

BOOT1

SW1

BOOT2

SW2

COMP1

SW1

SNSP3

SNSN3

SI

21

22

21

22

SCK

PGND

CSB

SO/FAULT_B

GND

23

24

23

24

SNSP2

SNSN2

Figure 3. BD18398RUV/EUV-M Pin Configuration

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Pin Descriptions

Pin Name

HTSSOP- HTSSOP-

C48R C48

Function

Unused Pin Setting

BD18397xxx-M

BD18398xxx-M

27, 34, 46 27, 39, 46

25, 36, 48 25, 37, 48

PGND

Power ground (channel common). Not unused

Supply input voltage for power

Not unused

stage (channel common).

18

21

7

4

SNSN1

N.C.

SNSN1

SNSN3

SNSN2

SNSP1

SNSP3

SNSP2

BOOT1

BOOT3

BOOT2

SW1

LED current sense input -

Open

(channel x).

24

1

SNSN2

SNSP1

N.C.

17

8

LED current sense input +

Open

20

5

(channel x).

23

2

SNSP2

BOOT1

N.C.

42

31

Connecting series resister and

40

33

boot strap capacitor for high side

gate drive (channel x).

Open

31

42

BOOT2

SW1

Switched output connecting the

inductor (channel x).

Connecting schottky barrier diode

to the SW3 pin.

43, 44

38, 39

29, 30

9

29, 30

34, 35

43, 44

16

N.C.

SW3

SW2

ISET/PWM1

N.C.

ISET/PWM1

ISET/PWM3

ISET/PWM2

COMP1

COMP3

COMP2

LED current setting in the LIMP-

HOME mode / PWM dimming

(channel x).

Pulled down by

external resister

10

15

11

14

ISET/PWM2

COMP1

N.C.

6

19

Connecting compensation

capacitor (channel x).

7

18

Open

8

17

COMP2

Supply input voltage for signal

block.

Regulator on-time setting resister

pin. Connect a resistor between

the TON pin and GND to set the

switching frequency.

12

13

VIN

Not unused

13

12

TON

Internal 5 V regulator output

connecting 4.7 µF capacitor.

14

1, 15

33

11

10, 24

40

5VREG

GND

5VREG

GND

Not unused

Signal ground.

5 V input power supply for the

internal gate drive's connecting 4.7 Not unused

µF capacitor.

5VEXT

Open for

STNAD-ALONE

5

4

3

20

21

22

SI

Serial data input for SPI.

Open for

STNAD-ALONE

SCK

CSB

Serial clock input for SPI.

Chip select input for SPI.

SCK

CSB

GND for

STNAD-ALONE

Serial data open drain output for

SPI.

In LIMP-HOME mode, fault

condition output (open drain

output and low level active)

Connecting pulled-up resister.

Exposed pad for thermal cooling

and internal connected to

GND.^{(Note 1)}

2

23

SO/FAULT_B

Open

TOP-EXP- BOTTOM-

PAD

(GND)

-

EXP-PAD

(GND)

-

N.C.

Non wire connecting.

Open

(x = 1, 2, 3)

(Note 1) Exposed PAD is signal ground (connecting to the GND pin internally). The exposed pad should not be connecting to Power-supply or any signal nodes.

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Block Diagram

Release

Hiccup

Time

+B

VIN

CVIN

PINUVLO

UVLO

RST

SWOCPx

CPINx

CBTx

RST

SWOCPx

BG

TSD

5V_LD O

TSD

3VIO

5VEXT

RST

BOOTx

UVLO

Blanking

Time

5VREG

C5VREG

GND

TSD

DRVH

DRVL

Q

Lx

PWMONx

CHONx

LOCPx

SWx

SYSCLK

V_TEMP

PO R

3VIO

OSC

2.5 MHz

Thermal

Sensor

POR

5VEXT

On time control

NLOCPx

C5VEX T

Q

V_PIN

V_SNSPx

RST

SET

PGND

TON

Inductor current ramp slope

ONTIME

V_CSOx

2.5 V

TONx[4:0]

SSCG[2:0]

V_COMPx

RTON

Spread

Spectrum

x1

2.5 V

K_SNSNx

SNSPx

SNSNx

COMP Clamp

Valley Inductor

current detect

GM error amplifire

L

sink current

H

L

V_COMPx

GM[1:0]

V_SNSx

COMPx

x 4

RSNSx

H

CCOMPx

Rail to Rail

current sense

PWMONx

LODx

VMODEx

2.55 V

0.2 V

VCOMPxSG

H

L

H

ISET/PWMx

MIN

SEL

VIV

-

V_DCDIMx

VISETx

convertor

1 / 12

L

COUTx

EXTPWM x

5VREG

H

L

0.15 V/0.17 V

0.44 V/0.46 V

H

L

LIMPH

V_PWMx

PWMONx

LED short to

ground detect

LSDx

INTPWMx

LIMPH

1.95 V

V_LSDx

SYSCLK

PO R

ISETDIMx

LIMPH

TSD

Positive LED over

current detect

PINUVLO

UVLO

SWOCP x

V_CSOx

ISETx[9:0]

VMODEx

10 bit

D/A

3VIO

I/O

LOCPx

4 x ΔVSNSLOC

CSB

SCK

LOGIC

LOCPx

Negative LED over

current detect

TONx[4:0]

SSCG[2:0]

GMx[1:0]

LODx

VCSOx

SI

NLOCPx

4 x ΔVSNSNLOC

V_FSRADC= 2.5 V

LSDx

V_IN

VPIN

SO/FAULT_B

LOCPx

V_5VEXT

V_SNSNx

VISETx

V_TEMP

ADMON[9:0]

MUX

A/D

10 bit A/D

Figure 4. Block Diagram

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Absolute Maximum Ratings (Ta = 25 °C)

Parameter

Symbol

V_IN

Rating

-0.3 to +50

-0.3 to +70

-0.3 to +7

-0.3 to V_PIN

-0.8 to +0.8

-0.3 to +7

-0.3 to V_IN

-0.3 to +7

-0.3 to +50

-0.3 to +7

150

Unit

V

VIN Supply Voltage

PIN Supply Voltage

V_PIN

V

5VEXT Supply Voltage

BOOTx to SWx Voltage

SWx to PGND Voltage

SNSPx, SNSNx Voltage

SNSPx to SNSNx Voltage

ISET/PWMx Input Voltage

TON Input Voltage

V_5VEXT

V

V_BTSWx

V

V_{SWx_PGND}

V_SNSPx,V_SNSNx,

V_SNSx

V

V_ISET/PWMx

V_TON

V

5VREG Output Voltage

VIN to 5VREG Voltage

SI, SCK, CSB Input Voltage

SO/FAULT_B Output Voltage

Maximum Junction Temperature

V_5VREG

V

V_{VIN_5VREG}

V_SI, V_SCK, V_CSB

V_{SO/FAULT_B}

Tjmax

V

°C

Storage Temperature Range

(x = 1, 2, 3)

Tstg

-55 to +150

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing

board size and copper area so as not to exceed the maximum junction temperature rating.

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Thermal Resistance

Thermal Resistance (Typ)

Parameter

Symbol

Unit

JEDEC 2s2p

JEDEC 2s2p^{(Note 5)}

+ Heat sink^{(Note 3)}

HTSSOP-C48R

Junction to Ambient^{(Note 1)}

Junction to Case-top^{(Note 2)}

Junction to Board Characterization Parameter^{(Note 1) (Note 4)}

θ_JA

θ_{JC_TOP}

Ψ_JB

54

1.12

31

13.3

°C/W

-

7

(Note 1) θ_JA, Ψ_JBis measured with JEDEC 2s2p mounted.

(Note 2) θ_JC-TOPis measured with the IC pressed against the cold plate. The result of N = 1 pc.

For more information about traditional and new thermal metrics, see the Measurement Method and Usage of Thermal Resistance RthJC application

note.

(Note 3) Heat sink: 57 mm x 50 mm x 30 mmt, Number of FINs is 6, FIN width 1 mm, Thermal interface material thickness is 1 mm and Thermal conductivity 3.2

W/mK.

(Note 4) The thermal characterization parameter to report the difference between junction temperature and the temperature at the board located within 1 mm

from the IC.

(Note 5) Using a PCB board based on JESD51-5, 7.

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 8)}

2s2p^{(Note 9)}

HTSSOP-C48

Junction to Ambient^{(Note 6)}

Junction to Top Characterization Parameter^{(Note 6) (Note 7)}

θ_JA

62

3

22

2

°C/W

Ψ_JT

(Note 6) Based on JESD51-2A(Still-Air).

(Note 7) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface

of the component package.

(Note 8) Using a PCB board based on JESD51-3.

(Note 9) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Thermal Via^{(Note 10)}

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 10) This thermal via connects with the copper pattern of all layers.

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Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

VIN Continuous Supply Voltage^{(Note 1)}

PIN Continuous Supply Voltage^{(Note 1)}

5VEXT Continuous Supply Voltage^{(Note 1)}

SNSNx LED Output Voltage

V_IN

V_PIN

5

13

-

45

65

5.5

60

V

5

V_5VEXT

V_OUTx

4.5

2.5

5.0

Bootstrap Voltage between the BOOTx Pin and the

SWx Pin

Continuous Average LED Current

for channel 1, channel 2

V_BTSWx

I_LED1,I_LED2

I_{LED3_SBD}

3.5

-

V

A

-

1.6

Continuous Average LED Current

for channel 3 with the SBD^(Note2)

f_PWM= 200 Hz

-

0.8

1.1

1.4

A

Continuous Average LED

Current for channel 3

without the SBD ^(Note3)

f_PWM= 400 Hz

I_{LED3_NO_SBD}

f_PWM= 800 Hz

f_PWM= 1200 Hz

-

1.6

A

(external PWM only)

PWM Dimming Frequency for all channel

Channel 3 is disable

f_{PWM_CH3OFF}

f_{PWM_SBD}

200

-

Hz

PWM Dimming Frequency for all channel

Channel 3 is enabled with the SBD^(Note2)

I_{LED3_NO_SBD}= 0.8 A

200

400

800

1200

-

Hz

A

PWM Dimming Frequency for

all channel without the

SBD^(Note3)

I_{LED3_NO_SBD}= 1.1 A

I_{LED3_NO_SBD}= 1.4 A

I_{LED3_NO_SBD}= 1.6 A

BD18397RUV-M

BD18398RUV-M

BD18397EUV-M

BD18398EUV-M

f_{PWM_NO_SBD}

-

3.2

4.8

2.7

2250

-

A

Continuous Total Average LED

Current^{(Note 4)}

I_{LED_TOTAL}

-

A

-

A

Setting Switching Frequency

f_SWx

T_PWMONx

T_PWMOFFx

Topr

200

50

-40

kHz

μs

°C

PWM Dimming on Pulse Width^(Noet5)

PWM Dimming off Pulse Width^(Noet6)

-

Operating Temperature

+125

(Note 1) ASO should not be exceeded.

(Note 2) For the BD18398xxx-M only, Schottky Barrier Diodes should be needed between the SW3 Pin and the PGND Pin can support higher current setting for

the channel 3 and using lower PWM frequency, the forward drop voltage of required SBD is less than 0.81 V at the forward current 2 A.

(Note 3) For the BD18398xxx-M only, without Schottky Barrier Diodes between the SW3 Pin and the PGND Pin, minimum PWM frequency for all channel and

maximum current setting for channel 3 should be limited.

(Note 4) Set LED current for each channel less than total LED current: I_{LED_TOTAL}for the BD18397xxx-M = I_LED1+ I_LED2, I_{LED_TOTAL}for the BD18398xxx-M = I_LED1

I_LED2+ I_LED3.

+

(Note 5) Set PWM dimming on pulse width higher than T_PWMONxfor stable average LED current regulation and detecting LED open.

(Note 6) Set PWM dimming off pulse width higher than T_PWMOFFxfor stable average LED current regulation. T_PWMOFFxshould be set higher than following condition:

T_PWMOFFx> I_LEDx/ (V_OUTx/ L).

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Recommended Setting Parts Range

Parameter

Symbol

Min

Typ

Max

Unit

Coupling Capacitor Connecting to the VIN Pin^{(Note 1)}

Coupling Capacitor Connecting to the PIN Pin^{(Note 1)}

Coupling Capacitor Connecting to the 5VEXT Pin^{(Note 1)}

C_VIN

C_PINx

0.2

1.0

2.0

1

-

μF

4.7

C_5VEXT

Compensation Capacitor Connecting to the 5VREG

Pin^{(Note 1)}

C_5VREG

C_COMPx

2.0

0.01

-

4.7

0.10

0

-

μF

kΩ

Switching Compensation Capacitor Connecting to the

COMPx Pin^{(Note 1)}

Switching Compensation Series Resistor

for CC Mode Connecting to the COMPx Pin

R_{COMPx_CC}

1

Switching Compensation Series Resistor

for CV Mode Connecting to the COMPx Pin

R_{COMPx_CV}

C_OUTx

-

4.7

-

kΩ

μF

Coupling Capacitor Connecting to the SNSNx Pin

0.10

1.0

0.47

2.2

Boot Strap Capacitor Connection between the BOOTx

C_BTx

4.7

Pin and the SWx Pin^{(Note 1)}

Series Resistor Connecting to the BOOTx Pin^{(Note 2)}

Total Coupling Output Capacitor for CV Mode

Resistor Connecting to the TON Pin

R_BTx

C_{OUTx_cv}

R_TON

0.0

10

9.1

1

4.7

22.0

-

Ω

μF

kΩ

mΩ

kΩ

-

100

-

Pulled-up Resistor Connecting to the SO/FAULT_B Pin

Current Sense Resister

R_SO

-

R_SNSx

91

0.82

-

1.00

-

Resistor Connecting to the SNSPx Pin, the SNSNx Pin

Pulled-down Resistor Connecting to Output^{(Note 3)}

R_ISPx,R_ISNx

R_OUTx

1.50

100

(Note 1) Set the capacitor taking temperature characteristics, DC bias characteristics, etc. into consideration.

(Note 2) Set the series resister to improve electromagnetic interference performance.

(Note 3) Set the resister to discharge output capacitor during corresponding channel disable.

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Electrical Characteristics

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Limit

Unit

Conditions

Parameter

Symbol

Min

Typ

Max

[Total]

VIN Sleep Circuit Current

I_INSLP

I_INSTB

-

0.65

1.8

1.20

3.3

3.6

80

mA

BD18397xxx-M

BD18398xxx-M

-

VIN STANDBY

Circuit Current

-

2.0

PIN STANDBY Circuit Current

I_PINSTB

-

43

μA No-Switching

5VEXT STANDBY Circuit Current

I_5VEXTSTB

-

65

130

-

BD18397xxx-M

BD18398xxx-M

4.2

mA

V

5VEXT Switching

Circuit Current

All Channels Switching

f_SWx= 400 kHz

I_5VEXTSW

-

6.3

-

3.80

4.15

-

4.10

4.50

0.40

4.10

4.50

0.40

4.10

4.20

0.10

2.70

2.90

0.20

4.30

4.73

-

V_INUVD

V_INUVR

Falling Detect Threshold

Rising Release Threshold

Hysteresis

VIN UVLO Threshold

PIN UVLO Threshold

V

V_INUVHYS

V_PINUVD

V

3.80

4.15

-

4.30

4.73

-

V

Falling Detect Threshold

Rising Release Threshold

Hysteresis

V_PINUVR

V

V_PINUVHYS

V_5VUVD

V

3.80

3.90

-

4.30

4.40

-

V

Falling Detect Threshold

Rising Release Threshold

Hysteresis

5VREG, 5VEXT

UVLO Threshold

V_5VUVR

V

V_5VUVHYS

V_5VRPORD

V_5VRPORR

V_5VRPORHYS

V

2.50

2.70

-

2.90

3.10

-

V

Falling Detect Threshold

Rising Release Threshold

Hysteresis

5VREG POR Threshold

V

[Reference Voltage]

C_5VREG= 4.7 μF

I_5VREG= 0 mA to 25 mA

5VREG Reference Voltage

V_5VR

4.85

5.00

5.15

V

V_IN= 4.75 V

I_5VREG= 25 mA

5VREG Drop Voltage

V_5VRDP

I_5VRLM

-

0.15

0.35

V

5VREG Output Current Limit

100

-

mA

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BD18397RUV-M BD18398RUV-M BD18397EUV-M BD18398EUV-M

Electrical Characteristics - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[DCDC Convertor Switching]

I_SWx= -10 mA,

Tj = -40 °C to +25 °C

-

360

-

470

720

340

550

4.2

mΩ

A

SWx ON Resistor High Side

SWx ON Resistor Low Side

R_SWxONH

-

I_SWx= -10 mA, Tj = 150 °C

I_SWx= 10 mA,

Tj = -40 °C to +25 °C

260

-

R_SWxONL

-

I_SWx= 10 mA, Tj = 150 °C

SWx Over Current Protection

Threshold

I_SWxOCP

t_SWxOCPBLK

t_HICCUPx

t_OCPx

3.0

3.6

SWx Over Current Protection

Blanking Time

-

80

128

1.0

-

ns

μs

SWx Over Current Protection

Hiccup Time

-

SWx Over Current Protection

Flag Set Delay Time

0.7

1.3

ms

SWx Over Current Protection

Flag Release Delay Time

t_OCPxR

SWx Minimum On Time

SWx Minimum Off Time

[On Time]

t_SWxONMIN

t_SWxOFFMIN

-

90

145

150

ns

V_SNSNx= 0 V

100

V_SNSPx- V_SNSNx= 0 V

V_SNSPx= 30 V, R_TON= 51 kΩ

TONx[5:0] = 7 (default)

t_ONx1

t_ONx2

t_ONx3

1.120

0.219

0.214

1.250

0.243

0.237

1.380

0.267

0.260

μs

V_SNSPx= 30 V, R_TON= 51 kΩ

TONx[5:0] = 43

V_SNSPx= 30 V, R_TON= 9.1 kΩ

TONx[5:0] = 7 (default)

On Time Setting

-

1044

536

-

Hz

-

SSCG[2:0] = 7

SSCG[2:0] = 5

283

-

f_SSFM

SSCG[2:0] = 3

155

--

SSCG[2:0] = 1

Not applicable

SSCG[2:0] = 0 (default)

On Time Spread Spectrum

Width

t_ONSSFMW

-

±6

-

%

[GM Error Amplifier]

-

1360

870

530

300

240

120

60

-

GMx[1:0] = 0 (default)

GMx[1:0] = 1

Trans Conductance

gm

μS

GMx[1:0] = 2

GMx[1:0] = 3

GMx[1:0] = 0 (default)

GMx[1:0] = 1

COMP Source Current

COMP Sink Current

I_COMPSO

μA

GMx[1:0] = 2

30

GMx[1:0] = 3

240

120

60

GMx[1:0] = 0 (default)

GMx[1:0] = 1

I_COMPSI

GMx[1:0] = 2

30

GMx[1:0] = 3

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BD18397RUV-M BD18398RUV-M BD18397EUV-M BD18398EUV-M

Electrical Characteristics - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[Current Sense Amplifier]

V_SNSxAVE

100%H

V_SNSNx= 4 V, R_ISNx= 1 kΩ

ISETx[9:0] = 1023

184.7

160.6

90.7

15.1

153.3

-

191.5

166.6

95.6

19.1

166.6

0.203

±2

198.2

172.6

100.5

23.1

179.9

-

mV

LSB

mV

V/V

μA

V_SNSxAVE

87%H

V_SNSNx= 4 V, R_ISNx= 1 kΩ

ISETx[9:0] = 901 (default)

SNSPx to SNSNx

Total Average Current Sense

Threshold Voltage

Including SNSPx and SNSNx

Differential Input Current

Voltage Drop Over R_ISNx= 1 kΩ

V_SNSxAVE

50%H

V_SNSNx= 4 V, R_ISNx= 1 kΩ

ISETx[9:0] = 552

V_SNSxAVE

10%H

V_SNSNx= 4 V, R_ISNx= 1 kΩ

ISETx[9:0] = 176

V_SNSxAVE

87%L

V_SNSNx= 0 V, Low-side-sense

ISETx[9:0] = 901 (default)

Current Sense Threshold

Resolution

ΔV_SNSxLSB

ΔV_SNSxDNL

V_SNSxD

G_SNS

Current Sense Threshold

Differential Non-Linearity

-

Input Differential Sense Voltage

Dynamic Range

-200

-

+200

-

V_SNSxVoltage

Input Differential Sense Voltage

Output Gain

V_SNSxInput to Output for GM

Error Amplifier Gain

4

V_SNSx= 191.5 mV

V_SNSNx= 4 V

38.0

-1.5

-1.0

1.80

7

54.5

0

85.0

+1.5

+1.0

2.10

13

SNSPx Input Current

SNSNx Input Current

I_SNSPx

V_SNSx= 191.5 mV

V_SNSNx= 4 V

I_SNSNx

μA

I_{DIF_SNSx}

_100%H

V_SNSx= 191.5 mV

V_SNSNx= 4 V

μA

SNSPx and SNSNx Differential

Input Current

I_{DIF_SNSx}

_10%H

V_SNSx= 19.1 mV

V_SNSNx= 4 V

0

μA

LED Short to Ground Detect

Status Set Threshold

1.95

10

V_LSDx

V

V_SNSNxFalling

LED Short to Ground Flag Set

Delay Time

t_SNSxLVD

t_SNSxLVDR

ms

LED Short to Ground Flag

Release Delay Time

0.7

1

1.3

V_SNSxRising

ISETx[9:0] = 82 Rising

or VMODEx = 1

LED Over Current Protection

Threshold

320

390

500

ΔV_SNSxLOCP

mV

V_SNSxfalling

ISETx[9:0] = 82 Rising,

or VMODEx = 1

Negative LED Over Current

Protection Threshold

ΔV_SNSxNLOCP

-500

-390

-320

LED Over Current Protection

Blanking Time

-

120

80

-

t_SNSxLOCBLK

t_SNSxNLOCBLK

V_COMPxSG

t_SNSxSG

ns

V

Negative LED Over Current

Protection Blanking Time

LED Status Good COMP Over

Threshold

-

2.55

10

-

LED Status Good Flag Set

Delay Time

7

13

1.3

ms

LED Status Good Flag Release

Delay Time

0.7

1

t_SNSxSGR

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Electrical Characteristics - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[Voltage Sense]

SNSNx Voltage Sense Resistor

Divider Ratio

-

0.037

-

K_SNSNx

-

V_{SNSNx_1}

V_{SNSNx_2}

V_{SNSNx_3}

V_{SNSNx_4}

V_{SNSNx_5}

46.5

23.5

14.1

6.60

4.75

50.0

25.0

15.0

7.00

5.00

53.5

26.5

15.9

7.40

5.25

V

ISETx[9:0] = 758

ISETx[9:0] = 379

ISETx[9:0] = 227

ISETx[9:0] = 106

ISETx[9:0] = 76

SNSNx

Voltage Sense Threshold

SNSNx Voltage Sense

Threshold Resolution

-

0.066

-

ΔV_SNSNxLSB

V

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Electrical Characteristics - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

[A/D Convertor]

A/D Resolution

RES_ADC

t_ADC

-

10

-

bit

μs

A/D Conversion Time

11.2

A/D Full Scale

Reference Voltage

2.43

2.50

2.57

V_FSRADC

V

Integral Nonlinearity

INL

-

±2

-

LSB

V

Differential Nonlinearity

DNL

V_FSR1

V_FSR2

V_FSR3

V_FSR4

V_FSR5

48

V_IN

70

V

V_PIN

ADC Monitoring Nodes

Full Scale Range

67.5

5.5

V

V_SNSNx

V_5VEXT

V_ISET/PWMx

V

V_FSRADC

V

ADC Monitoring Nodes

Read Values Total Accuracy

-6

-

+6

ΔADC

%

394

577

418

602

442

627

ADC_TEMP25

ADC_TEMP150

-

Tj = 25 °C

Thermal Sensor Voltage ADC

Read Value

Tj = 150 °C

[PWM Dimming]

ISET/PWMx Input for DC/DC

Switching On Threshold 1

Rising

In the LEDACTIVE

V_PWMxH1

V_PWMxL1

0.42

0.40

0.46

0.44

0.50

0.48

V

ISET/PWMx Input for DC/DC

Switching Off Threshold 1

Falling

In the LEDACTIVE

Rising

In the LIMP-HOME

or STAND-ALONE

ISET/PWMx Input for DC/DC

Switching On Threshold 2

0.15

0.13

0.17

0.15

0.19

0.17

V_PWMxH2

V

Falling

In the LIMP-HOME

or STAND-ALONE

ISET/PWMx Input for DC/DC

Switching Off Threshold 2

V_PWMxL2

ISET/PWMx to DC/DC

Switching On Transition Delay

-

0.1

0.2

1.0

t_PWMxH

t_PWMxL

μs

ISET/PWMx to DC/DC

Switching Off Transition Delay

-

203

407

610

814

-

Hz

PWMDIV[2:0] = 1 (default)

PWMDIV[2:0] = 4

Internal PWM Frequency

f_PWM

PWMDIV[2:0] = 6

PWMDIV[2:0] = 7

[LOGIC I/O SCK, CSB, SI, SO/FAULT_B]

Internal Oscillator Frequency

Input Voltage High

f_OSC

V_IHxx

2.0

2.2

-

2.5

-

3.0

-

MHz

V

SCK, CSB, SI pins

Input Voltage Low

V_ILxx

-

0.6

1000

-

V

Input Pull-down Resister

CSB Pull-up Current

R_{INxx_PD}

I_CSBOL

250

-

500

10

kΩ

μA

SCK, SI pins

V_CSB= 0 V

SO/FAULT_B Output Low

Voltage

SO/FAULT_B Output Leakage

Current

V_{SO/FAULT_}

B_OL

-

0.6

1

V

I_{SO/FAULT_B_O}= 10 mA

V_{SO/FAULT_B}= 5 V

I_{SO/FAULT_}

B_LEAK

μA

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BD18397RUV-M BD18398RUV-M BD18397EUV-M BD18398EUV-M

Description of Blocks

1

Buck Converter LED Current Regulation

The BD18397/98xxx-M is synchronous buck converter with nearly fixed switching frequency and provides stable LED current

over wide input and output voltage dynamic range. The BD18397/98xxx-M is using average inductor current regulation by

control inductor valley current in average inductor current sensing feedback loop. In buck convertor topology, Inductor current

is same with LED current, so that this inductor valley current control can be used for accurate LED current regulation loop.

The BD18397/98xxx-M are using constant on time topology supporting nearly fixed switching frequency over input and

output voltage change. The internal on-time generator supporting nearly fixed switching frequency makes timing for the buck

converter SW output tuned off (“RST”) based on desired switching on-duty calculated by the real time sensing V_PINand

V_SNSPxvoltage.

The internal valley current detector makes timing for the buck converter SW output turned on (“SET”) compared with inductor

valley current and integrated error output signal V_COMPxof the GM amplifier inputs between LED current regulation reference

voltage V_DCDIMxand LED current sensing differential voltage V_SNSxbetween the SNSPx pin and the SNSNx pin.

BOOTx

ILEDxAVE

Q

DRVH

On time control

RST

SNSP x

ILEDx

SWx

ONTIME

TON

CBTx

5VEX T

5VEXT

DRVL

BOOTx

Average LED current control

SET

Q

PGND

V_COMPx

x 1

V_CSOx

Rail to Rail

current sense

Valley Inductor

current detect

GM error amplifire

SNSPx

SNSNx

COMPx

V_COMPx

RSNSx

x 4

VSNSx

GM[1:0]

V_FSRADC

0.2 V

-

VISETx_DAC

VDCDIMx

VIV

convertor

10 bit

D/A

ISETx[9:0]

COUTx

1 / 12

Figure 5. Buck Converter LED Current Regulation

On Time (T_ONx) control

→Inductor current ripple（ΔI_LEDx）control

I_LEDx

ΔI_LEDx

I_LEDxAVE

TONx

Average LED current (I_LEDxAVE） control

→Inductor bottom current control

0

T

V_SWx

0

T

Figure 6. Buck Converter LED Current Regulation Waveforms

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Description of Blocks - continued

2

LED Current Setting (Current Sense)

Full-scale LED average current can be set by resistor R_SNSxconnected between the SNSPx pin and the SNSNx pin and can

be programmable by SPI register ISETx[9:0]. The internal Rail-to-Rail current sense amplifier is monitoring LED current by

differential voltage (V_SNSx) over R_SNSbetween the SNSPx pin and SNSNx pin and generating an error output voltage

compared between the V_SNSxand the scaled reference voltage (V_DCDIMx/ 12). This error output will be integrated by the

compensation capacitor C_COMPXconnecting to the COMPx pin.

The Internal reference voltage V_DCDIMxis defined by the fixed internal offset voltage (-0.2 V) and the programable Voltage

V_{ISETx_DAC}set by the ISETx[9:0]. The 10-bit DAC convertor full scale range is 2.5 V (V_FSRADC) same with the internal 10-bit

ADC .Programmable LED average current can be calculated by as following formula.

ꢀ

ꢀ_{퐷퐶퐷ꢁ푀푥}

ꢀ

− 0.2 ꢀ

푆푁푆푥퐴푉퐸

ꢁ푆퐸푇푥_퐷퐴퐶

퐼_{퐿퐸퐷푥퐴푉퐸}

=

푅_푆푁푆푥

12 × 푅_푆푁푆푥

[

]

퐼ꢂꢃꢄꢅ 9: 0

1

= (

× ꢀ_{퐹푆ꢆ퐴퐷퐶}− 0.2 ꢀ ) ×

1024

12 × 푅_푆푁푆푥

Where:

ꢀ

is the average current sense regulation voltage.

푆푁푆푥퐴푉퐸

ꢀ_{퐷퐶퐷ꢁ푀푥}is the internal reference voltage before scaling (1 / 12) for the Rail-to-Rail current sense amplifier.

[

]

ꢀ

is the 10-bit DAC outputs set by the 퐼ꢂꢃꢄꢅ 9: 0 to define the ꢀ_{퐷퐶퐷ꢁ푀푥}

.

ꢁ푆퐸푇푥_퐷퐴퐶

ꢀ_{퐹푆ꢆ퐴퐷퐶}is the reference voltage of the 10-bit DAC outputs for the ꢀ

.

ꢁ푆퐸푇푥_퐷퐴퐶

2.5 V

V_COMPx

x 1

V_CSOx

Rail to Rail

current sense

Valley Inductor

current detect

SNSPx

GM error amplifire

V_COMPx

RSNSx

VSNSx

x 4

ILEDxAVE

SNSNx

COMPx

GMx[1:0]

V_FSRADC

0.2 V

ISETx[9:0]

-

V_{ISETx_DAC}

V_DCDIMx

VIV

convertor

1 / 12

10 bit

D/A

COUTx

Figure 7. LED Current Setting

VSNSxAVE

191.5 mV

Constant Ripple Voltage

ΔV_SNSx

V_{SNSx_PK}

V_SNSxAVE= ⊿V_DCDIMx/ 12

V_{SNSx_VAL}

Dis-continuous

V_FSRADC

0 mV

0

2.5 V V_{ISETx_DAC}

0.2 V

0 %

⊿V_DCDIMx

100 %

1024

ISETx[9:0]

0

82

1023

Figure 8. Current Sense Regulation Voltage Setting

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Description of Blocks - continued

3

DCDC Switching Frequency

The buck converter switching on-duty (D_ONx) and frequency (f_SWx) is defined as following.

ꢀ

ꢇ_푂푁푥

1

ꢀ

푆푁푆푃푥

ꢇ_푂푁푥

=

,

ꢄ_푂푁푥

=

→ 푓

=

×

푆푊푥

ꢀ_푃ꢁ푁

푓

푆푊푥

ꢄ_푂푁푥ꢄ_푂푁푥

ꢀ_푃ꢁ푁

The buck converter switching frequency (f_SWx) can be nearly fixed by the adapting constant on time, this on-time T_ONxwill be

proportional to switching on-duty D_ONxby monitoring the buck converter input voltage as the V_PINand output voltage as the

V_SNSPxas following formula.

1

ꢀ

푆푁푆푃푥

푓

푆푊푥

≒

×

≒ ꢈ표푛푠푡푎푛푡 → ꢄ_푂푁푥∝

ꢄ_푂푁푥

ꢀ_푃ꢁ푁

The BD18397/98xxx-M has the individual on-time circuit in channels generating adapting constant on time T_ONxset by the

SPI. The On time itself will be changed over switching on-duty changed for fixed switching frequency so that the buck

converter switching frequency is set by the SPI register TONx[5:0] and the external resistor (R_TON).

푘

ꢀ

푆푁푆푃푥

ꢄ_푂푁푥

≒

× 푅_푇푂푁

×

× 10^ꢋ6+ 20 × 10^ꢋꢌ, ꢍ푘 = 0.00038ꢎꢏ

[

]

ꢄꢉꢊꢅ 5: 0 + 1

ꢀ_푃ꢁ푁

1

ꢀ

푆푁푆푃푥

푓

푆푊푥

×

푘

ꢀ

푆푁푆푃푥

ꢀ_푃ꢁ푁

× 푅_푇푂푁

×

× 10^ꢋ6+ 20 × 10^ꢋꢌ

[

]

ꢄꢉꢊꢅ 5: 0 + 1

*More than 2.25 MHz setting cannot be used.

Figure 9. DCDC Switching Frequency vs TON_X[5:0] (D_ONx= 0.5, R_TON= 51 kΩ)

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3

DCDC Switching Frequency - continued

2800

2400

2000

1600

1200

800

400

0

20

40

60

80

100

120

R_TON[kΩ]

Figure 10. Switching Frequency vs R_TON(D_ONx= 0.5, TONx[5:0] = 7)

The BD18397/98xxx-M has built-in spread spectrum function and the modulation switching frequency is ± 6% (Typ) around

the setting frequency f_SWx. The spread spectrum modulation frequency can be programmable by the register SSCG[2:0].

When SSCG[2:0] is set to 0, spread spectrum modulation is not applicable. When enable the SSCG function, all channels

of ON time generator use same modulation frequency (f_SSFM) to make spread on time based on monitoring on-duty.

SSCG[2:0]

0x0

f_SSFM[Hz]

SSCG Not applicable

0x1

0x2

0x3

0x4

0x5

0x6

0x7

155

185

283

361

536

763

1044

f_SWx± 6 %

fSWx

fSSFM = 0 %

f_SSFM

T

Figure 11. Spread Spectrum

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Description of Blocks - continued

4

Internal PMW Dimming Setting (In the LEDACTIVE Mode)

The BD18397/98xxx-M has an internal 10-bit PWM dimming generator to make timing for individual buck converter switching

on/off. The internal PWM dimming (INTPWMx) ON duty cycle (D_PWMx) set by SPI register the DPWMx[9:0].

PWM dimming frequency f_PWMcan be set by SPI register the PWMDIV[2:0] and this PWM dimming frequency setting is

commonly used in all buck channels for synchronous PMW dimming within the device itself.

[

]

ꢇꢐꢑꢒꢅ 9: 0 + 1

ꢇ_푃푊푀푥

=

, ꢄ_{푃푊푀푂푁푥}=

1024

푓

푃푊푀

f_PWM[Hz]

PWMDIV[2:0]

0x0

0x1

0x2

0x3

0x4

0x5

0x6

0x7

153

203

244

305

407

488

610

814

Minimum PWM dimming pulse width is depends on using inductor and average current setting because of inductor current

charge per one DCDC switching on cycle limited.

I_LEDx

I_LEDxAVE

I_{LEDx_VAL}

T_ONx

0

T

T_PWMONx

PWMONx

T

Figure 12. PWM Dimming Waveform

5

External PWM Dimming Setting (In the LEDACTIVE Mode)

PWM Dimming on Pulse Width T_PWMONxis controlled by internal PWM dimming generator or external PWM dimming control

by the ISET/PWMx pin when the ISETDIMx bit is set in the LEDDC register. If the ISET/PWMx pin is set to high level, TPWM

is equal with internal PWM on cycle (DPWM_x). If the ISET/PWMx pin is set to low level, TPWM goes low and LED current

force turned off. In case of PMM dimming setting DPWMx100% (default), the ISET/PWMx pin can be used for external PWM

dimming control for LED current on/off same with internal PWM dimming use case. Minimum PWM dimming pulse width is

depends on using inductor and average current setting because of inductor current charge per one DCDC switching on

cycle limited.

PWMONx Definition for channel x

ISETDIMx

LEDACTIVE

DPWMx[9:0]

ISET/PWMx pin & DPWMx[9:0]

LIMP-HOME or STAND-ALONE

0

1

ISET/PWMx pin

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Description of Blocks - continued

6

Hybrid External Analog and PWM Dimming Setting (In the LIMP-HOME and STAND-ALONE Mode)

The BD18397/98xxx-M supports “External Analog Dimming mode when the IC state is into the LIMP-HOME or STAND-

ALONE mode.

In the external analog dimming mode, internal reference voltage for current regulation can be defined by the ISET/PWMx

pin voltage (V_ISET/PWMx). When the external input voltage V_ISET/PWMxpin voltage is less than internal reference voltage

V_{ISETx_DAC}, feed-back voltage V_SNSxwill be regulated by external pin voltage setting.

In case of using analog dimming and PWM dimming by the ISET/PWMx pin, applying PWM peak voltage defines analog

dimming level I_LEDxAVEand PWM duty (D_PWMx) defines PWM dimming ON time T_PWMONx. The analog dimming peak voltage

V_{PWMx_PK}can be set by the voltage divider (R_ISX1and R_ISX2) and PWM duty (D_PWMx) control by external NPN transistor by

applying invert PWM signals (PWMx_B).

Current Setting Definition for channel x

LEDACTIVE

LIMP-HOME or STAND-ALONE

ISETx[9:0]

ISETx[9:0] & ISET/PWMx pin

if ꢀ

> ꢀ

ꢁ푆퐸푇/푃푊푀푥

ꢁ푆퐸푇푥_퐷퐴퐶

ꢀ_{퐷퐶퐷ꢁ푀푥}= ꢀ

− 0.2 ꢀ,

ꢁ푆퐸푇/푃푊푀푥

ꢀ_{퐷퐶퐷ꢁ푀푥}= ꢀ

− 0.2 ꢀ

ꢁ푆퐸푇푥_퐷퐴퐶

if ꢀ

< ꢀ

ꢁ푆퐸푇푥_퐷퐴퐶

ꢁ푆퐸푇/푃푊푀푥

ꢀ_{퐷퐶퐷ꢁ푀푥}= ꢀ

− 0.2 ꢀ

ꢁ푆퐸푇푥_퐷퐴퐶

Rail to Rail

current sense

GM error amplifire

SNSPx

SNSNx

VCOMPx

V5VREG

V_ISET/PWMx

x 4

VSNSx

RISx1

RISx2

0.2 V

VISET/PWMx

ISET/PWMx

H

t

-

V_DCDIMx

VIV

MIN

SEL

convertor

1 / 12

L

PWMx_B

H

EMHx

PWMONx

5VREG

L

0.17 V / 0.15 V

V_PWMx

INTPWMx

LIMPH-HOME

or

STAND-ALONE

V_FSRADC

10bit

LOGIC

D/A

V_{ISETx_DAC}

ISETx[9:0]

Figure 13. Hybrid External Analog and PWM Dimming

T_PWMONx

I_LEDxAVE

V_DCDIMx= V_{ISETx_DAC}

V_{ISETx_DAC}

V_DCDIMx= V_{PWMx_PK}

T

0

V_ISET/PWMx

D_PWMx

VISETx_DAC

V_{PWMx_PK}

V_PWMx

T

V_{PWMx_B}

Figure 14. Hybrid External Analog and PWM Dimming Waveforms

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Description of Blocks - continued

7

Bootstrap Charge

The BD18397/98xxx-M is synchronous buck DC/DC LED drivers and contains high side and low side N-channel FETs.

The high side gate driver can be working by proper power supply voltage input between the BOOTx pin and the SWx pin.

The connecting bootstrap capacitor C_BTxcan be charged from the 5VEXT pin supply through the internal diode during the

SWx pin is pull-down. During the SWx pin switching, corresponding channel bootstrap voltage can maintain by refreshed

capacitor energy. When the SWx pin is Hi-z (CHONx = 0 or corresponding channel PWM dimming off time), the bootstrap

voltage cannot maintain and becomes lower voltage than recommended bootstrap voltage (V_BTSWx> 3.5 V). Alarge bootstrap

capacitor is required to prevent lower bootstrap voltage operation when using lower PWM frequency. An external bleeder

resistor R_OUTxconnecting to the output is required to charge the bootstrap capacitor during the SWx pin is Hi-z (CHONx =

0) and to reduce negative inductor current energy from the output by the SWx pin pulled-down for bootstrap charged at

channel turned on. In case of an adding bleeder resistor is not enough off time (CHONx = 0) for completely discharging

output capacitor energy, the output capacitor can be fast discharged by the negative inductor current regulation setting

(recommended ISETx[9:0] = 57) before channel turned off (CHONx = 0). When turning on the corresponding channel, the

output voltage must be sufficiently discharged (V_OUTx< 1.5 V) before turning on the corresponding channel (CHONx = 1) to

ensure that the bootstrap voltage is above the recommended operating voltage (V_BTSWx> 3.5 V).

I_LEDxAVE

T_PWMONx

PWM dimming off

0

T

refresh bootstrap

capcitor energy

V_BTSWx

large bootstrap capacitor reuqired

Recommended bootstrap voltage

3.5 V

small bootstrap

capacitor

T

Figure 15. Bootstrap Charge During PWM Dimming Waveforms

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7

Bootstrap Charge - continued

I_LEDxAVE

CHONx = 1

ISETx[9:0] = 901 ISETx[9:0] = 57

CHONx = 0

CHONx = 1

ISETx[9:0] = 901

Negative LED

current regulation

Start-up

0

T

V_OUTx

witout negative LED current regulation

fast dischaged by negative LED

current regulation

Compltely dischaged

T

refresh bootstrap capcitor energy

V_BTSWx

3.5 V

Recommended bootstrap voltage

T

Figure 16. Bootstrap Charge During Channel Off Waveforms

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Description of Blocks - continued

8

Voltage Regulation (In the LEDACTIVE Mode)

The BD18397/98xxx-M supports “Voltage regulation mode when the VMODEx bit is set in the DCDCSET4 register.

In the voltage mode, the BD18397/98xxx-M regulates the SNSNx pin voltage (V_SNSNx) by control inductor valley current in

average voltage sensing feedback loop. In the voltage mode, The BD18397/98xxx-M are using constant on time topology

supporting nearly fixed switching frequency over input and output voltage change. The internal on-time generator supporting

nearly fixed switching frequency makes timing for the buck converter SW output tuned off (“RST”) based on desired switching

on-duty calculated by the real time sensing V_PINand V_SNSNxvoltage.

The internal valley current detector makes timing for the buck converter SW output turned on (“SET”) compared with inductor

valley current and integrated error output signal V_COMPxof the GM amplifier inputs between reference voltage V_DCDIMxand

output voltage V_SNSNxpin.

For soft-output-start to reduce rush charge output current, programmed soft-ramp-up reference voltage (V_DCDIMx) or soft-

ramp-up the COMP pin voltage by more compensation capacitor (C_COMPx).

The voltage regulation mode setting is only activated in LEDACTIVE MODE. In case of LIMP-HOME or STAND-ALONE

mode, DCDC coveter should be disabled by corresponding the ISET/PWMx pin pulled down.

ꢀ

=

^{퐼ꢂꢃꢄꢅ_ꢇꢓꢈ}= (^{퐼ꢂꢃꢄꢅꢔ9:0ꢕ}× ꢀ_{ꢖꢂ푅ꢓꢇꢈ}) ×

1

ꢀ_{ꢂꢊꢂꢊꢅ}

퐾_{ꢂꢊꢂꢊꢅ}

1024

퐾_{ꢂꢊꢂꢊꢅ}

Where:

ꢀ_{ꢂꢊꢂꢊꢅ}is the output regulation voltage.

퐾_{ꢂꢊꢂꢊꢅ}is the internal voltage divider. 퐾_{ꢂꢊꢂꢊꢅ}= 1 / 27.

[

]

ꢀ_{퐼ꢂꢃꢄꢅ_ꢇꢓꢈ}is the 10-bit DAC outputs set by the 퐼ꢂꢃꢄꢅ 9: 0 for the internal reference voltage

of the GM amplifier to define the ꢀ_{ꢂꢊꢂꢊꢅ}

ꢀ_{ꢖꢂ푅ꢓꢇꢈ}is the reference voltage of the 10-bit DAC outputs the ꢀ_{퐼ꢂꢃꢄꢅ_ꢇꢓꢈ}

.

BOOTx

ILEDxAV E

Q

DRVH

On time control

RST

ILEDx

SNSPx

SWx

TON

ONTIME

C_BTx

5VEXT

DRVL

BOOTx

Average LED current control

SET

Q

PGND

V_COMPx

x 1

CC

V_CSOx

Rail to Rail

current sense

Valley Inductor

current detect

SNSPx

SNSNx

GM error amplifire

COMPx

CV

CC

CV

VCOMPx

RSNSx

x 4

VSNSNx

0.2 V

VIV

convertor

1 / 12

10 bit

D / A

COUTx

ISETx [9:0]

V_DCDIMx

Voltage sense divider

kV_SNSNx

K_SNSNx

Figure 17. Buck Converter Voltage Regulation

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8

Voltage Regulation (In the LEDACTIVE Mode) - continued

V_SNSNx

V_SNSNxAVE

T

On Time (T_ONx) control

→Inductor current ripple（ΔI_LEDx）control

I_LEDx

ΔI_LEDx

T_ONx

Average Voltage (V_SNSNxAVE） control

→Inductor bottom current control

0

T

V_SWx

0

T

Figure 18. Buck Converter Voltage Regulation Waveforms

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Description of Blocks - continued

9

Abnormal Detection/Protection Function

Detecting Condition

(all the value is typical)

Detection/

Description in Detecting

SO/FAULT_B

Output

Protection

Function

Detection

Release

Buck DCDC

Register

ADC

STAND-

ALONE

MODE

5VREG

POR

V_5VREG

2.7 V

≤

V_5VREG

2.9 V

≥

All channels

SWx = Hi-Z

All registers

initialized.

Not

Available

Hi-Z

5VREG off

All channels

SWx = Hi-Z

Not updated

All registers will

be initialized by

5VREG POR.

Not

Available

VIN UVLO

V_IN≤ 4.1 V

V_IN≥ 4.5 V

COMPx discharged

5VREG

5VEXT

UVLO

V_5VREG≤ 4.1 V

or

V_5VEXT≤ 4.1 V

V_5VREG≥ 4.2 V

or

V_5VEXT≥ 4.2 V

All channels

SWx = Hi-Z

COMPx discharged

UVLO bit is set in

the Status

Not

Available

Hi-Z

register.

All channels

SWx = Hi-Z

COMPx discharged

PIN UVLO bit is

set in the Status

register.

Not

Available

PIN UVLO

V_PIN≤ 4.1 V

V_PIN≥ 4.5 V

Corresponding

channel

SWx = Pull-down

COMPx discharged

with

Corresponding the

SWOCPERRx bit

is set in the status

register and

will be reset after

10 ms counts by

SWOCPx release.

SWx Over

Current

Protection

(SWOCPx)

I_SWx> 3.6 A

I_SWx< 3.6 A

Available

Low

Hiccup time (128

μs)

Corresponding

channel

SWx = Pull-down

COMPx

LED Over

Current

Protection

(LOCPx)

Corresponding the

LEDOCPERRx bit

is set in the status

register.

V_SNSx

V_SNSxAVE

390 mV

>

V_SNSx

V_SNSxAVE

390 mV

<

+

Available

Low

discharged.

Negative

LED Over

Current

Protection

(NLOCPx)

Corresponding the

LEDOCPERRx bit

is set in the status

register.

V_SNSx

V_SNSxAVE

390 mV

<

V_SNSx

V_SNSxAVE

390 mV

>

Corresponding

channel

SWx = Pull-up

-

Corresponding the

LODx bit is set in

LED Open

Detection

(LODx)

V_COMPx

2.55 V and

PWMONx = H

>

V_COMPx<

2.55 V and

PWMONx = H

Continue switching. the status register Available

after 10 ms

counts.

Continue switching

Corresponding the

and common mode

LSDx bit is set in

input range (SNSPx

the status register Available

and SNSNx)

LED Short

to ground

Detection

(LSDx)

V_SNSNx

1.95 V

<

V_SNSNx

1.95 V

>

Hi-Z

after 10 ms

switched to low-

counts.

side-sense.

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Description of Blocks - continued

10 5VREG, 5VEXT

The 5VREG voltage 5.0 V (Typ) is generated from the VIN pin voltage. This voltage is used as the internal power supply of

the IC. 5VEXT is external power supply input for the Gate Driver. The 5VREG can be used for connecting to the 5VEXT for

the power supply. 5 V external power supply can be connecting to the 5VEXT for internal gate drive power supply to reduce

power loss with high frequency switching in the device. The total current supplied for the internal gate driving should not

exceed I_5VRLM. The current supplied to the internal gate driving per channel can be calculated by the following formula.

퐼_퐹퐸푇/푐ℎ푎푛푛푒푙 = 푄_퐺× 푓

= 4.8 [푛ꢈ] × 푓

푆푊푥

Where:

푄_퐺is the internal gate charge of the MOSFETs per channel (in case of applying V_PIN= 60 V).

is the DC/DC switching frequency.

푓

푆푊푥

Connect C_5VREG= 4.7 µF as phase compensation capacitor to the 5VREG pin. Connect C_5VEXT= 4.7 µF as Coupling capacitor

to the 5VEXT pin. Place ceramic capacitor close to the IC to minimize trace length to the 5VREG pin and 5VEXT pin to the

IC ground. The 5VREG pin will not be used for as a power supply other than this IC.

11 Power on Reset (POR)

The BD18397/98xxx-M has a POR circuit monitoring the internal power supply output V_5VREG. When detecting POR, Internal

all circuits and logic registers will be initialized. POR circuit main purpose is internal logic initialized in POR condition by

reset signal. Between the POR detection threshold and UVLO detection threshold of the 5VREG pin, internal register values

will not be reset and can be read by SPI.

12 Under Voltage Locked Out (UVLO)

The BD18397/98xxx-M has UVLO circuits monitoring the input power supplies V_INfor the internal reference circuits including

TSD circuit and V_5VREGfor the internal 5 V LDO output, and V_5VEXTfor the internal gate drives and Logic and POR and analog

circuits includes thermal sensor, and V_PINfor drain node of high-side FET and SWOCPx circuit in all channels.

When detecting a UVLO by the V_INor V_5VREGor V_5VEXTor V_PIN, all buck DC/DC converter, including ADC convertor are

immediately shutdown and all SW outputs are Hi-Z. Internal analog circuits are initialized so that all COMP pins will be

discharged. When detecting a UVLO by the V_PIN, corresponding buck DC/DC converter is disabled immediately and SWx

output is off and the COMPx pin will be discharged. When recover a UVLO, buck DC/DC converter needs wait time for start-

up until the COMPx pin charged up and reach to desired inductor valley regulation voltage.

in start-up

after UVLO release

in UVLO

detecting

in UVLO

detecting

I_LEDx

I_LEDxAVE

0

T

V_COMPx

2.5 V

0

T

V_SWx

0

T

Figure 19. Buck Converter Start-up Waveform

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Description of Blocks - continued

13 Thermal Shutdown (TSD)

In case of a TSD as Tj > 175 °C (Typ), all the buck DC/DC converters will be disable immediately and Internal all circuits

and logic registers will be initialized and the SO/FAULT_B pin goes low level output. When TSD recovered at Tj < 150 °C

(Typ), the SO/FAULT_B pin goes high level output, the DC/DC converters will be in the SPIWAIT state until start-up sequence

trigger happened.

14 SW Over Current Protection (SWOCPx)

The device has a SWOCPx circuit monitoring the output current of the SWx pin. In case of inductor peak current is not

limited during the internal high side FET switched on, the internal OCP is detected when the SWx output current exceeds

3.6 A typical. The corresponding channel SWx output will be immediately switched off, and the COMPx pin will be discharged

and the SWOCPERRx bit is set in status register. After recovery switching during T_OCPRx(10 ms) counts without detecting

SWOCPx, the SWOCPERRx bit is reset (set flag latched in case of SWOCPLAT = 1).

I_SWx

SWx short to GND

T_HICCUPx

in start-up

T_HICCUPx

I_SWOCPx

0

SWOCPx

reg SWOCPx

T_OCPRx= 10 ms

Figure 20. SW Over Current Protection Waveform

15 LED Over Current Protection and Negative LED Over Current Protection (LOCPx and NLOCPx)

The device has LOCPx and NLOCPx circuits and are monitoring LED current by output of the internal Rail-to-Rail current

sense amplifier sensing differential voltage over R_SNSxbetween the SNSPx pin and SNSNx pin.

Internal LOCPx is detected when the V_SNSxvoltage exceeds ΔV_SNSxLOCP(390 mV fixed value) from setting regulation voltage.

The corresponding channel the SWx pin output will be immediately switched off, and the COMPx pin will be discharged until

LOCPx detecting release. In detecting the LOCPx, corresponding channel of the LEDOCPERRx bit is set in status register

(set flag latched in case of LEDOCPLAT = 1).

Internal NLOCPx is detected when the negative V_SNSxvoltage exceeds ΔV_SNSxNLOCP(-390 mV fixed value) from setting

regulation voltage. The corresponding channel the SWx pin output will be immediately switched on (cycle by cycle). In

detecting the NLOCPx, corresponding channel of the LEDOCPERRx bit is set in status register (set flag latched in case of

LEDOCPLAT = 1).

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Description of Blocks - continued

16 LED Open Detection

LED open detection will happen in a LED open failure, a connector to a LED’s boars opened. When a LED opened, a LED

current is not flowing through the shunt resistor R_SNSxbetween the SNSPx pin and SNSNx pin so that its differential average

voltage V_SNSxAVEgoes zero level input for average current regulation loop. Internal average LED current regulation loop get

feed-back of lower current compared with desired LED current setting. So that the internal error GM amplifier output as the

COMP pin output voltage V_COMPxwill be increased and clamp to the COMPx pin over voltage detect level V_COMPxSG. This

clamp level is optimized, and clamp level is much closed to regulation DC voltage. This technology will help eliminating LED

over current incase of LED open failure recovery or lower input voltage recovery. In detecting LED open, corresponding

channel of the LODx bit is set in status register after t_SNSxSG(10 ms) counts. When LED open detect release by average

current sense voltage V_SNSxAVEgoes high level, the LODx bit is reset after t_SNSxSGR(1 ms) counts.

in LED Open

detecting

in start-up

after LED Open release

V_LEDx

V_PIN

LED Open

I_LEDxAVE

Continue switching

0

V_COMPx

V_COMPxSG

COMP clamp

LODx

t_SNSxSG

t_SNSxSGR

reg LODx

Figure 21. LED Open Detection Waveform

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Description of Blocks - continued

17 LED Short to GND Detection

LED short can be detected by a LED anode voltage at the SNSNx pin less than V_LSDx(1.95 V). In case of a LED short to

ground condition time is more than t_SNSxLVD(10 ms), the corresponding channel of the LSDx bit is set in status register. When

a LED short to ground release by the SNSNx pin voltage higher than the V_LSDx, the corresponding channel of LSDx bit is

reset after t_SNSxLVDR(1 ms) counts. In a LED short to ground, the device will continue LED average current regulation and

buck DC/DC on time is limited by internal minimum on time t_SWxONMIN(90 ns) .and LED ripple current ΔI_{LED_ON}(regulated

LED ON current) during t_SWxONMINwill be higher than expected LED ripple. In addition, LED current down slope is more less

than LED minimum output connecting case and the LED valley detect comparator (for sending ON signal) will wait long off

time (T_OFFx) until inductor current going down to desired bottom (Valley) current based on regulation loop.

LED short detection is activated by corresponding channel of the CHONx bit is set in CHEN register, including PMWOFF

condition so that long PWM off condition will be results in LED short detection flag set in the status register and depends on

remaining output capacitor at the SNSNx pin.

in LED Short to Ground

ΔI_{LED_ON}

I_LEDxΔI_LEDx

I_LEDxAVE

T_ONx

t_SWxONMIN

T_OFFx

0

T

V_SNSNx

V_LSDx

0

T

LSDx

t_SNSxLVD

reg LSDx

Figure 22. LED Short to GND Detection Waveform

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Description of Blocks - continued

18 State Machine

Low quiescent current mode

(no oscillation)

RESET

release POR & TSD

automatic

operation

CSB pin = low > 0.8 ms

SPI

WAIT

STAND

ALONE

CSB pin = high

WDTEN = 1 &

No SPI Access > 1 s

SPI Access

STAND

BY

released

UVLOVIN &

SLEEP = 0

WDTEN = 1 &

No SPI Access > 1 s

ALL

CHONx = 0

ANY

LIMP

HOME

CHONx = 1

SLEEP

SPI Access

detecting

UVLOVIN ||

SLEEP = 1

LED

ACTIVE

SPI Access: SPI access and CRC OK

No SPI Access: no access or access but CRC NG

Figure 23. State Machine

Table 1. State Machine Description

Quiescent

Current

SO/FAULT_B

(Operation)

State

LED Lighting

Description

RESET

Low

OFF

Hi-Z

All internal block is initialized.

Dimming mode is selected in this state. IC

can enter STAND-ALONE mode by CSB =

Low for 0.8 ms. This feature can only be used

in this state. If not used, this feature can be

available after POR or TSD.

SPIWAIT

Normal

Hi-Z

During setting register or turn off

A/D conversion is available.

STANDBY

LEDACTIVE

SLEEP

Normal

Low

OFF

SO

Lighting

(Programmed by

SPI)

Dimming is programmed by SPI setting.

A/D conversion is available. Protection status

can be checked by Register polling.

Keep Low quiescent current until SLEEP = 0.

All register value is kept (not initialized).

OFF

When MCU cannot communicate with this IC,

This IC keeps lighting by external resistor

setting. No communication includes CRC NG

SPI Communication.

When CSB = Low for 0.8 ms, This IC keeps

lighting by external resistor setting. Protection

can be checked by monitoring SO/FAULT_B

= Low.

Lighting

(Programmed by

external resistor)

LIMP-HOME

Normal

SO

Lighting

(Programmed by

external resistor)

STAND-ALONE

FAULT_B

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18 State Machine - continued

Table 2. State Machine Description for Dimming

ISETDIM

(Register)

State

RESET

LED Lighting

LED Current Setting

PWM Dimming Setting

-

0

-

SPIWAIT

0

0/1

0

OFF

STANDBY

DPWMx[9:0] register

LEDACTIVE

Lighting

ISETx[9:0] register

-

DPWMx[9:0] register

& ISET/PWMx pin

1

SLEEP

0/1

OFF

-

LIMP HOME

STAND-ALONE

ISETx[9:0] register &

ISET/PWMx pin

0/1

Lighting/OFF

ISET/PWMx pin

*ISETDIMx initial value = 0

Ex1. ) LED ON in LIMP-HOME/STAND-ALONE

with ISETDIMx = 0

Ex2. ) LED OFF in LIMP-HOME/STAND-ALONE

with ISETDIMx = 0

ISET/PWMx pin > VPWMx

RESET

ISET/PWMx pin < VPWMx

RESET

STAND-ALONE

LED ON

LED OFF

write ISETDIMx = 0

DPWMx = 50 %

write ISETDIMx = 0

DPWMx = 50 %

LEDACTIVE

LED ON

DPWMx = 50 %

LEDACTIVE

LED ON

DPWMx = 50 %

LIMP-HOME

LED ON

DPWMx = 100 %

LIMP-HOME

LED OFF

Ex3. ) LED ON in LIMP-HOME/STAND-ALONE

with ISETDIMx = 1

Ex4. ) LED OFF in LIMP-HOME/STAND-ALONE

with ISETDIMx = 1

ISET/PWMx pin > VPWMx

RESET

ISET/PWMx pin < VPWMx

RESET

STAND-ALONE

LED OFF

LED ON

write ISETDIMx = 1

DPWMx = 50 %

write ISETDIMx = 1

DPWMx = 50 %

LEDACTIVE

LED ON

DPWMx = 50 %

LIMP-HOME

LED ON

DPWMx = 100 %

LEDACTIVE

LED OFF

STAND-ALONE

LED OFF

Figure 24. Example of Operation Flow

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Description of Blocks - continued

19 SPI Protocol and AC Electrical Characteristics

This IC can be accessed via SPI using CSB, SCK, SI, SO/FAULT_B terminals as shown in.

CSB

– Chip Select

SCK

– Serial Clock

SI

– Serial Data input

– Serial Data output

SO/FAULT_B

CSB

SCLK

MOSI

BD18397/98xxx-M

SO/FAULT_B

MCU

MISO

Figure 25. MCU Connection

Select the IC to be accessed by setting the CSB to low. Send the data based on the format as shown in. Data to be sent

follow a MSB first 24-bit data format for write: 1-bit RW (read or write), 7-bit register address, 8-bit register data (to be written)

and 8-bit CRC. SPI can be accessed in daisy chain connection or parallel connection. There is no multiple bytes write/read

feature. After each command, fix SI to low and CSB to high. SI data is outputted with 24 bits shift from SO/FAULT_B.

SO/FAULT_B keeps Hi-z when CSB = high.

CSB

SCK

Address

Data

CRC

AD AD AD AD AD AD AD WD WD WD WD WD WD WD WD WC WC WC WC WC WC WC WC

[6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]

RW

SI

SO/FAULT_B

w_crc_ok

(internal signal)

update

Register

Figure 26. Data Format (Write)

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19 SPI Protocol and AC Electrical Characteristics - continued

Read Command data format is sent as follows: 1-bit RW, 7-bit register address, fixed 0xFF for register data and 8-bit CRC.

When CRC is OK (w_crc_ok = high) after the Read command as shown in, it is necessary to toggle CSB (low -> high ->

low) to store the read data.

To output the data, it is necessary to send 24-bit High input data (Dummy Data).

MCU must calculate CRC using 0 as initial value.

For input data: use 16-bit data for calculation. 16-bit data = (RW, Address[6:0], Data[7:0])

For output data: use 15-bit data for calculation.

<RDMODE = 0> 15-bit data = (Address[6:0], Data[7:0]) Not including MSB.

<RDMODE = 1> 15-bit data = (5-bit (blank data), Data0[7:0], Data1[1:0]) Not including MSB.

RDMODE = 0

CSB

SCK

Address

Data(fixed high)

CRC

AD AD AD AD AD AD AD

WC WC WC WC WC WC WC WC

RW

SI

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

24-bit input data high (dummy data )

Data from Register

w_crc_ok

(internal signal)

Address

CRC

AD AD AD AD AD AD AD RD RD RD RD RD RD RD RD RC RC RC RC RC RC RC RC

SO/FAULT_B

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

RDMODE = 1

CSB

SCK

SI

Address

Data(fixed high)

CRC

AD AD AD AD AD AD AD

[6] [5] [4] [3] [2] [1] [0]

WC WC WC WC WC WC WC WC

[7] [6] [5] [4] [3] [2] [1] [0]

RW

24-bit input data high (dummy data )

1

w_crc_ok

(internal signal)

Data from Register 1

(next address)

Data from

Register 0

CRC

RD1 RD1 RC RC RC RC RC RC RC RC

RD0 RD0 RD0 RD0 RD0 RD0 RD0

RD0

[7]

[1]

[0]

[7]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

SO/FAULT_B

Figure 27. Data Format (Read)

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19 SPI Protocol and AC Electrical Characteristics - continued

SPI AC Timing

SPI AC characteristics is as shown in.

t_csbh

f_freq

V_IHxx

CSB

V_ILxx

t_csbSCK

V_IHxx

t_SCKcsb

V_ILxx

SCK

SI

t_setup1

t_hold1

t_setup2

VIHxx

t_hold2

V_ILxx

t_sodelay2

t_sodelay1

SO/FAULT_B

V_{SO/FAULT_B_OL}

Figure 28. SPI AC Timing

Table 3. SPI AC Timing

Recommended Operation Condition

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = -40 °C to +150 °C)

Item

SPI Frequency

Symbol

f_freq

Unit

MHz

ns

Min

0.1

Typ

Max

-

1.0

CSB - SCK Timing

t_csbSCK

t_SCKcsb

t_setup1

t_setup2

t_hold1

1,000

500

200

-

SCK - CSB Timing

ns

-

Setup Time1 (low -> high)

Setup Time2 (high -> low)

Hold Time1 (low -> high)

Hold Time2 (high -> low)

SO Delay (low -> high)

SO Delay (high -> low)

CSB High Pulse

ns

-

ns

-

ns

-

t_hold2

ns

t_sodelay1

t_sodelay2

t_csbh

ns

200

-

ns

-

ns

1,000

(Output load capacitance: 15 pF)

NOTE (Countermeasure of Noise)

The CSB is used for resetting, clock and enable in SPI and register circuit. If this signal includes glitch around CSB to "high ->

low" by communication path noise, internal noise or more, SPI mistake to operate register. Because this condition is not approved

in this product. But there is countermeasure for this issue. SPI receives at least one SCK clock pulse (maximum clock pulse is no

limitation) during CSB = high after writing data until next writing command. This SPI can protect this wrong operation. Because

register return to "no update condition" with SCK clock during CSB = high.

next writing command

more than one clock

tcsbh + tcsbsck

CSB

SCK

Address

Data(fixed high)

CRC

Address

Data(fixed high)

CRC

AD AD AD AD AD AD AD

WC WC WC WC WC WC WC WC

[7] [6] [5] [4] [3] [2] [1] [0]

AD AD AD AD AD AD AD

WC WC WC WC WC WC WC WC

[7] [6] [5] [4] [3] [2] [1] [0]

RW

SI

[6]

[5]

[4]

[3]

[2]

[1]

[0]

[6]

[5]

[4]

[3]

[2]

[1]

[0]

Figure 29. Countermeasure of Noise

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19 SPI Protocol and AC Electrical Characteristics - continued

SPI Protocol

Write/Read, Address

bit 7

RW

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

AD[6:0]

bit

Parameter

Function

AD[6:0]

Register Address

0x00 to 0x1B

Note: There is no access to addresses that are not between the specified range.

bit

Parameter

Read/Write

Function

0: read access

1: write access

RW

Data

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

WD/RD[7:0]

bit

Parameter

Value

WD/RD[7:0]

Data of Write/Read

0x00 to 0xFF

CRC

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

WC/RC[7:0]

bit

Parameter

CRC data of Write/Read

Value

WC/RC[7:0]

0x00 to 0xFF

This IC has a CRC (cyclic redundancy check) function for detecting errors in the SPI communication.

CRC for write command is calculated using RW bit, 7-bit register address and 8-bit register data and is calculated MSB first.

Read output is calculated the same.

CRC formula is” x⁸+x⁵+x⁴+1” which is translated as the circuit as shown in. Initial value of CRC is 0x00.

(It doesn't change value until '1' input because initial 0. (The result of "011111111111111111111111" (binary) is same as result

of "111111111111111111111111".))

Input Bit

XOR

0

1

2

3

4

5

6

7

Figure 30. CRC Circuit

NOTE (SPI Restrictions):

Command with the following input is not valid RW = 0, Address = 0x00, Data = 0x00, CRC = 0x00.

SPI will not execute the read command it is treated as dummy and will only shift the input by 24-bit.

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SPI Protocol – continued

SPI Protocol – Daisy-chain Connection

This IC has daisy chain function for SPI communication. Total of 8 devices can be connected in daisy-chain as shown in.

Select the device address by controlling CSB input see.

CSB

SCK

write

Address

Data

CRC

SI

SO/FAULT_B

w_crc_ok

(internal signal)

ADTRG

register

0

1

Figure 31. Example of Daisy-chain

When there is a total of N number of devices in the daisy-chain and M is the target device to be written/read, to execute

write command, it is necessary to input dummy data (M - 1) to propagate the write command to the desired device in a daisy-

chain connection as shown in.

N – Total number of devices connected in daisy-chain

M – Target device to be written/read

SI

0

1

M - 1

M

M + 1

N - 1

N

SO

Figure 32. Data Input Image in a Daisy-chain Connection

Device 1

CSB

SCK

24-bit data

WRITE CMD

DUMMY 1

DUMMY 2

DUMMY M - 1

WRITE CMD

SI (1)

Device M

"High"

shift data

SI (M)

SO/FAULT_B(M)

Device N

SO/FAULT_B (N)

Figure 33. SPI Write in Daisy-chain Connection

Likewise, in Read command, it is necessary to input dummy data (M-1) to propagate the read command to the desired

device toggle CSB and input the rest of the dummy data (total of N dummy data) to propagate the Read data output up to

the last device in the daisy chain connection. Dummy is 24-bit low data input.

Device 1

CSB

SCK

24-bit data

SI (1)

READ CMD

DUMMY 1

DUMMY 2

DUMMY M -1 DUMMY M

DUMMY M+1

DUMMY

DUMMY N

DUMMY

Device M (target)

READ CMD

DUMMY

SI (M)

SO/FAULT_B (M)

READ DATA

DUMMY

Device N

SO/FAULT_B (N)

READ DATA

Figure 34. SPI Read in Daisy-chain Connection

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SPI Protocol – Daisy-chain Connection – continued

In Daisy-chain connection, writing to multiple devices is possible; refer to the timing chart. In this SPI transaction, Set CSB

to “low”, send the write command consecutively for the target devices starting from Target device M up to Dev 1, Set CSB

to “high” to trigger writing to the target registers in the corresponding device number.

N – Total Device in Daisy-chain connection

Dev M to Dev 1 – Target Device to be written (Dev M is between Dev N and Dev 1)

Device 1

CSB

SCK

24-bit data

WRITE to Dev M

WRITE to Dev M - 1

WRITE to Dev M - 2

WRITE to Dev M

WRITE to Dev 2

WRITE to Dev 3

WRITE to Dev M

WRITE to Dev 1

WRITE to Dev 2

WRITE to Dev M-1

WRITE to Dev M

SI (1)

Update

REGISTER (1)

Device 2

SI (2)

WRITE to Dev M

REGISTER (2)

Device M - 1

S1 (3)

REGISTER (3)

Device M

S1 (3)

REGISTER (3)

Figure 35. Writing Protocol for Multiple Devices

Reading for multiple devices is also possible in a daisy-chain connection; refer to the timing chart. In this SPI Transaction,

Set the CSB to “low”, send the Read Command consecutively starting from target Device M up to Device 1, toggle the CSB

to “low -> high -> low”, send total DUMMY data based on total Number of devices (N). It is necessary to input this much

DUMMY data to be able to propagate the Read Data output up to the last device in the daisy chain connection.

N – Total Device in Daisy-chain connection

Dev M to Dev 1 – Target Device to be read (Dev M is between Dev N and Dev 1)

Device 1

CSB

SCK

input N total dummy data

SI (1)

READ to Dev M

READ to Dev M-1

READ to Dev 3

READ to Dev 2

READ to Dev 3

READ to Dev 1

READ to Dev 2

READ to Dev M

DUMMY

SO/FAULT_B (1)

READ data Dev 1

READ data Dev 2

Device 2

SI (2)

DUMMY

READ data Dev 1

DUMMY

SO/FAULT_B (2)

Device M

READ data Dev M- READ data Dev M-

S1 (M)

DUMMY

READ data Dev M-

SO/FAULT_B (M)

Device N

READ data Dev M

DUMMY

SO/FAULT_B (N)

READ data Dev 2

READ data Dev 1

Figure 36. Reading Protocol for Multiple Devices

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SPI Protocol – Daisy-chain Connection – continued

Example 1)

Writing data for 1 device

Address = 0x15 (ADTRG)

Data = 0x80

CRC = 0x40

CSB

SCK

write

Address

Data

CRC

SI

SO/FAULT_B

w_crc_ok

(internal signal)

ADTRG

register

0

1

Figure 37. SPI Protocol of the 1 byte Write to Device #1

Example 2)

Reading data for 1 device (RDMODE = 1)

Address = 0x16 (VMON)

Data = 0xFF (dummy)

CRC = 0x98 (MCU -> this device)

Read data = 0x05

CRC = 0x59 (this device -> MCU)

Device 1

CSB

SCK

Dummy data

CRC

Address

Read

SI

Read data

CRC

SO/FAULT_B

w_crc_ok

(internal signal)

VMON

Register

0x05

Figure 38. SPI Protocol of the 1 byte Read to Device #1

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SPI Protocol – continued

SPI Protocol – Parallel Connection

This IC can be connected in Parallel for SPI connection as shown in. In this connection, each device has separate CSBx.

SI and SO connection are shared. User can choose which DUT to write based on CSBx as shown in.

V5VEXT

Device 2

R

SO

SI

MOSI

BD18397/98xxx-M

SO/FAULT_B

CSB SCK

Device 1

SO/FAULT_B

SI

BD18397/98xxx-M

SCK

CSB

MCU

CSB1

CSB2

SCLK

MISO

Figure 39. SPI Parallel Connection

Device 1

CSB

high

SCK

SI

AD AD AD AD AD AD AD WD WD WD WD WD WD WD WD WC WC WC WC WC WC WC WC

[6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]

RW

high(Hi-z)

SO/FAULT_B

w_crc_ok

(internal signal)

not update

Register

Device 2

CSB

SCK

SI

AD AD AD AD AD AD AD WD WD WD WD WD WD WD WD WC WC WC WC WC WC WC WC

[6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]

RW

SO/FAULT_B

high(Hi-z)

w_crc_ok

(internal signal)

update

Register

Figure 40. SPI Write to Device #2 in Parallel Connection

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SPI protocol – Parallel Connection – continued

Device 1

CSB

"high"

SCK

R

W

AD AD AD AD AD AD AD

[6] [5] [4] [3] [2] [1] [0]

WC WC WC WC WC WC WC WC

[7] [6] [5] [4] [3] [2] [1] [0]

SI

w_crc_ok

(internal signal)

SO/FAULT_B

"high"(Hi-z)

Device 2

CSB

SCK

Address

CRC

Data(fixed "high")

AD AD AD AD AD AD AD

WC WC WC WC WC WC WC WC

[7] [6] [5] [4] [3] [2] [1] [0]

RW

SI

[5]

[6]

[4] [3] [2] [1] [0]

w_crc_ok

(internal signal)

Address

CRC

Data from Register

AD AD AD AD AD AD AD RD RD RD RD RD RD RD RD RC RC RC RC RC RC RC RC

[6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0] [7] [6] [5] [4] [3] [2] [1] [0]

SO/FAULT_B

Figure 41. SPI Read to Device #2 in Parallel Connection

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20 Register

Register MAP(Address 0x00 to 0x1B)

This is register MAP of BD18398xxx-M. The channel 3 setting is not included in BD18397xxx-M. (ex, ISETSDIM3, VMODE3,

CHON3, ERRDET3, address 0x08-0x09, 0x0E to 0x0F, 0x12, 0x1B), These registers is blank (0x00). If you read these data,

it returns 0.

Register

RegisterNam e

Address

bit[7]

bit[6]

bit[5]

bit[4]

bit[3]

bit[2]

bit[1]

bit[0]

initial

com m ents

Access

register access control

sleep setting, software reset

NOTE : POR/TSD for reset of SWRST

SYSSET

-

0x00

0x01

W

LOCK

-

W

DTEN

-

RDM ODE

SLEEP

-

SW RST

-

R/W

-

0x40

-

Notused

protectionlatchsettingandlatchreleased

setting

ERRSET1

0x02

-

FLTRST

LEDOCPLAT

ISETDIM 2

SW OCPLAT

ISETDIM 1

R/W

0x00

ISET settingselection,outputPW

M

PW M DIV[2:0]

DIM SET

ISET1H

0x03

0x04

0x05

0x06

0x07

0x08

0x09

0x0A

0x0B

0x0C

0x0D

0x0E

0x0F

PHEN

ISETDIM 3

R/W

frequencysetting,settingofPhaseshift

ISET1[9:2]

ISET2[9:2]

0xE1 Currentsettingforchannel1

0x01 Currentsettingforchannel1

0xE1 Currentsettingforchannel2

0x01 Currentsettingforchannel2

0xE1 Currentsettingforchannel3

0x01 Currentsettingforchannel3

ISET1[1:0]

ISET1L

-

ISET2H

ISET2[1:0]

ISET3[1:0]

ISET2L

ISET3[9:2]

ISET3H

ISET3L

DPW M 1[9:2]

DPW M 2[9:2]

DPW M 3[9:2]

DPW M 1H

DPW M 1L

DPW M 2H

DPW M 2L

DPW M 3H

DPW M 3L

0xFF PW

0x03 PW

0xFF PW

0x03 PW

0xFF PW

0x03 PW

M

ON Dutyforchannel1

ON Dutyforchannel2

ON Dutyforchannel3

DPW M 1[1:0]

DPW M 2[1:0]

DPW M 3[1:0]

switchingfrequencysettingforchannel1

varycurrentdetectorripplegain

GM 1[1:0]

GM 2[1:0]

GM 3[1:0]

TON1[5:0]

DCDCSET1

DCDCSET2

DCDCSET3

0x10

0x11

0x12

R/W

0x07

switchingfrequencysettingforchannel2

varycurrentdetectorripplegain

TON2[5:0]

TON3[5:0]

switchingfrequencysettingforchannel3

varycurrentdetectorripplegain

SSCG[2:0]

DCDCSET4

CHEN

0x13

0x14

-

VM ODE3

PW M DIM 3

VM ODE2

VM ODE1

-

R/W

0x00 SSCG setting,Voltagem odesetting

0x00 DC/DC enable,PW Dim m ingenable

PW M DIM 2

PW M DIM 1

CHON3

CHON2

CHON1

M

VIN,PIN,V_5VEXT,V _SNSN1,V _SNSN2,V _SNSN3

therm al,ISET1,ISET2,ISET3voltage

,

VM ONSEL[3:0]

ADSEL

0x15

ADTRG

-

ADM ODE

R/W

0x10

m onitor,A/D convertertriggerinm anual

m ode

VM ON[9:2]

VM ONH

0x16

0x17

0x18

RO

0x00 Voltagem onitorbyA/D,

0x00 Errorstatusregistertotal

VM ON[1:0]

VM ONL

-

DTERR

-

ERRSTALL

W

CRCERR

PINUVLO

UVLO

ERRDET3

ERRDET2

LOD1

ERRDET1

LSD1

Errorstatusregister

0x00 LED openerror,LED shorterror

SW OCP1,LOCP1

ERRST1

ERRST2

ERRST3

0x19

0x1A

0x1B

-

LEDOCPERR1

LEDOCPERR2

LEDOCPERR3

SW OCPERR1

RO

Errorstatusregister

-

SW OCPERR2

SW OCPERR3

LOD2

LOD3

LSD2

LSD3

0x00 LED openerror,LED shorterror

SW OCP2,LOCP2

Errorstatusregister

0x00 LED openerror,LED shorterror

SW OCP3,LOCP3

WO: Write Only, RO: Read Only, R/W: Read and Write

SWRST register reset condition is POR/TSD. All other registers reset condition is POR/TSD/SWRST.

(Note 1) SWRST, FLTRST and ADTRG are “write only”, and reset condition of SWRST is only “POR/TSD”.

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20 Register - continued

Description of Registers

●Address 0x00: SYSSET

System setting

[Read/Write]

initial value 0x40

bit No

Name

Initial value

bit[7]

WLOCK

0

bit[6]

WDTEN

1

bit[5]

RDMODE

0

bit[4]

SLEEP

0

bit[3]

-

0

bit[2]

-

0

bit[1]

-

0

bit[0]

SWRST

0

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

bit[0]

SWRST

SWRST register return ‘0’ automatically. Hence, this register is “Write only”.

Set this register when you want to reset digital circuit.

Table 4. SWRST Operation

SWRST

Reset

0

1

Normal

Reset for digital circuit (return ‘0’ automatically)

bit[4]

SLEEP

This IC has sleep mode which stops internal clock, so this IC is in low “quiescent current” condition. This IC

keeps register value when SLEEP = 1.

Table 5. SLEEP Operation

SLEEP

0

Operation

Normal

Low “quiescent current” condition.

1

Oscillator is stopped. So, DC/DC and Current Driver are

OFF. Only internal regulator is available.

bit[5]

RDMODE

This register controls Read protocol. If RDMODE = 1, it outputs Read Data (target address 8-bit + next

address bit[1:0]). The detail of protocol can be referred in "SPI Protocol" section.

Table 6. RDMODE Operation

RDMODE

Operation

Outputs target address data

Outputs target address data + next address data bit [1:0]

0

1

CSB

SCK

RDMODE = 0

SO/FAULT_B

AD

[6]

AD

[5]

AD

[4]

AD

[3]

AD

[2]

AD

[1]

AD

[0]

RD

[7]

RD

[6]

RD

[5]

RD

[4]

RD

[3]

RD

[2]

RD

[1]

RD

[0]

RC

[7]

RC

[6]

RC

[5]

RC

[4]

RC

[3]

RC

[2]

RC

[1]

RC

[0]

ex.) VMON [9:2]

target address

VMON [9:2]

RDMODE = 1

SO/FAULT_B

RD

[7]

RD

[6]

RD

[5]

RD

[4]

RD

[2]

RD

[1]

RD

[0]

RD

[1]

RD

[0]

RC

[7]

RC

[6]

RC

[5]

RC

[4]

RC

[3]

RC

[2]

RC

[1]

RC

[0]

[3]

ex.) VMON [9:2] + VMON [1:0]

target address

VMON [9:2]

next address

VMON [1:0]

Figure 42. RDMODE Operation

bit[6]

WDTEN

This register is “Watchdog timer” function enable. If WDTEN = 1, LIMP-HOME function is available by “Watch

Dog Timer error” when state is “LEDACTIVE” or “STANDBY”.

Table 7. “Watch Dog Timer” Enable

WDTEN

Enable

“Watch Dog Timer” is not available

“Watch Dog Timer” is available

0

1

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Description of Registers – continued

bit[7]

WLOCK

DPWMx registers are split into two registers (higher and lower byte). Normally, whenever a byte (higher or

lower) is written, it will immediately be reflected in PWM dimming control. If WLOCK function is used, PWM

dimming control will not be updated until the two bytes (higher and lower) are written.

Note that it doesn't matter whether the higher or lower byte is written first.

Table 8. WLOCK Function

WLOCK

Operation

0

1

Normal update

PWM dimming control is not updated until writing the other address. (0x0A to 0x0F)

SPI

WLOCK

write DPWMxH

write DPWMxL

"Low"

DPWMx[9:2] register

DPWMx[1:0] register

update

PWM dimming control

for channel x

SPI

write DPWMxH

write DPWMxL

WLOCK

"High"

DPWMx[9:2] register

DPWMx[1:0] register

update

not updated

PWM dimming control

for channel x

Figure 43. WLOCK Function Example

●Address 0x01: Not Used

●Address 0x02: ERRSET1

protection setting

[Read/Write]

bit[2]

FLTRST

0

initial value 0x00

bit No

Name

bit[7]

-

bit[6]

bit[5]

bit[4]

-

0

bit[3]

-

0

bit[1]

bit[0]

SWOCPLAT

0

-

LEDOCPLAT

0

Initial value

0

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

bit[0]

SWOCPLAT

The releasing function of “SWx over current error protection” is programmed by this register. If SWOCPLAT

= ‘1’, The SWOCPERRx register doesn't become '0' until writing FLTRST = '1'. If SWOCPLAT = '0', The

SWOCPERRx becomes '0' by "SWx over current error" released.

Table 9. “SWx Over Current error protection” Latch Operation Setting

SWOCPLAT

Operation

If this error condition is released, error status register and FAULT_B returns normal

condition.

0

1

This IC keeps error condition until writing FLTRST = 1.

(x = 1, 2, 3)

bit[1]

LEDOCPLAT

The releasing function of “LED over current error protection” is programmed by this register. If LEDOCPLAT

= ‘1’, The LEDOCPERRx register doesn't become '0' until writing FLTRST = '1'. If LEDOCPLAT = '0', The

LEDOCPERRx becomes '0' by "LED over current error" released.

Table 10. “LED Over Current error protection” Latch Operation Setting

LEDOCPLAT

Operation

If this error condition is released, error status register and FAULT_B returns normal

condition.

0

1

This IC keeps error condition until writing FLTRST = 1.

(x = 1, 2, 3)

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Description of Registers – continued

bit[2]

FLTRST

The error status registers are initialized by this register. If each protection is latched, its condition is released.

Table 11. Error Status Reset

FLTRST

0

Operation

Normal

Initialize error status for LEDOCPERRx and SWOCPERRx, CRCERR and

WDTERR. This register is auto return to “0” (Address 0x19 to 0x1B)

1

(x = 1, 2, 3)

●Address 0x03: DIMSET

Dimming setting

[Read/Write]

bit[2]

initial value 0x00

bit No

Name

bit[7]

PHEN

0

bit[6]

bit[5]

bit[4]

0

bit[3]

-

0

bit[1]

bit[0]

ISETDIM1

0

PWMDIV[2:0]

0

ISETDIM3

0

ISETDIM2

0

Initial value

0

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

bit[2:0]

ISETDIMx

(ISETDIM3 is only used for the BD18398xxx-M)

This register selects the LED DC current setting data for channel x (x = 1, 2, 3). If ISETDIMx = 1, the ISETx

pin setting is available. If ISETDIMx = 0, LED DC current is programmed by ISETx register.

Table 12. ISET Select

ISETDIMx

0

PWMONx Definition

LED DC current is programmed by Selected by corresponding VMONSEL

ISETx[9:0] register [3:0] bit setting

ADC Monitor Select

LED DC current is programmed by Not applicable

ISETx[9:0] & ISET/PWMx pin

1

(x = 1, 2, 3)

bit[6:4]

PWMDIV

The output frequency is programmed for PWM dimming LED by this register. A/D conversion frequency

(ADMODE = 1) is also programed by this register.

Table 13. PWM Output Frequency Setting

PWMDIV[2:0]

Output Frequency [Hz]

0

1

2

3

4

5

6

7

153

203

244

305

407

488

610

814

bit[7]

PHEN

PWM dimming phase of channel 1 is programmed by this register as shown in Figure 44.

Table 14. PWM Phase Setting

Phase Setting

PHEN

BD18398xxx-M

All Channel: No Phase shift

Channel 1: no shift

Channel 2: 120 degree

Channel 3: 240 degree

BD18397xxx-M

All Channel: No Phase shift

Channel 1: no shift

Channel 2: 180 degree

-

0

1

PHEN = 1

OFF

Lighting

120 degree

240 degree

OFF

Lighting

LED current for channel 1

LED current for channel 2

LED current for channel 3

Figure 44. PWM Phase Shift Setting (for BD18398xxx-M)

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Description of Registers – continued

●Address 0x04: ISET1H

ISET setting for channel 1

[Read/Write]

bit[2]

initial value 0xE1

bit No

Name

bit[7]

bit[6]

bit[5]

bit[4]

ISET1 [9:2]

0

bit[3]

0

bit[1]

bit[0]

Initial value

1

0

1

●Address 0x05: ISET1L

ISET setting for channel 1

[Read/Write]

initial value 0x01

bit[1] bit[0]

ISET1[1:0]

bit No

Name

bit[7]

-

bit[6]

bit[5]

bit[4]

bit[3]

-

bit[2]

-

Initial value

0

1

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

ISET1H

bit[7:0]:

ISET1L

bit[1:0]:

ISET1[9:2]

ISET1[1:0]

LED DC current is programmed by this register as following formula.

Formula

[

]

퐼ꢂꢃꢄꢅ 9: 0

1

퐼_{퐿퐸퐷푥퐴푉퐸}= (

× 2.5 ꢀ − 0.2 ꢀ) ×

1024

12 × 푅_푆푁푆푥

●Address 0x06 to 0x09: ISETx[9:0] (x = 2 to 3)

This register is used to make setting of LED current for channel 2 and channel 3. The setting procedure is the same as that

for channel 1 with Address set to 0x04 and 0x05.

ISET3[9:0] is only used for the BD18398xxx-M.

●Address 0x0A: DPWM1H

PWM setting

bit[6]

[Read/Write]

bit[2]

initial value 0xFF

bit No

Name

bit[7]

bit[5]

1

bit[4]

DPWM1 [9:2]

1

bit[3]

1

bit[1]

bit[0]

1

Initial value

●Address 0x0B: DPWM1L

PWM setting

bit[6]

[Read/Write]

initial value 0x03

bit[1] bit[0]

DPWM1 [1:0]

bit No

Name

bit[7]

-

bit[5]

-

bit[4]

-

bit[3]

-

bit[2]

-

0

1

Initial value

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting. If you want to change value during dimming, WLOCK function can be used.

DPWM1H

bit[7:0]:

DPWM1L

bit[1:0]:

DPWM1[9:2]

DPWM1[1:0]

LED average current in PWM is programmed by this register. The dimming ratio is calculated as following

formula.

[

]

ꢇꢐꢑꢒꢅ 9: 0 + 1

ꢇ_푃푊푀푥

=

1024

PWM frequency by PWMDIV setting

ON Duty

LED current for channel x

OFF

Lighting

OFF

Lighting

Figure 45. PWM Dimming

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Description of Registers – continued

●Address 0x0C to 0x0F: DPWMx (x = 2 to 3)

This register is used to make setting of PWM for channel 2 and channel 3. The setting procedure is the same as that for

channel 1 with Address set to 0x0A and 0x0B

DPWM3 is only used for the BD18398xxx-M.

●Address 0x10: DCDCSET1

DC/DC setting for channel 1

[Read/Write]

bit[2]

TON1[5:0]

initial value 0x07

bit No

Name

bit[7]

bit[6]

bit[5]

bit[4]

bit[3]

0

bit[1]

bit[0]

GM1[1:0]

Initial value

0

1

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

bit[7:6]

GM1[1:0]

GM Amplifier Gain Setting

Table 15. DC/DC GM Amplifier Trans Conductance Setting

GM1[1:0] (Dec)

GM Amplifier Gain Setting [µS]

0

1

2

3

1360

870

530

300

bit[5:0]

TON1[5:0]

DC/DC Frequency setting is programmed for channel 1 by this register.

It is available to use DC/DC frequency setting under 2.25 MHz. (over 2.25 MHz setting is prohibited.)

Table 16. DC/DC Frequency Setting for Reference (R_TON= 51 kΩ)

TON1[5:0] (Dec)

DCDC Frequency [kHz]

0

1

2

3

4

5

6

7

8

10

12

14

16

18

30

42

50

100

150

200

250

300

350

400

450

550

650

750

850

950

1,550

2,150

Table 17. DC/DC Frequency Setting for Reference (R_TON= 9.1 kΩ)

TON1[5:0] (Dec)

DCDC Frequency [kHz]

0

1

2

3

4

5

6

7

280

560

841

1,121

1,401

1,681

1,962

2,242

●Address 0x11 to 0x12: DCDCSETx(x = 2 to 3)

This register is used to make setting of DC/DC setting and GM amplifier gain setting for channel 2 and channel 3. The setting

procedure is the same as that for channel 1 with Address set to 0x10.

DCDCSET3 is only used for the BD18398xxx-M.

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Description of Registers – continued

●Address 0x13: DCDCSET4 SSCG and Voltage control mode setting for DC/DC

[Read/Write] initial value 0x00

bit No

Name

Initial value

bit[7]

-

0

bit[6]

VMODE3

0

bit[5]

VMODE2

0

bit[4]

VMODE1

0

bit[3]

-

0

bit[2]

bit[1]

SSCG[2:0]

0

bit[0]

0

The data in register is updated to the newest data immediately when the new data is written.

Set these registers in initial setting.

bit[2:0]

SSCG[2:0]

The modulation DC/DC switching frequency is programmed for all channel by this register.

Table 18. SSCG Modulation Setting

SSCG[2:0]

SSCG Modulation Ratio [Hz]

0

1

2

3

4

5

6

7

SSCG OFF (Fixed frequency of DC/DC)

155

185

283

361

536

763

1,044

bit[6:4]

VMODEx

“Voltage control mode” for DC/DC is programmed by this register.

(VMODE3 is only used for the BD18398xxx-M)

Table 19. Voltage Control Mode Setting

VMODEx

Controlled Mode

Current control mode for channel x

Voltage control mode for channel x

0

1

(x = 1, 2, 3)

In the Voltage mode setting (VMODEx = 1), SNSN1 pin voltage is regulated by as following.

[

]

퐼ꢂꢃꢄꢅ 9: 0

ꢀ

푆푁푆푁푥

=

× ꢎ7.5 ꢀ ꢍ@ꢀꢒꢉꢇꢃꢅ = 1ꢏ

1024

●Address 0x14: CHEN

Channel enable and Dimming enable

[Read/Write]

bit[2]

initial value 0x00

bit No

Name

bit[7]

-

bit[6]

PWMDIM3

0

bit[5]

PWMDIM2

0

bit[4]

PWMDIM1

0

bit[3]

-

0

bit[1]

CHON2

0

bit[0]

CHON1

0

CHON3

0

Initial value

0

The data in register is updated to the newest data immediately when the new data is written.

bit[2:0] CHONx (CHON3 is only used for the BD18398xxx-M)

Each channel starts-up by this register. If CHONx = 1, LED dimming is available for channel x. (x = 1, 2, 3)

CHONx = 0, LED dimming is not available for channel x. Protection such as “LED short to ground error

protection”, “LED open error protection”, “SW Over Current error protection” and “LED Over Current error

protection” in the target channel is not available when CHONx = 0.

Table 20. Channel Enable

CHONx

Enable

0

1

Channel x is disable.

Channel x is enable.

(x = 1, 2, 3)

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Description of Registers – continued

bit[6:4]

PWMDIMx

The internal PWM dimming duty is programmed by this register. It is available to dim by the DPWMx[9:0]

register when the PWMDIMx = 1. The internal PWM duty can be set to 100 % when the PWMDIMx = 0.

Table 21. PWM Dimming Enable

PWMDIMx

0

Operation

PWM Duty is 100 % fixed.

PWM Dimming enable.

Dimming ratio is programmed by the DPWMx[9:0] register.

1

(x = 1, 2, 3)

Table 22. How to Dim by PWM

CHONx

PWMDIMx

DC/DC

OFF

ON

Internal PWM Dimming for Channel x

OFF

0

1

0

1

0

1

100 %

ON

Programmed by the DPWMx[9:0]

(x = 1, 2, 3)

●Address 0x15: ADSEL

A/D monitor channel select

[Read/Write]

bit[2]

initial value 0x10

bit No

Name

bit[7]

ADTRG

0

bit[6]

bit[5]

bit[4]

ADMODE

1

bit[3]

0

bit[1]

bit[0]

-

VMONSEL[3:0]

0

Initial value

0

The data in register is updated to the newest data immediately when the new data is written.

bit[3:0] VMONSEL[3:0]

VMON register is shared in for monitoring below node. This register should be programmed before reading

VMON register when target node voltage is need.

Register

ISETDIMx

PWMDIV[2:0]

PWM generator

ADTRG

1

0

s

ADMODE

VMONSEL[3:0]

V_SNSN3

V_SNSN2

VSNSN1

V_FSRADC= 2.5 V

VPIN

V_5VEXT

10

VMON[9:0]

A/D

SEL

V_IN

share one A/D

1

0

V_ISET3

SEL

ISET3

ISET2

1

0

V_ISET2

1

0

V_ISET1

V_TEMP

ISET1

Thermal

Figure 46. A/D System Structure

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Description of Registers – continued

Table 23. VMONSEL Status

VMONSEL

0x0

Monitor Node

Thermal (default)

ISET1

Other Register Set Needed

-

0x1

ISETDIM1 = 0

0x2

ISET2

ISETDIM2 = 0

0x3

ISET3

ISETDIM3 = 0

0x4

0x5

0x6

0x7

0x8

0x9

V_IN

V_5VEXT

V_PIN

V_SNSN1

V_SNSN2

V_SNSN3

Not Used

-

0xA to 0xF

bit[4]

ADMODE

There are two A/D converting modes.

When ADMODE = 1, A/D converter is operated automatically. Conversion frequency is determined by

PWMDIV register and is operational only in LEDACTIVE state.

When ADMODE = 0, A/D converter is operated manually by ADTRG. A/D converter becomes sleep condition

(low current consumption) after 1 conversion.

Table 24. ADMODE Operation

ADMODE

0

Operation

A/D conversion for only target node by ADTRG register

A/D conversion repeatedly. This period is programmed by

PWMDIV register.

1

bit[7]

ADTRG

A/D starts to convert the data selected by VMONSEL register after writing ADTRG = 1 during ADMODE = 0.

This register will return to ‘0’ after writing ‘1’. Updated data is available less than 24 µs.

Table 25. ADTRG

ADTRG

Operation

0

1

No conversion

Starts to convert data in ADMODE = 0

●Address 0x16: VMONH

common voltage monitor by A/D

[Read]

bit[2]

initial value 0x00

bit No

Name

bit[7]

bit[6]

0

bit[5]

0

bit[4]

bit[3]

0

bit[1]

bit[0]

VMON[9:2]

Initial value

0

●Address 0x17: VMONL

common voltage monitor by A/D

[Read]

initial value 0x00

bit No

Name

bit[7]

-

bit[6]

-

bit[5]

-

bit[4]

-

bit[3]

-

bit[2]

-

bit[1]

bit[0]

VMON[1:0]

Initial value

0

The register data is updated to the newest data immediately when the data are updated by A/D converting.

VMONH

bit[7:0]

VMONL

bit[1:0]:

VMON[9:2]

VMON[1:0]

This register is used for monitoring the thermal sensor voltage (V_TEMP), V_ISET/PWMx, V_IN, V_5VEXT, V_PINor V_SNSNx

node (x = 1, 2, 3). This operation is programmed by VMONSEL register.

This data is divided into two register address. If all of 10-bit data is required when ADMODE = 1, or RDMODE

function is available.

Formula 1 for thermal sensor voltage

Thermal sensor voltage ADC read value = 418 @25 deg

Thermal sensor voltage ADC read value = 602 @150 deg

1.472 count/temp (1 degree)

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Description of Registers – continued

Formula 2 for external input pin nodes

Monitor voltage 1 [V] = “X” x (VMON + 1) / 1024

V_IN: “X” = 48, V_PIN: “X” = 70, and V_SNSNx: “X” = 67.5, V_5VEXT: “X” = 5.5, V_ISET/PWMx: “X” = 2.5

●Address 0x18: ERRSTALL All error status each protection

[Read]

bit[2]

ERRDET3

0

initial value 0x00

bit No

Name

bit[7]

bit[6]

bit[5]

bit[4]

UVLO

0

bit[3]

-

0

bit[1]

bit[0]

ERRDET1

0

WDTERR CRCERR PINUVLO

ERRDET2

0

Initial value

0

The register data is updated to the newest data immediately when the data (one or more error/protection) is detected.

bit[2:0]

ERRDETx(ERRDET3 is only used for the BD18398xxx-M)

This register is error status each channel.

Table 26. Error Status of Each Channel

ERRDETx

0

Status

Normal

Detects error

LSDx || LODx || SWOCPERRx || LEDOCPERRx

1

(x = 1, 2, 3)

bit[4]

bit[5]

bit [6]

UVLO

This register is error status for UVLO.

Table 27. UVLO

UVLO

Status

0

1

Normal

Detects under voltage error for V_5VEXTor V_5VREG

PINUVLO

This register is error status for PINUVLO.

Table 28. PINUVLO

Status

PINUVLO

0

1

Normal

Detects under voltage error for PIN

CRCERR

This register is error status for CRC. If CRC error is detected, this register becomes 1. This register becomes

0 by FLTRST = 1. If CRC Error occurred to the SPI command sent after to sending FLTRST, this will not be

detected, for more details refer to Error sequence for “CRC Error”.

Table 29. CRC Error Status

CRCERR

Status

0

1

Normal

Detects CRC error

bit[7]

WDTERR

This register is error status for “Watch Dog Timer”. If “Watch Dog Timer error” is detected, this register

becomes 1. This register becomes 0 by FLTRST = 1.

Table 30. “Watch Dog Timer error” Status

WDTERR

Status

0

1

Normal

Detects “Watch Dog Timer error”

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Description of Registers – continued

●Address 0x19: ERRST1

channel 1 error status

[Read]

initial value 0x00

bit No

Name

Initial value

bit[7]

-

0

bit[6]

-

0

bit[5]

-

0

bit[4]

-

0

bit[3]

LEDOCPERR1

0

bit[2]

SWOCPERR1

0

bit[1]

LOD1

0

bit[0]

LSD1

0

The register data is updated to the newest data immediately when the data (“LED open error”, “LED short to ground error”,

“SW1 Over Current”, “LED Over Current”) is detected.

bit[0]

bit[1]

bit[2]

bit[3]

LSD1

This register is “LED short to ground error” status for channel 1. LSD1 becomes “1” when “LED short to

ground error” is detected, and LSD returns “0” when “LED short to ground error” is released.

There is filter for detecting (10 ms) and releasing (1 ms) each channel. This filter is shared for “LED short to

ground protection” and “LED open protection”.

Table 31. “LED short to ground error” Status Register

LSD1

0

1

Status

Normal

Detects LED short to ground error

LOD1

This register is “LED open error” status for channel 1. LOD1 becomes “1” when “LED open error” is detected,

and LOD1 returns “0” when “LED open error” is released.

There is filter for detecting (10 ms) and releasing (1 ms) each channel. This filter is shared for “LED short to

ground protection” and “LED open protection”.

Table 32. “LED open error” Status Register

LOD1

0

1

Status

Normal

Detects LED open error

SWOCPERR1

This register is “SW Over Current error” status for channel 1. If SWOCPLAT = 0, SWOCPERR1 becomes

“1” when “SW Over Current” is detected, and SWOCPERR1 returns “0” when “SW Over Current error” is

released. If SWOCPLAT = 1, SWOCPERR1 becomes “1” when “SW over current error” is detected, and

SWOCPERR1 becomes “0” by FLTRST = 1.

Table 33. SW Over Current Error Status

SWOCPERR1

Status

0

1

Normal

Detects SW Over Current error

LEDOCPERR1

This register is “LED Over Current error” status for channel 1. If LEDOCPLAT = 0, LEDOCPERR1 becomes

“1” when “LED Over Current” is detected, and LEDOCPERR1 returns “0” when “LED Over Current error” is

released. If LEDOCPLAT = 1, LEDOCPERR1 becomes “1” when “LED over current error” is detected, and

LEDOCPERR1 becomes “0” by FLTRST = 1.

Table 34. LED Over Current Error Status

LEDOCPERR1

Status

0

1

Normal

Detects LED Over Current error

●Address 0x1A to 0x1B: ERRSTx (x = 2 to 3)

These registers are error status for channel 2 and channel 3. These functions are the same as that for channel 1 with

Address set to 0x19. ERRST3 is only used for the BD18398xxx-M.

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Sequence

1

Start-up and Turn-off Sequence

Normal Start-up (No SPI Communication)

1

5

V_INUVD

V_INUVR

V_IN

2

3

4

CSB

SPI (SCK, SI)

V_5VUVR

V_5VRPORR

V_5VUVD

V_5VRPORD

V_5VREG

,

V_5VEXT

state

RESET

SPI WAIT

STANDBY

LED ACTIVE

STANDBY

RESET

internal OSC

CHONx

"ALL 0"

"NOT ALL 0"

"ALL 0"

(register)

OFF

Lighting

OFF

LED condition

Enlarged view

SPI

register Write:

Address 0x00 to 0x13

SPI

register Write:

CHONx

register Write:

CHONx

Figure 47. Start-up Sequence for Normal Operation

When you light the LED by general SPI control, follow the sequence below.

①

②

③

④

⑤

Input the power supply of VIN.

MCU starts communicating with SPI after waiting internal regulator to be stable.

Start dimming LED by CHONx = 1 (channel x).

Stop dimming LED by CHONx = 0.

Stop the input power supply of VIN.

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1 Start-up and Turn-off Sequence - continued

LIMP-HOME Start-up (No SPI Communication)

1

3

V_INUVD

V_INUVR

V_IN

CSB

"high"

SPI (SCK, SI)

V_5VUVR

V_5VRPORR

V5VUVD

V_5VRPORD

V_5VREG

V_5VEXT

,

1 s

2

state

RESET

SPI WAIT

LIMP HOME

RESET

internal OSC

CHONx

(register)

"ALL 0"

OFF

LED condition

Lighting

Figure 48. Start-up Sequence for LIMP-HOME

When you light the LED by LIMP-HOME mode, follow the sequence below.

OFF

①

②

③

Input the power supply of VIN.

Start lighting (by external resistor) after waiting 1 s from UVLO release.

Stop the input power supply of VIN.

STAND-ALONE Start-up (CSB = Low)

1

4

V_INUVD

V_INUVR

V_IN

3

CSB

"low"

SPI (SCK, SI)

V_5VUVR

V_5VRPORR

V5VUVD

V_5VRPORD

V_5VREG

V5VEXT

,

0.8 ms(typ)

SPI WAIT

2

state

RESET

STANDALONE

SPIWAIT

RESET

internal OSC

CHONx

"ALL 0"

(register)

LED condition

OFF

Figure 49. Start-up Sequence for STAND-ALONE

When you light the LED by STAND-ALONE mode, follow the sequence below.

Lighting

OFF

①

②

③

④

Input the power supply of VIN with CSB = low.

Start lighting (by external resistor) after waiting 0.8 ms from UVLO release.

Input CSB = high and stop lighting. From this point, dimming can be operated by register setting.

Stop to input the power supply of VIN.

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1 Start-up and Turn-off Sequence - continued

LIMP-HOME during SPIWAIT (Release by SPI Communication)

1

4

V_INUVR

V_INUVD

V_IN

3

CSB

"high"

SPI (SCK, SI)

V_5VUVR

V_5VRPORR

V_5VUVD

V_5VRPORD

V_5VREG

V_5VEXT

,

1 s

2

state

RESET

SPI WAIT

LIMP HOME

LED ACTIVE

RESET

internal OSC

CHONx

(register)

"ALL 0"

"NOT ALL 0"

Lighting

"ALL 0"

OFF

LED condition

OFF

Lighting

Enlarged view

SPI

register Write:

CHONx

Figure 50. Start-up Sequence for LIMP-HOME

When you light the LED by LIMP-HOME mode then MCU sends SPI commands, follow the sequence below.

①

②

③

Input the power supply of VIN.

Start lighting based on external resistor after waiting 1 s from UVLO release.

After SPI Access (CRC OK), it triggers LIMP-HOME to LEDACTIVE. Lighting is changed from “based on external

resistor” to SPI register controlled. If the previous state is SPIWAIT it returns to STANDBY or LEDACTIVE. In the

case above it returns to LEDACTIVE after writing on CHONx register.

④

Stop the input power supply of VIN.

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1 Start-up and Turn-off Sequence - continued

LIMP-HOME during LEDACTIVE (Release by SPI Communication)

1

5

V_INUVD

V_INUVR

V_IN

2

4

CSB

"high"

V_5VUVR

SPI (SCK, SI)

V5VUVD

V_5VRPORR

V_5VRPORD

3

V_5VREG

,

1 s

V_5VEXT

SPI WAIT

state

RESET

LED ACTIVE

LIMP HOME

LED ACTIVE

RESET

STANDBY

internal OSC

CHONx

(register)

"ALL 0"

OFF

"NOT ALL 0"

"ALL 0"

OFF

LED condition

Lighting

Enlarged view

SPI

register Write:

Address 0x00 to 0x13

SPI

register Write:

CHONx

SPI

register Write:

CHONx

Figure 51. Start-up Sequence for LIMP-HOME

When you light the LED by LIMP-HOME mode, follow the sequence below.

①

②

Input the power supply of VIN.

MCU starts communicating with SPI after waiting internal regulator to be stable.

Start dimming LED by CHONx = 1 (channel x).

③

④

Start lighting based on external resistor after waiting 1 s from UVLO release.

After SPI Access (CRC OK), it triggers LIMP-HOME to LEDACTIVE. Lighting is changed from “based on external

resistor” to SPI register controlled. If the previous state is LEDACTIVE, it returns to LEDACTIVE and continue

dimming by Register Setting.

⑤

Stop the input power supply of VIN.

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1 Start-up and Turn-off Sequence - continued

Sleep Mode

V_IN

CSB

1

2

3

4

SPI (SCK, SI)

V_5VREG,V_5VEXT

supply power

state

LED ACTIVE

STANDBY

SLEEP

stop

STANDBY

LED ACTIVE

internal

oscillator

clock is generated

CHONx

(register)

"ALL 0"

OFF

"NOT ALL 0"

Lighting

"NOT ALL 0"

LED condition

Lighting

Enlarged view

SPI

register

SPI

Write:

register

Write:

ALL CHONx = 0 SLEEP = 1

SLEEP = 0

CHONx = 1

Figure 52. Sequence for SLEEP Mode

When you use SLEEP mode by SPI control, follow the sequence below.

①

②

③

④

If ALL CHONx = 0, this IC stop lighting and go “STANDBY” state.

If SLEEP = 1, internal oscillator stops. (Low quiescent current by stopping internal clock.)

If SLEEP = 0, internal oscillator starts.

If ANY CHONx = 1, this IC starts lighting and go “LEDACTIVE” state.

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1 Start-up and Turn-off Sequence - continued

Cold Cranking Mode (Sleep by UVLO)

1

2

V_INUVD

V_INUVR

V_IN

CSB

"high"

no access

SPI (SCK, SI)

"low"

V_5VREG

,

supply power

V_5VEXT

state

LED ACTIVE

SLEEP

LED ACTIVE

internal

oscillator

CHONx

(register)

"NOT ALL 0"

Lighting

LED condition

OFF

Figure 53. Start-up Sequence for Cold Cranking Mode

When this IC is in “cold cranking” condition, sequence of operation is as follows.

Lighting

①

②

If this IC detects “VIN UVLO”, internal oscillator is stop and stop lighting. (Low quiescent current condition.)

When “VIN UVLO” is released, the internal oscillator starts, and this IC starts lighting with the same register

settings as before detecting “VIN UVLO”. However, when this IC detects "POR", it is initialized.

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1 Start-up and Turn-off Sequence - continued

Error Sequence for “CRC Error”

1

2

3

CSB

SPI input

state

"SLEEP", " STANDBY", "LED ACTIVE"

FLTRST register

CRCERR register

SO/FAULT_B

Figure 54. CRC Error Detection

①

CRC error is detected when data sent does not match the CRC value in the SPI command. This mismatch can be

caused by wrong data or noise in the SPI line. Write operation is not executed in the IC. Target Register is not updated.

In this case, CRC Error status register is updated to High. Protection is latched automatically, sending SPI command

with correct CRC does not clear CRCERR status register.

②

③

MCU sends Read Command to status registers to confirm CRC status register.

MCU sends FLTRST and dummy SPI (data 0x00) to release the status register.

Error Sequence for “WDT Error”

1

3

4

CSB

CRC NG

SPI input

WDTEN register

"1"

2

WDT counter

(internal signal)

state

"STANDBY or LED ACTIVE"

"LIMPHOME"

"STANDBY or LED ACTIVE"

No activity in the SPI > 1sec

FLTRST register

WDTERR register

SO/FAULT_B

Figure 55. WDT Error Detection

①

②

Watch Dog Timer starts to count at STANDBY or LEDACTIVE state. When there is no "CRC OK" detected in more

than 1 s, IC detects WDT Error.

WDT is detected, it sets the corresponding status register WDTERR to High and state changes from

STANDBY/LEDACTIVE/SPIWAIT to LIMP-HOME.

③

④

MCU sends Read command to Status register to confirm WDT status. This event releases LIMP-HOME mode.

WDT detection is latches automatically, MCU must send FLTRST to clear the WDTERR status register and

SO/FAULT_B output.

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Sequence - continued

2

A/D Control Sequence

ADMODE = 1 (Auto Mode)

PWMDIV setting

1

3

SPI

state machine

LEDACTIVE

PWM signal

(inernal)

2

A/D conversion

VMONSEL (register)

VMON [9:0] (register)

0x0

Enlarged view

SPI

register write

VMONSEL

register Read:

VMON

Figure 56. A/D Control (ADMODE = 1)

① If you want to know VIN voltage, VMON register is available by setting VMONSEL register.

② A/D conversion is executed every PWM timing (internal signal). This period is programmed by PWMDIV register. It is

necessary to set CHONx = 1 to go to LEDACTIVE state to operate this.

③ You should wait to access register after this period.

ADMODE = 0 (Manual Mode)

over 1 us

1

2

SPI

A/D conversion

VMONSEL (register)

VMON[9:0] (register)

0x0

VIN data

Enlarged view

SPI

register write

VMONSEL ADTRG

SPI

write

register Read:

VMON

Figure 57. A/D Control (ADMODE = 0)

① If you want to know VIN voltage, VMON register is available by setting ADSEL register, and A/D starts to convert by

ADTRG = 1.

② You should wait to access register after changing ADSEL. VMON register is available after 1 µs (include margin).

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Typical Performance Curves

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C)

Figure 58. Total Average Current Sense Threshold Voltage

vs Temperature

Figure 59. Total Average Current Sense Threshold Voltage

Error vs ISET Count

Figure 60. Total Average Current Sense Threshold Voltage

vs ISET Count

Figure 61. SNSPx Input Current vs Temperature

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Typical Performance Curves - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C)

Figure 62. SNSNx Input Current vs Temperature

Figure 63. SNSPx And SNSNx Differential Input Current vs

Temperature

Figure 64. SWx ON Resistor High Side vs Temperature

Figure 65. SWx ON Resistor Low Side vs Temperature

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Typical Performance Curves - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C)

Figure 66. SWx Minimum ON Time vs Temperature

Figure 67. SWx Minimum OFF Time vs Temperature

Figure 68. VIN UVLO Threshold vs Temperature

Figure 69. 5VREG UVLO Threshold vs Temperature

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Typical Performance Curves - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C )

Figure 70. 5VEXT UVLO Threshold vs Temperature

Figure 71. 5VREG POR Threshold vs Temperature

Figure 72. PIN UVLO Threshold vs Temperature

Figure 73. VIN Sleep Circuit Current vs Temperature

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Typical Performance Curves - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C )

Figure 74. Switching Frequency vs Temperature

(D_ONx= 0.5, R_TON= 51 kΩ)

Figure 75. Switching Frequency vs R_TON

(D_ONx= 0.5)

Figure 76. Switching Frequency vs TON Count

(D_ONx= 0.5, R_TON= 51 kΩ)

Figure 77. Internal Oscillator Frequency vs Temperature

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Typical Performance Curves - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V, Tj = 25 °C)

Figure 78. Thermal Sensor ADC Read Value vs Temperature

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Design Requirements

Parameter

VIN Continuous Supply Voltage

PIN Continuous Supply Voltage

SNSNx LED Output Voltage

Symbol

V_IN

Min

Typ

13

60

-

Max

Unit

V

-

58

3

0.2

-

62

54

2.0

1

V_PIN

V

V_OUTx

I_LEDx

V

Continuous Average LED Current

ΔPeak LED Current

-

A

ΔI_{LEDx_PEAK}

R_LEDx

f_SWx

-

A

LED String Series Resister at V_OUTx= 30 V

Setting Switching Frequency

-

2.4

400

54

25

-

Ω

-

kHz

V

Dynamic Voltage Changed of LEDs

Transition Time for Dynamic Voltage Change of LEDs

Ambient Temperature

ΔV_LEDx

T_LEDx

-

µs

°C

Topr

-

Design Procedure

1 Calculating Duty Cycle

Solve for the buck converter switching on-duty (D_ONx) and Max-on-duty (D_{ONx_MAX}) and Minimum-on-duty (D_{ONx_MIN}).

SNSPx voltage is almost same with SNSNx voltage.

ꢀ

푆푁푆푃푥

ꢇ_푂푁푥

=

,

ꢀ_푃ꢁ푁

ꢀ

=

54

58

3

푆푁푆푃푥

ꢗꢘ푋

=

= 0.931,

= 0.0483

ꢗꢘ푋

ꢀ_푃ꢁ푁

ꢗꢙꢚ

ꢀ

푆푁푆푃푥_푀ꢁ푁

ꢇ_{푂푁푥_푀ꢁ푁}

=

ꢀ_{푃ꢁ푁_푀퐴ꢛ}

ꢎ2

2

Calculating Minimum on-time and Minimum off-time

Solve for the buck converter switching on-time (T_ONx) and Minimum-on-time (T_{ONx_MIN}) and Minimum-off-time (T_{OFFx_MIN}).

ꢇ_푂푁푥

ꢄ_푂푁푥

=

,

푓

푆푊푥

ꢇ_{푂푁푥_푀ꢁ푁}

0.0483

400 × 10^ꢜ

ꢄ_{푂푁푥_푀ꢁ푁}

=

= 121 × 10^ꢋꢌ,

푓

푆푊푥

1 − ꢇ_{푂푁푥_푀퐴ꢛ}

0.0ꢎ9

400 × 10^ꢜ

ꢄ_{푂퐹퐹푥_푀ꢁ푁}

=

= 173 × 10^ꢋꢌ

푓

푆푊푥

If T_{ONx_MIN}≤ t_SWxONMIN

Desired switching frequency (f_SWx) will be less than setting frequency and desired Average LED current (I_LEDxAVE) can be

regulated.

If T_{OFFx_MIN}≤ t_SWxOFFMIN

Desired switching frequency (f_SWx) can be nearly fixed value and desired Average LED current (I_LEDxAVE) will be less than

setting value.

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Design Procedure – continued

3

4

5

LED Current Setting

Average LED current setting (I_LEDxAVE) should be lower than maximum average LED current (I_{LEDxAVE_MAX}) 2 A.

ꢀ

0.1915

푅_푆푁푆푥

푆푁푆푥퐴푉퐸ꢝꢞꢞ%퐻

퐼_{퐿퐸퐷푥퐴푉퐸}

푅_푆푁푆푥

=

ꢀ

=

≤ 퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}= 2

푅_푆푁푆푥

0.1915

푆푁푆푥퐴푉퐸ꢝꢞꢞ%퐻

≥

=

= 0.0958

퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

2

Average LED current setting in the LIMP-HOME or STAND-ALONE mode should be lower than 2 A.

ꢍ

ꢏ

퐼_{퐿퐸퐷푥퐴푉퐸}ꢟ푛 푡ℎ푒 ꢠ퐼ꢒꢐ‐ ꢡꢉꢒꢃ 표푟 푡ℎ푒 ꢂꢄꢓꢊꢇ‐ ꢓꢠꢉꢊꢃ

ꢀ

0.1ꢎꢎꢎ

푆푁푆푥퐴푉퐸ꢢꢣ%퐻

=

≤ 퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}= 2

푅_푆푁푆푥

Total LED Current Setting

Recommended Average LED current setting is less than 1.6 A, so that recommended tola LED current (I_{LEDxAVE_TOTAL}) is less

than 4.8 A for the BD18398RUV-M and 3.2 A for the BD18397RUV-M.

Recommended tola LED current (I_{LEDxAVE_TOTAL}) is less than 2.7 A for the BD18397/98EUV-M.

ꢍ

ꢏ

퐼_{퐿퐸퐷푥퐴푉퐸_푇푂푇퐴퐿}푓표푟 푡ℎ푒 퐵ꢇ18397푅푈ꢀ‐ ꢒ = 퐼_{퐿퐸퐷ꢝ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢤ퐴푉퐸}≤ 3.2

퐼_{퐿퐸퐷푥퐴푉퐸_푇푂푇퐴퐿}푓표푟 푡ℎ푒 퐵ꢇ18398푅푈ꢀ‐ ꢒ = 퐼_{퐿퐸퐷ꢝ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢤ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢜ퐴푉퐸}≤ 4.8

ꢍ

ꢏ

퐼_{퐿퐸퐷푥퐴푉퐸_푇푂푇퐴퐿}푓표푟 푡ℎ푒 퐵ꢇ18397ꢃ푈ꢀ‐ ꢒ = 퐼_{퐿퐸퐷ꢝ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢤ퐴푉퐸}≤ 2.7

ꢍ

ꢏ

푓표푟 푡ℎ푒 퐵ꢇ18398ꢃ푈ꢀ‐ ꢒ = 퐼_{퐿퐸퐷ꢝ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢤ퐴푉퐸}+ 퐼_{퐿퐸퐷ꢜ퐴푉퐸}≤ 2.7

퐼_{퐿퐸퐷푥퐴푉퐸}

ꢥꢦꢥꢘꢧ

If Average LED current setting of the CH 1 for the BD18398RUV-M is 2.0 A, Average LED current setting of the CH 2 and

CH 3 needs lower setting than 1.4 A/channel.

Inductor Selection

The inductor is selected to meet recommended inductor peak to peak ripple (ΔI_LPP/ I_{LEDxAVE_MAX}) range (10 % to 100 %). For

a stable LED current regulation, required minimum inductor ripple (ΔI_{LPP_MINx}) is more than 10 % (results in 19.1 mV ripple

voltage between the SNSPx and SNSNx) to detect inductor bottom current, and required maximum inductor ripple current

(ΔI_{LPP_MAX}) is less than 100 % (results in 200 mV ripple voltage between the SNSPx and the SNSNx) for nominal operation

without detecting switch-overcurrent-protection (SWOCPx) and LED-current-protection (LOCPx).

훥퐼_{퐿푃푃_푀퐴ꢛ}

ꢀ_{푃ꢁ푁_푀퐴ꢛ}

4 × ꢠ × 푓 × 퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

=

퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

푆푊푥

ꢎ2

= 0.587 ≤ 1

4 × 33 × 10^ꢋ6× 400 × 10^ꢜ× 2

In case of the minimum off time.

훥퐼_{퐿푃푃_푀ꢁ푁ꢝ}

ꢀ

푆푁푆푃푥_푀퐴ꢛ

=

× ꢄ_{푂퐹퐹푥_푀ꢁ푁}

퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

ꢠ × 퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

54

=

× 173 × 10^ꢋꢌ= 0.141 ≥ 0.10

33 × 10^ꢋ6× 2

In case of the minimum on time.

훥퐼_{퐿푃푃_푀ꢁ푁ꢤ}

ꢀ_{푃ꢁ푁_푀퐴ꢛ}− ꢀ

푆푁푆푃푥_푀ꢁ푁

=

× ꢄ_{푂푁푥_푀ꢁ푁}

퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

ꢠ × 퐼_{퐿퐸퐷푥퐴푉퐸_푀퐴ꢛ}

ꢎ2 − 3

× 121 × 10^ꢋꢌ= 0.108 ≥ 0.10

33 × 10^ꢋ6× 2

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Design Procedure - continued

6

Output Capacitor Selection

The minimum output capacitor (C_{OUTx_MIN}) is selected to meet continuous LED current (I_LEDx) over LEDs itself to fulfill the

LED peak to peak current (I_{LEDx_PP}) is not more than twice the minimum LED current (I_{LEDx_MIN}). The maximum output

capacitor (C_{OUTx_MAX}) will be selected to reduce LED peak current (ΔI_{LEDx_PEAK}) into LEDs by discharged capacitor energy

over dynamic LED voltage changed (ΔV_LEDx).

퐼_{퐿퐸퐷푥_푃푃}≤ 2 × 퐼_{퐿퐸퐷푥_푀ꢁ푁_}= 2 × 0.2 = 0.4

훥퐼_{퐿푃푃_푀퐴ꢛ}

0.587 × 2

8 × 400 × 10^ꢜ× 0.4 × 2.4

ꢈ_{푂ꢨ푇푥_푀ꢁ푁}

=

8 × 푓

× 퐼_{퐿퐸퐷푥_푃푃}× 푅_퐿퐸퐷푥

푆푊푥

= 0.38 × 10^ꢋ6

훥퐼_{퐿퐸퐷푥_푃퐸퐴ꢩ}

1

ꢈ_{푂ꢨ푇푥_푀퐴ꢛ}

=

× ꢄ_퐿퐸퐷푥

=

× 25 × 10^ꢋ6= 0.4ꢎ × 10^ꢋ6

훥ꢀ

54

퐿퐸퐷푥

→ ꢈ_푂ꢨ푇푥= 0.47 × 10^ꢋ6

7

Compensation Capacitor for Constant Current Mode (CC)

Recommended compensation capacitor (C_COMPx) and compensation network resister (R_COMPx) are selected for fast response

against PWM dimming and dynamic voltage changed.

In case of 400 kHz switching frequency.

ꢈ_{퐶푂푀푃푥}= 0.1 × 10^ꢋ6

푅_{퐶푂푀푃푥}= 1 × 10^ꢜ

In case of 2 MHz switching frequency, compensation network resister should not be used.

ꢈ_{퐶푂푀푃푥}= 0.022 × 10^ꢋ6

푅_{퐶푂푀푃푥}= 0

8

Compensation Capacitor for Constant Voltage Mode (CV)

Recommended compensation capacitor (C_COMPx) and compensation network resister (R_COMPx) are selected for fast response

against load changed and total output capacitor (C_OUTx) should be increased to reduce voltage drop by load response.

In case of 400 kHz switching frequency.

ꢈ_푂ꢨ푇푥= 10 × 10^ꢋ6

ꢈ_{퐶푂푀푃푥}= 0.1 × 10^ꢋ6

푅_{퐶푂푀푃푥}= 1 × 10^ꢜ

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Typical Application Examples

CPIN5

CPIN1

CPIN4

CPIN6

CPIN7

CPIN2 CPIN3

VIN

GND

PGND

LED Board

+B

RISN1

RISP1

GND

CVIN

SNSN1

SNSP1

GND

COUT1

RBT1

RBT2

RBT3

CBT1

C5VREG

C5VEXT

BOOT1

SW1

0

5VREG

5VEXT

・・・

L1

RSNS1

RSNS2

RSNS3

LED1+

ROUT1

for PWM dimming

PWM1_B

PWM2_B

PWM3_B

RTON

TON

COMP1

EMH1

RCOMP1

CCOMP1

CCOMP2

CCOMP3

RISN2

RISP2

GND

RCOMP2

RCOMP3

COMP2

COMP3

SNSN2

SNSP2

COUT2

CBT2

BOOT2

SW2

EMH2

EMH3

RIS21 RIS11

RIS31

・・・

ISET/PWM1

ISET/PWM2

ISET/PWM3

LED2+

ROUT2

L2

RIS32

RIS22 RIS12

RSO

RISN3

RISP3

GND

SI

SNSN3

SNSP3

SCK

COUT3

CBT3

CSB

BOOT3

SW3

・・・

SO/FAULT_B

LED3+

ROUT3

L3

D3

EXP_PAD

Figure 79. Application Circuit

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Application Parts Choice Examples

Component

Component Value

Product Name

Manufacturer

Name

C_PIN1

C_PIN2

C_PIN3

C_PIN4

C_PIN5

C_PIN6

C_PIN7

C_VIN

4.7 µF

GCM32DC72A475KE02#_X7S_±10 %

Murata

ROHM

-

GCM32DC72A475KE02#_X7S_±10 %

4.7 µF

GCM32DC72A475KE02#_X7S_±10 %

4.7 µF

GCM32DC72A475KE02#_X7S_±10 %

0.1 µF

GCJ188R72A104KA01#_X7R_±10 %

0.1 µF

GCJ188R72A104KA01#_X7R_±10 %

0.1 µF

GCJ188R72A104KA01#_X7R_±10 %

1.0 µF

GCM21BR71H105KA01#_X7R_±10 %

C_5VREG

C_5VEXT

C_COMPx

C_BTx

4.7 µF

GCM21BR71C475KA67#_X7R_±10 %

4.7 µF

GCM21BR71C475KA67#_X7R_±10 %

0.1 µF

GCM188L81H104KA57#_X8L_±10 %

2.2 µF

GCM188C71A225KE01#_X7S_±10 %

0.22 µF x 2 (CC mode)

4.7 µF x 2 (CV mode)

51 kΩ

GCM31MR72A224KA01#_X7R_±10 %

C_OUTx

R_TON

GCM32DC72A475KE02#_X7S_±10 %

MCR03

0 Ω (CC mode)

4.7 kΩ (CV mode)

4.7 kΩ

R_COMPx

MCR03

R_SO

MCR03

R_ISNx

R_ISPx

R_SNSx

R_BTx

1 kΩ

MCR03

1 kΩ

MCR03

0.091 Ω

LTR18

4.7 Ω

MCR03

R_OUTx

47 kΩ

MCR03

Open (CC mode)

47 kΩ (CV mode)

10 kΩ (CC mode)

Open (CV mode)

22 µH

-

R_ISx1

MCR03

ROHM

-

MCR03

R_Isx2

-

L_x

XAL5050-223ME

RB068MM100TF

DTC144EE

Coil Craft

ROHM

D₃

100 V, 2A

-

EMHx

(x = 1, 2, 3)

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Application Typical Waveforms

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V)

COMPx [2 V/div.]

SWx [30 V/div.]

COMPx [2 V/div.]

SWx [30 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [200 µs/div.]

Figure 80. ON Sequence

(C_COMPx= 0.1 µF)

Figure 81. OFF Sequence

(C_COMPx= 0.1 µF)

COMPx [2 V/div.]

SWx [30 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [200 µs/div.]

Figure 82. ON Sequence

(C_COMPx= 10 nF)

Figure 83. OFF Sequence

(C_COMPx= 10 nF)

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Application Typical Waveforms - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V)

V_OUTx[30 V/div.]

V_OUTx[10 V/div.]

SWx [10 V/div.]

SWx [30 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [1 µs/div.]

ILx [1 A/div.]

Time [500 µs/div.]

ILEDx [1 A/div.]

Figure 84. Normal Operation

Figure 85. PWM Dimming Operation

V_OUTx[10 V/div.]

SWx [50 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [5 µs/div.]

Figure 86. Internal PWM Dimming (Rising Edge)

Figure 87. Internal PWM Dimming (Falling Edge)

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Application Typical Waveforms - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V)

V_OUTx[30 V/div.]

SWx [30 V/div.]

V_OUTx[30 V/div.]

SWx [30 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

Figure 88. Output Short Circuit Fault

(C_COMPx= 0.1 µF)

Figure 89. Output Short Circuit Fault Recovery

(C_COMPx= 0.1 µF)

V_OUTx[30 V/div.]

SWx [30 V/div.]

V_OUTx[30 V/div.]

SWx [30 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

Figure 90. Output Short Circuit Fault

(C_COMPx= 10 nF)

Figure 91. Output Short Circuit Fault Recovery

(C_COMPx= 10 nF)

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Application Typical Waveforms - continued

(Unless otherwise specified V_IN= 13 V, V_PIN= 60 V, V_5VEXT= 5 V)

V_OUTx[50 V/div.]

SWx [50 V/div.]

V_OUTx[50 V/div.]

SWx [50 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

Figure 92. Output Open Circuit Fault

(C_COMPx= 0.1 µF)

Figure 93. Output Open Circuit Fault Recovery

(C_COMPx= 0.1 µF)

V_OUTx[50 V/div.]

SWx [50 V/div.]

V_OUTx[50 V/div.]

SWx [50 V/div.]

ILx [1 A/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

ILEDx [1 A/div.]

Time [50 µs/div.]

Figure 94. Output Open Circuit Fault

(C_COMPx= 10 nF)

Figure 95. Output Open Circuit Fault Recovery

(C_COMPx= 10 nF)

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Layout Example

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I/O Equivalence Circuits

Pin No.

Name

I/O Equivalence Circuit

HTSSOP HTSSOP

-C48R

-C48

-C48R

-C48

5VREG

SO/FAULT_B

SO/

FAULT_

B

CSB

2

23

3

22

CSB

GND

SCK

SI

4

21

SCK

5

20

SI

GND

5VREG

6

7

8

19

18

17

COMP1

ISET/

PWM1

9

16

15

ISET/

PWM1,

ISET/

PWM3

(Note 1)

COMPx

COMP3

(Note 1)

ISET/

PWM3

10

COMP2

GND

VIN

5VREG

ISET/

PWM2

ISET/

PWM2

11

14

13

12

TON

GND

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I/O Equivalence Circuits – continued

Pin No.

Name

I/O Equivalence Circuit

HTSSOP HTSSOP

-C48R

-C48

-C48R

-C48

17

20

23

8

5

2

SNSP1

(Note 1)

VIN

SNSP3

SNSPx

SNSP2

5VREG

GND

14

11

5VREG

SNSNx

GND

18

21

24

7

4

1

SNSN1

(NNootete11)

SNSN3

SNSN2

5VEXT

BOOTx

29,30

38,39

43,44

34,35

29,30

SW2

(Note 1)

5VEXT

SW3

SW1

33

40

5VEXT

31

40

42

33

31

BOOT2

(Note 1) SWx

BOOT3

PGND

BOOT1

(Note 1) BD18397: COMP3, ISET/PWM3, SNSP3, SNSN3, SW3, BOOT3 = N.C.

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

6. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

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Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 96. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat

damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

14. Functional Safety

“ISO 26262 Process Compliant to Support ASIL-*”

A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in

the datasheet.

“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”

A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.

“Functional Safety Supportive Automotive Products”

A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the

functional safety.

Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.

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Ordering Information

B D 1

8

3

9

x

-

M E 2

Output

Package

Product Rank

Channel

7: 2 channel

8: 3 channel

RUV: HTSSOP-C48R

EUV: HTSSOP-C48

M: for Automotive

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagrams

HTSSOP-C48R (TOP VIEW)

Part Number Marking

LOT Number

Pin 1 Mark

HTSSOP-C48 (TOP VIEW)

Part Number Marking

LOT Number

Pin 1 Mark

Lineup

Output Channel

Part Number Marking

BD18397

Package

Orderable Part Number

HTSSOP-C48R

HTSSOP-C48

HTSSOP-C48R

HTSSOP-C48

BD18397RUV-ME2

BD18397EUV-ME2

BD18398RUV-ME2

BD18398EUV-ME2

2 ch

3 ch

BD18397EUV

BD18398

BD18398EUV

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Physical Dimension and Packing Information

Package Name

HTSSOP-C48R

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Physical Dimension and Packing Information – continued

Package Name

HTSSOP-C48

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Revision History

Date

Revision

001

Changes

15.Feb.2022

New Release

Adding Lineup

Before: BD18397RUV-M, BD18398RUV-M

After: BD18397RUV-M, BD18398RUV-M, BD18397EUV-M, BD18398EUV-M

P1 updating Key Specification

LED Output Voltage Range

Before: 2 V to 60 V

After: 2.5 V to 60 V

P1 updating Typical Application Circuit

Figure 1. Typical Application Circuit

P3 updating Pin Descriptions

BOOT1, BOOT2, BOOT3

Before: Connecting boot strap capacitor

After: Connecting series resister and boot strap capacitor

SW1, SW2, SW3

Adding description: Connecting schottky barrier diode to the SW3 pin.

5VREG

Before: 2.2 μF

After: 4.7 μF

5VEXT

Before: 2.2 μF

After: 4.7 μF

P4 updating Bock Diagram

Figure 4. Block Diagram

01.Mar.2023

002

P6 updating Thermal Resistance

Adding item: HTSSOP-C48 for BD1839xEUV-M

P7 updating Recommended Operating Conditions

Note 2

Before: Schottky Barrier Diodes between

After: Schottky Barrier Diodes should be needed between

Adding item: PWM Dimming off Pulse Width and Note 6

Adding item: Continuous Total Average LED Current for BD1839xEUV-M

P8 updating Recommended Setting Parts Range

Adding item: R_BTxand Note 2

P14 updating Description of Blocks > Buck Converter LED Current Regulation

Before: by the real time sensing V_PINand V_SNSNxvoltage.

After: by the real time sensing V_PINand V_SNSPxvoltage.

P15 updating Description of Blocks > LED Current Setting (Current Sense)

Figure 7. LED Current Setting

P16 updating Description of Blocks > DCDC Switching Frequency

T_ONx

Before: k / (TONx[5:0] +1) x R_TONx V_SNSPx/ V_PIN+ 20 x 10^-9

After: k / (TONx[5:0] +1) x R_TONx V_SNSPx/ V_PINx 10^-6+ 20 x 10^-9

f_swx

Before: 1 / (k / (TONx[5:0] +1) x R_TONx V_SNSPx/ V_PIN+ 20 x 10^-9) x V_SNSPx/ V_PIN

After: 1 / (k / (TONx[5:0] +1) x R_TONx V_SNSPx/ V_PINx 10^-6+ 20 x 10^-9) x V_SNSPx/ V_PIN

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Revision History – continued

Date

Revision

Changes

P20 updating Description of Blocks > Bootstrap Charge

Adding description: When turning on the corresponding channel, the output voltage

must be sufficiently discharged (V_OUTx< 1.5 V) before turning on the corresponding

channel (CHONx = 1) to ensure that the bootstrap voltage is above the recommended

operating voltage (V_BTSWx> 3.5 V).

P24 updating Description of Blocks > Abnormal Detection/Protection Function

5VREG 5VEXT UVLO

Before: V5VREG ≥ 4.5 V or V5VEXT ≥ 4.5 V

After: V5VREG ≥ 4.2 V or V5VEXT ≥ 4.2 V

P25 updating Description of Blocks > Under Voltage Locked Out (UVLO)

Before: When detecting a UVLO by the V_INor V_5VREGor V_5VEXT

After: When detecting a UVLO by the V_INor V_5VREGor V_5VEXTor V_PIN

,

P26 updating Description of Blocks > SW Over Current Protection (SWOCPx)

Figure 20. SW Over Current Protection Waveform

P27 updating Description of Blocks > LED Open Detection

Figure 21. LED Open Detection Waveform

P28 updating Description of Blocks > LED Short to GND Detection

Figure 22. LED Short to GND Detection Waveform

P31 updating Description of Blocks > SPI Protocol and AC Electrical Characteristics

Adding description: SI data is outputted with 24 bits shift from SO/FAULT_B.

SO/FAULT_B keeps Hi-z when CSB = high.

01.Mar.2023

002

P33 updating Description of Blocks > SPI Protocol and AC Electrical Characteristics

> SPI AC Timing

Adding item: NOTE (Countermeasure of Noise)

Adding item: Figure 29. Countermeasure of Noise

P34 updating Description of Blocks > SPI Protocol and AC Electrical Characteristics

> SPI Protocol > CRC

Adding description: (It doesn't change value until '1' input because initial 0. (The result

of "011111111111111111111111" (binary) is same as result of "111111111111111111111111".))

P41 updating Description of Blocks > Register > Description of Registers

initial value of Address 0x00: SYSSET

Before: initial value 0x00

After: initial value 0x40

P43 updating Description of Blocks > Register > Description of Registers

Description of Address 0x03: DIMSET bit[7] PHEN

Before: as shown in Figure 41.

After: as shown in Figure 44.

P44 updating Description of Blocks > Register > Description of Registers

Description of Address 0x04 & 0x05

Removing description: If you want to change value during dimming, WLOCK function

can be used.

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Revision History – continued

Date

Revision

Changes

P45 updating Description of Blocks > Register > Description of Registers

Table 15. DC/DC GM Amplifier Trans Conductance Setting

GM1[1:0] = 0

Before: 1200

After: 1360

GM1[1:0] = 1

Before: 750

After: 870

GM1[1:0] = 2

Before: 430

After: 530

GM1[1:0] = 3

Before: 240

After: 300

P57 updating Sequence > Start-up and Turn-off Sequence > Error Sequence for “WDT

Error”

Description of Error Sequence for “WDT Error” ①

Removing description: and SO/FAULT_B output is set to low

P66 updating Design Procedure > Total LED Current Setting

Adding description and formula for BD1839xEUV-M

P66 updating Design Procedure >Inductor Selection

Before: in case of the minimum on time

After: in case of the minimum off time

01.Mar.2023

002

Before: in case of the maximum on time

After: in case of the minimum on time

P68 updating Typical Application Examples

Figure 79. Application Circuit

P69 updating Application Parts Choice Example

C_OUTx

Before: 10 μF, GCM31MR72A224KA01#_X7R_±10 %

After: 4.7 μF x 2, GCM32DC72A475KE02#_X7S_±10 %

Lx

Before: XAL8050-223ME

After: XAL5050-223M

D₃

Before: RB068LAM100

After: RB068MM100TF

Adding item: R_BTx

P74 updating Layout Example

P75 updating I/O Equivalence Circuits

Adding item: New package Pin No.

P79 updating Ordering Information and Marking Diagram and Lineup

Adding item: HTSSOP-C48 for BD1839xEUV-M

P81 updating Physical Dimension and Packing Information

Adding item: HTSSOP-C48 for BD1839xEUV-M

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD18397RUV-M
厂家：	ROHM
描述：	BD18397RUV-M是一款双通道同步降压型DC-DC LED驱动器，采用ON-Time拓扑结构支持接近恒定的开关频率和快速开关占空比调节，并采用平均LED电流反馈降压拓扑结构在更宽输入和LED输出范围内实现更出色的LED电流调节系统。开关驱动驱动器
文件：	总87页 (文件大小：5027K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD18397RUV-M [ROHM]

相关型号：

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BD18BC0T

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