BD34301EKV [ROHM]
BD34301EKV是一款融入ROHM自有音质设计技术的32位立体声D/A转换器。实现了适用于高端音响的出色数值性能[SNR： 130dB(Typ), THD+N： -115dB(Typ)]。可通过切换两种FIR数字滤波器（Sharp Roll-Off, Slow Roll-Off）来选择喜欢的音质。配备PCM I/F和DSD I/F，最高采样频率分别支持768kHz和22.4MHz。竭力追求音频产品所需的数值性能和音质性能提升，并将ROHM工程师们的热情诉诸ROHM音频IC，打造出高端品牌。ROHM Musical Device“MUS-IC"“MUS-IC"特设页面;
| 型号： | BD34301EKV |
| 厂家： | 
ROHM |
| 描述： | BD34301EKV是一款融入ROHM自有音质设计技术的32位立体声D/A转换器。实现了适用于高端音响的出色数值性能[SNR： 130dB(Typ), THD+N： -115dB(Typ)]。可通过切换两种FIR数字滤波器（Sharp Roll-Off, Slow Roll-Off）来选择喜欢的音质。配备PCM I/F和DSD I/F，最高采样频率分别支持768kHz和22.4MHz。竭力追求音频产品所需的数值性能和音质性能提升，并将ROHM工程师们的热情诉诸ROHM音频IC，打造出高端品牌。ROHM Musical Device“MUS-IC"“MUS-IC"特设页面 PC 转换器 |
| 文件： | 总54页 (文件大小：2446K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
High Sound Quality Audio D/A Converters
32-bit, 768 kHz Sampling
Stereo Audio D/A Converter
BD34301EKV
General Description
Key Specifications
BD34301EKV is 32-bit high sound quality Stereo Audio
D/A converter with ROHM original sound quality design,
realizing excellent numerical performance (SNR: 130 dB
(Typ), THD+N: -115 dB (Typ)) suitable for high-end audio.
Favourite sound is selectable by switching 2 kinds of
digital FIR filters (Sharp Roll-Off, Slow Roll-Off). PCM I/F
supports up to 768 kHz and DSD I/F supports up to 22.4
MHz.
Supply Voltage Range of AVCC(Note 2) 4.5 V to 5.5 V
Supply Voltage Range of DVDD
Supply Voltage Range of DVDDIO
SNR(Note 1)
1.4 V to 1.6 V
3.0 V to 3.6 V
130 dB (Typ)
-115 dB (Typ)
130 dB (Typ)
THD+N(Note 1)
Dynamic Range(Note 1)
Operation Temperature Range
-25 °C to +85 °C
Package
HTQFP64BV
Features
W (Typ) x D (Typ) x H (Max)
12.0 mm x 12.0 mm x 1.0 mm
MUS-ICTM Series
SNR 130 dB (Typ), THD+N -115 dB (Typ) (Note 1)
Sampling Frequency 32 kHz to 768 kHz(Note 1)
2 Kinds of Digital FIR Filters (Note 1)
DSD 2.8 MHz, 5.6 MHz, 11.2 MHz, 22.4 MHz
Available
Supports Stereo Mode (2ch) and Mono Mode (1ch)
Selectable 4 Device Addresses (38h, 3Ah, 3Ch, 3Eh)
.
Applications
CD/SACD Player
Digital Audio Player (DAP)
USB-DAC and Others
(Note 1) PCM mode
(Note 2) AVCC, AVCC_R and AVCC_L in Typical Application Circuit
Typical Application Circuit
AVCC_L
5.0 V
DVDDIO
3.3 V
DVDD
1.5 V
100 μF
0.1 μF
100 μF 100 μF
0.1 μF 0.1 μF
100 μF
100 μF
100 μF
100 μF
0.1 μF
100 μF
0.1 μF
100 μF
0.1 μF
100 μF
C35
C15
C17
C16
C18
C7
C8
C1
C2
C19
C20
C3
C4
C5
C6
C11
C12
C13
C14
C9
1500 pF
C10
R5
0.1 μF 0.1 μF
0.1 μF 0.1 μF
R7
R11
390 Ω
64
2
7
9
17
15
11
63
59
61
50
48
53
55
58
56
44～47
1 kΩ
560 Ω + 820 Ω
R9
C38
1500 pF
Lch Out
Single
C36
1500 pF
IOUT_LP
IOUT_LN
C37
51
52
R6
BCLK/DSDCLK
BCLK
Current
Segment
R10
R12
1 kΩ
12
R8
C39
1500 pF
AVCC
5.0 V
Over
560 Ω + 820 Ω
C21
LRCLK/DSD2
LRCLK
Lch Out
Differential
Sampling
Digital
FIR
PCM
100 μF
C22
ΔΣ
Modulator
13
DSP
AVCC 42
I/F
0.1 μF
AVCC_L
5.0 V
100 μF
C23
Audio
Function
Control
DIN/DSD1
DIN
Filter
0.1 μF
14
VREF_L
C24
43
EXT_RES_L
41
(Note 3)
R1
MCLK
The written values of external parts
are checked by sound test. Changing
these values can affect the sound
quality. Please check the sound
when the values are changed.
VREF
910 Ω
R2
EXT_RES_R
40
910 Ω
AVCC_R
5.0 V
VREF_R
DSD
I/F
C25
C26
38
0.1 μF
100 μF
C40
1500 pF
AGND
39
R13
R15
560 Ω + 820 Ω
R19
390 Ω
IOUT_RP
IOUT_RN
1 kΩ
30
29
Current
MCLK
60
2-wire
System
Control
R17
Master
Clock
C43
1500 pF
Rch Out
Single
Segment
I/F
C41
1500 pF
C42
R14
R18
1 kΩ
R16
C44
1500 pF
8
10
16
18
19
20
21
3
4
5, 6
31
33
28
0.1 μF
26
23
0.1 μF
25
1
34 ～ 37
560 Ω + 820 Ω
R20
0.1 μF 0.1 μF
R3
2.2 kΩ
C33
C34
C31
C32
C29
C30
C27
C28
Rch Out
Differential
DVDDIO
3.3 V
R4
2.2 kΩ
100 μF
100 μF
100 μF
100 μF
CPU
AVCC_R
5.0 V
Figure 1. Typical Application Circuit
MUS-ICTM is a trademark or a registered trademark of ROHM Co., Ltd.
〇Product structure : Silicon integrated circuit 〇This product has not designed protection against radioactive rays.
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Datasheet
BD34301EKV
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Key Specifications ..........................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Typical Application Circuit...............................................................................................................................................................1
MUS-ICTM .......................................................................................................................................................................................3
Pin Configuration ............................................................................................................................................................................4
Pin Descriptions..............................................................................................................................................................................5
Block Diagram ................................................................................................................................................................................7
Absolute Maximum Ratings ............................................................................................................................................................8
Thermal Resistance........................................................................................................................................................................8
Recommended Operating Conditions.............................................................................................................................................8
Electrical Characteristics.................................................................................................................................................................9
Measurement Circuit.....................................................................................................................................................................11
DC Characteristics........................................................................................................................................................................12
AC Characteristics (MCLK, RESETB) ..........................................................................................................................................12
AC Characteristics (PCM Mode)...................................................................................................................................................13
AC Characteristics (DSD Mode) ...................................................................................................................................................13
AC Characteristics (2-wire I/F)......................................................................................................................................................14
Typical Performance Curves.........................................................................................................................................................15
2-wire I/F.......................................................................................................................................................................................16
Register Map ................................................................................................................................................................................18
Register Description .....................................................................................................................................................................20
System Clock................................................................................................................................................................................35
Power-On Sequence ....................................................................................................................................................................36
Power-Off Sequence.....................................................................................................................................................................38
Mode Switching Sequence ...........................................................................................................................................................39
Recommended Settings................................................................................................................................................................41
Sound Settings .............................................................................................................................................................................41
Application Examples ...................................................................................................................................................................42
Operational Notes.........................................................................................................................................................................47
Ordering Information.....................................................................................................................................................................49
Marking Diagrams.........................................................................................................................................................................49
Physical Dimension and Packing Information...............................................................................................................................50
Revision History............................................................................................................................................................................51
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Datasheet
BD34301EKV
MUS-ICTM
MUS-ICTM stands for ROHM Musical Device MUS-IC. MUS-IC™ series are products designed for high-end audio.
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Datasheet
BD34301EKV
Pin Configuration
(TOP VIEW)
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
49
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
N.C.
N.C.
50
AGND1_L
AGND1_R
IOUT_RP
IOUT_RN
AGND2_R
N.C.
51
IOUT_LP
52
IOUT_LN
53
AGND2_L
54
N.C.
55
AVCC2_L
AVCC2_R
AVCC3_R
N.C.
56
AVCC3_L
EXP-PAD
57
N.C.
58
AGND3_L
AGND3_R
N.C.
59
DGND2
60
MCLK
TEST7
61
DVDDIO2
TEST6
62
N.C.
TEST5
63
DVDD2
TEST4
64
DVDD1
DVDD1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Figure 2. Pin Configuration
Caution:
Open the N.C. pins and the TEST pins (TEST1 to TEST7).
The EXP-PAD should be connect to AGND.
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Datasheet
BD34301EKV
Pin Descriptions
Pin No.
Pin Name
RESETB
DGND1
SDA
D/A(Note 1) I/O(Note 2)
Function
1
2
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
-
I
-
Reset (L: Reset)
Digital ground
2-wire I/F data(Note 3)
3
I/O
I
4
SCL
2-wire I/F clock
5
ADDR1
ADDR2
DVDD1
TEST1
DGND1
TEST2
DVDDIO1
I
2-wire I/F device address selector1 (38h/3Ah/3Ch/3Eh)
2-wire I/F device address selector2 (38h/3Ah/3Ch/3Eh)
Digital core power supply (1.5 V)
The TEST pin(Note 4)
6
I
7
-
8
I
9
-
Digital ground
The TEST pin(Note 4)
10
11
I
-
Digital I/O power supply (3.3 V)
PCM I/F bit clock / DSD clock
PCM I/F LR clock / DSD2 data
PCM I/F serial data / DSD1 data
Digital ground
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
DGND1
TEST3
I
I
I
-
I
The TEST pin(Note 4)
DVDD1
-
Digital core power supply (1.5 V)
The TEST pin(Note 4)
TEST4
I
TEST5
I
The TEST pin(Note 4)
The TEST pin(Note 4)
The TEST pin(Note 4)
No connection(Note 4)
TEST6
I
TEST7
I
N.C.
-
AGND3_R
N.C.
A
-
-
Rch analog ground
No connection(Note 4)
-
AVCC3_R
AVCC2_R
N.C.
A
A
-
-
Rch analog power supply (5.0 V)
Rch analog power supply (5.0 V)
No connection(Note 4)
-
-
AGND2_R
IOUT_RN
IOUT_RP
AGND1_R
N.C.
A
A
A
A
-
-
Rch analog ground
O
O
-
Rch negative output
Rch positive output
Rch analog ground
No connection(Note 4)
-
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Datasheet
BD34301EKV
Pin Descriptions - continued
Pin No.
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
-
Pin Name
AVCC1_R
AVCC_R
AVCC_R
AVCC_R
AVCC_R
VREF_R
AGND
D/A(Note 1)
I/O(Note 2)
Function
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
-
-
-
Rch analog power supply (5.0 V)
Rch analog power supply for Current Segment (5.0 V)
Rch analog power supply for Current Segment (5.0 V)
Rch analog power supply for Current Segment (5.0 V)
Rch analog power supply for Current Segment (5.0 V)
Rch external capacitor (Recommended: 0.1 μF + 100 μF)
Analog ground
-
-
-
O
-
EXT_RES_R
EXT_RES_L
AVCC
O
O
-
Rch external register (Recommended: 910 Ω)
Lch external register (Recommended: 910 Ω)
Analog power supply (5.0 V)
VREF_L
AVCC_L
AVCC_L
AVCC_L
AVCC_L
AVCC1_L
N.C.
O
-
Lch external capacitor (Recommended: 0.1 μF + 100 μF)
Lch analog power supply for Current Segment (5.0 V)
Lch analog power supply for Current Segment (5.0 V)
Lch analog power supply for Current Segment (5.0 V)
Lch analog power supply for Current Segment (5.0 V)
Lch analog power supply (5.0 V)
No connection(Note 4)
-
-
-
-
-
AGND1_L
IOUT_LP
IOUT_LN
AGND2_L
N.C.
A
A
A
A
-
-
Lch analog ground
O
O
-
Lch positive output
Lch negative output
Lch analog ground
No connection(Note 4)
-
AVCC2_L
AVCC3_L
N.C.
A
A
-
-
Lch analog power supply (5.0 V)
Lch analog power supply (5.0 V)
No connection(Note 4)
-
-
AGND3_L
DGND2
A
D
D
D
-
-
Lch analog ground
-
Digital ground for MCLK
MCLK
I
Master clock
DVDDIO2
N.C.
-
Digital I/O power supply for MCLK (3.3 V)
No connection(Note 4)
-
DVDD2
D
D
-
-
Digital power supply for MCLK (1.5 V)
Digital core power supply (1.5 V)
Connect the EXP-PAD to AGND.
DVDD1
-
EXP_PAD
-
(Note 1) D/A means D: Digital pin, A: Analog pin.
(Note 2) I/O means I: Input, O: Output.
(Note 3) In 2-wire I/F operation, this pin becomes open-drain output.
(Note 4) Open the N.C. pins and TEST pins (TEST1 to TEST7)
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Datasheet
BD34301EKV
Block Diagram
61
50
48
53
55
58
56
64
2
7
9
17 15 11 63 59
44 ～ 47
51
IOUT_LP
IOUT_LN
Current
12
13
14
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
Segment
52
Over
Sampling
Digital
FIR
PCM
ΔΣ
I/F
Modulator
42
Audio
AVCC
Filter
Function
Control
43
41
VREF_L
EXT_RES_L
VREF
40
38
EXT_RES_R
VREF_R
DSD
I/F
39
AGND
30
29
IOUT_RP
IOUT_RN
Current
2-wire
System
Master
Clock
60
MCLK
Segment
I/F
Control
8
10
16
18
19
20
21
3
4
5, 6
1
31
33
28
26
23
25
34 ～ 37
Figure 3. Block Diagram
Table 1. Description of Blocks
Description
Block
Digital audio interface for PCM audio format 2ch stereo
Supports 32 kHz to 768 kHz input sampling frequency
Supports 16-bit to 32-bit data formats
PCM I/F
DSD I/F
BCLK = 64 fs
Digital audio interface for DSD audio format 2ch stereo
Supports 2.8 MHz, 5.6 MHz, 11.2 MHz, 22.4 MHz DSD
Master Clock
2-wire I/F
Clock control
2-wire interface block for register settings
Supports 400 kHz data transmission speed
4 device addresses (38h, 3Ah, 3Ch, 3Eh) are selectable
System Control
System control by register setting
Audio format control
Audio Function Control
PCM mode: LR swap -> stereo/mono -> polarity inversion
DSD mode: stereo/mono -> LR swap -> polarity inversion
Over sampling digital FIR filter
Over Sampling Digital FIR Filter
ΔΣ Modulator
Sharp Roll-Off / Slow Roll-Off filter are selectable
ΔΣ modulator
Current Segment
VREF
Current segment
Voltage reference
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Datasheet
BD34301EKV
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
Rating
Unit
V
AVCC
DVDDIO
DVDD
Vin
7.0
Supply Voltage
7.0
2.1
Input Voltage
-0.3 to DVDDIO + 0.3
-55 to +150
150
V
Storage Temperature Range
Maximum Junction Temperature
Tstg
°C
°C
Tjmax
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing
board size and copper area so as not to exceed the maximum junction temperature rating.
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s (Note 3)
2s2p (Note 4)
HTQFP64BV
Junction to Ambient
Junction to Top Characterization Parameter (Note 2)
θJA
64.5
3
16.1
2
°C/W
°C/W
ΨJT
(Note 1) Based on JESD51-2A(Still-Air).
(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface
of the component package.
(Note 3) Using a PCB board based on JESD51-3.
(Note 4) Using a PCB board based on JESD51-7.
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3 mm x 76.2 mm x 1.57 mmt
Top
Copper Pattern
Thickness
70 μm
Footprints and Traces
Thermal Via (Note 5)
Layer Number of
Measurement Board
Material
FR-4
Board Size
114.3 mm x 76.2 mm x 1.6 mmt
2 Internal Layers
Pitch
Diameter
4 Layers
1.20 mm
Φ0.30 mm
Top
Copper Pattern
Bottom
Thickness
70 μm
Copper Pattern
Thickness
35 μm
Copper Pattern
Thickness
70 μm
Footprints and Traces
74.2 mm x 74.2 mm
74.2 mm x 74.2 mm
(Note 5) This thermal via connects with the copper pattern of all layers.
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
AVCC
DVDDIO
DVDD
Topr
4.5
3.0
1.4
-25
5.0
3.3
1.5
+25
5.5
3.6
1.6
+85
Operating Supply Voltage
Operating Temperature
V
°C
Caution: Operating supply voltage and operating temperature are the ranges in which the IC is available for basic operation.
(Basic operation means that the IC operates without emitting unexpected noise or stopping signal.)
Characteristics and rating are not warranted in the whole operating supply voltage and operating temperature.
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Datasheet
BD34301EKV
Electrical Characteristics
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V, Input signal frequency = 1 kHz, 20-
kHz AES17 LPF, Differential output (XLR) measurement, PCM Mode, 24-bit I2S input, fs = 44.1 kHz, MCLK = 11.2896 MHz,
Clock 2 (06h) = 01h, FIR Filter 1 (30h) = 01h, FIR Filter 2 (31h) = 80h, Delta Sigma (40h) = 00h
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
Power Supply Current
AVCC Current
AVCC_L + AVCC_R + AVCC
-∞ dBFS (PCM, No signal)
IAVCC
IDVDDIO
IDVDD1
IDVDD2
-
-
-
-
30.5
10
45.0
100
20
mA
μA
DVDDIO Current
DVDD Current 1
DVDD Current 2
-∞ dBFS (PCM, No signal)
-∞ dBFS (PCM, No signal)
0 dBFS, fs = 44.1 kHz
10
mA
mA
11
22
0 dBFS, fs = 96 kHz, (30h) =
02h, (31h) = 01h, (40h) = 11h,
MCLK = 24.5760 MHz
0 dBFS, fs = 192 kHz, (30h) =
04h, (31h) = 02h, (40h) = 11h,
MCLK = 24.5760 MHz
0 dBFS, fs = 384 kHz, (30h) =
08h, (31h) = 00h, (40h) = 11h,
MCLK = 24.5760 MHz
DVDD Current 3
DVDD Current 4
DVDD Current 5
IDVDD3
IDVDD4
IDVDD5
-
-
-
18
17
10
36
34
20
mA
mA
mA
0 dBFS, fs = 44.1 kHz, (30h) =
01h, (31h) = 00h, (40h) = 11h,
MCLK = 22.5792 MHz
DVDD Current 6
IDVDD6
-
21
42
mA
(Max DVDD current setting)
PCM AC Characteristics
SNR
20-kHz AES17 LPF
+ A-weight
20-kHz AES17 LPF,
-3 dBFS
20-kHz AES17 LPF
+ A-weight, -60 dBFS
0 dBFS,
20-kHz AES17 LPF
-∞ dBFS (No signal),
Bias current single output
SNR_P
THD_P
DR_P
GM_P
ICN_P
IPP_P
fs
126
-
130
-115
130
0
-
dB
dB
dB
dB
mA
THD+N
-100
-
Dynamic Range
Channel Gain Mismatch
Output Center Current
Peak Output Current
Sampling Frequency
Bit Length
126
-0.5
4.6
8.5
32.0
16
+0.5
6.0
5.3
9.8
44.1
-
11.1
768.0
32
mApp 0 dBFS, Current amplitude
kHz
Bit
Bit
IOUT
Output Center Current
Peak Output Current
t
Figure 4. Peak Output Current
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Datasheet
BD34301EKV
Electrical Characteristics - continued
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Input Signal Frequency = 1 kHz, 20-kHz AES17 LPF, Differential output (XLR) measurement
DSD Mode, fDSD = 5.6448 MHz, MCLK = 45.1584 MHz, Clock 2 (06h) = 01h, DSD Filter (16h) = 01h
Limit
Parameter
DSD AC Characteristics
SNR
Symbol
Unit
Conditions
Min
Typ
Max
20-kHz AES17 LPF
+ A-weight(Note 1)
20-kHz AES17LPF,
0 dBFS
20-kHz AES17 LPF
+ A-weight, -60 dBFS
SNR_D
THD_D
DR_D
ICN_D
115
-
125
-113
120
5.3
5.3
-
-
-103
-
dB
dB
dB
mA
THD+N
Dynamic Range
Output Center Current
Peak Output Current
DSD Clock
107
4.6
-∞ dBFS (No signal),
Bias current single output
6.0
IPP_D
4.6
6.0
mApp 0 dBFS, Current amplitude
MHz
fDSD
2.8224
22.5792
(Note 1) The silent input pattern of DSD data is a repetition of 5Ah.
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Datasheet
BD34301EKV
Measurement Circuit
AVCC_L
5.0 V
DVDDIO
3.3 V
DVDD
1.5 V
1500 pF
100 μF
0.1 μF
100 μF 100 μF
0.1 μF 0.1 μF
100 μF
100 μF
100 μF
100 μF
0.1 μF
100 μF
0.1 μF
100 μF
100 μF
1 kΩ
0.1 μF
64
0.1 μF 0.1 μF
63 59
61
0.1 μF 0.1 μF
2
7
9
17
15
11
50
48
53
55
58
56
44～47
1500 pF
Lch Out
Differential
IOUT_LP
IOUT_LN
51
52
BCLK/DSDCLK
12
Current
1 kΩ
Segment
AVCC
5.0 V
Over
Audio
LRCLK/DSD2
Sampling
Digital
FIR
PCM
100 μF
0.1 μF
ΔΣ
Modulator
13
Precision
APX555
AVCC
42
I/F
AVCC_L
5.0 V
100 μF
Audio
Function
Control
DIN/DSD1
I-V Translate Circuit
Filter
0.1 μF
14
VREF_L
43
41
EXT_RES_L
VREF
910 Ω
910 Ω
EXT_RES_R
40
AVCC_R
5.0 V
VREF_R
DSD
I/F
38
39
0.1 μF
100 μF
1500 pF
AGND
1 kΩ
IOUT_RP
IOUT_RN
30
29
Current
MCLK
60
2-wire
I/F
System
Control
Master
Clock
Segment
Rch Out
Differential
1500 pF
1 kΩ
8
10
16
18
19
20
21
3
4
5
6
31
33
28
0.1 μF
26
23
0.1 μF
25
1
34 ～ 37
0.1 μF 0.1 μF
DVDDIO
3.3 V
DVDDIO
3.3 V
100 μF
100 μF
100 μF
100 μF
I-V Translate Circuit
AVCC_R
5.0 V
(Note 1)
CPU
The written values of external parts are checked
by sound test. Changing these values can affect
the sound quality. Please check the sound when
the values are changed.
Figure 5. Measurement Circuit
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Datasheet
BD34301EKV
DC Characteristics
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
MCLK, DIN/DSD1,
LRCLK/DSD2,
0.8 x
DVDDIO
High Level Input Voltage
VIH
-
-
V
BCLK/DSDCLK, RESETB,
SCL, SDA, ADDR1, ADDR2
pin
0.2 x
DVDDIO
Low Level Input Voltage
VIL
-
-
-
V
MCLK, DIN/DSD1,
LRCLK/DSD2,
BCLK/DSDCLK, RESETB,
SCL, SDA pin
IIN1
-10
+10
μA
Input Leakage Current
IIN2
-500
-
-
-
+500
0.4
μA
V
ADDR1, ADDR2 pin
SDA pin, IO: 3 mA
Low Level Output Voltage
VOL
MCLK/DSDCLK,
DIN/DSD1,
LRCLK/DSD2,
RESETB,
80%
20%
VIH
VIL
SDA
0.4 V
VOL
ADDR1, ADDR2,
SCL, SDA
Figure 6. High/Low Level Specifications
AC Characteristics (MCLK, RESETB)
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Limit
Parameter
Symbol
fMCLK
tMCH
Unit
MHz
ns
Conditions
Min
Typ
Max
MCLK Frequency
2.8224
-
49.1520
MCLK “H” Length
MCLK “L” Length
MCLK Duty
8.1
8.1
40
1
-
-
-
-
tMCL
ns
DUTYM
tRST
50
-
60
-
%
tMCH / (tMCH + tMCL)
RESETB Pulse Width
μs
tMCL tMCH
MCLK
tRST
1 / fMCLK
RESETB
Figure 7. Timing Specifications of MCLK
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Datasheet
BD34301EKV
AC Characteristics (PCM Mode)
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
LRCLK Frequency
fLRC
tLRH
32
-
768
kHz
ns
fLRC = fs
LRCLK Hold Time
LRCLK Setup Time
LRCLK Duty
8.1
8.1
40
-
-
-
tLRSU
DUTYL
fBC
-
ns
50
-
60
%
BCLK Frequency
BCLK “H” Length
BCLK “L” Length
BCLK Duty
2.048
8.1
8.1
40
49.152
MHz
ns
fBC = 64 fLRC
tBCH
-
-
-
tBCL
-
ns
DUTYB
tDINS
tDINH
50
-
60
-
%
tBCH / (tBCH + tBCL)
DIN Setup Time
DIN Hold Time
8.1
8.1
ns
-
-
ns
1 / fLRC
LRCLK
BCLK
DIN
tLRH tLRSU
tBCL tBCH
tDINS tDINH
1/fBC
Figure 8. Timing Specifications of I2S
AC Characteristics (DSD Mode)
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Limit
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
DSDCLK Frequency
fDSD
DUTYD
tDCH
2.8224
-
22.5792
MHz
%
DSDCLK Duty
40
50
-
60
-
tDCH / (tDCH + tDCL
)
DSDCLK “H” Length
DSDCLK “L” Length
DSD data Setup Time
DSD data Hold Time
17.7
17.7
17.7
17.7
ns
tDCL
-
-
ns
tDSDS
tDSDH
-
-
ns
-
-
ns
DSD1 data and DSD2 data are output from Lch and Rch respectively.
tDCL tDCH
DSDCLK
tDSDS tDSDH
1 / fDSD
DSD1
DSD2
Figure 9. Timing Specifications of DSD
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Datasheet
BD34301EKV
AC Characteristics (2-wire I/F)
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V
Limit
Parameter
Symbol
fSCL
Unit
kHz
μs
Min
-
Max
400
SCL Clock Frequency
Bus Free Time between a STOP and START Condition
Hold Time (Repeated) START Condition
LOW Period of the SCL Clock
tBUF
0.8
0.4
0.8
0.4
0.4
0
-
-
-
-
-
-
-
-
tHD_STA
tLOW
μs
μs
HIGH Period of the SCL Cock
tHIGH
μs
Setup Time for a Repeated START Condition
Data Hold Time
tSU_STA
tHD_DAT
tSU_DAT
tSU_STO
μs
μs
Data Setup Time
100
0.4
Ns
Μs
Setup Time for STOP Condition
tBUF
SDA
tHD_STA
tHD_STA
tSU_STO
tSU_DAT
tSU_STA
tHD_DAT
SCL
tLOW
tHIGH
STOP
START
RE-START
STOP
Figure 10. Timing Specifications of 2-wire I/F
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Datasheet
BD34301EKV
Typical Performance Curves
Unless otherwise specified Ta = 25 °C, AVCC = 5.0 V, DVDDIO = 3.3 V, DVDD = 1.5 V, Input signal frequency = 1 kHz,
20-kHz AES17 LPF, Differential output (XLR) measurement, PCM Mode, 24-bit I2S input, fs = 44.1 kHz,
MCLK = 11.2896 MHz, Clock 2 (06h) = 01h, FIR Filter 1 (30h) = 01h, FIR Filter 2 (31h) = 80h, Delta Sigma (40h) = 00h
0
-20
0
-20
Input Level = -∞ dBFS
-40
-60
-40
-80
-60
-100
-120
-140
-160
-180
-80
-100
-120
-100 -90 -80 -70 -60 -50 -40 -30 -20 -10
0
100
1k
10k
Input Level [dBFS]
Frequency [Hz]
Figure 11. THD+N vs Input Level
Figure 12. Amplitude vs Frequency
(External LPF: AUX-0025 (Audio Precision))
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Datasheet
BD34301EKV
2-wire I/F
Format
Device address and 1 byte of register address are sent in data write-in and data read-out.
The format of 2-wire I/F slave mode is shown below.
MSB
LSB
MSB
LSB
MSB
LSB
S
Device Address
A
Register Address
A
Data
A
P
Figure 13. 2-wire I/F Transmission Format
S
:
:
:
START Condition
Device Address of 8-bit data (MSB first)
Acknowledge. Acknowledge bit is added to send and receive data every byte.
When the correct data is sent and received, acknowledge is “L”.
In the case of “H”, there is no acknowledge.
Register Address of 8-bit data (MSB first)
Device Address
A
Register Address :
Data
P
:
:
Write-in or Read-out data of 8-bit (MSB first)
STOP Condition
START and STOP Conditions
MSB
D7
LSB
D0
SDA
D6
D5
D1
A
"H" during command
is not transmitting.
"H" during command
is not transmitting.
SCL
START Condition
When SCL = "H" and SDA↓
STOP Condition
When SCL = "H" and SDA↑
Figure 14. START and STOP Specifications
Device Address
The format of Device Address is shown below.
Four Device Addresses are selectable by setting of the ADDR1 and the ADDR2 pins
R/W bit is the mode setting of Write-in (R/W = 0) or Read-out (R/W = 1).
MSB
LSB
D0
D7
D6
0
D5
1
D4
1
D3
1
D2
D1
0
ADDR2 ADDR1
R/W
Figure 15. Device Address Data Format
The pins setting of Device Address are shown below.
Table 2. Pin Setting of Device Address
Pin Setting Device Address
Write-in
(R/W = 0)
Read-out
(R/W = 1)
ADDR2
ADDR1
L
L
L
H
L
38h
39h
3Bh
3Dh
3Fh
3Ah
H
H
3Ch
H
3Eh
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Datasheet
BD34301EKV
2-wire I/F - continued
Write Operation
In case of write-in, after sending a device address and a register address, send write data. Auto incremental function allows
consecutive data transmission. In case of forwarding data, repeat Step 6 to 7 of below table so that address will automatically
be +1. When the register address reaches FFh, it does not increase and repeats FFh. In the example shown below, N
consecutive registers from 20h are written.
Device
Address
38h
Register
Address
20h
S
A
A
Data 1
01h
A
…
A
Data N
EFh
A
P
Ex.
: from Master to Slave,
: from Slave to Master
Figure 16. Data Write-in format
Table 3. Write Operation Sequence
Slave
Step
Bit
Master
Note
38h, 3Ah, 3Ch or 3Eh
Register Address 8-bit
Write Data 8-bit
1
2
3
4
5
6
7
8
START Condition
Device Address
8
1
8
1
8
1
Acknowledge
Acknowledge
Acknowledge
Register Address
Write-in Data
STOP Condition
Read Operation
In case of read-out, at first send device address and a register address. Next send device address again and data is read.
Acknowledge should not be returned after finishing the command. Auto incremental function allows consecutive data
transmission. In case of forwarding consecutive data, repeat Step 9 to 10 of below table so that address will automatically be
+1. When the register address reaches FFh, it does not increase and repeats FFh. In the example shown below, N
consecutive registers from 30h are read.
Device
Address
38h
Register
Address
30h
S
A
A
A
A
Ex.
Device
Address
S
Data 1
Data 2
A
…
A
Data N
Ā
P
Ex.
39h
: from Master to Slave,
: from Slave to Master, A : Acknowledge, Ā : No acknowledge
Figure 17. Data Read-out format
Table 4. Read Operation Sequence
Step
1
Bit
Master
Slave
Note
START Condition
Device Address
2
7
1
8
1
1
8
1
8
1
38h, 3Ah, 3Ch or 3Eh
3
Acknowledge
Acknowledge
4
Register Address
5
6
START Condition
Device Address
7
39h, 3Bh, 3Dh or 3Fh
8
Acknowledge
Read-out Data
9
10
11
Acknowledge
STOP Condition
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Datasheet
BD34301EKV
Register Map
Do not change the setting which 0 or 1 is assigned in register map. Otherwise, normal operation is not guaranteed.
Add
ress
Register Name
R/W Initial
D7
D6
D5
D4
D3
D2
D1
D0
00h
01h
02h
03h
04h
05h
06h
07h
08h
↓
Software Reset
Chip Version
Digital Power
Analog Power
Clock 1
R/W
R
00h
01h
00h
00h
00h
00h
00h
04h
00h
00h
00h
0
0
0
0
0
0
0
SoftRst_X
01h
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
DigPon
AnaPon
MclkDiv[1:0]
(Reserved)
Clock 2
0
0
0
0
0
0
0
PhaseAdj
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
0
0
0
0Fh
DsdMute
Mode
10h
Audio I/F 1
R/W
0Bh
DsdOn
0
0
Fmt[1:0]
WLen[1:0]
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
↓
(Reserved)
Audio I/F 2
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
02h
00h
00h
11h
00h
00h
00h
48h
00h
00h
00h
00h
00h
08h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
00h
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
MonoSel[1:0]
Audio I/F 3
0
OutPol2
0
LrSwap
OutPol1
0
Audio Output Polarity
(Reserved)
DSD Filter
DsdFilter[1:0]
Audio Input Polarity
(Reserved)
InPol2
InPol1
0
0
0
0
0
0
1
0
0
0
(Reserved)
(Reserved)
(Reserved)
1Fh
20h
21h
22h
23h
↓
(Reserved)
Volume Transition Time
Volume 1
VolTranTime[3:0]
Vol1[7:0]
Vol2[7:0]
Volume 2
(Reserved)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
(Reserved)
0
28h
29h
2Ah
2Bh
↓
(Reserved)
0
Mute Transition Time
Mute
0
MuteTranTime[3:0]
0
0
0
0
0
0
0
0
0
0
0
Mute2_X
Mute1_X
(Reserved)
0
0
0
0
0
0
0
0
0
(Reserved)
0
2Eh
2Fh
30h
31h
32h
33h
34h
35h
↓
(Reserved)
0
RamClr
RAM Clear
FIR Filter 1
0
FirAlgo[3:0]
FIR Filter 2
(Reserved)
De-Emphasis 1
De-Emphasis 2
(Reserved)
(Reserved)
(Reserved)
Delta Sigma
Setting 1
HpcMode
0
0
0
0
0
0
0
0
FirCoef[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DempFs[1:0]
Demp2
Demp1
0
0
0
0
0
0
3Fh
40h
41h
42h
43h
44h
↓
DsSetting
Setting1[7:0]
DsOsr[1:0]
Setting 2
Setting2[7:0]
Setting3[7:0]
Setting 3
(Reserved)
(Reserved)
(Reserved)
Setting 4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
47h
48h
49h
↓
Setting4[7:0]
(Reserved)
(Reserved)
(Reserved)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5Fh
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Datasheet
BD34301EKV
Register Map - continued
Do not change the setting which 0 or 1 is assigned in register map. Otherwise, normal operation is not guaranteed.
Add
ress
Register Name
R/W Initial
D7
D6
D5
D4
Setting5[7:0]
Setting6[7:0]
D3
D2
D1
D0
60h
61h
62h
↓
Setting 5
Setting 6
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
00h
00h
00h
00h
00h
12h
00h
00h
00h
03h
00h
FFh
FFh
FFh
00h
00h
00h
02h
02h
02h
00h
00h
00h
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
1
0
1
1
1
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
0
67h
68h
69h
↓
A2h
A3h
A4h
A5h
A6h
A7h
A8h
↓
AFh
B0h
↓
B7h
B8h
↓
FFh
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Datasheet
BD34301EKV
Register Description
1. Address 00h (Software Reset)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
00h Software Reset R/W 00h
SoftRst_X
SoftRst_X: Software Reset Control
0
1
Software reset (All registers are not initialized) (default)
Normal operation
2. Address 01h (Chip Version)
Address
Register Name R/W Initial
D7
D6
D5
D4
D3
D2
D1
D0
01h
Chip Version
R
01h
ChipVer = 01h
ChipVer: Chip Version Register (Read only)
3. Address 02h (Digital Power)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
02h
Digital Power
R/W 00h
DigPon
DigPon: Digital Power Control
0
1
Power off and stop clock (default)
Power on and provide clock
4. Address 03h (Analog Power)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
03h
Analog Power R/W 00h
AnaPon
AnaPon: Analog Power Control
0
1
Power off (Current output off) (default)
Power on (Current output on)
5. Address 04h (Clock 1)
Address
Register Name R/W Initial
Clock 1 R/W 00h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
04h
MclkDiv[1:0]
MclkDiv[1:0]: MCLK Division Ratio Selection for Internal Clock
00 1 time (default)
01 2/3 times
10 1/2 times
11 1/3 times
There are some functions that cannot be used due to this setting. See the “System Clock” section for more details on
the available register combinations.
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Datasheet
BD34301EKV
Register Description - continued
6. Address 06h (Clock 2)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
06h
Clock 2
R/W 00h
PhaseAdj
PhaseAdj: Phase Adjustment Control for Internal Clock
0
1
Phase adjustment disabled (default)
Phase adjustment enabled
Audio characteristics may be improved.
Sound quality may be improved.
(DSD mode)
When this function is enabled, the frequency of MCLK must be twice of DSDCLK frequency.
See the “System Clock” section for the setting of MCLK frequency.
7. Address 10h (Audio I/F 1)
Address
Register Name R/W Initial
Audio I/F 1 R/W 0Bh
D7
D6
0
D5
0
D4
D3
D2
D1
D0
DsdMute
Mode
10h
DsdOn
Fmt[1:0]
WLen[1:0]
DsdOn: DSD Mode Selection
0
1
PCM mode (default)
DSD mode
DsdMuteMode: DSD Mute Enable (For DSD mode)
0
1
DSD Mute enabled (default)
DSD Mute disabled
Controlled by the setting of Mute (2Ah[1:0]).
Not be muted even if Mute (2Ah[1:0]) on.
Fmt[1:0]: Audio Data Input Format (For PCM mode)
00 Right justified
01 Left justified
10 I2S (default)
11 Prohibition
WLen[1:0]: Audio Data Input Bit Length (For PCM mode)
00 16-bit
01 20-bit
10 24-bit
11 32-bit (default)
Right Justified
1/fs
LRCLK
Left Channel
Rch Channel
BCLK
(64 fs)
MSB
LSB MSB
LSB
WLen = 32-bit
DIN
0
0
0
0
31 30
1
1
1
1
0
31 30
1
1
1
1
0
31 30
･･･…･･･････････････････････････････････
･･･…･･･････････････････････････････････
MSB
LSB
MSB
LSB
WLen = 24-bit
DIN
23 22
0
23 22
0
･･････････････････････
･･････････････････････
MSB
LSB
MSB
LSB
WLen = 20-bit
DIN
19 18
0
19 18
0
･････････････
･････････････
MSB
MSB
LSB
LSB
Wlen = 16-bit
DIN
15 14
0
15 14
0
･･･
･･･
Figure 18. Audio Data Input Format: Right Justified
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Datasheet
BD34301EKV
Address 10h (Audio I/F 1) - continued
Left Justified
1/fs
LRCLK
Left Channel
Rch Channel
BCLK
(64 fs)
MSB
LSB MSB
LSB
WLen = 32-bit
DIN
0
31 30
1
0
31 30
1
0
31 30
23 22
19 18
15 14
･･･…･･･････････････････････････････････
･･･…･･･････････････････････････････････
MSB
LSB
MSB
LSB
WLen = 24-bit
DIN
23 22
1
0
23 22
1
0
･･････････････････････
･･････････････････････
MSB
LSB
MSB
LSB
WLen = 20-bit
DIN
19 18
1
0
19 18
1
0
･････････････
･････････････
MSB
MSB
LSB
LSB
Wlen = 16-bit
DIN
15 14
1
0
15
14
1
0
･･･
･･･
Figure 19. Audio Data Input Format: Left Justified
I2S
1/fs
LRCLK
Left Channel
Rch Channel
BCLK
(64 fs)
MSB
LSB MSB
LSB
WLen = 32-bit
DIN
1
0
31 30
1
0
31 30
1
0
31
23
19
15
･･･…･･･････････････････････････････････
･･･…･･･････････････････････････････････
MSB
LSB
MSB
LSB
WLen = 24-bit
DIN
23 22
1
0
23 22
1
0
･･････････････････････
･･････････････････････
MSB
LSB
MSB
LSB
WLen = 20-bit
DIN
19 18
1
0
19 18
1
0
･････････････
･････････････
MSB
MSB
LSB
LSB
Wlen = 16-bit
DIN
15 14
1
0
15
14
1
0
･･･
･･･
Figure 20. Audio Data Input Format: I2S
8. Address 12h (Audio I/F 2)
Address
Register Name R/W Initial
Audio I/F 2 R/W 00h
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
12h
0
0
MonoSel[1:0]
MonoSel[1:0]: Monaural Mode Selection(Note 1)
Table 5. Stereo/Monaural Mode Settings for PCM Mode
MonoSel[1:0]
Mode
Lch output
Lch input
Rch output
Rch input
(default)
00
01
10
11
Stereo mode
Mixing mode
Mono mode Lch
Mono mode Rch
(Lch input + Rch input)/2
Lch input
Rch input
Table 6. Stereo/Monaural Mode Settings for PCM Mode
MonoSel[1:0]
Mode
Lch output
Lch input
Lch input
Rch output
Rch input
Rch input
00
01
10
11
Stereo mode
Stereo mode
Mono mode Lch
Mono mode Rch
(default)
Lch input
Rch input
(Note 1) This is the function of Audio Function Control bock in the “Block Diagram”.
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Datasheet
BD34301EKV
Register Description - continued
9. Address 13h (Audio I/F 3)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
0
D0
13h
Audio I/F 3
R/W 00h
LrSwap
LrSwap: Audio Data Swap Control(Note 1)
Table 7. LR Swap Setting
Lch output
LrSwap
Rch output
Rch input
Lch input
(default)
0
1
Lch input
Rch input
10. Address 14h (Audio Output Polarity)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
Audio Output
14h
R/W 00h
OutPol2 OutPol1
Polarity
OutPol1: Polarity Inversion Control for Lch(Note 2)
0
1
Normal (default)
Polarity inversion
OutPol2: Polarity Inversion Control for Rch(Note 2)
0
1
Normal (default)
Polarity inversion
11. Address 16h (DSD Filter)
Address
Register Name R/W Initial
DSD Filter R/W 00h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
16h
DsdFilter[1:0]
DsdFilter[1:0]: DSD Filter Selection. (For DSD mode)
Table 8. Cut Off Frequency of DSD Filter
Cut Off Frequency
DsdFilter
[1:0]
DSD 2.8 MHz
13 kHz
DSD 5.6 MHz
26 kHz
DSD 11.2 MHz
52 kHz
DSD 22.4 MHz
104 kHz
00
01
10
11
26 kHz
52 kHz
104 kHz
208 kHz
(default)
52 kHz
104 kHz
208 kHz
416 kHz
Prohibition
(Note 1) This is the function of Audio Function Control bock in the “Block Diagram”.
(Note 2) This is the function of ΔΣ Modulator bock in the “Block Diagram”.
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Datasheet
BD34301EKV
Register Description - continued
12. Address 17h (Audio Input Polarity)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
Audio Input
17h
R/W 00h
InPol2
InPol1
Polarity
InPol1: Polarity Inversion Control for Lch(Note 1)
0
1
Normal (default)
Polarity inversion
InPol2: Polarity Inversion Control for Rch(Note 1)
0
1
Normal (default)
Polarity inversion
13. Address 20h (Volume Transition Time)
Address
Register Name R/W Initial
D7
0
D6
1
D5
0
D4
0
D3
D2
D1
D0
Volume Transition
20h
R/W 48h
VolTranTime[3:0]
Time
VolTranTime[3:0]: Volume Transition Time Selection (For PCM mode)
The table below shows the volume transition time when the gain is switched from 0 dB to -∞ dB. The volume transition
time depends on the difference between target volume and current volume. For example, the volume transition time
when the gain is switched from 0 dB to -6 dB is half the time in the table below.
Table 9. Volume Transition Time
Transition Time (ms)
VolTran
Time[3:0]
Transition
Time
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
384 kHz
768 kHz
0
0h
1h - 7h
8h
0
Prohibition
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
32768/fs
65536/fs
Prohibition
10.7
(default)
32.0
64.0
128
23.2
46.4
92.9
186
21.3
42.7
85.3
171
5.33
10.7
21.3
42.7
85.3
171
2.67
5.33
10.7
21.3
42.7
85.3
171
1.33
2.67
5.33
10.7
21.3
42.7
85.3
9h
21.3
Ah
42.7
Bh
256
85.3
Ch
512
372
341
171
Dh
1024
2048
743
683
341
Eh
1486
1365
683
341
(Note 1) This is the function of Audio Function Control bock in the “Block Diagram”.
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Datasheet
BD34301EKV
Register Description - continued
14. Address 21h, 22h (Volume 1, Volume 2)
Address
Register Name R/W Initial
D7
D6
D5
D4
Vol1[7:0]
Vol2[7:0]
D3
D2
D1
D0
21h
22h
Volume 1
Volume 2
R/W 00h
R/W 00h
Vol1[7:0]: Digital Volume (Attenuation Level) Setting for Lch. (For PCM mode)
0 dB (00h, default) to -110.0 dB (DCh), -∞ dB (FFh)
0.5 dB step
In Mono mode, both Lch and Rch are controlled by Vol1[7:0].
Vol2[7:0]: Digital Volume (Attenuation Level) Setting for Rch (For PCM mode)
0 dB (00h, default) to -110.0 dB (DCh), -∞ dB (FFh)
0.5 dB step
In Mono mode, Vol2[7:0] is not used.
Table 10. Digital Volume (Attenuation Level) Setting
Setting
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
Gain[dB]
0.0
Setting
20h
21h
22h
23h
24h
25h
26h
27h
28h
29h
2Ah
2Bh
2Ch
2Dh
2Eh
2Fh
30h
31h
32h
33h
34h
35h
Gain[dB]
-16.0
-16.5
-17.0
-17.5
-18.0
-18.5
-19.0
-19.5
-20.0
-20.5
-21.0
-21.5
-22.0
-22.5
-23.0
-23.5
-24.0
-24.5
-25.0
-25.5
-26.0
-26.5
Setting
40h
41h
42h
43h
44h
45h
46h
47h
48h
49h
4Ah
4Bh
4Ch
4Dh
4Eh
4Fh
50h
51h
52h
53h
54h
55h
Gain[dB]
-32.0
-32.5
-33.0
-33.5
-34.0
-34.5
-35.0
-35.5
-36.0
-36.5
-37.0
-37.5
-38.0
-38.5
-39.0
-39.5
-40.0
-40.5
-41.0
-41.5
-42.0
-42.5
Setting
60h
61h
62h
63h
64h
65h
66h
67h
68h
69h
6Ah
6Bh
6Ch
6Dh
6Eh
6Fh
70h
71h
72h
73h
74h
75h
Gain[dB]
-48.0
-48.5
-49.0
-49.5
-50.0
-50.5
-51.0
-51.5
-52.0
-52.5
-53.0
-53.5
-54.0
-54.5
-55.0
-55.5
-56.0
-56.5
-57.0
-57.5
-58.0
-58.5
Setting
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
Gain[dB]
-64.0
-64.5
-65.0
-65.5
-66.0
-66.5
-67.0
-67.5
-68.0
-68.5
-69.0
-69.5
-70.0
-70.5
-71.0
-71.5
-72.0
-72.5
-73.0
-73.5
-74.0
-74.5
Setting
A0h
A1h
A2h
A3h
A4h
A5h
A6h
A7h
A8h
A9h
AAh
ABh
ACh
ADh
AEh
AFh
B0h
B1h
B2h
B3h
B4h
B5h
Gain[dB]
-80.0
-80.5
-81.0
-81.5
-82.0
-82.5
-83.0
-83.5
-84.0
-84.5
-85.0
-85.5
-86.0
-86.5
-87.0
-87.5
-88.0
-88.5
-89.0
-89.5
-90.0
-90.5
Setting
C0h
C1h
C2h
C3h
C4h
C5h
C6h
C7h
C8h
C9h
CAh
CBh
CCh
CDh
CEh
CFh
D0h
D1h
D2h
D3h
D4h
D5h
Gain[dB]
-96.0
-0.5
-1.0
-1.5
-2.0
-2.5
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
-8.0
-8.5
-9.0
-9.5
-10.0
-10.5
-96.5
-97.0
-97.5
-98.0
-98.5
-99.0
-99.5
-100.0
-100.5
-101.0
-101.5
-102.0
-102.5
-103.0
-103.5
-104.0
-104.5
-105.0
-105.5
-106.0
-106.5
16h
17h
18h
19h
1Ah
-11.0
-11.5
-12.0
-12.5
-13.0
36h
37h
38h
39h
3Ah
-27.0
-27.5
-28.0
-28.5
-29.0
56h
57h
58h
59h
5Ah
-43.0
-43.5
-44.0
-44.5
-45.0
76h
77h
78h
79h
7Ah
-59.0
-59.5
-60.0
-60.5
-61.0
96h
97h
98h
99h
9Ah
-75.0
-75.5
-76.0
-76.5
-77.0
B6h
B7h
B8h
B9h
BAh
-91.0
-91.5
-92.0
-92.5
-93.0
D6h
D7h
D8h
D9h
DAh
-107.0
-107.5
-108.0
-108.5
-109.0
1Bh
1Ch
1Dh
1Eh
1Fh
-13.5
-14.0
-14.5
-15.0
-15.5
3Bh
3Ch
3Dh
3Eh
3Fh
-29.5
-30.0
-30.5
-31.0
-31.5
5Bh
5Ch
5Dh
5Eh
5Fh
-45.5
-46.0
-46.5
-47.0
-47.5
7Bh
7Ch
7Dh
7Eh
7Fh
-61.5
-62.0
-62.5
-63.0
-63.5
9Bh
9Ch
9Dh
9Eh
9Fh
-77.5
-78.0
-78.5
-79.0
-79.5
BBh
BCh
BDh
BEh
BFh
-93.5
-94.0
-94.5
-95.0
-95.5
DBh
DCh
DDh
-109.5
-110.0
prohibition
prohibition
prohibition
-∞
↓
FEh
FFh
Example of Volume Switching (fs = 44.1 kHz)
In case of setting VolTranTime (20h[3:0]) = 8h (1024/fs), Vol1 (21h[7:0]) = -∞ dB (FFh), 0 dB (00h)
Vol1
= -∞ dB
VolTranTime
= 1024/fs
Vol1
= 0 dB
2-wire I/F
(SDA, SCL)
(20h)
48h
(21h)
FFh
(21h)
00h
1024/fs = 23.2 ms
1024/fs = 23.2 ms
0 dB
0 dB
-∞ dB
IOUT_L
Figure 21. Example of Volume Switching
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BD34301EKV
Register Description - continued
15. Address 29h (Mute Transition Time)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
D2
D1
D0
Mute Transition
29h
R/W 48h
MuteTranTime[3:0]
Time
MuteTranTime[3:0]: Mute Transition Time Selection (For PCM mode)
The table blow shows the transition time when muting from 0 dB to -∞ dB.
If the setting time is short, pop noise may occur. Please evaluate it carefully before determining the setting value.
Table 11. Mute Transition Time in PCM Mode
Transition Time (ms)
MuteTran
Time[3:0]
Transition
Time
32 kHz
44.1 kHz
48 kHz
96 kHz
192 kHz
384 kHz
768 kHz
0
0h
1h - 7h
8h
0
Prohibition
1024/fs
2048/fs
4096/fs
8192/fs
16384/fs
32768/fs
65536/fs
Prohibition
10.7
(default)
32
64
23.2
46.4
92.9
186
21.3
42.7
85.3
171
5.33
10.7
21.3
42.7
85.3
171
2.67
5.33
10.7
21.3
42.7
85.3
171
1.33
2.67
5.33
10.7
21.3
42.7
85.3
9h
21.3
Ah
128
256
512
1024
2048
42.7
Bh
85.3
Ch
372
341
171
Dh
743
683
341
Eh
1486
1365
683
341
Table 12. Mute Transition Time in DSD Mode
Transition Time (ms)
MuteTran
Time[3:0]
2.8224
MHz
5.6448
MHz
11.2896
MHz
22.5792
MHz
0
0h
1h - 7h
8h
Prohibition
(default)
17.41
34.83
8.71
4.35
8.71
2.18
4.35
9h
17.41
34.83
Ah
69.66
17.41
34.83
69.66
139.32
278.64
557.28
8.71
Bh
139.32
278.64
557.28
1114.56
2229.12
69.66
17.41
34.83
69.66
139.32
278.64
Ch
139.32
278.64
557.28
1114.56
Dh
Eh
Fh
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BD34301EKV
Register Description - continued
16. Address 2Ah (Mute)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
2Ah
Mute
R/W 00h
Mute2_X Mute1_X
Mute1_X: Digital Mute Control for Lch
0
1
Mute on (default)
Mute off
Mute2_X: Digital Mute Control for Rch
0
1
Mute on (default)
Mute off
Example of Mute switching (fs = 44.1 kHz)
In case of setting MuteTranTime (29h[3:0]) = 8h (1024/fs), Mute (2Ah[1:0])= On (3h), Off (0h)
MuteTranTime
= 1024/fs
Mute Off
Mute On
2-wire I/F
(SDA, SCL)
(29h)
08h
(2Ah)
03h
(2Ah)
00h
1024/fs = 23.2 ms
1024/fs = 23.2 ms
0 dB
IOUT_L
IOUT_R
-∞ dB
-∞ dB
Figure 22. Example of Mute On/Off
17. Address 2Fh (RAM Clear)
Address
Register Name R/W Initial
RAM Clear R/W 00h
D7
D6
0
D5
0
D4
0
D3
D2
0
D1
0
D0
0
2Fh
RamClr
0
RamClr: RAM Clear and Initialization Control (For PCM mode)
0
1
RAM clear off (default)
RAM clear on
It is necessary to turn RAM clear on and off when changing the clock and filter settings.
See the “Mode Switching Sequence” section for more details.
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BD34301EKV
Register Description - continued
18. Address 30h, 31h (FIR Filter 1, FIR Filter 2)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
0
D3
0
D2
FirAlgo[3:0]
FirCoef[2:0]
D1
D0
30h
31h
FIR Filter 1
FIR Filter 2
R/W 00h
R/W 00h HpcMode
0
0
0
FirAlgo[3:0]: FIR Calculation Algorithm Selection (For PCM mode)
FirCoef[2:0]: FIR Coefficient Selection (For PCM mode)
Pleases set the FIR filter according to the table below. The frequency responses are shown in “Frequency Response
of FIR Filter" section.
When changing the filter settings, it is necessary to execute the mode switching sequence. The filter settings are
reflected when RAM clear in the mode switching sequence is executed. See the “Mode Switching Sequence” section
for more details
Table 13. FIR Filter Setting
FirAlgo[3:0]
0h
FirCoef[2:0]
fs
-
Filter Setting
FIR Stop (-∞ dB Output)
Sharp Roll-Off
Slow Roll-Off
(default)
0h
0h
3h
1h
4h
2h
5h
32 kHz,
44.1 kHz,
48 kHz
1h
2h
4h
Sharp Roll-Off
Slow Roll-Off
88.2 kHz,
96 kHz
Sharp Roll-Off
Slow Roll-Off
176.4 kHz,
192 kHz
362.8 kHz,
384 kHz
705.6 kHz,
768 kHz
8h
0h
FIR Bypass
Others
Prohibition
HpcMode: High Precision Calculation Mode Control (For PCM mode)
0
1
High precision calculation on (default)
High precision calculation off
Sound quality and audio characteristics can be adjusted with this set up. Please note that when high precision
calculation is turned on, the DVDD operating current also increases as the amount of calculation increases
accordingly. In case of fs = 705.6 kHz / 768 kHz or MCLK division ratio (MclkDiv (04h[1:0])) = 10 or 11, this function is
not available and must be turned off. See the “System Clock” section for more details on the available register
combinations.
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BD34301EKV
Address 30h, 31h (FIR Filter 1, FIR Filter 2) - continued
Frequency Response of FIR Filter
Sharp Roll-Off Filter
0
-50
0
-1.0 dB @ 0.454 fs
-50
-100
-150
-200
-250
-0.06 dB @ 0.454 fs
-100
-150
-200
-250
fs = 44.1 kHz
Group Delay = 36/fs
fs = 96 kHz
Group Delay = 24/fs
0
20
40
60
80
0
10
20
Frequency [kHz]
Figure 23. Gain vs Frequency
30
40
Frequency [kHz]
Figure 24. Gain vs Frequency
0
-50
-1.0 dB @ 0.454 fs
-100
-150
-200
-250
fs = 192 kHz
Group Delay = 24/fs
0
40
80
120
160
Frequency [kHz]
Figure 25. Gain vs Frequency
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Address 30h, 31h (FIR Filter 1, FIR Filter 2) - continued
Frequency Response of FIR Filter
Slow Roll-Off Filter
0
0
-50
-3.5 dB @ 0.454 fs
-3.5 dB @ 0.454 fs
-50
-100
-100
-150
-200
-150
fs = 96 kHz
Group Delay = 20/fs
fs = 44.1 kHz
Group Delay = 36/fs
-200
0
20
40
60
80
0
10
20
30
40
Frequency [kHz]
Frequency [kHz]
Figure 26. Gain vs Frequency
Figure 27. Gain vs Frequency
0
-50
-3.5 dB @ 0.454 fs
-100
-150
-200
fs = 192 kHz
Group Delay = 20/fs
0
40
80
Frequency [kHz]
Figure 28. Gain vs Frequency
120
160
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Register Description - continued
19. Address 33h, 34h (De-Emphasis 1, De-Emphasis 2)
Address
Register Name R/W Initial
33h De-Emphasis 1 R/W 00h
34h De-Emphasis 2 R/W 00h
D7
0
D6
0
D5
0
D4
0
D3
0
D2
0
D1
D0
DempFs[1:0]
0
0
0
0
0
0
Demp2 Demp1
DempFs[1:0]: Sampling Frequency Selection for De-Emphasis (For PCM mode)
This register is available when De-Emphasis is enabled by Demp1 / Demp2 setting.
00 Through (De-Emphasis is disabled) (default)
01 fs = 32 kHz
10 fs = 44.1 kHz
11 fs = 48 kHz
The frequency responses are shown in "Frequency Response of De-Emphasis Filter" section.
Demp1: De-Emphasis Control for Lch (For PCM mode)
0
1
De-Emphasis disabled (default)
De-Emphasis enabled
Demp2: De-Emphasis Control for Rch (For PCM mode)
0
1
De-Emphasis disabled (default)
De-Emphasis enabled
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Address 33h, 34h (De-Emphasis 1, De-Emphasis 2) - continued
Frequency Response of De-Emphasis Filter
2
0
2
0
-2
-4
-6
-8
-2
-4
-6
-8
fs = 44.1 kHz
fs = 32 kHz
-10
-10
-12
-12
0
2
4
6
8
10 12 14 16 18 20 22
0
2
4
6
8
10
12
14
16
Frequency [kHz]
Frequency [kHz]
Figure 29. Gain vs Frequency
Figure 30. Gain vs Frequency
2
0
-2
-4
-6
-8
fs = 48 kHz
-10
-12
0
2
4
6
8
10 12 14 16 18 20 22 24
Frequency [kHz]
Figure 31. Gain vs Frequency
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Register Description - continued
20. Address 40h (Delta Sigma)
Address
Register Name R/W Initial
D7
0
D6
0
D5
0
D4
D3
0
D2
0
D1
D0
40h
Delta Sigma
R/W 00h
DsSetting
DsOsr[1:0]
DsSetting: ΔΣ Modulator Setting
DsOsr[1:0]: Oversampling Rate Selection for ΔΣ Modulator
(PCM mode)
The over sampling rate of ΔΣ Modulator can be changed. The sound quality and audio characteristics are adjustable
by this setting.
The setting of over sampling rate should be changed according to the MCLK division ratio setting. See the “System
Clock” section for more details on the available register combinations.
Table 14. Over Sampling Rate Setting of ΔΣ Modulator
DsSetting
DsOsr[1:0]
Over Sampling Rate
(default)
00
01
10
11
00
01
10
11
x8
x16
0
x32
Prohibition
x16
x32
1
Prohibition
Prohibition
(DSD mode)
In DSD mode, over sampling rate cannot be changed
Set DsSetting = 0, DsOsr[1:0] = 10.
21. Address 41h, 42h, 43h, 48h (Setting 1, Setting 2, Setting 3, Setting 4)
Address
Register Name R/W Initial
D7
D6
D5
D4
D3
D2
D1
D0
41h
42h
43h
48h
Setting 1
Setting 2
Setting 3
Setting 4
R/W 00h
R/W 00h
R/W 00h
R/W 00h
Setting1[7:0]
Setting2[7:0]
Setting3[7:0]
Setting4[7:0]
Setting1[7:0]
Setting2[7:0]
Setting3[7:0]
Setting4[7:0]
Set 00h
Set 34h
Set B8h
Set 0Dh
Set these registers in power-on sequence. See the "Power-On Sequence" section for more details.
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Register Description - continued
22. Address 60h, 61h (Setting 5, Setting 6)
Address
Register Name R/W Initial
D7
D6
D5
D4
D3
D2
D1
D0
60h
61h
Setting 5
Setting 6
R/W 00h
R/W 00h
Setting5[7:0]
Setting6[7:0]
Setting5[7:0]
Setting6[7:0]
In the case of PCM mode, set 16h.
In the case of DSD mode, set 9Eh
In the case of PCM mode, set 16h
In the case of DSD mode, set 1Eh
23. Address D0h, D3h (Boot 1, Boot 2)(Note 3)
Address
Register Name R/W Initial
D7
D6
D5
D4
Boot1[7:0]
Boot2[7:0]
D3
D2
D1
D0
D0h
D3h
Boot 1
R/W 00h
Boot 2
R/W 00h
(Note 3) These registers are not listed in the register map because they are used only in power-on sequence.
Boot1[7:0]
Boot2[7:0]
This register is used to prevent pop noise in power-on sequence.
This register is used to prevent pop noise in power-on sequence.
The operation to prevent pop noise is shown below and it is necessary to keep the order.
1. Boot1[7:0] (D0h) = 6Ah
2. Boot2[7:0] (D3h) = 10h
3. Boot2[7:0] (D3h) = 00h
4. Boot1[7:0] (D0h) = 00h
Please refer to the “Power-On Sequence” section for more details.
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BD34301EKV
System Clock
This section describes the system clock setting in PCM mode and DSD mode. When switching the system clock, it is
necessary to execute the mode switching sequence. See the “Mode Switching Sequence” section for more details and see
the “Recommended Settings” section for more details on recommended settings for each fs.
(PCM mode)
The system clocks required for PCM mode are MCLK, BCLK, and LRCLK. These clocks need to be synchronized but not in
phase. The frequency of MCLK should be 22.5792 MHz or 24.5760 MHz. When fs = 32 kHz / 44.1 kHz / 48 kHz, the frequency
of internal clock is lowered by MCLK division ratio setting (MclkDiv (04h[1:0]) = 10 (1/2 times) or 11 (1/3 times)). As a result,
DVDD operating current can be reduced. In this case, high precision calculation (HpcMode (31h[7])) function cannot be used
and over sampling rate setting of ΔΣ modulator (DsSetting (40h[4]), DsOsr (40h[1:0])) must be changed according to the
MCLK division ratio setting. The following table shows system clock frequency settings and available combinations of register
setting.
Table 15. System Clock Frequency Settings in PCM Mode
LRCLK
(kHz)
BCLK
(MHz)
MCLK
(MHz)
MclkDIv
(04h[1:0])
HpcMode
(31h[7])
DsSetting
(40h[4])
DsOsr
(40h[1:0])
00
x16
x32
x8
2/3
times
01
0/1
On/Off
1
0
1
0
01
00
01
10
00
01
00
01
10
00
01
00
01
00
01
00
01
32
2.0480
768 fs 24.5760
1/3
times
11
00
10
1
0/1
1
Off
x16
x32
x16
x32
x8
1
time
On/Off
Off
44.1
48
2.8224
3.0720
22.5792
512 fs
24.5760
1/2
times
x16
x32
x16
x32
x16
x32
x16
x32
x8
88.2
96
5.6448
6.1440
22.5792
256 fs
1
time
00
00
00
00
0/1
0/1
1
On/Off
On/Off
Off
1
1
1
0
24.5760
176.4
192
11.2896
12.2880
22.5792
128 fs
1
time
24.5760
352.8
384
22.5792
24.5760
22.5792
64 fs
1
time
24.5760
705.6
768
45.1584
49.1520
22.5792
32 fs
1
time
1
Off
24.5760
x16
(DSD mode)
The system clocks required for DSD mode are MCLK and DSDCLK. These system clocks need to be synchronized but not
in phase. The frequency of MCLK should be same as DSDCLK or double. When the phase adjustment function for internal
clock is enabled (PhaseAdj (06h [0]) = 1), the frequency of MCLK must be double DSDCLK. The following table shows system
clock frequency settings.
Table 16. System Clock Frequency Setting in DSD Mode
MCLK
(MHz)
DSDCLK
(MHz)
PhaseAdj (06h[0])
0
1
2.8224
5.6448
2.8224
5.6448
11.2896
22.5792
5.6448
11.2896
22.5792
45.1584
11.2896
22.5792
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BD34301EKV
Power-On Sequence
In the power-on sequence, the power supply is turned on in the order of DVDDIO, DVDD, and AVCC. After all power supply
turned on, MCLK inputting, hard reset releasing (RESETB), and register settings with 2-wire I / F must be done. In the power-
on sequence, initial setting must be done for all registers. Please execute the power-on sequence according to the following
register setting and “Timing Chart”. In case these sequences are not followed properly, normal operation cannot be
guaranteed.
Table 17. Register Settings in Power-On Sequence
Register
Address
Step
1
Operations
Initial Setting
Register Settings
04h
06h
10h
12h
13h
14h
16h
17h
20h
21h
22h
29h
30h
31h
33h
34h
40h
41h
42h
43h
48h
60h
61h
00h
02h
Clock 1
Clock 2
Audio I/F 1
Audio I/F 2
Audio I/F 3
Audio Output Polarity
DSD Filter
Audio Input Polarity
Volume Transition Time
Volume 1
Volume 2
Mute Transition Time
FIR Filter 1
FIR Filter 2
De-Emphasis 1
De-Emphasis 2
Delta Sigma
= 00h
= 34h
= B8h
= 0Dh
Setting 5
Setting 6
2
3
4
Software Reset Off
Digital Power On
= 01h
= 01h
Pop Nose Prevention
D0h
D3h
D3h
D0h
03h
2Fh
2Fh
2Ah
= 6Ah
= 10h
= 00h
= 00h
= 01h
= 80h
= 00h
= 03h
5
6
7
8
Analog Power On
RAM Clear On
RAM Clear Off
Mute Off
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Power-On Sequence - continued
Timing Chart
DVDDIO is risen up to 3 V or more.
DVDDIO
3.0 V
t1
DVDDIO1
DVDDIO2
DVDD is risen up to 1.4 V or more.
DVDD
1.4 V
(t2 – t1) ≥ 1 μs
DVDD1
DVDD2
t2
AVCC is risen up to 4.5 V or more.
AVCC
4.5 V
(t3 – t2) ≥ 1 μs
AVCC
AVCC_L(R)
AVCC1_L(R)
AVCC2_L(R)
AVCC3_L(R)
t3
MCLK
MCLK
(t4 – t3) ≥ 1 μs
DVDDIO
0.8 x DVDDIO
RESETB
0.2 x DVDDIO
t5
Pop Noise Privention
①
(t6 – t5) ≥ 1 μs
②
③
④
⑤
⑥
⑦
⑧
Mute
Off
t4
Sofware
Digital
Analog
RAM Clear RAM Clear
On Off
Reset Off Power On
Power On
2-wire I/F
(2Ah)
03h
Initial
Setting
(00h) (02h) (D0h) (D3h) (D3h) (D0h)
01h 01h 6Ah 10h 00h 00h
(03h)
01h
(2Fh) (2Fh)
80h 00h
SCL
SDA
t6
t7
(t8 – t7) ≥ 1 μs
t8
t9
t10
t11
t13
t14
t15
t16
t17
(t11 – t10) ≥ 10 μs
(t12 – t11) ≥ 0 μs
Audio Data
t12
-∞ dB Data
BCLK
LRCLK
DIN
Audio
Data
(t15 – t11) ≥ C(VREF) [μF] x 0.04
(4.0 s when C(VREF) = 100.1 μF)
Differential
Output
9.8 mApp
(PCM Mode,
0 dBFS, Typ)
5.3 mA (Typ)
Please set external mute.
(Note 1) C(VREF) is capacitance between VREF_L(R) and AVCC_L(R).
Please consider the variation and temperature characteristic of the capacitance.
(Note 2) RAM Clear on/off are necessary only for PCM Mode.
Mute Transition Time (29h)
Group Delay (30h, 31h)
(PCM Mode)
Figure 32. Power-On Sequence
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Power-Off Sequence
In the power-off sequence, the power supply must be tuned off after register setting shown in the table below. The power
supply should be turned off in the order of AVCC, DVDD, DVDDIO. Please execute the power-off sequence according to the
following register settings and “Timing Chart“. In case these sequences are not followed properly, normal operation cannot
be guaranteed.
Table 18. Register Settings in Power-Off Sequence
Register
Address
Step
Operations
Mute On
Register Settings
1
2
3
2Ah
= 00h
= 00h
= 00h
Analog Power Off
Digital Power Off
03h
02h
Timing Chart
DVDDIO is fallen down to 0.8 V or less.
DVDD is fallen down to 0.8 V or less.
AVCC is fallen down to 0.8 V or less.
DVDDIO
0.8 V
(t12 – t11) ≥ 1 μs
DVDDIO1
DVDDIO2
t12
DVDD
(t11 – t10) ≥ 1 μs
0.8 V
DVDD1
DVDD2
t11
AVCC
AVCC
AVCC_L(R)
AVCC1_L(R)
AVCC2_L(R)
AVCC3_L(R)
(t10 – t9) ≥ 1 μs
0.8 V
t10
MCLK
MCLK
t9
①
②
③
Digital
Power Off
(t9 – t8) ≥ 0 μs
Mute
On
Analog
Power Off
2-wire I/F
(03h)
00h
(02h)
00h
(2Ah)
00h
SCL
SDA
t1
t3
t4
t6
t7
(t6 – t5) ≥ 1 μs
Audio Data
BCLK
LRCLK
DIN
Audio Data
(t8 – t7) ≥ 0 μs
t8
(t5 – t4) ≥ 1 μs
Mute Transition Time (29h)
t2
t5
Differential
Output
5.3 mA (Typ)
Please set external mute.
9.8 mApp
(PCM Mode,
0 dBFS, Typ)
Figure 33. Power-Off Sequence
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Mode Switching Sequence
Mode switching means switching from PCM mode to DSD mode, switching from DSD mode to PCM mode, and change of
input signals (MCLK, BCLK / DSDCLK, LRCLK / DSD2, DSIN / DSD1) that accompany changes in sampling frequency in
each mode. These input signals must be switched during software reset is on (SoftRst_X (00h[0]) = 0).
Please execute the mode switching sequence according to the following register settings and timing charts. See the
“Recommended Settings” section for more details on recommended register settings.
Table 19. Register Settings in Mode Switching Sequence
Register
Address
PCM
Mode
DSD
Mode
Step
Operations
Mute On
Register Settings
1
2
3
4
2Ah
02h
00h
= 00h
= 00h
= 00h
○
○
○
○
○
○
Digital Power Off
Software Reset On
Mode Switching
04h
06h
10h
16h
30h
31h
40h
60h
61h
00h
02h
2Fh
2Fh
2Ah
Clock 1
Clock 2
○
○
○
-
○
○
○
○
-
Audio I/F 1
DSD Filter
FIR Filter 1
○
○
○
○
○
○
○
○
○
○
FIR Filter 2
-
Delta Sigma
○
○
○
○
○
-
Setting 5 = 16h (PCM) / 9Eh (DSD)
Setting 6 = 16h (PCM) / 1Eh (DSD)
5
6
7
8
9
Software Reset Off
Digital Power On
RAM Clear On
RAM Clear Off
Mute Off
= 01h
= 01h
= 80h
= 00h
= 03h
-
○
Caution: If mode switching sequence not be done according to the following timing charts, pop noise may occur.
In such cases, please set external mute in parallel.
Timing Chart
PCM Mode to DSD Mode
①
②
③
④
⑤
⑥
⑨
2-wire I/F
(SDA,SCL)
(2Ah)
00h
(02h) (00h)
00h 00h
(00h) (02h) (2Ah)
01h 01h 03h
Mode Switching
Mute
On
DigPon Software
Off Reset On
≥ 10 clocks
Software DigPon Mute
Reset Off On Off
≥ 10 clocks
Software Reset
MCLK
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
PCM Audio Data
PCM -∞ dB Data
DSD -∞ dB Data
DSD Audio Data
(Note 1) MCLK, BCLK ,LRCLK, DIN must be switched
during software reset is on (= "0")
IOUT_L
IOUT_R
Mute Transition Time (29h)
(PCM Mode)
Mute Transition Time (29h)
(DSD Mode)
Figure 34. Mode Switching Sequence from PCM Mode to DSD Mode
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Mode Switching Sequence - continued
DSD Mode to PCM Mode
①
②
③
④
⑤
⑥
⑦
⑧
⑨
2-wire I/F
(SDA,SCL)
(2Ah)
00h
(02h) (00h)
00h 00h
(00h) (02h) (2Fh) (2Fh) (2Ah)
01h 01h 80h 00h 03h
Mode Switching
Mute
On
DigPon Software
Off Reset On
≥ 10 clocks
Software DigPon RAM Clear Mute
Reset Off On On/Off Off
≥ 10 clocks
Software Reset
MCLK
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
DSD Audio Data
DSD -∞ dB Data
PCM -∞ dB Data
PCM Audio Data
Group Delay (30h, 31h)
(PCM Mode)
(Note 1) MCLK, BCLK ,LRCLK, DIN must be switched
during software reset is on (= "0")
IOUT_L
IOUT_R
Mute Transition Time (29h)
(DSD Mode)
Mute Transition Time (29h)
(PCM Mode)
Figure 35. Mode Switching Sequence from DSD Mode to PCM Mode
Mode Switching between PCM Modes
①
②
③
④
⑤
⑥
⑦
⑧
⑨
2-wire I/F
(SDA,SCL)
(2Ah)
00h
(02h) (00h)
00h 00h
(00h) (02h) (2Fh) (2Fh) (2Ah)
01h 01h 80h 00h 03h
Mode Switching
Mute
On
DigPon Software
Off Reset On
Software DigPon RAM Clear Mute
Reset Off On On/Off Off
≥ 10 clocks
≥ 10 clocks
MCLK
PCM Audio Data
PCM -∞ dB Data
PCM -∞ dB Data
PCM Audio Data
Group Delay (30h, 31h)
(PCM Mode)
(Note 1) MCLK, BCLK ,LRCLK, DIN must be switched
during software reset is on (= "0")
IOUT_L
IOUT_R
Mute Transition Time (29A)
(PCM Mode)
Mute Transition Time (29A)
(PCM Mode)
Figure 36. Mode Switching Sequence between PCM Modes
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Recommended Settings
The recommended settings shown in the tables below get a good balance between electrical characteristics and sound quality
for PCM mode and DSD mode.
Table 20. Recommended Settings in PCM Mode
44.1
48
88.2
96
176.4
192
362.8
384
705.6
768
fs (kHz)
32
22.5792
24.5760 24.5760
22.5792
24.5760
22.5792
24.5760
22.5792
24.5760
22.5792
24.5760
MCLK (MHz)
Address
04h
Register
Recommended Setting
00h
Clock 1
03h 02h
06h
Clock 2
00h
0Bh
10h
Audio I/F 1
FIR Filter 1
30h
01h
80h
83h
02h
02h
01h
04h
04h
02h
05h
11h
08h
80h
Sharp Roll-Off
Slow Roll-Off
31h
FIR Filter 2
40h
60h
61h
Delta Sigma
Setting 5
01h
16h
16h
Setting 6
Table 21. Recommended Settings in DSD Mode
DSDCLK (MHz)
MCLK (MHz)
2.8224
5.6448
11.2896
22.5792
= DSDCLK
Address
04h
Register
Recommended Setting
Clock 1
00h
00h
8Bh
06h
Clock 2
10h
Audio I/F 1
DSD Filter
Delta Sigma
Setting 5
16h
02h
01h
00h
40h
02h
9Eh
1Eh
60h
61h
Setting 6
Sound Settings
In addition to selecting FIR filter (Sharp Roll-Off or Slow Roll-Off) or DSD filter, some register settings such that High Precision
Calculation Mode, which is ROHM’s original function, provide further adjustment of the sound quality. The registers are shown
in the table below. Changing these register settings may affect audio characteristics such as THD+N. Please evaluate the
register settings carefully before determining the setting value.
Table 22. Registers for Sound Setting
Register
PhaseAdj (06h[0])
Function
Phase adjustment for internal clock
High precision calculation for FIR filter
Over sampling rate of ΔΣ Modulator
HpcMode (31h[7])
DsSetting (40h[4]), DsOsr (40h[1:0])
See the “Register Description” for more details on each register.
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Application Examples
Stereo 2ch
AVCC_L
5.0 V
DVDDIO
3.3 V
DVDD
1.5 V
100 μF
0.1 μF
100 μF 100 μF
0.1 μF 0.1 μF
100 μF
100 μF
100 μF
100 μF
0.1 μF
100 μF
0.1 μF
100 μF
100 μF
1500 pF
0.1 μF
64
0.1 μF 0.1 μF
63 59
61
0.1 μF 0.1 μF
2
7
9
17
15
11
50
48
53
55
58
56
44～47
1 kΩ
560 Ω + 820 Ω
390 Ω
Lch Out
Single
1500 pF
1500 pF
IOUT_LP
IOUT_LN
51
52
BCLK
BCLK/DSDCLK
Current
1 kΩ
12
Segment
AVCC
5.0 V
Over
1500 pF
560 Ω
+ 820 Ω
LRCLK LRCLK/DSD2
13
Sampling
Digital
FIR
PCM
I/F
Lch Out
Differential
100 μF
0.1 μF
ΔΣ
Modulator
DSP
AVCC 42
AVCC_L
5.0 V
100 μF
Audio
Function
Control
DIN
DIN/DSD1
I-V Translate Circuit
Filter
0.1 μF
14
VREF_L
EXT_RES_L
43
MCLK
41
VREF
910 Ω
910 Ω
EXT_RES_R
40
AVCC_R
5.0 V
VREF_R
DSD
I/F
38
39
0.1 μF
100 μF
1500 pF
AGND
1 kΩ
IOUT_RP
IOUT_RN
560 Ω + 820 Ω
390 Ω
30
29
Current
MCLK
60
2-wire
I/F
System
Control
Master
Clock
Rch Out
Single
Segment
1500 pF
1500 pF
1 kΩ
8
10
16
18
19
20
21
3
4
5
6
31
33
28
0.1 μF
26
23
0.1 μF
25
1
34 ～ 37
1500 pF
560 Ω
0.1 μF 0.1 μF
+ 820 Ω
DVDDIO
3.3 V
2.2 kΩ
Rch Out
Differential
DVDDIO
3.3 V
2.2 kΩ
100 μF
100 μF
100 μF
100 μF
2.2 kΩ
2.2 kΩ
I-V Translate Circuit
AVCC_R
5.0 V
CPU
(Note 1)
The written values of external parts are checked by
sound test. Changing these values can affect the
sound quality. Please check the sound when the
values are changed.
Figure 37. Application Circuit
I-V Translate Circuit (Enlarged)
1500 pF
1 kΩ
IOUT_LP
IOUT_RP
560 Ω + 820 Ω
390 Ω
Single out
1500 pF
1500 pF
1 kΩ
IOUT_LN
IOUT_RN
1500 pF
560 Ω
+ 820 Ω
Differential
Figure 38. Application Circuit (I/V Translate Circuit)
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Application Examples - continued
Mono Mode x2 - A
BCLK
3000 pF
IOUT_LP
IOUT_LN
51
52
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
12
13
14
1000 Ω // 1000 Ω
560 Ω + 820 Ω
390 Ω
LRCK
DIN
DSP
Lch Out
Single
1500 pF
3000 pF
BD34301EKV 1
1000 Ω
// 1000 Ω
MCLK
1500 pF
560 Ω
+ 820 Ω
IOUT_RP 30
IOUT_RN 29
Lch Out
Differential
MCLK
60
DVDDIO
3
4
5
6
1
DVDDIO
2.2 kΩ
3000 pF
IOUT_LP
IOUT_LN
51
52
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
12
13
14
1000 Ω // 1000 Ω
560 Ω + 820 Ω
390 Ω
Rch Out
Single
1500 pF
3000 pF
BD34301EKV 2
1000 Ω
// 1000 Ω
1500 pF
560 Ω
+ 820 Ω
IOUT_RP 30
IOUT_RN 29
Rch Out
Differential
MCLK
60
3
4
5
6
1
(Note 1)
The written values of external parts are checked by
sound test. Changing these values can affect the
sound quality. Please check the sound when the
values are changed.
SCL
SDA RESETB
CPU
Figure 39. Application Circuit of Mono Mode x2 - A
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Application Examples - continued
Mono Mode x2 - B
Stereo 2ch circuit can also configure Lch / Rch differential output in Mono Mode.
Table 23. Lch / Rch Differential Output Setting in Mono Mode
MonoSel
(12h[1:0])
OutPol2
(14h[1:0])
Chip No.
Function
Lch Output
Rch Output
02h
1
2
02h
03h
(IOUT_R inverted)
02h
(IOUT_R inverted)
1500 pF
1 kΩ
390 Ω
560 Ω + 820 Ω
51
52
IOUT_LP
IOUT_LN
1500 pF
1500 pF
OUT+
1 kΩ
1500 pF
560 Ω + 820 Ω
Lch/Rch Out
Differential
1500 pF
1 kΩ
560 Ω + 820 Ω
390 Ω
30
29
IOUT_RP
IOUT_RN
1500 pF
1500 pF
OUT-
1 kΩ
1500 pF
560 Ω + 820 Ω
Figure 40. Application Circuit of Mono Mode x2 - B
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Application Examples - continued
2ch x 2 = 4ch
BCLK
IOUT_LP
IOUT_LN
51
52
I-V Translate Circuit
BCLK/DSDCLK
12
13
14
(Figure 38)
1ch Out
LRCLK
LRCLK/DSD2
DIN/DSD1
DSP
BD34301EKV 1
DIN1
DIN2
I-V Translate Circuit
(Figure 38)
IOUT_RP 30
IOUT_RN 29
MCLK
2ch Out
MCLK
60
DVDDIO
3
4
5
6
1
DVDDIO
2.2 kΩ
I-V Translate Circuit
(Figure 38)
IOUT_LP
IOUT_LN
51
52
BCLK/DSDCLK
LRCLK/DSD2
DIN/DSD1
12
13
14
3ch Out
BD34301EKV 2
IOUT_RP 30
IOUT_RN 29
I-V Translate Circuit
(Figure 38)
4ch Out
MCLK
60
3
4
5
6
1
SCL
SDA RESETB
CPU
Figure 41. Application Circuit of 4ch Output
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Application Examples - continued
2ch x 4 = 8ch
BCLK
LRCLK
DIN1
BCLK
LRCLK
DIN1
I-V Translate Circuit
(Figure 38)
IOUT_LP
IOUT_LN
51
52
12 BCLK/DSDCLK
13 LRCLK/DSD2
14 DIN/DSD1
1ch Out
BD34301EKV 1
DSP
DIN2
I-V Translate Circuit
(Figure 38)
IOUT_RP 30
IOUT_RN 29
DIN3
DVDDIO
2ch Out
60 MCLK
DIN4
3
4
5
6
1
MCLK
I-V Translate Circuit
(Figure 38)
BCLK
LRCLK
DIN2
IOUT_LP
IOUT_LN
51
52
12 BCLK/DSDCLK
13 LRCLK/DSD2
14 DIN/DSD1
3ch Out
BD34301EKV 2
I-V Translate Circuit
(Figure 38)
IOUT_RP 30
IOUT_RN 29
MCLK
4ch Out
60 MCLK
3
4
5
6
1
DVDDIO
2.2 kΩ
BCLK
LRCLK
DIN3
I-V Translate Circuit
(Figure 38)
IOUT_LP
IOUT_LN
51
52
12 BCLK/DSDCLK
13 LRCLK/DSD2
14 DIN/DSD1
5ch Out
BD34301EKV 3
I-V Translate Circuit
(Figure 38)
IOUT_RP 30
IOUT_RN 29
MCLK
6ch Out
60 MCLK
3
4
5
6
1
DVDDIO
2.2 kΩ
BCLK
LRCLK
DIN4
IOUT_LP
51
I-V Translate Circuit
(Figure 38)
12 BCLK/DSDCLK
13 LRCLK/DSD2
14 DIN/DSD1
IOUT_LN
52
7ch Out
BD34301EKV 4
I-V Translate Circuit
(Figure 38)
IOUT_RP 30
IOUT_RN 29
MCLK
8ch Out
60 MCLK
3
4
5
6
1
DVDDIO
2.2 kΩ
SCL
SDA RESETB
CPU
Figure 42. Application Circuit of 8ch Output
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Operational Notes
1. Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply
pins.
2. Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3. Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
4. Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5. Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
6. Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.
Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing
of connections.
7. Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject
the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should
always be turned off completely before connecting or removing it from the test setup during the inspection process. To
prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and
storage.
8. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
9. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge
acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause
unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power
supply or ground line.
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Operational Notes - continued
10. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 43. Example of Monolithic IC Structure
11. Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
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Ordering Information
B D 3
4
3
0
1
E
K
V -
E 2
Package
EKV: HTQFP64BV
Packaging and forming specification
E2: Embossed tape and reel
Marking Diagrams
HTQFP64BV (TOP VIEW)
”MUS-IC” Logo
Part Number Marking
LOT Number
BD34301EKV
Pin 1 Mark
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© 2020 ROHM Co., Ltd. All rights reserved.
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02.Jul.2020 Rev.001
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Datasheet
BD34301EKV
Physical Dimension and Packing Information
Package Name
HTQFP64BV
www.rohm.com
© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
TSZ02201-0C2C0E300770-1-2
02.Jul.2020 Rev.001
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Datasheet
BD34301EKV
Revision History
Date
Revision
001
Changes
02.Jul.2020
New Release
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© 2020 ROHM Co., Ltd. All rights reserved.
TSZ22111 • 15 • 001
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02.Jul.2020 Rev.001
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Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
相关型号：
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