BD37069FV-ME2 [ROHM]
Sound Processor for Car Audio with Built-in High-Voltage Amplifier;
| 型号： | BD37069FV-ME2 |
| 厂家： | 
ROHM |
| 描述： | Sound Processor for Car Audio with Built-in High-Voltage Amplifier |
| 文件： | 总41页 (文件大小：2840K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
Sound Processor for Car Audio
with Built-in High-Voltage Amplifier and
2nd Order Post Filter
BD37069FV-M
General Description
Key Specifications(Note2)
TotalHarmonic Distortion:
BD37069FV-M is a sound processor developed for car
audio with built-in selector of six stereo inputs and output
interfaced to ADC after adjusting signal level.
BD37069FV-M has a 6-channel volume circuit and
built-in 2nd order post filter which reduces the out-of
-band noise. The High-Voltage function is capable to
reach up to 5.2VRMS maximum output. Furthermore, the
IC is simple to design due to the built-in TDMA noise
reduction systems.
0.003%(Typ)
2.1VRMS(Typ)
55dB(Min)
Maximum Input Voltage:
Common Mode Rejection Ratio :
Maximum Output Voltage:
Output Noise Voltage:
Residual Output Noise Voltage:
Ripple Rejection Ratio:
5.2VRMS(Typ)
23μVRMS(Typ)
10.5μVRMS(Typ)
-70dB (Typ)
Operating Temperature Range:
(Note2)These specifications are High-Voltage mode2.
-40°C to +85°C
Features
AEC-Q100 Qualified (Note1)
Package
W(Typ) x D(Typ) x H(Max)
13.60mm x 7.80mm x 2.00mm
Built-in differential input selector that can select
single-ended / differential input
SSOP-B40
Reduce switching pop noise of input gain control due
to the built-in advanced switch circuit
Less out-of-band noise of DAC by built-in 2nd order
post filter
Built-in buffered ground isolation amplifier to achieve
high CMRR characteristics
Built-in TDMA noise reduction circuit reduces the
additional components for external filter
Available to output 5.2VRMS by High-Voltage function
(This device is possible to 3.2VRMS output by using
another High-Voltage mode, VCCH=11.5V)
Available to control by 3.3V / 5V for I2C-bus
controller
The input and output terminals are located together to
arrange the flow of signal in a same direction making
the PCB layout easier and PCB area smaller
(Note 1) Grade 3
Applications
Car Audio and Other Audio Equipment
Typical Application Circuit
DSP
ADC
DAC
IG1 IG2 INF2 INF1 INR2 INR1
A1
INS INC
BD37069FV-M
CD
Main Gain adjust Sub Gain adjust
A2
B1
Fader
boost
2nd order
LPF
Fader
Level
Shift
OUTC
OUTS
★
USB
ATT★
B2
CP1
CN
2nd order
LPF
Fader
boost
Fader
ATT★
Sub SEL
★
Level
Shift
TUN
AUX
AUX
CP2
DP1
DN
Level
Shift
Fader
OUTR1
OUTR2
Fader
2nd order
LPF
ATT★
★
boost
Rear SEL
Front SEL
DP2
2nd order
LPF
Fader
Level
Shift
Fader
ATT★
EP1
EN
★
boost
★
EP2
Fader
Fader
Level
Shift
2nd order
LPF
OUTF1
OUTF2
★
boost
ATT
★
FP1
FN1
FN2
★
2nd order
LPF
Fader
Level
Shift
Fader
BT
★
boost
★
ATT
FP2
Advanced Switch
MIN
NAVI
Figure 1. Typical Application Circuit
○Product structure：Silicon monolithic integrated circuit ○This product has no designed protection against radioactive rays
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BD37069FV-M
Contents
General Description........................................................................................................................................................................1
Features..........................................................................................................................................................................................1
Key Specifications(Note2) ..................................................................................................................................................................1
Package..........................................................................................................................................................................................1
Applications ....................................................................................................................................................................................1
Typical Application Circuit ...............................................................................................................................................................1
Contents .........................................................................................................................................................................................2
Pin Configuration ............................................................................................................................................................................3
Pin Descriptions..............................................................................................................................................................................3
Block Diagram ................................................................................................................................................................................4
Absolute Maximum Ratings (Ta=25°C)...........................................................................................................................................5
Thermal Resistance(Note 1) ...............................................................................................................................................................5
Recommended Operating Condition...............................................................................................................................................5
Electrical Characteristics.................................................................................................................................................................6
Typical Performance Curve(s) ........................................................................................................................................................9
I2C-bus CONTROL SIGNAL SPECIFICATION .............................................................................................................................11
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
Electrical specifications and timing for bus lines and I/O stages .....................................................................................11
I2C-bus FORMAT.............................................................................................................................................................12
I2C-bus Interface Protocol................................................................................................................................................12
Slave address..................................................................................................................................................................12
Select Address & Data.....................................................................................................................................................13
About power on reset ......................................................................................................................................................21
About start-up and power off sequence on IC .................................................................................................................21
About relations of power supply voltage and the DC-bias voltage...................................................................................22
About advanced switch circuit.......................................................................................................................................................23
Application Example .....................................................................................................................................................................28
I/O Equivalence Circuit .................................................................................................................................................................29
Application Information .................................................................................................................................................................31
1)
2)
3)
4)
5)
6)
7)
Absolute maximum rating voltage...................................................................................................................................31
About a signal input part.................................................................................................................................................31
About output load characteristics....................................................................................................................................31
About HIVOLB terminal(20pin) when power supply is off...............................................................................................32
About signal input terminals ...........................................................................................................................................32
About changing gain of Input Gain and Fader Volume ...................................................................................................32
About inter-pin short to VCCH........................................................................................................................................32
Operational Notes.........................................................................................................................................................................33
1.
2.
3.
4.
5.
6.
7.
8.
Reverse Connection of Power Supply............................................................................................................................33
Power Supply Lines........................................................................................................................................................33
Ground Voltage...............................................................................................................................................................33
Ground Wiring Pattern....................................................................................................................................................33
Thermal Consideration ...................................................................................................................................................33
Recommended Operating Conditions.............................................................................................................................33
Inrush Current.................................................................................................................................................................33
Operation Under Strong Electromagnetic Field ..............................................................................................................33
Testing on Application Boards ........................................................................................................................................33
Inter-pin Short and Mounting Errors ...............................................................................................................................34
Unused Input Pins ..........................................................................................................................................................34
Regarding the Input Pin of the IC ...................................................................................................................................34
9.
10.
11.
12.
Ordering Information.....................................................................................................................................................................35
Marking Diagram ..........................................................................................................................................................................35
Physical Dimension, Tape and Reel Information...........................................................................................................................36
Revision History............................................................................................................................................................................37
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Pin Configuration
SSOP-B40
(TOP VIEW)
A1
A2
B1
1
2
3
40 OUTC
39 OUTS
38 OUTR1
37 OUTR2
36 OUTF1
35 OUTF2
34 INF2
B2
4
5
CP1
CN
6
7
CP2
33 INF1
DP1
DN
8
9
32 INR2
31 INR1
DP2 10
EP1 11
EN 12
30 INS
29 INC
28 IG1
27 IG2
26 VCCL
EP2 13
FP1 14
FN1 15
FN2 16
FP2 17
MIN 18
SEL 19
HIVOLB 20
25 VREF
24 GND
23 SDA
22 SCL
21 VCCH
Figure 2.Pin Configuration
Pin Descriptions
Pin No.
Pin Name
Description
A input terminal of 1ch
Pin No.
21
Pin Name
VCCH
Description
VCCH terminal for power supply
I2C-bus clock terminal
I2C-bus data terminal
1
A1
A2
2
3
A input terminal of 2ch
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
SCL
SDA
B1
B input terminal of 1ch
4
B2
B input terminal of 2ch
GND
GND terminal
5
CP1
CN
C positive input terminal of 1ch
C negative input terminal
VREF
VCCL
IG2
BIAS terminal
6
VCCL terminal for power supply
Input gain output terminal of 2ch
Input gain output terminal of 1ch
Center input terminal
7
CP2
DP1
DN
C positive input terminal of 2ch
D positive input terminal of 1ch
D negative input terminal
8
IG1
9
INC
10
11
12
13
14
15
16
17
18
19
20
DP2
EP1
EN
D positive input terminal of 2ch
E positive input terminal of 1ch
E negative input terminal
INS
Subwoofer input terminal
Rear input terminal of 1ch
Rear input terminal of 2ch
Front input terminal of 1ch
Front input terminal of 2ch
Front output terminal of 2ch
Front output terminal of 1ch
Rear output terminal of 2ch
Rear output terminal of 1ch
Subwoofer output terminal
Center output terminal
INR1
INR2
INF1
EP2
FP1
FN1
FN2
FP2
MIN
SEL
HIVOLB
E positive input terminal of 2ch
F positive input terminal of 1ch
F negative input terminal of 1ch
F negative input terminal of 2ch
F positive input terminal of 2ch
Mixing input terminal
INF2
OUTF2
OUTF1
OUTR2
OUTR1
OUTS
OUTC
High Voltage output mode Select
Output Gain control terminal
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Block Diagram
INC
INS
IG1
IG2
VCCL VREF GND SDA
SCL VCCH
OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2
INR1
28
40
39
38
37
35
34
33
32
31
30
29
27
26
24
22
25
23
21
36
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
100kΩ 100kΩ 100kΩ
100kΩ 100kΩ 100kΩ
I2C-bus LOGIC
REG(4.15V)
Sub SEL
■Fader : +23dB～-79dB、-∞/1dBstep
■Input Gain : +23dB～-15dB/1dBstep
■Front Mixing : on/off
Sub
Gain adjust
Main Gain adjust
2nd order LPF
★ Advanced Switch
■2nd order LPF: fc=70kHz
■Main/Sub Gain Adjust 0dB/6dB
■Anti-GSM circuit
Rear SEL
■High Voltage Output
Front
SEL
Level Shift = 2dB(normal mode)
Level Shift = 4.6dB(Hi-voltage mode1)
Level Shift = 8.3dB(Hi-voltage mode2)
★
Input Gain
Input selector (2 single-ended and 4 stereo ISO)
GND
ISO
GND
amp
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
amp
amp
amp
amp
amp
amp
amp
100kΩ
100kΩ
250kΩ
250kΩ 250kΩ
250kΩ 250kΩ
250kΩ
100kΩ
250kΩ 250kΩ 250kΩ
250kΩ 250kΩ 250kΩ 250kΩ
250kΩ 250kΩ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
MIN
SEL
HIVOLB
A1
A2
B1
B2
CP1
CN
CP2
DP1
DP2
EP1
EN
EP2
FP1
FN1
FN2
FP2
DN
Figure 3. Block Diagram
・The outputs of Pin 27 and Pin 28 are selected by the input selector, from the inputs Pin 1 to Pin 17.
Otherwise, these signals are possible to output directly on Pin 35 to Pin 40.
・6-channel input signals from DSP on Pin 29 to Pin 34 pass through the volume circuit (Fader) and 2nd order post filter to the
output terminals Pin 35 to Pin 40 .
・It is possible for 6-channel inputs to set the gain up to +6dB by Gain adjust function and to set the gain up to +8.3dB by Level
Shift Circuit (High-Voltage Mode).
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Absolute Maximum Ratings (Ta=25°C)
Parameter
Symbol
VCCL
VCCH
Rating
10
18
GND-0.3 to +7
GND-0.3 to VCCL+0.3
-55 to +150
Unit
V
V
Power Supply Voltage
Input Voltage
SCL, SDA
Other
VIN
V
Storage Temperature
TSTG
°C
°C
Maximum Junction Temperature
TJMAX
+150
Caution: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated over the
absolute maximum ratings.
Thermal Resistance(Note 1)
Thermal Resistance (Typ)
Parameter
Symbol
Unit
1s(Note 3)
2s2p(Note 4)
SSOP-B40
Junction to Ambient
Junction to Top Characterization Parameter(Note 2)
θJA
103.6
17
58.8
10
°C/W
°C/W
ΨJT
(Note 1)Based on JESD51-2A(Still-Air)
(Note 2)The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside
surface of the component package.
(Note 3)Using a PCB board based on JESD51-3.
(Note 4)Using a PCB board based on JESD51-7
Layer Number of
Measurement Board
Material
FR-4
Board Size
Single
114.3mm x 76.2mm x 1.6mmt
Top
Copper Pattern
Thickness
Footprints and Traces
70μm
.
Layer Number of
Measurement Board
Material
FR-4
Board Size
114.3mm x 76.2mm x 1.6mmt
2 Internal Layers
4 Layers
Top
Copper Pattern
Bottom
Copper Pattern
74.2mm x 74.2mm
Thickness
Copper Pattern
Thickness
35μm
Thickness
Footprints and Traces
70μm
74.2mm x 74.2mm
70μm
Recommended Operating Condition (Ta= -40°C to +85°C)
Parameter
Symbol
VCCL
Min
7.0
Typ
9
Max
9.5
Unit
V
Power Supply Voltage
VCCH
VCCL
17
17.8
V
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Electrical Characteristics
Unless otherwise specified, Ta=25°C, VCCL=9V, VCCH=17V, f=1kHz, VIN=1VRMS, RL=10kΩ,
Input selector A, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON (High-Voltage mode2), LPF ON, Fader 0dB,
Input point=A1/A2, Monitor point=IG1/IG2
Limit
Parameter
Symbol
IQ_VCCL
Unit
mA
Conditions
Min
-
Typ
30
Max
43
Current Consumption (VCCL)
No signal
No signal
Current Consumption (VCCH)
Input Impedance (A)
IQ_VCCH
RIN_S
-
7
10
mA
kΩ
kΩ
70
100
250
130
325
Input Impedance (B, C, D, E, F)
RIN_D
175
Voltage Gain
GV
CB
-1.5
-1.5
-
0
0
1.5
1.5
dB
dB
%
GV = 20log(VOUT/VIN)
CB = GV1-GV2
Channel Balance
VOUT = 1VRMS
BW = 400-30kHz
RG = 0Ω
BW = IHF-A
VIM at THD+N(VOUT) = 1%
BW = 400-30kHz
RG = 0Ω
CTC = 20log(VOUT/VOUT’)
BW = IHF-A
Total Harmonic Distortion
Output Noise Voltage (Note1)
THD+N
0.003
0.05
VNO1
VIM
-
3.1
2.2
8.0
-
μVRMS
Maximum Input Voltage
2.0
VRMS
Crosstalk Between Channels (Note1)
CTC
CTS
-
-
-100
-100
-90
-90
dB
dB
RG = 0Ω
CTS = 20log(VOUT/VOUT’)
Crosstalk Between Selectors(Note1)
BW = IHF-A
XP1 and XN input
XP2 and XN input
CMRR = 20log(VIN/VOUT
Common Mode Rejection Ratio
(C, D, E, F) (Note1)
CMRR
55
65
-
dB
)
BW = IHF-A, [X=C,D,E,F]
Input Gain = -15dB
VIN = 0.1VRMS
GIN = 20log(VOUT/VIN)
Input Gain = 23dB
VIN = 0.1VRMS
Minimum Input Gain
Maximum Input Gain
GIN_MIN
-17
21
-15
23
-13
25
dB
dB
GIN_MAX
GIN = 20log(VOUT/VIN)
Gain Set Error
GIN_ERR
ROUT
-2
-
0
-
+2
50
dB
Input Gain = -15 to +23dB
Output Impedance
Ω
THD+N = 1%
BW = 400-30kHz
VOM
2.0
2.2
-
VRMS
Maximum Output Voltage
(Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase.
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Unless otherwise specified, Ta=25°C, VCCL=VCCH=9V, f=1kHz, VIN=0.9VRMS, RL=10kΩ,
Input selector A, Input Gain 0dB, Gain Adjust +6dB, High-Voltage OFF(normal mode), LPF ON, Fader 0dB,
Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS
Limit
Parameter
Symbol
Unit
Conditions
Min
-
Typ
-
Max
50
Output Impedance
ROUT
VOM
Ω
VIN = 1VRMS
THD+N = 1%
BW = 400-30kHz
☆Maximum Output Voltage
☆Output Gain
2.3
0.5
2.5
2
-
VRMS
GH(OUT)
3.5
dB
GH(OUT) = 20log(VOUT/VIN)
☆This Item is designated by ROHM only to discriminate between other items and it.
Unless otherwise specified, Ta=25°C, VCCL=9V, VCCH=11.5V, f=1kHz, VIN=0.9VRMS, RL=10kΩ,
Input selector A, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON(High-Voltage mode1), LPF ON, Fader 0dB,
Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS
Limit
Parameter
Symbol
Unit
Conditions
Min
-
Typ
-
Max
50
Output Impedance
ROUT
VOM
Ω
VIN=1VRMS
THD+N=1%
BW=400-30kHz
☆Maximum Output Voltage
☆Output Gain
3.2
2.6
3.4
4.6
-
VRMS
GH(OUT)
6.6
dB
GH(OUT)=20log(VOUT/VIN)
☆This Item is designated by ROHM only to discriminate between other items and it.
Unless otherwise specified, Ta=25°C, VCCL=9V, VCCH=17V, f=1kHz, VIN=0.9VRMS, RL=10kΩ,
Input selector A, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON(High-Voltage mode2), LPF ON, Fader 0dB,
Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS
Limit
Parameter
Symbol
Unit
Conditions
Min
-
Typ
-
Max
50
Output Impedance
ROUT
VOM
Ω
VIN=1VRMS
THD+N=1%
BW=400-30kHz
☆Maximum Output Voltage
☆Output Gain
5.0
6.3
5.2
8.3
-
VRMS
GH(OUT)
10.3
dB
GH(OUT)=20log(VOUT/VIN)
☆This Item is designated by ROHM only to discriminate between other items and it.
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Unless otherwise specified, Ta=25°C, VCCL=9V, VCCH=17V, f=1kHz, VIN=0.9VRMS, RL=10kΩ,
Input selector A, Input Gain 0dB, Gain Adjust +6dB, High-Voltage ON(High-Voltage mode2), LPF ON, Fader 0dB,
Input point=INF1/INF2/INR1/INR2/INC/INS, Monitor point=OUTF1/OUTF2/OUTR1/OUTR2/OUTC/OUTS
Limit
Parameter
Symbol
Unit
Conditions
Min
21
Typ
23
0
Max
25
Fader Boost Gain = +23dB
VIN=0.1VRMS
GF=20log(VOUT/VIN)-GH(OUT)
Gain Adjust=0dB
Maximum Boost Gain
Channel Balance
GF BST
dB
dB
CB
-1.5
1.5
CB = GV1-GV2
BW=400-30kHz
Gain Adjust = 0dB
RG = 0Ω
Total Harmonic Distortion
Output Noise Voltage (Note1)
THD+N
VNO1
－
－
0.003
23
0.05
40
%
μVRMS
BW = IHF-A
Fader Attenuation = -∞dB
RG = 0Ω
BW = IHF-A
VIM at THD+N(VOUT)=1%
BW=400-30kHz
Gain Adjust = 0dB
RG = 0Ω
Residual Output Noise Voltage
VNOR
－
2.0
－
10.5
2.1
20
－
μVRMS
VRMS
dB
(Note1)
Maximum Input Voltage
VIM
Crosstalk Between Channels (Note1)
Maximum Attenuation (Note1)
CTC
GF MIN
-100
-100
-90
-90
CTC=20log(VOUT/VOUT´
BW = IHF-A
)
Fader Attenuation = -∞dB
GF=20log(VOUT/VIN)
BW = IHF-A
－
dB
Fader Boost Gain
Gain Set Error
GF ERR
GF ERR1
GF ERR2
-2
-2
-3
0
0
0
2
2
3
dB
dB
dB
=
+1 to +23dB
Fader Attenuation
0 to -15dB
Fader Attenuation
-16 to -47dB
Fader Attenuation
-48 to -79dB
Attenuation Set Error 1
Attenuation Set Error 2
=
=
Attenuation Set Error 3
GF ERR3
RRVCCL
-4
0
4
dB
dB
=
VRR=0.1VRMS
fRR=1kHz
－
-70
-40
RRVCCL=20log(VOUT /VCCL
VRR=0.1VRMS
fRR=1kHz
)
Power Supply Rejection Ratio
RRVCCH
RIN_M
－
70
-70
100
2.2
-40
130
-
dB
kΩ
RRVCCH=20log(VOUT /VCCH
)
Input Impedance
VIM_M at THD+N(VOUT)=1%
BW=400-30kHz
Maximum Input Voltage
VIM_M
2.0
VRMS
Input point=MIN
Front Mixing=OFF
GMX=20log( VOUT /VIN)
BW=IHF-A
(Note1)
Maximum Attenuation
GMX MIN
-
-100
-85
dB
Input point=MIN
Front Mixing=ON
GMX=20log(VOUT/VIN)- GH(OUT)
Mixing Gain
GMX
-2
0
2
dB
Input Impedance
RIN_M
70
100
130
kΩ
Gain Adjust=6dB
VIN=0.1VRMS
4
6
8
dB
Boost Gain
GF BST
GF=20log(VOUT/VIN)- GH(OUT)
-1.5
0
1.5
dB
CB = GV1-GV2
Channel Balance
CB
(Note1) VP-9690A (Average value detection, effective value display) filter by Panasonic is used for measurement. Input and output are in-phase.
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BD37069FV-M
Typical Performance Curve(s)
30
25
20
15
10
5
40
35
30
25
20
15
10
(VCC=VCCL=VCCH
)
5
0
0
0
2
4
6
8
10 12 14 16 18
0
1
2
3
4
5
6
7
8
9
10
VCCH [V]
VCC [V]
Figure 5. VCCH vs. IQ_VCCH
(High-Voltage mode)
Figure 4. VCC vs. IQ_VCCL+IQ_VCCH
10
8
10
1
10
f=10kHz
High-Voltage mode2
1
6
f=1k,100Hz
4
High-Voltage mode1
Normal mode
0.1
0.1
0.01
0.001
2
Normal mode
0
0.01
-2
-4
0.001
10
100
1k
10k
100k
0.001
0.01
0.1
1
10
Frequency [Hz]
VIN [VRMS
]
Figure 6. Gain vs. frequency
(Normal / High-Voltage mode)
Figure 7. THD+N vs. VIN / VO
(Gain Adjust=+6dB)
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BD37069FV-M
0
-20
0
-20
-40
-60
-80
RG=1kΩ
RG=470Ω
RG=0Ω
-40
-60
-80
-100
-120
-100
10
10
100
1k
10k
100k
100
1k
Frequency [Hz]
10k
100k
Frequency [Hz]
Figure 9. Crosstalk (between Channels) vs.
frequency
Figure 8. CMRR vs. frequency
5
0
0
-20
-5
-40
-10
-15
-20
-60
-80
-100
10
100
1k
10k
100k
10
100
1k
10k
100k
Frequency [Hz]
Frequency [Hz]
Figure 10. PSRR vs. frequency
Figure 11. Gain(LPF ON/pass) vs. frequency
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BD37069FV-M
I2C-bus CONTROL SIGNAL SPECIFICATION
(1)
Electrical specifications and timing for bus lines and I/O stages
SDA
tBUF
tHD;STA
tSP
tLOW
SCL
tSU;STO
tSU;STA
tHD;STA
tSU;DAT
tHD;DAT
tHIGH
S
P
P
Figure 12. Definition of Timing on the I2C-bus
Table 1 Characteristics of the SDA and SCL bus lines for I2C-bus devices
Parameter
Fast-modeI2C-bus
Symbol
Unit
Min
Max
400
kHz
1
2
SCL Clock Frequency
fSCL
tBUF
0
Bus Free Time between STOP and START Condition
1.3
－
μsec
Hold Time (repeated) START condition.
After this period, the first clock pulse is generated
3
tHD;STA
0.6
－
μsec
4
5
6
LOW Period of the SCL Clock
tLOW
tHIGH
1.3
0.6
0.6
－
－
－
μsec
μsec
μsec
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
tSU;STA
7
8
9
Data Hold Time
tHD;DAT
tSU; DAT
tSU;STO
0*
－
－
－
μsec
nsec
μsec
Data Set-up Time
100
0.6
Set-up Time for STOP Condition
All values referred to VIH min. and VIL max. Levels (see Table 2).
Table 2 Characteristics of the SDA and SCL I/O stages for I2C-bus devices
Fast-modeI2C-bus
Parameter
Symbol
Unit
Min
-0.5
2.3
Max
10 LOW level input voltage: Fixed input levels
11 HIGH level input voltage: Fixed input levels
VIL
VIH
1
-
V
V
12 Pulse width of spikes, which must be suppressed by the input filter.
tSP
VOL1
II
0
0
50
0.4
10
nsec
V
LOW level output voltage (open drain or open collector): At 3mA sink
current
13
Input current each I/O pin with an input voltage between 0.4V and 0.9
VDD max.
14
-10
μA
ｔHD;STA
2µsec
ｔHD;DAT
1µsec
ｔSU;DAT
1µsec
ｔSU;STO
2µsec
SCL
SDA
ｔBUF
4µsec
ｔLOW
3µsec
ｔHIGH
1µsec
SCL clock frequency:250kHz
Figure 13. I2C-bus data transmission timing
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BD37069FV-M
(2)
I2C-bus FORMAT
MSB
Slave Address
8bit
LSB
MSB
Select Address
8bit
LSB
MSB
LSB
S
1bit
A
1bit
A
1bit
Data
8bit
A
P
1bit 1bit
S
= Start condition (Recognition of start bit)
Slave Address = Recognition of slave address. 7 bits in upper order are optional.
The least significant bit is “L” due to write format.
A
= ACKNOWLEDGE bit (Recognition of acknowledgement)
Select Address = Selection of register that contain data on volume, bass and treble settings.
Data
P
= Data on every volume and tone to be stored in selected register.
= Stop condition (Recognition of stop bit)
(3)
I2C-bus Interface Protocol
1)Basic form
Slave Address
MSB LSB
S
A
Select Address
MSB LSB
A
Data
MSB LSB
A
P
2）Automatic increment (Select Address increases (+1) according to the number of data.)
S
Slave Address
MSB LSB
A
Select Address
MSB LSB
A
Data1
MSB
A
Data2
A
････
DataN
MSB
A
P
LSB MSB
LSB
LSB
(Example) ① Data1 shall be set as data of address specified by Select Address.
② Data2 shall be set as data of address specified by Select Address +1.
③ DataN shall be set as data of address specified by Select Address +N-1.
3）Configuration unavailable for transmission (In this case, only Select Address1 is set.)
S
Slave Address
A
Select Address1
A
Data
A
Select Address 2
A
Data
A P
MSB
LSB
MSB LSB MSB LSB MSB
LSB MSB LSB
(Note)If any data is transmitted as Select Address 2 next to data,
It is recognized as data, not as Select Address 2.
(4)
Slave address
MSB
A6
LSB
A5
0
A4
0
A3
0
A2
0
A1
0
A0
0
R/W
0
1
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BD37069FV-M
(5)
Select Address & Data
Select
Address
(hex)
MSB
D7
Data
D3
LSB
D0
Items
D6
0
D5
D4
D2
D1
0
Advanced
Switch
ON/OFF
Advanced Switch
Time of Input
Gain/Fader
High-Voltage
Mode Select
Initial Setup 1
01
0
0
0
Rear
Front
Selector Selector
Initial Setup 2
Input Selector
02
05
0
0
Sub Selector
0
0
0
0
0
0
0
Input Selector
Input Gain
Input Gain
06
28
29
2A
2B
2C
2D
Fader 1ch Front
Fader 2ch Front
Fader 1ch Rear
Fader 2ch Rear
Fader Center
Fader Boost Gain / Attenuation
Fader Boost Gain / Attenuation
Fader Boost Gain / Attenuation
Fader Boost Gain / Attenuation
Fader Boost Gain / Attenuation
Fader Boost Gain / Attenuation
Fader Subwoofer
Front
Mixing
ON/OFF
Sub
Gain
Adjust
Main
Gain
Adjust
LPF Setup
Mixing ON/OFF
30
LPF fc
0
0
0
0
Test Mode
F0
FE
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
1
System Reset
Advanced switch
Notes on data format
1. “Advanced switch” function is available for the hatched parts on the above table.
2. In case of transferring data continuously, Select Address flows by Automatic Increment function, as shown below.
→ 01(hex)→02(hex)→05(hex)→06(hex)→28(hex)→29(hex)→2A(hex)→2B(hex)→2C(hex)→2D(hex)→ 30(hex)
3. Input selector that is not corresponded for “Advanced switch” function, cannot reduce the noise caused when
changing the input selector. Therefore, it is recommended to turn on mute when changing these settings.
4. In case of setting to infinite “-∞” by using Fader when input selector setting is changed, please consider “Advanced
switch” time.
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BD37069FV-M
Explanation of each Select Address
High-Voltage Mode Select
Level Shift output gain
Select Address 01(hex)
Front Mixing
Select Address 30(hex)
Main/Sub Gain Adjust
Select Address 30(hex)
INC
INS
IG1
IG2
VCCL VREF GND SDA
SCL VCCH
22
OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2
INR1
28
40
39
38
37
35
34
33
32
31
30
29
27
26
24
25
23
21
36
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
100kΩ 100kΩ 100kΩ
100kΩ 100kΩ 100kΩ
I2C-bus LOGIC
REG(4.15V)
Sub Selector
Select Address 02(hex)
Sub SEL
■Fader : +23dB～-79dB、-∞/1dBstep
■Input Gain : +23dB～-15dB/1dBstep
■Front Mixing : on/off
Fader Boost/Attenuation
Select Address 28-2D(hex)
Sub
Gain adjust
Main Gain adjust
2nd order LPF
★ Advanced Switch
■2nd order LPF: fc=70kHz
LPF fc
Select Address 30(hex)
■Main/Sub Gain Adjust 0dB/6dB
■Anti-GSM circuit
Rear SEL
■High Voltage Output
Front
SEL
Level Shift = 2dB(normal mode)
Level Shift = 4.6dB(Hi-voltage mode1)
Level Shift = 8.3dB(Hi-voltage mode2)
Rear Selector
Select Address 02(hex)
★
Input Gain
Input selector (2 single-ended and 4 stereo ISO)
Front Selector
Select Address 02(hex)
GND
ISO
GND
amp
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
amp
amp
amp
amp
amp
amp
amp
100kΩ
100kΩ
250kΩ
250kΩ 250kΩ
250kΩ 250kΩ
250kΩ
100kΩ
250kΩ 250kΩ 250kΩ
250kΩ 250kΩ 250kΩ 250kΩ
250kΩ 250kΩ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FN2
17
18
MIN
19
20
Input Gain
Select Address 06(hex)
SEL
HIVOLB
A1
A2
B1
B2
CP1
CN
CP2
DP1
DP2
EP1
EN
EP2
FP1
FN1
FP2
DN
Input Selector
Select Address 05(hex)
Figure 14. Block diagram for explanation of Select Address
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BD37069FV-M
Command Specification
Initial Condition,
1/0
Fixed value
Do not send the data not designated
High-Voltage Mode Select
Select Address 01 (hex)
Mode
MSB
LSB
D0
D7
D6
0
D5
D4
D3
D2
D1
0
High-Voltage mode2
(+8.3dB)
High-Voltage mode1
(+4.6dB)
0
0
0
1
MSB
D7
Advanced Switch Time of Input Gain/Fader(Note1,2)
LSB
D0
Mode
D6
0
D5
0
D4
0
D3
D2
D1
0
4.7 msec
7.1 msec
11.2 msec
14.4 msec
0
1
1
0
0
0
1
1
(Note1) Advanced switch time is Typ value. Max value is 1.4 times of Typ value.
(Note2) If changing Advanced switch time while Advanced switch function is activated, Advance switch time is changed immediately.
MSB
D7
0
Advanced Switch ON/OFF(Note3)
LSB
D0
Mode
D6
0
D5
D4
D3
D2
D1
0
OFF
ON
0
0
1
(Note3) If Advanced switch ON/OFF is changed while Advanced switch function is activated, it will become effective from the next switching operation.
Select Address 02 (hex)
MSB
D7
Front Selector
LSB
D0
0
Mode
D6
0
D5
D5
D4
D3
D2
0
D1
Front
Inside Through
0
0
1
MSB
D7
Rear Selector
LSB
D0
Mode
D6
0
D4
D3
D2
0
D1
0
Rear
0
0
Front Copy
1
MSB
D7
Sub Selector
LSB
D0
Mode(Note4)
D6
0
D5
0
0
1
1
D4
D3
D2
0
D1
OUTC(INS)/OUTS(INS)
OUTC(INR1)/OUTS(INR2)
OUTC (INC)/OUTS(INS)
Prohibition
0
1
0
1
0
0
(Note4) xxx(INxx) : “xxx” means “Output terminal”, “(INxx)” means “Output signal”
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BD37069FV-M
Command Specification
Initial Condition,
1/0
Fixed value
Do not send the data not designated
Input Selector
Select Address 05(hex)
Mode
MSB
D7
LSB
D6
D5
D4
D3
0
D2
0
D1
0
D0
0
A
B
0
0
0
1
C single
D single
E single
F single
C diff.
0
0
0
0
0
0
1
1
1
1
0
0
0
1
0
1
0
1
1
0
0
0
0
0
D diff.
0
1
1
1
E diff.
1
0
0
0
F full-diff.
1
0
0
1
1
1
:
0
0
:
1
1
:
0
1
:
Prohibition
1
1
1
1
List of active input terminal when set input selector
Lch positive input
terminal
Lch negative input
terminal
Rch positive input
terminal
Rch negative input
terminal
Mode
A
1pin(A1)
3pin(B1)
-
2pin(A2)
4pin(B2)
-
B
-
-
C single
D single
E single
F single
C diff.
D diff.
E diff.
5pin(CP1)
8pin(DP1)
11pin(EP1)
14pin(FP1)
5pin(CP1)
8pin(DP1)
11pin(EP1)
-
7pin(CP2)
10pin(DP2)
13pin(EP2)
17pin(FP2)
7pin(CP2)
10pin(DP2)
13pin(EP2)
-
-
-
-
-
-
-
6pin(CN)
9pin(DN)
12pin(EN)
6pin(CN)
9pin(DN)
12pin(EN)
F full-diff.
14pin(FP1)
15pin(FN1)
17pin(FP2)
16pin(FN2)
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BD37069FV-M
Command Specification
Initial Condition,
1/0
Fixed value
Do not send the data not designated
Input Gain
Select Address 06 (hex)
Mode
MSB
D7
LSB
D0
0
D6
D5
0
:
D4
0
:
D3
0
:
D2
0
:
D1
0
:
Prohibition
:
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
:
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
:
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
:
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
:
0
+23dB
+22dB
+21dB
+20dB
+19dB
+18dB
+17dB
+16dB
+15dB
+14dB
+13dB
+12dB
+11dB
+10dB
+9dB
+8dB
+7dB
+6dB
+5dB
+4dB
+3dB
+2dB
+1dB
0dB
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
:
0
0
-1dB
-2dB
-3dB
-4dB
-5dB
-6dB
-7dB
-8dB
-9dB
-10dB
-11dB
-12dB
-13dB
-14dB
-15dB
1
:
Prohibition
1
1
1
1
1
1
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BD37069FV-M
Command Specification
Initial Condition,
1/0
Fixed value
Do not send the data not designated
Fader Boost / Attenuation
Select Address 28, 29, 2A, 2B, 2C, 2D (hex)
MSB
LSB
D0
0
Boost & Attenuation
D7
0
D6
D5
0
D4
0
D3
0
D2
0
D1
0
0
0
:
0
0
0
0
0
0
1
:
Prohibition
:
:
:
:
:
:
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
0
1
1
0
1
0
1
+23dB
+22dB
+21dB
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
・
+10dB
+9dB
+8dB
+7dB
+6dB
+5dB
+4dB
+3dB
+2dB
+1dB
0dB
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
-1dB
-2dB
-3dB
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
・ ・
-78dB
-79dB
1
1
1
:
1
1
1
:
0
0
0
:
0
0
1
:
1
1
0
:
1
1
0
:
1
1
0
:
0
1
0
:
Prohibition
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
1
-∞dB
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BD37069FV-M
Details of Fader Boost / Attenuation
Initial Condition,
(dB)
+23
+22
+21
+20
+19
+18
+17
+16
+15
+14
+13
+12
+11
+10
+9
+8
+7
+6
+5
+4
+3
+2
+1
D7 D6 D5 D4 D3 D2 D1 D0
(dB)
-29
-30
-31
-32
-33
-34
-35
-36
-37
-38
-39
-40
-41
-42
-43
-44
-45
-46
-47
-48
-49
-50
-51
-52
-53
-54
-55
-56
-57
-58
-59
-60
-61
-62
-63
-64
-65
-66
-67
-68
-69
-70
-71
-72
-73
-74
-75
-76
-77
-78
-79
-∞
D7 D6 D5 D4 D3 D2 D1 D0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
0
-1
-2
-3
-4
-5
-6
-7
-8
-9
-10
-11
-12
-13
-14
-15
-16
-17
-18
-19
-20
-21
-22
-23
-24
-25
-26
-27
-28
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TSZ22111・15・001
BD37069FV-M
Command Specification
Initial Condition,
1/0
Fixed value
Do not send the data not designated
Main Gain Adjust
Select Address 30(hex)
Mode
MSB
LSB
D0
0
D7
D6
D5
D4
D3
D2
D1
0dB
0
0
0
0
+6dB
1
MSB
D7
Sub Gain Adjust
LSB
D0
Mode
D6
D5
0
D4
D3
D2
0
D1
0
0dB
0
0
+6dB
1
MSB
D7
LPF fc
LSB
D0
Mode
D6
0
1
D5
0
D4
0
D3
D2
0
D1
70kHz
PASS
0
MSB
D7
0
Front Mixing ON/OFF
LSB
D0
Mode
D6
D5
0
D4
D3
D2
0
D1
OFF
ON
0
0
1
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BD37069FV-M
(6)
About power on reset
It is possible for the reset circuit inside the IC to initialize when supply voltage is turned on. Please send data to all
address as initial data when the supply is turned on, and turn on mute until all initial data are sent.
Limit
Item
Symbol
tRISE
Unit
Condition
Min
250
Typ
－
Max
－
Rise time of VCCL
VCCL voltage of
release power on
reset
µsec VCCL rise time to 5V
V
VPOR
－
4.1
－
(7)
About start-up and power off sequence on IC
By setting the terminal voltage of HIVOLB and SEL, it is possible to change the output gain.
At the same time, output DC voltage will also be changed at each mode.
HIVOLB
Terminal Voltage
SEL
Terminal Voltage
High-Voltage
ON
High-Voltage mode
GND to 1.0V
2.3V to VCCL
GND to 0.5V
1.5V to VCCL
High-Voltage mode1
High-Voltage mode2
OFF
Please set HIVOLB terminal voltage between the ranges showed by the above tables. If HIVOLB terminal is open,
the terminal voltage will be set to 5V due to the pull-up voltage inside the IC. In this case, the IC will be set to
“High-Voltage OFF” mode. SEL terminal is 4.15V due to the pull-up voltage inside the IC.
Output DC voltage and Output gain, that are changed by the combination of “HIVOLB” terminal and “SEL” terminal
shows as the following table.
VCCH
Supplied Voltage
9 V
11.5 V
17 V
HIVOLB
Terminal Voltage
5 V
0V
(High-Voltage ON)
(High-Voltage OFF)
SEL
Terminal Voltage
0V
(High-Voltage mode1)
Open (4.15 V)
(High-Voltage mode2)
0 V
Open (4.15 V)
(High-Voltage mode2)
(High-Voltage mode1)
Output DC
Bias Voltage
4.35 V
5.6 V
8.35 V
8.3 dB
Level Shift
Output gain
2 dB
4.6 dB
If HIVOLB terminal voltage is changed during its operation, Output DC voltage will be also changed shown as
above. For reducing these variations, turn the power on after setting the status of the HIVOLB and SEL terminal
according to the output gain. The start-up and power off sequence is shown next.
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BD37069FV-M
VCCH Typ
VCCL Typ
t2-t1≧250µsec
t1h-t2≧0µsec
t3-t2h≧0µsec
～
～
～
16.7V
11.3V
～
VCCH
VCCL
7.0V
VCC Typ
t2-t1≧250µsec
7.0V
POR Max.
5.0V
VCCL
5.0V
3.0V
POR Min.
POR Max.
～
1.0V
/VCCH
～
～
OFF Voltage
～
～
～
～
～
POR Min.
3.0V
1.0V
1.0V
～
～
～
～
OFF Voltage
1.0V
t1 t2
t1h t2h
1.0V
t1 t2
Mode = High-Voltage ON
SEL=”0V”/”open” High-Voltage mode1/mode2
200msec
HIVOLB
SEL
I2C-bus Select
Address
Mode = High-Voltage OFF
HIVOLB
20msec
I2C-bus Select
Address
01(hex)
01(hex)
t3
External
MUTE
External
MUTE
normal term
power off
start-up
normal term
power off
start-up
Figure 15. Normal mode(High-Voltage OFF) operation
Figure 16. High-Voltage mode operation
(High-Voltage mode1 and mode2 common)
HIVOLB in the figure above is used to select the Output gain. This IC will become active-state by sending data of Select Address
01(hex) on I2C-bus after 20msec from that VCCL reaches over 7.0V. High-Voltage Output gain is selected by setting SEL terminal
voltage and sending I2C-bus data. Therefore, this command must always be sent in the start-up sequence. In addition, “External
MUTE” in the figure above is the recommended period that the muting is activated from outside the IC. In addition, the starting
sequence of VCCL and VCCH does not have the limit, but please start VCCL earlier to reduce a pop noise.
For HIVOLB terminal, there is countermeasure taken for protection from voltage spikes. But, please take care that the output DC
voltage may fluctuate, if the period of voltage spike is over 50nsec.
(8) About relations of power supply voltage and the DC-bias voltage
Output DC-bias voltage is decided by the regulator that is embedded in this IC, DC-bias does not fluctuate up to a constant level
even if power supply voltage is lowered. The following graphs show the relationship between DC-bias voltage and power supply
voltage.
10
9
8
7
6
5
4
3
2
1
0
10
9
8
7
6
5
4
3
2
1
0
High Voltage mode2
9.3V
5.5V
High Voltage mode1
High Voltage OFF
5.5V
6.5V
5.5V
5.2V
VCCH=9.0V(High-Voltage OFF)
VCCH=11.5V(High-Voltage mode1)
VCCH=17.0V(High-Voltage mode2)
VCCL=9.0V
4
5
6
7
8
9
10
4
5
6
7
8
9
10
VCCL [V]
VCCH [V]
Figure 17. VCCH vs DC Bias
Figure 18. VCCL vs DC Bias
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BD37069FV-M
About advanced switch circuit
【1】Advanced switch technology
1-1. Advanced switch effects
Advanced switch technology is ROHM original technology that can prevent from switching pop noise. If changing the gain
setting (for example Fader) immediatery, the audible signal will become discontinuously and pop noise will be occured.
This Advanced switch technology will prevent this discontinuous signal by completing the signal waveform and will
significantly reduce the noise.
select
slave
data
I2C-bus
28 86
80
If the gain instantly changes after the data is transmitted, the DC
fluctuation will occur as much as before and after the oscillation
different. This technology makes this fluctuation changes slow.
DC level change
Advanced switch
waveform
Figure 19. Advanced switch waveform
This Advanced switch circuit will start operating when the data is transmitted from microcontroller.
Advanced switch waveform is shown as the figure above. For preventing switching noise, This IC will operate optimally by
internal processing after the data is transmitted from microcontroller.
However, sometimes the switching waveform is not like the intended form depends on the transmission timing.
Therefore, below is the example of the relationship between the transmission timing and actual switching time. Please
consider this relationship for the setting.
1-2. The kind of the Transferring Data
・Data setting that is not corresponded to Advanced switch
( (5)Select Address & data Data format without hatching)
There is no particular rule about transferring data.
・Data setting that is corresponded to Advanced switch (Note1)
((5)Select Address & data Data format with hatching)
There is no particular rule about transferring data, but Advanced switch must follow the switching sequence as
mentioned in【2】as follows.
(Note1) The blocks that are corresponded Advanced switch are “Input Gain”,“Fader”and ”Front Mixing
ON/OFF”(In detail, please refer to (5) Select Address & data).
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BD37069FV-M
【2】Data transmission that is corresponded to Advanced switch
2-1. Switching time of Advanced switch
Switching time includes [Twait(Wait time)], [Tsft(A→B switching time)] and [Tsft(B→A switching time)].
25msec is needed per 1 switching. (Tsoft = Twait + 2 * Tsft, Twait=2.3msec, Tsft=11.2msec)
[wait time]
=Twait
[A→B switching time]
=Tsft
[B→A switching time]
=Tsft
Current XdB
Send YdB
Change YdB
W
A → B
B → A
Advanced Switch Time (Tsoft)
Figure 20. About Advanced switching time
In the figure above, Start/Stop state is expressed as “A” and temporary state is expressed as “B”.
The switching sequence of Advanced switch consists of the cycle “A(start)→B(temporary)→A(stop)”. Therefore, switching
sequence will not stop at B state.
For example, switching is performed from A(Initial gain)→B(set gain)→A(set gain) when switching from initial gain to set
gain. And switching time (Tsft) of A→B or B→A are equal.
2-2. Explanation on data transmission’s timing and switching operation.
The following examples show the timing chart from data transmission to starting of switching.
Definition of example expression :
F1=Fader 1ch Front, F2=Fader 2ch Front, R1=Fader 1ch Rear, R2=Fader 2ch Rear
C=Fader Center, S=Fader Subwoofer, MIX=Front Mixing
■
Transmission example 1
This is an example when transmitting data in same block with “enough interval for data transmission”.
(enough interval for data transmission : 1.4 x Tsoft * ”1.4” includes tolerance margin.)
slave select data ack
I2C-bus
80 28 80
(F1 0dB)
80 28 FF
(F1 -∞dB)
Tsoft * 1.4 msec
A → B B → A
W
W
A → B
B → A
Advanced Switch time
F1 output
Figure 21. Transmission example 1
■
■
■
Transmission example 2
This is an example when the transmission interval is not enough (smaller than “Transmission example 1”).
When the data is transmitted during first switching operation, the second data will be reflected after the first switching
operation. In this case, there is no wait time (Twait) before the second switching operation.
slave select data ack
I2C-bus
80 28 80
(F1 0dB)
80 28 FF
(F1 -∞dB)
W
A → B
B → A
A → B
B → A
Advanced Switch time
F1 output
Figure 22. Transmission example 2
24/37
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TSZ22111・15・001
BD37069FV-M
■
Transmission example 3
This is an example when transmission interval is smaller than “Transmission example 2”).
When the data is transmitted during the first switching operation, and transmission timing is just during A→B switching
operation, the second data will be reflected at B→A switching term in case of Fader.
slave select data ack
I2C-bus
80 28 80
(F1 0dB)
80 28 FF
(F1 -∞dB)
W
A → B
B → A
Advanced Switch time
F1 output
Figure 23. Transmission example 3
Please take care as follows when transmitting data to multiple channels.
It is possible that Lch and Rch in same block(Front/Rear/Center,Subwoofer) can be switched at the same timing.
For example, if the data transmission is set as the figure below, F1 and F2 can be switched at the same timing.
(Data ①is sent for F1 (Lch) and data ②is sent for F2 (Rch).)
Twait (designed to 2.3 msec) is the wait time for starting switching.
Twait may change from 1.2msec (Min.) to 4.6msec (Max.) by considering tolerance margin.
80 28 ｘｘ
80 29 ｘｘ
①
②
I2C-bus
T
ꢀ＜ Twait
②-①
W
A → B
B → A
①
Advanced Switch time
OutputꢀF1
Initial
Initial
Initial → ①
Initial → ②
OutputꢀF2
②
Figure 24. The operation during multi-channels (Lch, Rch) data transmission (smaller than Twait interval).
Next, if data ②is not transmitted during the Twait, the switching operation will be as the figure below.
80 28 ｘｘ
80 29 ｘｘ
①
②
I2C-bus
T
ꢀ＞ Twait
A → B
②-①
W
B → A
A → B
B → A
Advanced Switch time
OutputꢀF1
Initial
Initial
Initial → ①
①
OutputꢀF2
Initial → ②
②
Figure 25. The operation during multiple channels (Lch, Rch) data transmission (larger than Twait interval).
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2-3. Multiple blocks data transmission timing and switching operation.
In case the data is transmitted to multiple blocks, the processing is performed internally by BS (Block state) unit.
Starting order of Advanced switch is determined by BS unit.
■Transmission example 1
slave select data ack
I2C-bus
80 28 80
(F1 0dB)
80 2A 80
(R1 0dB)
80 2C 80
(C 0dB)
F1 Advanced Switch
R1 Advanced Switch
C Advanced Switch
W
A → B
B → A
A → B
B → A
A → B
B → A
Advanced Switch time
F1 output
R1 output
C output
Figure 26. Multi-blocks data transmission timing
There are no timing regulations of I2C-bus data transmission. But next switching will start after the end of the current
switching. The timing of Advanced switch is depended, not on the order of data transmission, but on the order of the figure
below. The blocks in the same group (For example, BS1, BS3) can start switching at the same time.
BS0
BS3
BS1
BS2
Input
Gain
Fader
Center
Fader
1ch Front
Fader
1ch Rear
‘h06
‘h2C
‘h28
‘h2A
Fader
Subwoofer
Fader
2ch Front
Fader
2ch Rear
‘h2D
‘h29
‘h2B
Front
Mixing
‘h30
Select address
Figure 27. The turn of Advanced switch start
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■Transmission example 2
In case of that the transmission order is different with actual switching order.
ex：①F1 -6dB
80 xx ｘｘ
ꢀ ②F1 -20dB
①
② ③ ④
ꢀ ③C -6dB
ꢀ ④R1 -6dB
I2C-bus
F1 Advanced Switch
R1 Advanced Switch
C Advanced Switch
F1 Advanced Switch
W
A → B
B → A
A → B
B → A
A → B
B → A
A → B
B → A
Advanced Switch time
OutputꢀF1
Initial Initial → ①
①
① → ②
②
OutputꢀR1
OutputꢀC
Initial
Initial
Initial → ④
④
Initial → ③
③
Figure 28. In case of the transmission order is different with actual switching order
If the data of Front/Rear/Center setting is transmitted during the switching of Front, Rear and Center switching have
priority over Front switching. In order to proceeding the switching starts as the data transmission order, please transmit
the next data after the end of current switching.
■Transmission example 3
If Refresh data that is same as current setting is transmitted, gain switching operation will not start.
The below figure shows the case of transmitting data after Refresh data.
slave select data ack
I2C-bus
80 28 80
(F1 0dB)
80 28 80
(F1 0dB)
80 2A 80
(R1 0dB)
Refresh Data
F1 Advanced Switch
R1 Advanced Switch
W
A → B
B → A
A → B
B → A
Advanced Switch time
Figure 29. In case of the transmission of Refresh data
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Application Example
VCCL=9V
10µF
VCCH=11.5V/17V
10µF
INC
INS
IG1
IG2
OUTC OUTS OUTR1 OUTR2 OUTF1 OUTF2 INF2 INF1 INR2
INR1
VREF
SCL
GND SDA
10µF 10µF
10µF
10µF
10µF
10µF
10µF 10µF 2.2µF
2.2µF 2.2µF
2.2µF 2.2µF 2.2µF
10µF
28
40
39
38
37
35
34
33
32
31
30
29
27
26
24
22
25
23
21
36
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
Level
Shift
100kΩ 100kΩ 100kΩ
100kΩ 100kΩ
100kΩ
I2C-bus LOGIC
REG(4.15V)
Sub SEL
■Fader : +23dB～-79dB、-∞/1dBstep
■Input Gain : +23dB～-15dB/1dBstep
■Front Mixing : on/off
Sub
Gain adjust
Main Gain adjust
2nd order LPF
★ Advanced Switch
■2nd order LPF: fc=70kHz
■Main/Sub Gain Adjust 0dB/6dB
■Anti-GSM circuit
Rear SEL
■High Voltage Output
Front
SEL
Level Shift = 2dB(normal mode)
Level Shift = 4.6dB(Hi-voltage mode1)
Level Shift = 8.3dB(Hi-voltage mode2)
★
Input Gain
Input selector (2 single-ende- d and 4 stereo ISO)
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
GND
ISO
amp
amp
amp
amp
amp
amp
amp
amp
100kΩ
100kΩ
250kΩ
250kΩ 250kΩ
250kΩ
250kΩ 250kΩ 250kΩ
250kΩ 250kΩ 250kΩ
250kΩ 250kΩ 250kΩ
100kΩ
250kΩ 250kΩ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
2.2µF
2.2µF
2.2µF
2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 2.2µF 2.2µF 10µF 10µF
2.2µF 2.2µF
MIN
SEL
HIVOLB
A1
A2
B1
B2 CP1 CN CP2 DP1 DN DP2 EP1 EN EP2 FP1 FN1 FN2 FP2
Figure 30. Application Example
UNIT
RESISTANCE: Ω
CAPACITANCE: F
Notes on wiring
①Please connect the decoupling capacitor of a power supply as close as possible to GND.
②Lines of GND shall be one-point connected.
③Wiring pattern of Digital unit shall be away from that of analog unit and crosstalk shall not be acceptable.
④Lines of SCL and SDA of I2C-bus shall not be parallel if possible. The lines shall be shielded, if they are adjacent
to each other.
⑤Lines of analog input shall not be parallel if possible. The lines shall be shielded, if they are adjacent to each other.
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I/O Equivalence Circuit
Terminal
No
Terminal
Name
Terminal
Voltage
Equivalence Circuit
Terminal Description
A terminal for signal input
1
A1
A2
4.15V
VCCL
2
The input impedance is 100kΩ(Typ).
29
30
31
32
33
34
18
INC
INS
INR1
INR2
INF1
INF2
MIN
100kΩ
4.15V
GND
Input terminal
3
4
B1
B2
4.15V
Single/Differential mode is selectable.
The input impedance is 250kΩ(Typ).
5
CP1
CN
VCCL
6
7
CP2
DP1
DN
8
9
10
11
12
13
14
15
16
17
27
28
DP2
EP1
EN
250kΩ
4.15V
GND
EP2
FP1
FN1
FN2
FP2
IG2
IG1
Input gain output terminal
4.15V
VCCL
GND
Fader Output terminal
VCCH
35
36
37
38
39
40
OUTF2
OUTF1
OUTR2
OUTR1
OUTS
(1) 4.35V
(2) 5.6V
(1) Normal mode : 4.35V
(2) High-Voltage mode1 : 5.6V
(3) High-Voltage mode2 : 8.35V
(3) 8.35V
OUTC
GND
The figures in the pin explanation and input/output Equivalence circuit are reference values, it doesn’t guarantee exact values.
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Terminal
No
Terminal
Name
Terminal
Voltage
Equivalence Circuit
Terminal Description
VCCL
Output gain control terminal
20
HIVOLB
5V
5V
Low(0V supply) : High-Voltage ON
100kΩ
High(terminal open) : High-Voltage OFF
1.65V
GND
Power supply terminal.
21
26
VCCH
VCCL
17/11.5/9V
9V
Terminal for clock input of I2C-bus
communication.
VCCL
－
22
SCL
Note: When this pin is shorted to next pin(VCCH), it
may result in property degradation and destruction of
the device.
1.65V
GND
Terminal for data input of I2C-bus
communication.
VCCL
－
23
SDA
1.65V
GND
Ground terminal.
BIAS terminal.
24
25
GND
0V
VCCL
VREF
4.15V
Voltage for reference bias of analog signal
system. The simple precharge circuit and
simple discharge circuit for an external
capacitor are built in.
12.5kΩ
4.15V
GND
High Voltage Output Select terminal
19
SEL
4.15V
VCCL
Low(0V supply) : High-Voltage mode1
High(terminal open) : High-Voltage mode2
250kΩ
GND
The figures in the pin explanation and input/output Equivalence circuit are reference values, it doesn’t guarantee exact values.
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Application Information
1) Absolute maximum rating voltage
When voltage is impressed to VCCL/VCCH exceeding absolute maximum rating voltage, circuit current increases
rapidly and it may result in property degradation and destruction of a device. When impressed by a VCCL terminal
(26pin) especially by surge examination etc., even if it includes an of operation voltage +surge pulse component,
be careful not to impress voltage (about 14V) much higher than absolute maximum rating voltage. And, be careful
that there is no more than 18V on the VCCH terminal (21pin).
2) About a signal input part
In the signal input terminal, the value of the input coupling capacitor C(F) should be sufficient to match the value
of input impedance RIN(Ω) inside the IC. The first HPF characteristic of CR is as shown below.
G[dB]
C [F]
0
A(f)
G
RIN
Frequency[Hz]
f
(2πf・C・RIN)2
A(f)=
1+(2πf・C・RIN)2
Figure 31. Input Equivalence Circuit
3) About output load characteristics
The usages of load for output are below (reference). Please use the load more than 10 kΩ(Typ).
Output terminal
Terminal
Terminal
Name
IG1
Terminal
No.
Terminal
Name
OUTF1
OUTF2
Terminal
No.
Terminal
Name
OUTR1
OUTR2
Terminal
No.
Terminal
Name
OUTC
OUTS
No.
28
27
36
35
38
37
40
39
IG2
3
2.5
2
6
5
4
3
2
1
1.5
1
IG1/IG2
VCCL=9V
VCCH=17V
THD+N=1%
OUTF1/OUTF2
VCCL=9V
VCCH=17V
THD+N=1%
BW=400 to 30kHz
BW=400 to 30kHz
0.5
0
0
100
1k
10k
100k
100
1k
10k
100k
Load Resistance [Ω]
Load Resistance [Ω]
Figure 32. Output load characteristic at VCCL=9V, VCCH=17V(Reference)
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BD37069FV-M
4) About HIVOLB terminal(20pin) when power supply is off
Any voltage shall not be supplied to HIVOLB terminal (20pin) when power-supply is off. Please insert a resistor (about
2.2kΩ) to HIVOLB terminal in series, in case voltage is supplied to HIVOLB terminal. (Please refer Application Circuit
Diagram.)
5) About signal input terminals
Because the inner impedance of the terminal becomes 100 kΩ or 250 kΩ when the signal input terminal makes a
terminal open, the plunge noise from outside sometimes becomes a problem.When there is an unused signal input
terminal, design so it is shorted to ground.
6) About changing gain of Input Gain and Fader Volume
When increasing the input gain and fader volume, especially those exceeding 20dB, the switching pop noise sometimes
becomes big. In this case, we recommend changing the gain in 1 dB steps, without abruptly changing the gain at once.
Also, the pop noise can sometimes be reduced by increasing the advanced switch time.
7) About inter-pin short to VCCH
VCCH terminal(21pin) is assumed at applied high voltage(Max 17.8V) for 5.2VRMS(Max) output. And so, avoid short
between VCCH and SCL. When Inter-pin shorts occur, circuit current increases rapidly, and it may result in property
degradation and destruction of a device.
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Operational Notes
1.
2.
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the
digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog
block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and
aging on the capacitance value when using electrolytic capacitors.
3.
4.
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5.
Thermal Consideration
Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may
result in deterioration of the properties of the chip. In case of exceeding this absolute maximum rating, increase the
board size and copper area to prevent exceeding the maximum junction temperature rating.
6.
7.
Recommended Operating Conditions
These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.
The electrical characteristics are guaranteed under the conditions of each parameter.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
8.
9.
Operation Under Strong Electromagnetic Field
Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
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BD37069FV-M
Operational Notes – continued
10. Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
11. Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
12. Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 33. Example of monolithic IC structure
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BD37069FV-M
Ordering Information
B D 3 7 0 6 9
F
V -
ME 2
Package
FV: SSOP-B40
Product Rank
M: for Automotive
Part Number
Packaging and forming specification
E2: Embossed tape and reel
(SSOP-B40)
Marking Diagram
SSOP-B40(TOP VIEW)
Part Number Marking
LOT Number
BD37069FV
1PIN MARK
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Physical Dimension, Tape and Reel Information
Package Name
SSOP-B40
(Max 13.95 (include. BURR)
(UNIT ; mm)
PKG : SSOP-B40
Drawing No. EX157-5001
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BD37069FV-M
Revision History
Date
Revision
001
Changes
12.MAY.2016
New Release
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Notice
Precaution on using ROHM Products
(Note 1)
1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment
,
aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,
bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales
representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any
ROHM’s Products for Specific Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.
Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the
use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our
Products under any special or extraordinary environments or conditions (as exemplified below), your independent
verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (even if you use no-clean type fluxes, cleaning residue of
flux is recommended); or Washing our Products by using water or water-soluble cleaning agents for cleaning
residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse. is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PAA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PAA-E
Rev.003
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Pro ducts, you are requested to care fully read this document and fully understand its contents.
ROHM shall not be in an y way responsible or liable for failure, malfunction or accident arising from the use of a ny
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this docume nt is current as of the issuing date and subj ect to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the la test information with a ROHM sale s
representative.
3. The information contained in this doc ument is provi ded on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate an d/or error-free. ROHM shall not be in an y way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
Datasheet
BD37069FV-M - Web Page
Part Number
Package
Unit Quantity
BD37069FV-M
SSOP-B40
2000
Minimum Package Quantity
Packing Type
Constitution Materials List
RoHS
2000
Taping
inquiry
Yes
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