BD41003FJ-C_技术文档

Datasheet

CXPI Transceiver for Automotive

BD41003FJ-C

General Description

Key Specifications

BD41003FJ-C can reduce EMI (Electromagnetic

Emission) noise of AM frequency band in comparison

with BD41000AFJ-C. BD41003FJ-C is a transceiver for

the CXPI (Clock Extension Peripheral Interface)

communication. Switching between Master/Slave Mode

can be done using the external pin (the MS pin). Low

power consumption during standby (non-communication)

using Power Saving function. Arbitration function stops

transmitter output upon the detection of BUS data

collision. Also Fail-safe function stops transmitter output

upon the detection of under voltage or temperature

abnormality.

◼Power Supply Voltage:

+7 V to +18 V

◼Absolute Maximum Rating of BAT: -0.3 V to +40 V

◼Absolute Maximum Rating of BUS: -27 V to +40 V

◼Power OFF Mode Current:

3 μA (Typ)

-40 °C to +125 °C

◼Operating Temperature Range:

Package

SOP-J8

W(Typ) x D(Typ) x H(Max)

4.90 mm x 6.00 mm x 1.65 mm

Features

◼ AEC-Q100 Qualified^{(Note 1)}

◼ CXPI Standards Qualified

◼ Transmission Speed Range from 18.8 kbps to 20 kbps

◼ Master/Slave Switching Function

◼ Microcontroller Interface Corresponds to 3.3 V/5.0 V

◼ Built-in Terminator (30 kΩ(Typ))

◼ Power Saving Function

◼ Data Arbitration Function

SOP-J8

◼ Built-in Under Voltage Lockout (UVLO) Function

◼ Built-in Thermal Shutdown (TSD) Function

◼ Low Electro Magnetic Interference (EMI)

◼ High Electro Magnetic Susceptibility (EMS)

◼ High Electro Static Discharge (ESD) Robustness

(Note 1) Grade 1

Applications

◼ Automotive Networks

Typical Application Circuit

CXPI

BUS

V_ECU

Master node

Regulator

10kΩ

2.7kΩ

MS(8)

BD41003FJ-C

GND(5)

VDD

INT

BAT(7)

RXD(1)

TXD(4)

CLK(3)

NSLP(2)

RXD

100nF

1nF

Micro

TXD

CLK

I/O

Controller

(Note 2)

1kΩ

BUS(6)

GND

Slave node

Regulator

(Note 3)

10kΩ

2.7kΩ

MS(8)

BD41003FJ-C

GND(5)

VDD

INT

BAT(7)

RXD

RXD(1)

100nF

220pF

Micro

TXD

CLK

I/O

TXD(4)

CLK(3)

NSLP(2)

Controller

(Note 2)

BUS(6)

GND

(Note 2) INT: Interrupt, RXD: UART RXD, TXD: UART TXD, CLK: Clock, I/O: General Purpose I/O

(Note 3) While using slave, it is no problem that the CLK pin is opened in the case of non-using the CLK output.

Figure 1. Typical Application Circuit

Consider the actual application design confirming the following linked document before applying this product.

◼ Application Note

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays

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Pin Configuration

(TOP VIEW)

RXD

NSLP

CLK

MS

1

8

BAT

2

3

7

6

5

BUS

GND

TXD

4

Figure 2. Pin Configuration

Pin Description

Table 1. Pin Description

Received data output pin

Pin No.

Pin Name

RXD

Function

1

Power saving control input pin

(“H”: Change to “Codec Mode”,

“L”: Change to “Power OFF Mode”)

2

NSLP

CLK

Clock signal input/output pin

(Master setting: Input, Slave setting: Output)

3

4

5

6

7

TXD

GND

BUS

BAT

Transmission data input pin

Ground

CXPI BUS pin

Power supply pin

Master/Slave switching pin

(“H”: Master, “L”: Slave)

8

MS

Block Diagram

7

BAT

Thermal

Shutdown

(TSD)

Under Voltage

Lockout

(UVLO)

Power on

Reset

(POR)

Regulator

To each block

MS

8

1

LOGIC

Low Pass

Filter

RXD

6

BUS

Decoder

Wakeup

Timer

Slope Control

4

TXD

Arbiter

Encoder

Dominant

Timeout Counter

(DTC)

Controller

Slope

Timer

2

3

NSLP

CLK

Timing

Generator

Oscillator

5

GND

Figure 3. Block Diagram

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Description of Blocks

State Transition Diagram

BD41003FJ-C has “Power OFF Mode”, “Through Mode”, “RX Through Mode” other than “CODEC Mode” for power saving

control. Each mode is controlled by the NSLP, BUS, and TXD pins.

Non-power Supply

When V_BAT<V_PORis established

in all modes, It shifts to

Non-power supply state

V_BAT≥V_POR

Power OFF Mode

Hi-Z(H) fixed

Weak pull-up

RXD output

CLK output (slave)

BUS output

BUS terminator

BUS

TXD

Wakeup pulse detect^{(Note 4)}

Wakeup input detect^{(Note 5)}

NSLP=L

NSLP=H

RX Through Mode

Output is reversed at every

CODEC Mode

Through Mode

Output BUS signal

Decode BUS signal,

and output it

RXD output

BUS signal rising edge

by through

NSLP=H

BUS clock output

Hi-Z(H) fixed

CLK output (slave)

BUS output

CLK output (slave)

BUS output

CLK output (slave)

BUS output

Code TXD signal,

and output it.

Output TXD signal

by through

Hi-Z(H) fixed

30 kΩ(Typ) pull-up

BUS terminator

(Note 4) Refer to the Wakeup pulse detection LO time of the electrical characteristics.

(Note 5) Refer to the Wakeup input detection time (TXD) of the electrical characteristics.

Figure 4. State Transition Diagram

While using master, the CLK pin becomes input pin, and uses to input BUS clock in “CODEC Mode”.

Power OFF Mode

“Power OFF Mode” reduces power consumption by not supplying powers to any circuits other than necessary ones for

“Wakeup pulse detection (the BUS pin)” and “Wakeup input detection (the TXD pin)”.

When the TXD pin is “H”, Wakeup input is detected, and then changes to “Through Mode”. If shift to “Power OFF Mode”,

set the TXD pin to “L” and then set the NSLP pin to “L”.

“Through Mode” and “RX Through Mode” cannot change to “Power OFF Mode” directly. Change it via “CODEC Mode” by

setting the NSLP pin to “H”.

Through Mode

“Through Mode” does not process Coding/Decoding. It only drives signals from the TXD pin to the BUS pin and from the

BUS pin to the RXD pin directly.

When sending Wakeup pulse, change to “Through Mode” with the TXD pin as “H”.

RX Through Mode

“RX Through Mode” reverses the RXD pin output at each rising edge of the BUS pin.

When detecting Wakeup pulse in “Power OFF Mode”, monitor the change of the RXD pin.

Not a rising edge of BUS, BD41003FJ-C reverses RXD output at the time of RX through mode transition only when it

changes from a power off mode to RX through mode in the first Dominant signal after power off mode transition.

BD41003FJ-C reverses the RXD output afterwards whenever BD41003FJ-C recognizes the rising edge of BUS signal

after the second.

CODEC Mode

“CODEC Mode” is the mode of CXPI communication. NSLP should be “H” for the chip to enter “CODEC Mode”.

The RXD output changes synchronized with the falling edge of the CLK pin when in the Master setting, and with the falling

edge of the BUS pin when in the Slave setting. The BUS output is delayed for 2.0±0.5 T_bitfrom the TXD input, and the

RXD output is delayed for 1.0±0.5 T_bitfrom the BUS input.

For about the jitter of the clock signal supplying the CLK pin when in the Master setting, input the signal satisfies the CXPI

standard (±1.0 %) considering the jitters occurs in the BD41003FJ-C (±0.2 %).

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Description of Blocks – continued

Sequence Diagram

Show the examples of the BD41003FJ-C control sequence which corresponding to the mode management of CXPI

standard, “Sleep Mode”, “Standby Mode” and “Normal Mode”.(Refer to the CXPI standard for specifications about the

detail of mode management.)

1. The Sequence from “Normal Mode” to “Sleep Mode”

When changing to “Sleep Mode”, the NSLP pin should be switched from “H” to “L”, and then turn the IC to “Power OFF

Mode”. The TXD pin has built-in pull-down resistor in case of a fail-safe. Fix the TXD pin to “L” before BD41003FJ-C

enters “Power OFF Mode” to prevent extra currents from MCU side while “Sleep Mode”.

Fix the CLK pin to “L” just like the TXD pin, because the pull-down resister of the CLK pin is active in the case of Master

setting.

Master Node

Slave Node

Micro Controller

(MCU)

Micro Controller

(MCU)

BD41003FJ-C

Sleep condition

establish

TXD (Sleep flame)

Sleep flame transmit

Sleep flame detect

Sleep flame transmit

(with coding)

Sleep flame transmit

(with coding)

(Note 6)

Sleep flame

RXD (Sleep flame)

Sleep flame detect

Normal Mode

CODEC Mode

CLK (“L” fixed)

CLK output stop

TXD output control

Power OFF indicate

BUS clock supply stop

TXD (“L” output)

NSLP (“L” fixed)

TXD (“L” output)

TXD output control

Power OFF indicate

NSLP (“L” output)

Sleep Mode

Power OFF Mode

Sleep Mode

(Note 6) Refer to sleep flame shown in the JASO D015-3 standard.

Figure 5. The Sequence from “Normal Mode” to “Sleep Mode”

Master Node

Operating

mode

CODEC Mode

Power OFF Mode

NSLP

Sleep flame transmit

TXD

CLK

RXD

Sleep flame receive

(Note 7)

Tclock_stop_m

BUS

Sleep flame

(Note 7) Refer to Tclock_stop_m shown in the JASO D015-3 standard.

Figure 6. The Timing Chart from “Normal Mode” to “Sleep Mode” (Master)

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1. The Sequence from “Normal Mode” to “Sleep Mode” – continued

Slave Node

Operating

CODEC Mode

mode

Power OFF Mode

NSLP

TXD

RXD

Sleep flame receive

Sleep flame

(Note 8)

Tsleep_s

BUS

(Note 8) Refer to Tsleep_s shown in the JASO D015-3 standard.

Figure 7. The Timing Chart from “Normal Mode” to “Sleep Mode” (Slave)

2. The Sequence from “Sleep Mode” to “Normal Mode” (Master Node Trigger)

To wakeup the node by an internal factor, switch the IC to “CODEC Mode” by setting the NSLP pin to “H”. The TXD pin

should be “H” within 30 µs before changing from “Power OFF Mode” to “CODEC Mode” in order to prevent abnormal the

BUS output or the RXD output.

In the case of slave node, BD41003FJ-C reverses RXD output at every rising edge of the BUS signal after receiving the

BUS clock. When start wakeup detecting at the RXD first falling edge, start micro controller initializing operation. To

establish wakeup pulse, check if the RXD pin is “H” after initializing operation or detect RXD rising edge.

To change from “Standby Mode” to “Sleep Mode” because the slave node cannot receive the second rising pulse within

the specified time, return to “Power OFF Mode” with the NSLP pin as “L” again after the change to “CODEC Mode” with

the NSLP pin as “H”.

Master Node

Slave Node

Micro Controller

(MCU)

Micro Controller

(MCU)

BD41003FJ-C

Sleep Mode

Wakeup factor

CLK (Output start)

CLK output start

TXD output control

Power OFF reset

Power OFF Mode

Sleep Mode

Standby Mode

TXD (“H” output)

NSLP (“H” output)

CLK transmit

(with coding)

Wakeup pulse receive

(First rising edge)

BUS clock supply start

RXD (“L” output)

Normal Mode

CODEC Mode

Wakeup detect

Initializing

operation

Wakeup pulse receive

(Second rising edge)

RXD (“H” output)

Wakeup decision

After that, Output reverse by

every BUS signal pull up edge

RX Through Mode

Standby Mode

TXD (“H” output)

NSLP (“H” output)

TXD output control

Power OFF control

CODEC Mode

Normal Mode

Figure 8. The Sequence from “Sleep Mode” to “Normal Mode” (Master Node Trigger)

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2. The Sequence from “Sleep Mode” to “Normal Mode” (Master Node Trigger) – continued

Master Node

Operating

mode

Power OFF Mode

CODEC Mode

Within 30μs

NSLP

TXD

CLK

RXD

BUS

Figure 9. The Timing Chart from “Sleep Mode” to “Normal Mode” (Master Node Trigger, Master)

Slave Node

Operating

mode

RX Through

Mode

Pow er OFF Mode

CODEC Mode

NSLP

TXD

Within 30μs

CLK

RXD

BUS

Wakeup pulse

(Clock signal)

Figure 10. The Timing Chart from “Sleep Mode” to “Normal Mode” (Master Node Trigger, Slave)

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Sequence Diagram – continued

3. The Sequence from “Sleep Mode” to “Normal Mode” (Slave Node Trigger)

When waking up the slave node by an internal factor, shift to “Through Mode” by setting the TXD pin to “H” and then

send wakeup pulse.

After receiving the wakeup pulse in the Master Node, the RXD output reverses at every rising edge of the BUS signal.

Master node should establish wakeup pulse at the RXD first falling edge.

To change from “Standby Mode” to “Sleep Mode”, in case the master node cannot receive BUS clock within the

specified time, return to “Power OFF Mode” with the NSLP pin as “L” again after the change to “CODEC Mode” with the

NSLP pin as “H”.

Master Node

Slave Node

Micro Controller

(MCU)

MicroController

(MCU)

BD41003FJ-C

Sleep Mode

Wakeup factor

Power OFF Mode

TXD (“H” output)

Wakeup BD41003FJ-C

when it exceeds tTXD_WAKEUP

TXD output control

Sleep Mode

Power OFF Mode

TXD (Wakeup pulse)

Wakeup pulse transmit

(without coding)

Wakeup pulse receive

RXD (“L” output)

Wakeup pulse

Wakeup decision

CLK output start

After that, Output reverse at

every BUS signal rising edge

Standby Mode

CLK (Output start)

In the caseofit cannotreceive

clock within the role time,

Wakeup pulse retransmit

RX Through Mode

Standby Mode

Through Mode

TXD (“H” output)

NSLP (“H” output)

TXD output control

Power OFF control

Clock transmit

(with coding)

Clock receive

RXD(Clock signal)

Normal Mode

BUS clock supply start

CODEC Mode

Clock signal detect

Power OFF control

Through output

NSLP (“H” output)

CODEC Mode

Normal Mode

Figure 11. The Sequence from “Sleep Mode” to “Normal Mode” (Slave Node Trigger)

Master Node

Operation

mode

Power OFF Mode

Rx Through Mode

CODEC Mode

NSLP

TXD

Within 30μs

CLK

RXD

BUS

(

10)

Note

(Note 9)

Ttx_wakeup

Tclock_start_m

(Note 9) Refer to Ttx_wakeup shown in the JASO D015-3 standard.

(Note 10) Refer to Tclock_start_m shown in the JASO D015-3 standard.

Figure 12. The Timing Chart from “Sleep Mode” to “Normal Mode” (Slave Node Trigger, Master)

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3. The Sequence from “Sleep Mode” to “Normal Mode” (Slave Node Trigger) – continued

Slave Node

Operation

mode

Power OFF Mode

Through Mode

CODEC Mode

Wakeup pulse

NSLP

_{Ttx_wakeup_space}(Note 12)

TTXD_wakeup

TXD

_{Ttx_wakeup}(Note 11)

CLK

RXD

BUS

(Note 11) Refer to Ttx_wakeup shown in the JASO D015-3 standard.

(Note 12) Refer to Ttx_wakeup_space shown in the JASO D015-3 standard.

Figure 13. The Timing Chart from “Sleep Mode” to “Normal Mode” (Slave Node Trigger, Slave)

Transmission and Reception Starting Effective Time after Shift to CODEC Mode

After changing to “CODEC Mode” by setting the NSLP pin to “H”, BD41003FJ-C detect the clock period and then learn the

LO width of logic value1. To secure the learning time of the LO width of logic value1, start to transmit and receive data after

the time equal to 16 T_bitclocks at least. (After setting the NSLP pin to “H”, 6 T_bit(maximum) clocks are necessary to output

clock signal to the BUS signal input or the CLK signal input.)

Master

Prohibit Transmit and Receive

Transmit and Receive possible

state

Master

CLK

Master

NSLP

Max 6Tbit

16Tbit

BUS

Slave

RXD

Slave

NSLP

16Tbit

Max 6Tbit

Slave

CLK

Slave

state

Transmit and Receive

possible

RX

Through

PowerOFF

Prohibit Transmit and Receive

Figure 14. The Actual Time of Transmission and Reception after “CODEC Mode” Changing

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Arbitration Function

To carry out collision resolution functions that defined by CXPI specification, both micro controller and BD41003FJ-C

share functions. Basically, BD41003FJ-C arbitrates the bit data in the UART flame and micro controller arbitrates the byte

data between the UART flames.

1. In case of collision is happened by transmitting from other node at the same time

In the case of collision (arbitration defeat) is happened by transmitting from other node at the same time, it stops the

transmission of remaining UART flame data after the collision from micro controller side. It is necessary to have the

interval of 1 T_bitor more (BUS baud rate period) to transmit again after arbitration defeat. Set the wait time in consideration

of the frequency deviation of the baud rate clock in micro controller side and BUS side and the delay at UART circuit in

micro controller side.

When arbitration defeat is detected,

more than 1 Tbit interval is needed at next transmition

Start

Bit

Stop

Bit

Start

Bit

1

0

1

0

1

0

1

0

1

0

1

TXD

Arbitration defeat

2.0±0.5Tbit delay

1

0

1

0

BUS

RXD

1.0±0.5Tbit delay

Start

Bit

Stop

Bit

Start

Bit

0

1

Transmit

prohibit signal

(Internal signal)

While transmit prohibit signal is set “H”,

BUS output is stopped

Arbitration

BUS output can generate

defeat

(TXD≠RXD)

When arbitration defeat is detected,

remainig UART output data is stopped

Figure 15. Arbitration Function (When the Collision is detected after Data Transmission)

2. In case of collision is detected by receiving from other node before transmission is started.

After BD41003FJ-C detects transmission of other node on BUS, BD41003FJ-C stops to transmit data for 10 T_bitperiod not

to destroy other node transmission. If the TXD signal is inputted to BD41003FJ-C while stopping to transmit data,

BD41003FJ-C stops to transmit data for further 10 T_bitperiod of the transmit data.

When arbitration defeat is detected,

more than 1 Tbit interval is needed at next transmition

Start

Bit

Stop

Bit

Start

Bit

1

0

1

0

1

0

1

0

1

TXD

2.0±0.5Tbit delay

0

1

0

1

BUS

RXD

1.0±0.5Tbit delay

Start

Bit

Stop

Bit

0

1

Transmit

prohibit signal

(Internal signal)

While transmit prohibit signal is set “H”,

BUS output is stopped

Receive

detect

BUS output can generate

When the receive data is detected BUS output is stopped for 10 Tbit period.

and then, while stopping BUS output, if TXD signal is inputted,

BUS output is stopped for further 10 Tbit period

Figure 16. Arbitration Function (When receive data is detected before transmission)

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Arbitration Function – continued

3. In case of arbitration function failure is happened because micro controller outputs transmission data to

BD41003FJ-C at the out of range of BD41003FJ-C arbitration function.

The BUS output is delayed for 2.5 T_bit(Maximum) from the TXD input and the RXD output is delayed for 1.5 T_bit(Maximum)

from BUS input. When micro controller outputs transmission data to BD41003FJ-C at the timing that shown in Figure 17,

CXPI frame of other node is destroyed because BD41003FJ-C outputs PID just after receive PID.

Micro controller should stop transmission while receiving UART flame.

Figure 17 shows the example in case of 2.0 T_bitdelay from the TXD input to the BUS output and 1.0 T_bitdelay from the

BUS input to the RXD output.

Since the transmission delay is 2.0± 0.5 Tbit, there is a timing that the data transmitted to the TXD is

Range of stopping transmission by detecting receive data from other node

(explained operation in previous page)

transmitted to the BUS before the stopbit detection (Maximum 2.5 Tbit) on the micro controller side

(The time to stop TXD after detecting stopbit depends on the processing on the micro controller side)

Start

1

0

TXD

0

1

0

Bit

CXPI frame of other node is destroyed

2.0± 0.5Tbit delay

PID transmission from other node

because irregular own node PID is outputted

1

0

1

0

1

0

1

0

1

0

1

BUS

RXD

1.0± 0.5Tbit delay

Start

Bit

Stop

Bit

Start

Bit

0

1

Transmit

prohibit signal

(Internal signal)

While transmit prohibit signal is set “H”,

BUS output is stopped

Receive

detect

BUS output can generate

When the receive data is detected BUS output is stopped for 10 Tbit period.

Figure 17. Arbitration Function (When micro controller detects receive data with stopbit)

In case of supporting event trigger method of CXPI standard, not to destroy CXPI flame, micro controller should detect

startbit of UART receive flame before transmitting PID, and then stop transmission of PID.

Fail-safe Function

BD41003FJ-C has built in fail-safe mode such as DTC (TXD Dominant Abnormal Detection Circuit), TSD (Abnormal

Thermal Detection Circuit) and UVLO/POR (Under Voltage Lockout Circuit/Power ON Reset Circuit).

The operations of each abnormal situation are as follows;

Table 2. Fail-safe Functions

CLK Output

(While using

slave)

Fail-safe Function

State Transition

No change

BUS Output

RXD Output

CODEC Mode: Logical value1

output^{(Note 13)}

Through Mode: Hi-Z(H) fixed

BUS signal

output

DTC abnormality

Hi-Z(H) fixed

TSD abnormality

UVLO abnormality

POR abnormality

No change

Hi-Z(H) fixed

Power OFF Mode

(Note 13) In the case of TXD fixed L, Logical value0 is outputted only in first 10bit. Logical value1 is outputted before DTC abnormality is detected.

When “L” time of the TXD pin is more than t_DTC, DTC (Dominant Timeout Counter) detects abnormality, and then it stops

output. It can return to normal status with the TXD pin as “H”

When the junction temperature exceeds T_TSD,TSD (Thermal Shutdown) circuit detects abnormality, and then it stops

output. It can return to normal status when the temperature drops T_{TSD_HYS.}

Operations of UVLO (Under Voltage Lockout) and POR (Power ON Reset) are as follows;

When supply voltage is V_UVLOor less, UVLO abnormality is detected, and then the BUS, the RXD and the CLK outputs

(only slave) are fixed Hi-Z(H).

When power supply When power supply is V_UVLOor more, transceiver restarts output. When supply voltage drops below

V_POR,POR abnormality is detected, and then it changes to “Power OFF Mode”, and reset status.

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Fail-safe Function – continued

Absolute maximum rating

40V

0V

5V

6.7V 7V

18V

BAT

voltage

POR

Activation range

UVLO

Activation range

Operating guarantee range

UVLO

detection state

Power OFF

Normal operation

Mode

Figure 18. Internal Status and Mode by Supply Voltage

Absolute Maximum Ratings

Table 3. Absolute Maximum Ratings

Parameter

Symbol

Rating

Unit

V

Supply Voltage

V_BAT

V_MS

-0.3 to +40.0

-0.3 to +7.0

-27.0 to +40.0

-0.3 to +7.0

+150

Input Voltage

V

V_NSLP,V_TXD

V_RXD

Output Voltage

Input/Output Voltage

V_BUS

V_CLK

Junction Max Temperature

Storage Temperature

Electro Static Discharge (HBM)^{(Note 14)}

Tjmax

Tstg

°C

V

-55 to +150

4000

V_ESD

(Note 14) JEDEC qualified.

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB boards with thermal resistance taken into consideration by

increasing board size and copper area so as not to exceed the maximum junction temperature rating.

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Thermal Resistance^{(Note 15)}

Table 4. Thermal Resistance

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 17)}

2s2p^{(Note 18)}

SOP-J8

Junction to Ambient

θ_JA

149.3

18

76.9

11

°C/W

Junction to Top Characterization Parameter^{(Note 16)}

Ψ_JT

(Note 15) Based on JESD51-2A(Still-Air)

(Note 16) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 17) Using a PCB board based on JESD51-3(Table 5).

(Note 18) Using a PCB board based on JESD51-7(Table 6).

Table 5. 1 Layer Board

Layer Number of

Material

Board Size

Measurement Board

Single

FR-4

114.3mm x 76.2mm x 1.57mmt

Top

Copper Pattern

Thickness

70µm

Footprints and Traces

Table 6. 4 Layers Board

Board Size

Layer Number of

Measurement Board

Material

4 Layers

FR-4

114.3mm x 76.2mm x 1.6mmt

2 Internal Layers

Top

Copper Pattern

Bottom

Copper Pattern

74.2mm x 74.2mm

Thickness

70µm

Copper Pattern

Thickness

35µm

Thickness

70µm

Footprints and Traces

74.2mm x 74.2mm

Recommended Operating Conditions

Table 7. Recommended Operating Conditions

Parameter

Supply Voltage

Operating Temperature

Symbol

Min

Typ

Max

Unit

V_BAT

Topr

7.0

12.0

+25

18.0

V

-40

+125

°C

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BD41003FJ-C

Electrical Characteristics (Unless Otherwise Specified Ta=-40°C to +125°C, V_BAT=7V to 18V)

Table 8. Electrical Characteristics (1)

Parameter

Symbol

Min

Typ

Max

Unit

µA

Conditions

BAT

After NSLP shifts from H to

Supply Current 1

I_{BAT_SLP}

I_{BAT_NOR}

-

3

10

L

NSLP=H, MS=H,

Supply Current 2

mA CLK=20kHz (Duty=50%)

TXD=10kHz (Duty=50%)

TXD, NLSP, CLK (When Input)

H Level Input Voltage

L Level Input Voltage

Input H Current

V_{IHMCU_IN}

V_{ILMCU_IN}

I_{IHMCU_IN}

I_{ILMCU_IN}

2.0

-

V

0.8

V

6.0

-5.0

14.0

0.0

40.0

+5.0

µA Input Voltage=5V

µA

Input L Current

Wakeup Input Detection Time

(TXD)

t_{TXD_WAKEUP}

D_DUTYCLK

30

48

100

50

150

95

µs H Width

Input Clock Duty

(CLK)

%

Duty Rule of H Width

MS

H Level Input Voltage

L Level Input Voltage

Input H Current

V_{IHMS_IN}

V_{ILMS_IN}

I_{IHMS_IN}

I_{ILMS_IN}

V_BAT-1.0

-

V

V_BAT-3.0

+5.0

-5.0

µA Input Voltage= V_BAT=18V

µA In Power OFF Mode

Input L Current

+5.0

RXD, CLK (When Output)

Output ON Current

Output OFF Current

BUS (DC Characteristics)

I_{OLMCU_OUT}

I_{OHMCU_OUT}

1.3

3.5

0.0

-

mA Output Pin=0.4V

µA Output Pin=5V

-5.0

+5.0

Recessive Output Voltage

V_BAT

x 0.9

V_{BUS_RES}

V_{BUS_DOM_1}

V_{BUS_DOM_2}

V_{BUS_DOM_3}

V_{BUS_DOM_4}

-

1.2

-

V

R_L=500Ω

(Note 19)

Dominant Output Voltage 1

-

V_BAT=7V, R_L=500Ω

V_BAT=7V, R_L=1kΩ

V_BAT=18V, R_L=500Ω

V_BAT=18V, R_L=1kΩ

(Note 19)

Dominant Output Voltage 2

0.6

-

(Note 19)

Dominant Output Voltage 3

2.0

-

(Note 19)

Dominant Output Voltage 4

0.8

(Note 19)

When Recessive Output

V_BAT=V_BUS=18V

H Level Leakage Current

I_IHBUS

-5.0

0.0

+5.0

µA

Pull-up Resister

R_BUS

I_OCPBUS

I_OLBUS

I_LBUS

20

40

-1

-

30

-

50

200

-

kΩ V_BAT=12V

Short-circuit Output Current

mA V_BAT=V_BUS=18V, R_L=0Ω

mA V_BAT=12V, V_BUS=0V

µA V_BAT=8V, V_BUS=18V

(Note 19)

L Current at Receiver Operating

-

Input Leakage Current at

Receiver Operating

-

20

Leakage Current when

NO_GND

GND=V_BAT=12V,

mA

I_{LBUS_NO_GND}

-1

-

+1

V_BUS=0V to 18V

Leakage Current when NO_BAT

Input H Threshold Voltage

I_{LBUS_NO_BAT}

V_{IHBUS_REC}

-

100

µA V_BAT=0V, V_BUS=0V to 18V

V

V_BAT

x 0.556

-

V_BAT

x 0.423

V_BAT

x 0.525

V_BAT

Input L Threshold Voltage

V_{ILBUS_DOM}

V_THCBUS

-

V

Input Threshold Voltage

(Typical)

V_BAT

x 0.475

V_BAT

x 0.5

Input Hysteresis Voltage

V_HYSBUS

-

x 0.133

(Note 19) R_Lis pull-up resistor that is connected between BAT and BUS terminal outside.

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Electrical Characteristics – continued

Table 9. Electrical Characteristics (2)

Parameter

Symbol

Min

Typ

Max

Unit

Conditions

BUS (AC Characteristics)

LO Level Time 1 of Logical

0.39T_bit

+0.6τ

t_{TX_1_LO_REC}

t_{TX_1_LO_DOM}

t_{TX_0_HI}

-

t_{H_REC}=70%

Value “1”^{(Note 20)}

LO Level Time 2 of Logical

Value “1”

HI Detection Time of

Receiving

0.11

0.06

-

T_bitt_{H_DOM}=30%

T_bitt_{H_REC}=55.6%

-

Difference of LO Level Time

between Logical Value “1” and

Logical Value “0”

t_{TX_DIF}= t_{TX_0_LO}

t_{TX_1_LO}

-

t_{TX_DIF}

0.06

-

T_bit

Delay Time from the LO Level

Detection to Logical Value “0”

Output

t_{TX_0_PD}

-

0.11

T_bitt_{H_DOM}=30%

t_{TX_1_LO_REC}

+ 0.06

t_{TX_1_LO_DOM}

+ 0.06

LO Time 1 of Logical Value “0”

t_{TX_0_LO_REC}

-

T_bitt_{H_REC}=70%

T_bitt_{H_DOM}=30%

LO Time 2 of Logical Value “0”

t_{TX_0_LO_DOM}

t_{TX_1_DOM_M}

-

BUS Pull-down Time

-

0.16

T_bitt_{H_DOM}=30%

Ratio for the

Recessive Voltage

Recessive Voltage of Logical

Value “0”

V_{_REC_0}

93

-

%

(V_{_REC_1}

)

when logical value is

1

Wakeup Pulse Detection LO

Time for Master Setting

t_{RX_WAKEUP_MASTER}

30

100

3

150

5

µs

t_{H_DOM}=42.3%

Wakeup Pulse Detection LO

Time for Slave Setting

t_{RX_WAKEUP_SLAVE}

0.5

t_{H_DOM}=42.3%

TSD

TSD Detection Temperature

T_TSD

150

-

200

°C

(Note 21)

TSD Hysteresis Temperature

T_{TSD_HYS}

-

14

-

(Note 21)

UVLO

UVLO Detection Voltage

POR

V_UVLO

V_POR

t_DTC

5.0

-

6.7

5.0

22

V

POR Detection Voltage

DTC

Dominant Time-out Time

9

13

ms

(Note 20) τ is a fixed number when BUS (1μs ≤ τ ≤ 5μs)

(Note 21) It is a design guarantee parameter, and is not production tested.

Tbit

t_{TX_1_LO_REC}

t_{TX_1_LO_DOM}

V_{_REC_1}

BUS Wave

Logical Value “1”

t_{H_REC}

(Note 22)

t_{H_DOM}

(Note 22)

t_{TX_DIF}

t_{TX_0_LO_REC}

t_{TX_0_LO_DOM}

t_{TX_0_HI}

V_{_REC_0}

BUS Wave

Logical Value “0”

t_{H_REC}

(Note 22)

t_{H_DOM}

(Note 22)

t_{TX_1_DOM_M}

(Note 22) These parameters are shown as the ratio of V_BAT

.

Figure 19. BUS Waves of Logical Value 1, 0

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Application Example

Slave node (Applicable secondary clockmaster option)

CXPI BUS

V_ECU

Regulator

(Note 24)

2.7kΩ

10kΩ

MS(8)

BD41003FJ-C

GND(5)

VDD

INT

BAT(7)

RXD

RXD(1)

100nF

220pF

Micro

TXD

CLK

I/O

TXD(4)

CLK(3)

NSLP(2)

Controller

(Note 23)

BUS(6)

I/O

GND

(Note 23) INT: Interrupt, RXD: UART RXD, TXD: UART TXD, CLK: Clock, I/O: General Purpose I/O

(Note 24) While using slave, it is no problem that the CLK pin is opened in the case of non-using the CLK output.

Figure 20. Application Example of Secondary Clock Master Option

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I/O Equivalence Circuits

Type

Equivalence Circuit

Type

Equivalence Circuit

A

B

Output pin: RXD

Input pin: NSLP, TXD

BAT

BUS

C

D

1/2 x BAT

Input/output pin: CLK

CXPI BUS Input/output pin: BUS

E

Input pin: MS

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BD41003FJ-C

Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7.

8.

Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

10. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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BD41003FJ-C

Operational Notes – continued

11. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 21. Example of Monolithic IC Structure

12. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

13. Area of Safe Operation (ASO)

Operate the IC such that the output voltage, output current, and the maximum junction temperature rating are all within

the Area of Safe Operation (ASO).

14. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

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BD41003FJ-C

Ordering Information

B

D

4

1

0

3

F

J

C

E

2

-

Part Number

Package

Product Rank

FJ: SOP-J8

C: for Automotive

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

SOP-J8(TOP VIEW)

Part Number Marking

LOT Number

4 1 0 0 3

Pin 1 Mark

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BD41003FJ-C

Physical Dimension and Packing Information

Package Name

SOP-J8

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BD41003FJ-C

Revision History

Date

Revision

001

Changes

22.Dec.2020

New Release

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD41003FJ-C
厂家：	ROHM
描述：	BD41003FJ-C在AM频段的EMI噪声比BD41000AFJ-C更低。BD41003FJ-C是CXPI （Clock Extension Peripheral Interface，时钟扩展外围接口）通信用的收发器。支持主/从双向传输，可通过外部引脚进行切换。在不通信时，其节能功能可实现更低待机功耗。在总线数据冲突时，其数据仲裁功能将停止输出输出。另外，在发生异常时，其可以检测温度和电压异常的故障安全（Fail Safe）功能将会停止数据输出。通信时钟
文件：	总24页 (文件大小：1089K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD41003FJ-C [ROHM]

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