BD4157MUV_技术文档

Power Management Switch ICs for PCs and Digital Consumer Products

Power Switch IC

for ExpressCard^TM

No.11029EAT26

BD4157MUV

●Description

BD4157MUV is a power management switch IC for the next generation PC card (ExpressCard^TM) developed by the PCMCIA.

It conforms to the PCMCIA ExpressCard^TMStandard, ExpressCard^TMCompliance Checklist., and ExpressCard^TM

Implementation Guideline, and obtains Compliance ID “EC100395” from PCMCIA. The power switch offers a number of

functions - card detector, and system status detector - which are ideally suited for laptop and desktop computers.

●Features

1) Incorporates three low on-resistance FETs for ExpressCard^TM

.

2) Incorporates an FET for output discharge.

3) Incorporates an enabler.

4) Incorporates under voltage lockout (UVLO) protection.

5) Employs an VQFN020V4040 package.

6) Built-in thermal shutdown protector (TSD).

7) Built-in thermal shutdown protector (TSD).

8) Incorporates an overcurrent protection (OCP).

9) Built-in enable signal for PLL

10) Built-in Pull up resistance for detecting ExpressCard^TM

11) Conforms to the ExpressCard^TMStandard.

12) Conforms to the ExpressCard^TMCompliance Checklist.

13) Conforms to the ExpressCard^TMImplementation Guideline.

●Applications

Laptop and desktop computers, and other ExpressCard ^TMequipped digital devices.

●Product Lineup

Parameter

BD4157MUV

Package

VQFN020V4040

“ExpressCard^TM” is a registered trademark registered of the PCMCIA

(Personal Computer Memory Card International Association).

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2011.06 - Rev.A

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Technical Note

BD4157MUV

●Absolute Maximum Ratings

Parameter

Symbol

Ratings

-0.3～4.5 *¹

-0.3～V3AUX_IN+0.3 *¹

-0.3～V3AUX_IN+0.3

-0.3～4.5 *¹

1.0

Unit

V

Input Voltage

V3AUX_IN, V3_IN, V15_IN

EN,CPPE#,CPUSB#,SYSR,

PERST_IN#,RCLKEN

Logic Input Voltage 1

Logic Output Voltage 1

Logic Output Voltage 2

Output Voltage

V

RCLKEN

PERST#

V3AUX,V3, V15

IOV3AUX

IOV3

V

Output Current 1

A

Output Current 2

2.0

A

Output Current 3

IOV15

2.0

A

Power Dissipation 1

Power Dissipation 2

Operating Temperature Range

Storage Temperature Range

Pd1

0.34 *²

mW

℃

Pd2

0.70 *³

Topr

-40～+100

-55～+150

+150

Tstg

Maximum Junction Temperature

Tjmax

*1 Not to exceed Pd.

*2 Reduced by 2.7mW for each increase in Ta of 1℃ over 25℃

*3 Reduced by 5.6mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 74.2mm×74.2mm×1.6mm Glass-epoxy PCB）.

●Operating Conditions (Ta=25℃)

Ratings

Parameter

Input Voltage 1

Symbol

Unit

MIN

3.0

MAX

3.6

V3AUX_IN

V3_IN

V

Input Voltage 2

3.0

1.35

-0.3

0

3.6

1.65

Input Voltage 3

V15_IN

EN

V

Logic Input Voltage 1

Logic Input Voltage 2

Logic Output Voltage 1

Logic Output Voltage 2

Output Current 1

3.6

V

CPPE#,CPUSB#,SYSR,

PERST_IN#,RCLKEN

V3AUX_IN

275

V

RCLKEN

PERST#

IOV3AUX

IOV3

0

V

0

V

0

mA

A

Output Current 2

0

1.3

Output Current 3

IOV15

0

650

mA

★ This product is not designed to offer protection against radioactive rays.

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Technical Note

BD4157MUV

●ELECTRICAL CHARACTERISTICS (Unless otherwise noted, Ta=25℃, V3AUX_IN =V3_IN=3.3V, V15_IN=1.5V

VEN=OPEN,VSYSR=OPEN,CPPE#=0V,CPUSB#=OPEN,PERST_IN#=OPEN)

Limits

Parameter

Standby Current

Symbol

Unit

Condition

MIN

-

TYP

40

MAX

80

VEN=0V

IST

Icc1

Icc2

µA

(Include IEN, IRCLKEN)

VSYSR=0V,

CPPE#=OPEN

Bias Current 1

-

100

250

500

Bias Current 2

[Enable]

High Level Enable Input Voltage

VENHI

VENLOW

IEN

2.0

-0.2

10

-

3.6

0.8

30

V

Low Level Enable Input Voltage

Enable Pin Input Current

[Logic]

µA

VEN=0V

High Level Logic Input Voltage

VLHI

2.0

-

V

Low Level Logic Input Voltage

Logic Pin Input Current

RCLKEN Low Voltage

VLLOW

0.8

-

10

-

0

-

1

30

1

µA

CPPE#=3.6V

CPPE#=0V

ICPPE#

ICPUSB#

ISYSR

0

-

CPUSB#=3.6V

CPUSB#=0V

SYSR=3.6V

10

-

30

1

0

-

10

-

30

1

SYSR=0V

0

-

PERST_IN#=3.6V

PERST_IN#=0V

RCLKEN=3.6V

RCLKEN=0V

IPRT_IN#

IRCLKEN

10

-

30

1

0

-

10

30

VRCLKEN

IRCLKEN

-

0.1

-

0.3

1

V

IRCLKEN=0.5mA

VRCLKEN=3.6V

RCLKEN Leak Current

[Switch V3AUX]

µA

On Resistance

R_V3AUX

-

140

30

220

150

mΩ

Tj=-10～100℃

Discharge On Resistance

[Switch V3]

R_V3AUXDis

Ω

On Resistance

R_V3

-

50

30

90

mΩ

Discharge On Resistance

[Switch V15]

R_V3Dis

150

Ω

On Resistance

R_V15

-

50

30

90

mΩ

Discharge On Resistance

[Over Current Protection]

V3 Over Current

R_V15Dis

150

Ω

OCP_V3

OCP_V3AUX

OCP_V15

1.3

0.275

0.65

-

A

V3AUX Over Current

V15 Over Current

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Technical Note

BD4157MUV

Limits

TYP

Parameter

Symbol

Unit

Condition

MIN

MAX

[Under Voltage Lockout]

V3_IN UVLO OFF Voltage

VUVLO_{V3_IN}

2.60

50

2.80

100

2.80

100

1.20

100

3.00

150

3.00

150

1.30

150

V

mV

V

sweep up

V3_IN Hysteresis Voltage

⊿VUVLO_{V3_IN}

sweep down

sweep up

V3AUX_IN UVLO OFF Voltage

V3AUX_IN Hysteresis Voltage

V15_IN UVLO OFF Voltage

VUVLO_{V3AUX_IN}2.60

⊿VUVLO_{V3AUX_IN}

VUVLO_{V15_IN}

50

1.10

50

mV

V

sweep down

sweep up

V15_IN Hysteresis Voltage

[POWER GOOD]

⊿VUVLO_{V15_IN}

mV

sweep down

V3 POWER GOOD Voltage

PG_V3

PG_V3AUX

PG_V15

2.700 2.850 3.000

1.200 1.275 1.350

V

V3AUX POWER GOOD Voltage

V15 POWER GOOD Voltage

PERST# LOW Voltage

V

VPERST#_Low

VPERST#_HIGH

T_PERST#

-

3.0

4

0.01

0.1

-

V

I_PERST=0.5mA

PERST# HIGH Voltage

-

V

PERST# Delay Time

20

500

ms

ns

PERST# assertion time

[OUTPUT RISE TIME]

V3_IN to V3

Tast

-

T_V3

T_V3AUX

T_V15

0.1

-

3

ms

V3AUX_IN to V3AUX

V15_IN to V15

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Technical Note

BD4157MUV

●Reference data

CPPE#(2V/div)

V3(2V/div)

SYSR(2V/div)

V3(2V/div)

R_V3=3.3Ω

V3AUX(2V/div)

V15(1V/div)

V3AUX(2V/div)

R_V3AUX=13.2Ω

V3AUX(2V/div)

V15(1V/div)

R_V15=3Ω

V15(1V/div)

5.0ms/div

Fig.1 Card Assert/ De-assert

(Active)

5.0ms/div

Fig.2 Card Assert/De-assert

(Standby)

Fig.3 System Active

⇔Standby( Card Present)

SYSR(2V/div)

CPUSB#(2V/div)

V3(2V/div)

CPPE#(2V/div)

V3(2V/div)

V3AUX(2V/div)

V15(1V/div)

500µs/div

V15(1V/div)

500µs/div

V15(1V/div)

5.0ms/div

Fig.4 System Active

⇔Standby(No Card)

Fig.5 Wakeup Wave Form

(Card Assert)

Fig.6 Wakeup Wave Form

(USB2.0 Assert)

SYSR(2V/div)

V3(2V/div)

CPPE#(2V/div)

EN(2V/div)

V3(2V/div)

V3AUX(2V/div)

V15(1V/div)

500µs/div

V15(1V/div)

500µs/div

V15(1V/div)

500µs/div

Fig.8 Wakeup Wave Form

Fig.7 Wakeup Wave Form

Fig.9 Power Down Wave Form

(Card De-assert)

(Standby→Active)

(Shut Down→Active)

CPUSB#(2V/div)

V3(2V/div)

SYSR(2V/div)

EN(2V/div)

V3(2V/div)

V3AUX(2V/div)

V15(1V/div)

V3AUX(2V/div)

V15(1V/div)

5.0ms/div

500µs/div

Fig.10 Power Down Wave Form

(USB2.0 De-assert)

Fig.12 Power Down Wave Form

Fig.11 Power Down Wave Form

(Active→Shut Down)

(Active→Standby)

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Technical Note

BD4157MUV

CPPE#(2V/div)

V3(2V/div)

CPPE#(2V/div)

V3(2V/div)

V3AUX(2V/div)

RCLKEN(2V/div)

5.0ms/div

PERST#(2V/div)

5.0ms/div

Fig.13 PERST# Wave Form

(Card Assert/ De-assert)

Fig.14 RCLKEN Wave Form

(Card Assert/ De-assert)

Fig.15 PERST# Wave Form

(USB2.0 Assert/ De-assert)

CPUSB#(2V/div)

V3(2V/div)

PERST_IN#(2V/div)

V3(2V/div)

PERST_IN#(2V/div)

V3(2V/div)

V3AUX(2V/div)

RCLKEN(2V/div)

5.0ms/div

RCLKEN(2V/div)

1.0ms/div

PERST#(2V/div)

1.0ms/div

Fig.16 RCLKEN Wave Form

(USB2.0 Assert/ De-assert)

Fig.17 PERST# Wave Form

(PERST_IN# Input)

Fig.18 RCLKEN Wave Form

(PERST_IN# Input)

V3_IN(2V/div)

V3(2V/div)

V15_IN(2V/div)

V3(2V/div)

V3AUX_IN(2V/div)

V3(2V/div)

V3AUX(2V/div)

V15(1V/div)

500µs/div

V3AUX(2V/div)

V15(1V/div)

500µs/div

V15(1V/div)

500µs/div

Fig.19 Output Voltage

Fig.21 Output Voltage

Fig.20 Output Voltage

(V3_IN:OFF→ON)

(V15_IN:OFF→ON)

(V3AUX_IN:OFF→ON)

V3AUX_IN(2V/div)

V15_IN(2V/div)

V3_IN(2V/div)

V3(2V/div)

V3AUX(2V/div)

R

_V3=3.3Ω

R

_V3=3.3Ω

R_V3=3.3Ω

R_V3AUX=13.2Ω

R_V15=3Ω

R_V3AUX=13.2Ω

R_V15=3Ω

R_V3AUX=13.2Ω

R_V15=3Ω

V15(1V/div)

500µs/div

V15(1V/div)

500µs/div

Fig.23 Output Voltage

Fig.24 Output Voltage

Fig.22 Output Voltage

(V3AUX_IN:ON→OFF)

(V15_IN:ON→OFF)

(V3_IN:ON→OFF)

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Technical Note

BD4157MUV

●Block Diagram

3.3V/1.30A

V3-1

V3-2

V3_IN1

3

5

2

4

VD

3.3V

V3_IN2

TSD,CL,UVLO

VD

3.3V /275mA

V3AUX

V3AUX_IN

17

15

3.3V

TSD,CL,UVLO_AUX

V15_IN1

V15_IN2

1.5V/650mA

V15-1

12

14

11

13

V3AUX_IN

1.5V

V15-2

V3AUX_IN

VD

CPPE#

CPUSB#

SYSR

10

9

Input

logic

RCLKEN

18

Power

good

TSD,CL,UVLO

1

PERST#

8

6

EN,SYSR,CPUSB#,CPPE#

TSD

Thermal

V3AUX_IN

PERST_IN#

protection

V3_IN,V3AUX_IN,V15_IN

V3,V3AUX,V15

CL

EN

Reference

Block

V3_IN

N.C.

20

19

Under

V3AUX_IN

UVLO

voltage

lock out

VD

Charge

Pump

16 TEST

V15_IN

UVLO_AUX

7

GND

●Physical Dimensions

●Pin Function

PIN No

1

PIN NAME

PIN FUNCTION

Logic input pin

V3 input pin

4.0 0.1

SYSR

V3_IN1

V3-1

2

D4157

3

V3 output pin

V3 input pin

4

V3_IN2

V3-2

5

V3 output pin

6

PERST_IN# PERST# control input pin (SysReset#)

Lot No.

7

GND

PERST#

CPUSB#

CPPE#

V15-1

GND pin

S

8

Logic output pin

Logic input pin

9

0.08 S

10

11

12

13

14

15

16

17

Logic input pin

V15 output pin

2.1 0.1

C0.2

V15_IN1

V15-2

V15 input pin

1

5

V15 output pin

20

6

V15_IN2

V3AUX

TEST

V15 input pin

V3AUX output pin

Test pin. Must be open or GND.

V3AUX input pin 1

16

10

15

11

1.0

V3AUX_IN

+0.05

-0.04

0.25

0.5

Reference clock enable signal/

Power good signal (No delay）

18

RCLKEN

VQFN020V4040 Package (Unit:mm)

19

20

N.C.

EN

Must be open or GND.

Enable input pin

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Technical Note

BD4157MUV

●Description of block operation

EN

With an input of 2.0 volts or higher, this terminal goes HIGH to activate the circuit, and goes LOW to deactivate the circuit

(with the standby circuit current of 40 μA), It discharges each output and lowers output voltage when the input falls to 0.8

volts or less.

V3_IN, V15_IN, and V3AUX_IN

These are the input terminals for each channel of a 3ch switch. V3_IN and V15_IN terminals have two pins each, which

should be short-circuited on the pc board with a thick conductor. A large current runs through these three terminals :

(V3_IN: 1.3A; V3AUX_IN: 0.275 A; and V15_IN: 0.65 A). In order to lower the output impedance of the connected power

supply, it is recommended that ceramic capacitors (with B-type characteristics or better) be provided between these

terminals and the ground. Specifically, the capacitors should be on the order of 1 μF between V3_IN and GND, and

between V15_IN and GND; and on the order of 0.1 μF between V3AUX_IN and GND.

V3, V15, and V3AUX

These are the output terminals for each switch. The V3 and V15 terminals have two pins each, which should be

short-circuited on the PC board and connected to an ExpressCard connector with a thick conductor, as short as possible.

In order to stabilize the output, it is recommended that ceramic capacitors (with B-type characteristics or better) be

provided between these terminals and the ground. Specifically, the capacitors should be on the order of 10 μF between V3

and GND, and between V15 and GND; and on the order of 1 μF between V3AUX and GND.

CPPE#

This pin is used to find whether or not a PCI-Express signal compatible card is present. Turns to “High” level with an

input of 2.0 volts or higher, which means that no card is provided, while it turns to “Low” level when the input is lowered to

0.8 volts or less, which means that a card is provided. Controls the ON/OFF, switch selecting the proper mode based on

the status of the system. Pull up resistance (100kΩ～200kΩ) is built into, so the number of components is reduced.

CPUSB#

This pin is used to find whether or not a USB2.0 signal compatible card is present. Turns to “High” level with an input of

2.0 volts or higher, which means that no card is provided, while it turns to “Low” level when the input is lowered to 0.8 volts

or less, which means that a card is provided. Controls the ON/OFF switch, selecting the proper mode based on the

system status. Pull up resistance (100kΩ～200kΩ) is built into, so the number of components is reduced.

SYSR

This pin is used to detect the system status. Turns to “High” level with an input of 2.0 volts or higher, which means that

the system is activated, while it turns to “Low” level when the input is lowered to 0.8 volts or less, which means that the

system is on standby.

PERST_IN#

This pin is used to control the reset signal (PERST#) to a card from the system side. (Also referred to as “SysReset#” by

PCMCIA.) Turns to “High” level with an input of 2.0 volts or higher, and sets PERST# to “High” AND with a “Power Good”

output. Turns to “Low” level and sets PERST# to “Low” when the input falls to 0.8 volts or less.

PERST#

This pin is used to send a reset signal to a PCI-Express compatible card. Reset status is determined by the outputs,

PERST_IN#, CPPE# system status, and EN on/off status. Turns to “High” level and activates the PCI-Express

compatible card only if each output is within the “Power Good” threshold, with the card inserted and PERST_IN# turned to

“High” level.

RCLKEN

This pin is used to send an enable signal to the reference clock. Activation status is determined by the outputs, CPPE#

system status, and EN on/off status. Turns to “High” level and activates the reference clock PLL only if each output is

within the “Power Good” threshold, with the card kept inserted.

TEST

This pin is used to test, which should be short-circuited to the GND. When it is short-circuited to V3AUX_IN, UVLO

(V3_IN, V15_IN) turns OFF.

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Technical Note

BD4157MUV

●Timing Chart

Power ON/OFF Status of ExpressCard^TM

System Status

Power Switch Status

ExpressCard^TMModule

Status

Primary

(+3.3V and +1.5V)

Auxiliary

(3.3V Aux)

Primary

OFF

Auxiliary

OFF

Don’t care

De-asserted

OFF

ON

OFF

ON

Asserted

De-asserted

OFF

ON

Asserted Before This

Asserted After This

OFF

ExpressCard^TMStates Transition Diagram

SYSR=L

SYSR=H⇔L

CP#=H

CP#=L→H

SYSR=H

CP#=H→L

SYSR=L

SYSR=L→H

CP#=L

SYSR=H→L

CP#=L

CP#=H⇔L

V3AUX=OFF

V15=V3=OFF

V3AUX=ON

V15=V3=ON

V3AUX=ON

V15=V3=OFF

SYSR=H

SYSR=L→H

CP#=L

CP#=L→H

SYSR=H→L

CP#=L

SYSR=H

CP#=H

SYSR=L

⇔

CP#=L

System Status

:SYSR=L

:SYSR=H

:SYSR=H→L

Card Status

Stand-by Status

Card Asserted Status

:CP#=L

ON Status

Card De-asserted Status

:CP#=H

From ON to Stand-by Status

From De-asserted to Asserted Status

From Asserted to De-asserted Status

:CP#=H→L

:CP#=L→H

From Stand-by to ON Status :SYSR=L→H

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Technical Note

BD4157MUV

●ExpressCard^TMTiming Diagrams

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

PERST_IN#

CPPE#

a

Card Power

(V3AUX,V3,V15)

Tpd

a

Min

System Dependent

100

Max

Units

µs

RCLKEN

PERST#

b

-

b

c

System Dependent

d

REFCLK

g

c

d

e

100

-

µs

ms

e

f

4

-

20

10

f

g

Timing Signals-Card Present Before Host Power is On

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

PERST_IN#

CPUSB#

a

Card Power

(V3AUX,V3,V15)

RCLKEN

PERST#

Tpd

a

Min

Max

Units

ms

REFCLK

(Either Tri-Stated or Off)

System Dependent

10

b

-

Timing Signals-USB Present Before Host Power is On

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Technical Note

BD4157MUV

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

PERST_IN#

CPPE#

Card Power

(V3AUX,V3,V15)

RCLKEN

PERST#

REFCLK

Tpd

a

Min

Max

100

10

Units

µs

a

-

b

ms

b

c

d

c

System Dependent

e

d

e

4

10

ms

Timing Signals Host Power is On Prior to Card Insertion

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

PERST_IN#

CPUSB#

Card Power

(V3AUX,V3,V15)

RCLKEN

PERST#

Tpd

a

Min

-

Max

10

Units

ms

REFCLK

(Either Tri-Stated or Off)

a

Timing Signals Host Power is On Prior to USB Insertion

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Technical Note

BD4157MUV

●Application Information (continued)

Host Power

(V3AUX_IN)

Host Power

(V3_IN,V15_IN,SYSR)

PERST_IN#

CPPE#

Card Power

(V3AUX,V3,V15)

RCLKEN

PERST#

REFCLK

(Either Tri-Stated or Off)

Timing Signals-Host System In Standby Prior to Card Insertion

Host Power

(V3AUX_IN)

Host Power

(V3_IN,V15_IN,SYSR)

PERST_IN#

CPUSB#

Card Power

(V3AUX,V3,V15)

RCLKEN

PERST#

REFCLK

(Either Tri-Stated or Off)

Timing Signals-Host System In Standby Prior to USB Insertion

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Technical Note

BD4157MUV

Host Power

(V3AUX_IN,

V3_IN,V15_IN)

c

PERST_IN

CPPE#

Card Power

(V3AUX,V3,V15)

d

RCLKEN

PERST#

REFCLK

a

Tpd

a

Min

-

Max

2

Units

µs

e

b

System Dependent

Load Dependent

b

c

d

e

-

2

µs

Timing Signals Host Controlled Power Down

Host Power

(V3AUX_IN,

V3_IN,V15_IN)

a

PERST_IN

CPUSB#

Card Power

(V3AUX,V3,V15)

b

RCLKEN

PERST#

Tpd

a

Min

Max

Units

System Dependent

Load Dependent

b

REFCLK

(Either Tri-Stated or Off)

Timing Signals Host Controlled Power Down

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Technical Note

BD4157MUV

●Application Information (continued)

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

e

EN

Tpd

Min

Max

Units

CPPE#

f

Card Power

(V3AUX,V3,V15)

a

b

c

d

e

f

Load Dependent

System Dependent

-

500

2

ns

µs

RCLKEN

a

d

c

PERST#

b

System Dependent

REFCLK

Timing Signals Controlled Power Down When EN Asserted

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

b

EN

CPUSB#

c

Card Power

(V3AUX,V3,V15)

a

RCLKEN

PERST#

Tpd

a

Min

Max

Units

Load Dependent

System Dependent

b

REFCLK

(Either Tri-Stated or Off)

c

Timing Signals Controlled Power Down When EN Asserted

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2011.06 - Rev.A

14/24

Technical Note

BD4157MUV

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

RERST_IN#

CPPE#

Card Power

(V3AUX,V3,V15)

a

RCLKEN

PERST#

d

b

Tpd

a

Min

Load Dependent

500

System Dependent

Max

Units

ns

b

-

REFCLK

c

d

-

2

µs

Timing Signals-Surprise Card Removal

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

RERST_IN#

CPUSB#

Card Power

(V3AUX,V3,V15)

a

RCLKEN

PERST#

Tpd

a

Min

Max

Units

Load Dependent

REFCLK

(Either Tri-Stated or Off)

Timing Signals-Surprise USB Removal

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2011.06 - Rev.A

15/24

Technical Note

BD4157MUV

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

SYSR

CPPE#

Card Power

(V3AUX)

a

Card Power

(V3,V15)

Tpd

a

Min

Max

Units

b

System Dependent

b

c

PERST#

REFCLK

b

4

-

20

2

ms

µs

e

d

c

d

System Dependent

e

RCLKEN=OPEN, PERST_IN=3.3V,EN=3.3V

Timing Signals Power state transitions (Signal applies for SYSR)

Host Power

(V3AUX_IN,V3_IN,

V15_IN)

SYSR

CPUSB#

Card Power

(V3AUX)

a

Card Power

(V3,V15)

Tpd

a

Min

Max

Units

System Dependent

PERST#

REFCLK

(Either Tri-Stated or Off)

RCLKEN=OPEN, PERST_IN=3.3V,EN=3.3V

Timing Signals Power state transitions (Signal applies for SYSR)

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2011.06 - Rev.A

16/24

Technical Note

BD4157MUV

V3AUX_IN

EN

V3_IN,SYSR

V15_IN

PERST_IN#

CPPE#

Card Power

(V3AUX)

Tpd

a

Min

Max

Units

System Dependent

a

Card Power

(V3,V15)

b

4

-

20

2

ms

µs

b

c

PERST#

REFCLK

d

System Dependent

e

d

e

RCLKEN=OPEN, PERST_IN# is asserted in advance of power changes.

Timing Signals – Power state transitions

(SYSR and EN are connected to V3_IN/V3AUX_IN.)

V3AUX_IN

EN

V3_IN,SYSR

V15_IN

PERST_IN#

CPUSB#

Card Power

(V3AUX)

a

Card Power

(V3,V15)

PERST#

Tpd

a

Min

Max

Units

REFCLK

(Either Tri-Stated or Off)

System Dependent

RCLKEN=OPEN, PERST_IN# is asserted in advance of power changes.

Timing Signals – Power state transitions

(SYSR and EN are connected to V3_IN/V3AUX_IN.)

www.rohm.com

2011.06 - Rev.A

17/24

Technical Note

BD4157MUV

●Output Condition List(Output）

Power Supply

Logic input

SYSR

Output

State

V3AUX_IN

0

V3_IN

V15_IN

EN

CPPE# CPUSB# V3/V15

V3AUX

OFF

×

OFF

Shut down

1

×

1

×

1

0

1

OFF

1

×

0

1

0

OFF

ON

↓

Stand-by

1→0

×

ON

Stand-by

ON

0

1

×

OFF

1

×

0

1

0

OFF

ON

OFF

ON

×

ON

Logic input

Logic output

State

PERST_IN#

RCLKEN(Input)

PERST#

0

RCLKEN

OFF

×

0

Shut down

Stand-by

×

0

ON(No Card)

0

1

0

1

Hiz

0

1

0

1

0

1

0

ON(CPUSB#=0)

ON(CPPE#=0)

Hiz

0

Hiz

0

Hiz

0

www.rohm.com

2011.06 - Rev.A

18/24

Technical Note

BD4157MUV

●Application Circuit (Circuit for ExpressCard^TMCompliance Checklist)

CPPE#

RCLKEN

CPPE#(10pin)

RCLKEN(18pin)

V3_IN(2,4pin)

3.3V

CPUSB#

CPUSB#(9pin)

3.3V

V3(3,5pin)

V3AUX_IN(17pin)

V15_IN(12,14pin)

PERST_IN#(6pin)

EN(20pin)

BD4157MUV

3.3V

1.5V

V3AUX(15pin)

SysReset#

V15(11,13pin)

PERST#

PERST#(8pin)

TEST(16pin)

SYSR(1pin)

GND(7pin)

●Heat loss

Thermal design should allow the device to operate within the following conditions. Note that the temperatures listed are the

allowed temperature limits. Thermal design should allow sufficient margin from these limits.

1. Ambient temperature Ta can be no higher than 100℃.

2. Chip junction temperature Tj can be no higher more than 150℃.

Chip junction temperature Tj can be determined as follows:

Chip junction temperature Tj is calculated from ambient temperature Ta:

Tj=Ta+θj-a×W

＜Reference value＞

θj-c:VQFN020V4040 367.6℃/W IC only

178.6℃/W 1-layer (copper foil density 10.29mm²)

56.6℃/W

35.1℃/W

4-layer (copper foil density 10.29mm²/ 2,3-layer copper foil density 5505mm²)

4-layer (copper foil density 5505mm²)

Substrate size 74.2×74.2×1.6mm³(thermal vias in the board.)

Most of heat loss in the BD4157MUV occurs at the output switch. The power lost is determined by multiplying the

on-resistance by the square of output current of each switch.

www.rohm.com

2011.06 - Rev.A

19/24

Technical Note

BD4157MUV

●Equivalent Circuit

1pin<SYSR>

2,4pin<V3_IN>

8pin<PERST#>

11,13pin<V15>

16pin<TEST>

3,5pin<V3>

V3_IN

V3AUX_IN

V3

6pin<PERST_IN#>

9pin<CPUSB#>

12,14pin<V15_IN>

17pin<V3AUX_IN>

V3AUX_IN

10pin<CPPE#>

V3_IN

V3AUX_IN

V15

15pin<V3AUX>

V3AUX_IN

V3AUX

18pin<RCLKEN >

20pin<EN>

V3AUX_IN

www.rohm.com

2011.06 - Rev.A

20/24

Technical Note

BD4157MUV

●Notes for use

1. Absolute maximum ratings

Although quality is rigorously controlled, the device may be destroyed when applied voltage, operating temperature, etc.

exceeds its absolute maximum rating. Because the source (short mode or open mode) cannot be identified once the

IC is destroyed, it is important to take physical safety measures such as fusing when implementing any special mode

that operates in excess of absolute rating limits.

2. Thermal design

Consider allowable loss (Pd) under actual operating conditions and provide sufficient margin in the thermal design.

3. Terminal-to-terminal short-circuit and mis-mounting

When the mounting the IC to a printed circuit board, take utmost care to assure the position and orientation of the IC are

correct. In the event that the IC is mounted erroneously, it may be destroyed. The IC may also be destroyed when a

short-circuit is caused by foreign matter introduced into the clearance between outputs, or between an output and

power-GND.

4. Operation in strong electromagnetic fields

Using the IC in strong electromagnetic fields may cause malfunctions. Exercise caution in respect to electromagnetic

fields.

5. Built-in thermal shutdown protection circuit

This IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175℃ (standard

value) with a -15℃ (standard value) hysteresis width. When the IC chip temperature rises the TSD circuit is activated,

while the output terminal is brought to the OFF state. The built-in TSD circuit is intended exclusively to shut down the

IC in a thermal runaway event, and is not intended to protect the IC or guarantee performance in these conditions.

Therefore, do not operate the IC after with the expectation of continued use or subsequent operation once this circuit is

activated.

6. Capacitor across output and GND

When a large capacitor is connected across the output and GND, and the V3AUX_IN is short-circuited with 0V or GND

for any reason, current charged in the capacitor flows into the output and may destroy the IC. Therefore, use a

capacitor smaller than 1000 μF between the output and GND.

7. Set substrate inspection

Connecting a low-impedance capacitor to a pin when running an inspection with a set substrate may produce stress on

the IC. Therefore, be certain to discharge electricity at each process of the operation. To prevent electrostatic

accumulation and discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain

ESD damage, and continue observing ESD-prevention procedures in all handling, transfer and storage operations.

Before attempting to connect the set substrate to the test setup, make certain that the power supply is OFF. Likewise,

be sure the power supply is OFF before removing the substrate from the test setup.

8. IC terminal input

This integrated circuit is a monolithic IC, with P substrate and P⁺isolation between elements.

The P layer and N layer of each element form a, PN junction. When the potential relation is GND>terminal A>terminal

B, the PN junction works as a diode, and when terminal B>GND terminal A, the PN junction operates as a parasitic

transistor.

Parasitic elements inevitably form, due to the nature of the IC construction. The operation of the parasitic element

gives rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently,

take utmost care not to use the IC in a way that would cause the parasitic element to actively operate, such as applying

voltage lower than GND (P substrate) to the input terminal.

Resistor

Transistor (NPN)

B

Pin A

Pin B

C

E

Pin A

B

C

E

N

P⁺

N

P

N

Parasitic

element

Parasitic

element

P substrate

GND

Parasitic element

Other adjacent elements

9. GND wiring pattern

If both a small signal GND and a high current GND are present, it is recommended that the patterns for the high current

GND and the small signal GND be separated. Proper grounding to the reference point of the set should also be

provided. In this way, the small signal GND voltage will by unaffected by the change in voltage stemming from the

pattern wiring resistance and the high current. Also, pay special attention to avoid undesirable wiring pattern

fluctuations in any externally connected GND component.

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2011.06 - Rev.A

21/24

Technical Note

BD4157MUV

10. Electrical characteristics

The electrical characteristics in the Specifications may vary, depending on ambient temperature, power supply voltage,

circuit(s) externally applied, and/or other conditions. Therefore, please check all such factors, including transient

characteristics, that could affect the electrical characteristics.

11. Capacitors applied to input terminals

The capacitors applied to the input terminals (V3_IN, V3AUX_IN and V15_IN) are used to lower the output impedance

of the connected power supply. An increase in the output impedance of the power supply may result in destabilization

of input voltages (V3_IN, V3AUX_IN and V15_IN). It is recommended that a low-ESR capacitor be used, with a lower

temperature coefficient (change in capacitance vs. change in temperature), Recommended capacitors are on the order

of 0.1 μF for V3AUX_IN, and1 μF for V3_IN and V15_IN. However, they must be thoroughly checked at the

temperature and with the load range expected in actual use, because capacitor selection depends to a significant

degree on the characteristics of the input power supply to be used and the conductor pattern of the PC board.

12. Capacitors applied to output terminals

Capacitors for the output terminals (V3, V3_AUX, and V15), should be connected between each of the output terminals

and GND. A low-ESR, low temperature coefficient output capacitor is recommended-on the order of 1 μF for V3 and

V15 terminals, and 1μF less for V3_AUX. However, they must be thoroughly checked at the temperature and with the

load range expected in actual use, because capacitor selection depends to a significant degree on the temperature

and the load conditions.

13. Not of a radiation-resistant design.

14. Allowable loss (Pd)

With respect to the allowable loss, please refer to the thermal derating characteristics shown in the Exhibit, which serves

as a rule of thumb. When the system design causes the IC to operate in excess of the allowable loss, chip temperature

will rise, reducing the current capacity and decreasing other basic IC functionality. Therefore, design should always

enable IC operation within the allowable loss only.

15. Operating range

Basic circuit functions and operations are warranted within the specified operating range the working ambient

temperature range. Although reference values for electrical characteristics are not warranted, no rapid or extraordinary

changes in these characteristics are expected, provided operation is within the normal operating and temperature

range.

16. The applied circuit example diagrams presented here are recommended configurations. However, actual design

depends on IC characteristics, which should be confirmed before operation. Also, note that modifying external circuits

may impact static, noise and other IC characteristics, including transient characteristics. Be sure to allow sufficient

margin in the design to accommodate these factors.

17. Wiring to the input terminals (V3 IN, V3AUX IN, and V15 IN) and output terminals (V3, V3AUX and V15) of the built-in

FET should be carried out with special care. Using unnecessarily long and/or thin conductors may decrease output

voltage and degrade other characteristics.

18. Heatsink

The heatsink is connected to the SUB, which should be short-circuited to the GND. Proper heatsink soldering to the

PC board should enable lower thermal resistance.

www.rohm.com

2011.06 - Rev.A

22/24

Technical Note

BD4157MUV

●Power Dissipation

◎BD4157MUV

4.0

①3.56W

3.5

①4-layer (copper foil density 5505mm²)

θj-a=35.1℃/W

3.0

② 4-layer (copper foil density 10.29mm²)

(2,3-layer copper foil density 5505mm²)

θj-a=56.6℃/W

2.5

②2.21W

2.0

1.5

③

1-layer (copper foil density 10.29mm²)

θj-a=178.6℃/W

④IC only

θj-a=367.6℃/W

1.0

③0.70W

0.5

④0.34W

0.0

0

25

50

75

100

125

150

105

Ambient Temperature: Ta(℃)

www.rohm.com

2011.06 - Rev.A

23/24

Technical Note

BD4157MUV

●Ordering part number

B

D

4

5

1

7

M U

V

-

E

2

Part No.

Package

MUV:VQFN020V4040

Packaging and forming specification

E2: Embossed tape and reel

VQFN020V4040

4.0 0.1

Tape

Embossed carrier tape

2500pcs

Quantity

E2

Direction

of feed

1PIN MARK

The direction is the 1pin of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

S

(

)

0.08

S

2.1 0.1

C0.2

0.5

1

5

20

16

6

10

15

11

+0.05

Direction of feed

1pin

0.25

-0.04

1.0

Reel

(Unit : mm)

Order quantity needs to be multiple of the minimum quantity.

∗

www.rohm.com

2011.06 - Rev.A

24/24

Notice

N o t e s

No copying or reproduction of this document, in part or in whole, is permitted without the

consent of ROHM Co.,Ltd.

The content speciﬁed herein is subject to change for improvement without notice.

The content speciﬁed herein is for the purpose of introducing ROHM's products (hereinafter

"Products"). If you wish to use any such Product, please be sure to refer to the speciﬁcations,

which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein

illustrate the standard usage and operations of the Products. The peripheral conditions must

be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information speciﬁed in this document.

However, should you incur any damage arising from any inaccuracy or misprint of such

information, ROHM shall bear no responsibility for such damage.

The technical information speciﬁed herein is intended only to show the typical functions of and

examples of application circuits for the Products. ROHM does not grant you, explicitly or

implicitly, any license to use or exercise intellectual property or other rights held by ROHM and

other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the

use of such technical information.

The Products speciﬁed in this document are intended to be used with general-use electronic

equipment or devices (such as audio visual equipment, ofﬁce-automation equipment, commu-

nication devices, electronic appliances and amusement devices).

The Products speciﬁed in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a

Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard

against the possibility of physical injury, ﬁre or any other damage caused in the event of the

failure of any Product, such as derating, redundancy, ﬁre control and fail-safe designs. ROHM

shall bear no responsibility whatsoever for your use of any Product outside of the prescribed

scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or

system which requires an extremely high level of reliability the failure or malfunction of which

may result in a direct threat to human life or create a risk of human injury (such as a medical

instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-

controller or other safety device). ROHM shall bear no responsibility in any way for use of any

of the Products for the above special purposes. If a Product is intended to be used for any

such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology speciﬁed herein that may

be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to

obtain a license or permit under the Law.

Thank you for your accessing to ROHM product informations.

More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

www.rohm.com

R1120

A


型号：	BD4157MUV
厂家：	ROHM
描述：	Power Switch IC for ExpressCardTM 电源开关IC的ExpressCardTM 外围驱动器驱动程序和接口开关接口集成电路电源开关
文件：	总25页 (文件大小：501K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD4157MUV [ROHM]

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