BD4271HFP-C_技术文档

Datasheet

LDO Regulators with Watchdog Timer and Voltage Detector

550 mA Output LDO Regulator

with WDT and Voltage Detector

BD4271xxx-C Series

General Description

Key Specifications

BD4271xxx-C Series are automotive voltage regulators

with watchdog timer and offers the output current of 550

mA while limiting the quiescent current low. A logical

“HIGH” at the CTL pin enables the LDO regulator and

“LOW” disables the LDO regulator and keeps current

consumption low.

A reset signal is generated for an output voltage V_Oof

Typ 4.65 V.

The reset delay time and watchdog time (WDT) can be

programmed by the external capacitor.

◼ AEC-Q100 qualified ^{(Note 1)}

◼ Functional Safety Supportive Automotive Products

◼ Qualified for Automotive Applications

◼ Wide Temperature Range (Tj):

◼ Wide Operating Input Range:

◼ Low Quiescent Current:

◼ Output Load Current:

-40 °C to +150 °C

-0.3 V to +45 V

75 µA (Typ)

550 mA

◼ Output Voltage:

◼ Reset Detection Voltage Accuracy:

5.0 V (Typ) ± 2 %

4.53 V to 4.77 V

4.65 V (Typ)

◼ Enable input

◼ Over Current Protection (OCP)

◼ Thermal Shutdown (TSD)

(Note1: Grade 1)

Features

◼ Low ESR ceramic capacitors applicable for output

◼ Low drop voltage: PDMOS output transistor

◼ Power on and under-voltage reset

◼ Programmable reset delay and watchdog time by

Packages

W (Typ) x D (Typ) x H (Max)

9.395 mm x 10.540 mm x 2.005 mm

10.00 mm x 14.95 mm x 4.50 mm

4.9 mm x 6.0 mm x 1.0 mm

◼ HFP: HRP7

◼ FP2: TO263-7

◼ EFJ: HTSOP-J8

external capacitor

Applications

◼ Onboard Vehicle Device

(Engine ECU, Body-control, Car Stereos, Satellite

Navigation System, etc.)

HRP7

TO263-7

HTSOP-J8

Typical Application Circuit

C_IN≥ 0.1 µF, C_CT= 0.001 µF to 10 µF, C_O≥ 6 µF

CTL

GND

CLK

VCC

RO

CT

VO

C_IN

C_CTC_O

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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BD4271xxx-C Series

Pin Configurations (BD4271HFP-C, BD4271FP2-C)

TO263-7

(TOP VIEW)

HRP7

(TOP VIEW)

FIN

1 2 3 4 5 6 7

Pin Description (BD4271HFP-C, BD4271FP2-C)

Pin No.

Pin Name

VCC

CTL

Function

1

2

Input

Output control

Reset output

Ground

3

RO

4

GND

CT

5

Setting Reset Delay Time and WDT time

6

CLK

VO

Input CLK from Microcomputer

7

Output

FIN

GND

Ground

Pin Configuration (BD4271EFJ-C)

HTSOP-J8

(TOP VIEW)

8

7

6

5

1

2

EXP-PAD

3

4

Pin Description (BD4271EFJ-C)

Pin No.

Pin Name

Function

1

VCC

CTL

Input

2

Output control

No Connection^{(Note 1)}

3

N.C

4

RO

Reset output

5

GND

CLK

Ground

6

Input CLK from Microcomputer

Setting Reset Delay Time and WDT time

Output

7

8

CT

VO

EXP-PAD

No Connection^{(Note 2)}

(Note 1) This pin is not connected to the chip. It can keep open or it’s also possible to connect to GND.

If Pin No.3 is shorted to GND, Pin No.3 will be adjacent to Pin No.2 CTL and Pin No.4 RO on the board layout.

If adjacent pins are expected to be shorted, please confirm if there is any problem with the actual application.

(Note 2) It is recommended to connect the EXP-PAD to the GND pattern to improve heat dissipation.

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BD4271xxx-C Series

Block Diagram

VCC

VO

TSD

OCP

Error

Amplifier

CTL

Reference

VO

CT

RO

Control

Reference

UVLO

CLK

GND

Block Descriptions

Block Name

Function

Description of Blocks

The TSD protects the device from overheating.

TSD

Reference

OCP

Thermal shutdown protection If the chip temperature (Tj) reaches ca. 175 °C (Typ),

the output is turned off.

Reference voltage

Over current protection

Under voltage lock out

Error amplifier

The Reference generates the Reference Voltage.

The OCP protects the device from damage caused by over current.

The UVLO prevents malfunction of the reset block in case of very low

output voltage.

UVLO

The Error Amplifier amplifies the difference between the feedback

voltage of the output voltage and the reference voltage.

Error Amplifier

Control

RESET + WDT time control The reset delay time and watchdog time can be programmed.

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BD4271xxx-C Series

Absolute Maximum Ratings

Parameter

Symbol

Ratings

Unit

Supply Voltage

V_CC

V_CTL

V_RO

V_O

-0.3 to +45.0

-0.3 to +7.0 (≤ V_O+ 0.3)

-0.3 to +7.0

V

Output Control Voltage

RO Voltage

V

Output Voltage

V

CLK Voltage

V_CLK

Tj

-0.3 to V_O+ 0.3

-40 to +150

V

Junction Temperature Range

Storage Temperature Range

Maximum Junction Temperature

°C

Tstg

Tjmax

-55 to +150

+150

Caution:

Exceeding the absolute maximum rating for supply voltage, operating temperature or other parameters can result in damages to or

destruction of the chip. In this event it also becomes impossible to determine the cause of the damage (e.g. short circuit, open circuit, etc.).

Therefore, if any special mode is being considered with values expected to exceed the absolute maximum ratings,

implementing physical safety measures, such as adding fuses, should be considered.

Recommended Operating Conditions

Parameter

Supply Voltage (I_O≤ 300 mA)

Supply Voltage (I_O≤ 550 mA)

Output Control Voltage

Symbol

V_CC

Min

Max

Unit

V

5.5

6.0

45.0

V_CC

V

V_CTL

0

45.0

V

Start -Up Voltage ^{(Note 1)}

Output Current

V_CC

I_O

－

V

3.0

0

550

mA

°C

Operating Ratings Temperature

Ta

-40

+125

(Note 1)

When I_O= 0 mA.

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BD4271xxx-C Series

Thermal Resistance^{(Note 1)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s ^{(Note 3)}

2s2p ^{(Note 4)}

HRP7

Junction to Ambient

Junction to Top Characterization Parameter ^{(Note 2)}

θ_JA

96.0

6

22.0

2

°C/W

Ψ_JT

TO263-7

Junction to Ambient

Junction to Top Characterization Parameter ^{(Note 2)}

θ_JA

80.7

8

20.3

2

°C/W

Ψ_JT

HTSOP-J8

Junction to Ambient

Junction to Top Characterization Parameter ^{(Note 2)}

θ_JA

131.7

12

33.0

5

°C/W

Ψ_JT

(Note 1) Based on JESD51-2A (Still-Air)

(Note 2) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 3) Using a PCB board based on JESD51-3.

(Note 4) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Thermal Via^{(Note 5)}

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

(Note 5) This thermal via connects with the copper pattern of all layers.

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BD4271xxx-C Series

Electrical Characteristics (LDO)

(Unless otherwise specified, Tj = -40 °C to +150 °C, V_CC= 13.5 V, V_CTL= 5 V, I_O= 0 mA, the typical value is defined

at Tj = +25 °C)

Limit

Parameter

Circuit Current

Symbol

Unit

Conditions

Min

Typ

75

Max

150

I_CC

I_ST

－

μA

V

I_O= 0 mA

V_CTL= 0 V

Tj ≤ 125 °C

Standby Current

－

4.90

－

2.0

5.00

0.2

60

9.0

5.10

0.5

－

6 V ≤ V_CC≤ 40 V

0 mA ≤ I_O≤ 300 mA

Output Voltage

V_O

8 V ≤ V_CC≤ 26 V

I_O≤ 550 mA

Output Voltage

V_O

V

V_CC= 4.75 V

I_O= 300 mA

Dropout Voltage

ΔV_d

R.R.

Reg.I

Reg.L

TSD

I_O

V

f = 120 Hz, ein = 1 Vrms

I_O= 100 mA

Ripple Rejection

－

dB

mV

°C

mA

V

Line Regulation

-30

－

30

8 V ≤ V_CC≤ 16 V

10 mA ≤ I_O≤ 300 mA

Tj at TSD ON

Load Regulation

10

40

Thermal Shutdown

Over Current Protection

CTL ON Mode Voltage

CTL OFF Mode Voltage

CTL Input Current

－

175

－

550

2.7

－

V_thH

V_thL

I_CTL

Active Mode

Off Mode

－

0.8

30

V

－

15

µA

V_CTL= 5 V

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BD4271xxx-C Series

Electrical Characteristics (Reset, WDT Function)

(Unless otherwise specified, Tj = -40 °C to +150 °C, V_CC= 13.5 V, V_CTL= 5 V, I_O= 0 mA, the typical value is defined

at Tj = +25 °C)

Limit

Parameter

Symbol

Unit

Conditions

Min

Typ

Max

4.77

Reset Detection Voltage

Reset Detection Hysteresis

Reset Pull-up Resistance

Reset Low Voltage

V_RT

V_RHYS

R_RO

V_RO

V_{CT_H}

V_{CT_L}

I_{CT_C}

I_{CT_D}

t_d

4.53

4.65

V

mV

kΩ

V

－

25

18

－

8

60

30

100

46

0.4

－

1.80

0.45

16

V

CT Upper-side Threshold

CT Lower-side Threshold

CT Charge Current

－

V

－

μA

ms

V_CT= 0.15 V

V_CT= 1.35 V

CT Discharge Current

Delay Time L→H

3

－

11.5

45

16

66

15

C_CT= 0.1 μF ^{(Note 1)}

WDT Monitor Time

t_WH

30

5

WDT Reset Time

t_WL

9

V_O

CLK Input High Level Voltage

CLK Input Low Level Voltage

V_HCLK

－

V_O

V

x 0.8

V_O

CLK is pulled down inside the IC

when CLK open.

V_LCLK

I_CLK

t_PCLK

V_OPR

0

1.5

3

－

5

V

μA

μs

V

x 0.3

CLK Input Current

15

－

V_CLK= 5 V

CLK Input Pulse Width

Minimum Operation Voltage

－

1

RO < 0.5 V

(Note 1)

t_d, t_WH, and t_WLcan be varied by changing the CT capacitance value. (0.001 μF to 10 μF available)

t_d1(ms) ≈ t_d(the Delay Time at 0.1 μF) x C_CT(μF) / 0.1

for example: when C_CT= 1 μF, 80 ms ≤ t_d≤ 160 ms

t_WH1(ms) ≈ t_WH(the WDT Monitor Time at 0.1 μF) x C_CT(μF) / 0.1

for example: when C_CT= 1 μF, 300 ms ≤ t_d≤ 660 ms

t_WL1(ms) ≈ t_WL(the WDT Reset Time at 0.1 μF) x C_CT(μF) / 0.1

for example: when C_CT= 1 μF, 50 ms ≤ t_d≤ 150 ms

CT Capacitor: 0.1 μF ≤ C_CT≤ 10 μF

t_d2(ms) ≈ t_d(the Delay Time at 0.1 μF) x C_CT(μF) / 0.1 ± 0.1

for example: when C_CT= 0.01 μF, 0.7 ms ≤ t_d≤ 1.7 ms

t_WH2(ms) ≈ t_WH(the WDT Monitor Time at 0.1 μF) x C_CT(μF) / 0.1 ± 0.1

for example: when C_CT= 0.01 μF, 2.9 ms ≤ t_d≤ 6.7 ms

t_WL2(ms) ≈ t_WL(the WDT Reset Time at 0.1 μF) x C_CT(μF) / 0.1 ± 0.1

for example: when C_CT= 0.01 μF, 0.4 ms ≤ t_d≤ 1.6 ms

CT Capacitor: 0.001 μF ≤ C_CT< 0.1 μF

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BD4271xxx-C Series

Typical Performance Curves (Unless otherwise specified, Tj = 25 °C, V_CC= 13.5 V, V_CTL= 5 V)

6

5

4

3

2

1

0

6

5

4

3

2

1

0

Tj = -40 ℃

Tj = 25 ℃

Tj = 125 ℃

Tj = -40 ℃

Tj = 25 ℃

Tj = 125 ℃

0

10

20

30

40

50

0

2

4

6

8

10

Supply Voltage : V_CC[V]

Figure 1. Output Voltage vs Supply Voltage

(R_L= 25 Ω)

Figure 2. Output Voltage vs Supply Voltage

(R_L= 25 Ω)

5.2

5.1

5.0

4.9

4.8

1500

1200

900

600

300

0

Tj = -40 °C

Tj = 25 °C

Tj = 150 °C

-40

0

40

80

120

160

0

10

20

30

40

50

Supply Voltage : V_CC[V]

Junction Temperature : Tj [℃]

Figure 3. Output Voltage vs Junction Temperature

(R_L= 1 kΩ)

Figure 4. Circuit Current vs Supply Voltage

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Typical Performance Curves - continued

150

130

110

90

150

120

90

60

30

0

70

50

0

100

200

300

400

500

600

-40

0

40

80

120

160

Junction Temperature : Tj [℃]

Output Current : I_O[mA]

Figure 5. Circuit Current vs Junction Temperature

Figure 6. Circuit Current vs Output Current

6

5

4

3

2

1

0

1200

1100

1000

900

Tj = -40 °C

Tj = 25 °C

Tj = 150 °C

800

0

200

400

600

800

1000

1200

-40

0

40

80

120

160

Junction Temperature : Tj [℃]

Output Current : I_O[mA]

Figure 8. Output Current vs Junction

Temperature

Figure 7. Output Voltage vs. Output Current

(Over Current Protection)

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Typical Performance Curves - continued

600

6

5

4

3

2

1

0

Tj = -40 °C

Tj = 25 °C

500

Tj = 150 °C

400

300

200

100

0

100

120

140

160

180

0

100

200

300

400

500

Junction Temperature : Tj [℃]

Output Current : I_O[mA]

Figure 10. Output Voltage vs Junction Temperature

(Thermal Shutdown)

Figure 9. Dropout Voltage vs Output Current

(V_CC= 4.75 V)

5

4

3

2

1

0

6

5

4

3

2

1

0

CTL ON

CTL OFF

Tj = -40 °C

Tj = 25 °C

Tj = 150 °C

0

1

2

3

4

5

-40

0

40

80

120

160

CTL Voltage : V_CTL[V]

Junction Temperature : Tj [℃]

Figure 12. CTL Voltage vs Junction Temperature

Figure 11. Output Voltage vs CTL Voltage

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BD4271xxx-C Series

Typical Performance Curves - continued

30

25

20

15

10

5

4.9

4.8

4.7

4.6

4.5

4.4

V

+ V

VRT + VRHY

RT

RHYS

V

VRT

RT

0

-40

0

40

80

120

160

-40

0

40

80

120

160

Junction Temperature : Tj [℃]

Figure 14. Reset Detection Voltage vs

Junction Temperature

Figure 13. CTL Current vs Junction Temperature

6

5

4

3

2

1

0

6

Tj = -40 °C

Tj = 25 °C

Tj = 150 °C

Tj = -40 °C

Tj = 25 °C

Tj = 150 °C

5

4

3

2

1

0

4.4

4.5

4.6

4.7

4.8

0.0

1.0

2.0

3.0

4.0

5.0

6.0

Output Voltage : V_O[V]

Figure 15. RO Voltage vs Output Voltage

Figure 16. RO Voltage vs Output Voltage

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Typical Performance Curves - continued

2.4

2.0

1.6

1.2

0.8

0.4

0.0

20

16

12

ICT charge

I_{CT_C}

V_CT

VCTH

_H

I_{CT_D}

ICT discharge

V_{CT_L}

VCTL

8

4

0

-40

0

40

80

120

160

-40

0

40

80

120

160

Junction Temperature : Tj [℃]

Figure 18. CT Voltage vs Junction Temperature

Figure 17. CT Current vs Junction Temperature

16

14

12

10

8

10000

1000

100

10

1

0.1

0.01

-40

0

40

80

120

160

0.001

0.01

0.1

1

10

Junction Temperature : Tj [℃]

CT Capacitance : C_CT[μF]

Figure 19. Delay Time L→H vs Junction Temperature

(C_CT= 0.1 µF)

Figure 20. Delay Time L→H vs CT Capacitance

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Typical Performance Curves - continued

70

60

50

40

10000

1000

100

10

t

tWH

WH

30

20

10

0

t_WL

tWL

1

t_W

tW

H

t_WL

tWL

0.1

0.01

0.001

0.01

0.1

1

10

-40

0

40

80

120

160

CT Capacitance : C_CT[μF]

Junction Temperature : Tj [℃]

Figure 22. Watchdog Time vs CT Capacitance

Figure 21. Watchdog Time vs Junction Temperature

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BD4271xxx-C Series

Measurement Circuit

FIN

CTL

GND

CLK

CTL

GND

CLK

CTL

GND

CLK

VCC

RO

CT

VO

VCC

RO

CT

VO

VCC

RO

CT

VO

I_O

V

A

0.1µF

10µF

0.1µF

10µF

0.1µF

10µF

Measurement setup for Figure 1,2,3,10.

Measurement setup for Figure 4,5.

Measurement setup for Figure 6.

FIN

CTL

GND

CLK

CTL

GND

CLK

CTL

GND

CLK

VCC

RO

CT

VO

VCC

RO

CT

VO

VCC

RO

CT

VO

V

I_O

A

V

10µF

0.1µF

10µF

0.1µF

10µF

Measurement setup for Figure 7,8.

Measurement setup for Figure 9.

Measurement setup for Figure 11,12,13.

FIN

CTL

GND

CLK

CTL

GND

CLK

CTL

GND

CLK

VCC

RO

CT

VO

VCC

RO

CT

VO

VCC

RO

CT

VO

V

Hꢀz

ꢀ

Hz

V

0.1µF

A

V

0.1µF

10µF

0.1µF

10µF

Measurement setup for Figure 19,20,21,22.

Measurement setup for Figure 17,18.

Figure 23. Measurement Circuit

Measurement setup for Figure 14,15,16.

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BD4271xxx-C Series

Timing Chart

1. When supply voltage V_CCis ON ↔ OFF (Not to input CLK voltage V_CLKwhen output voltage V_O= Low)

V_CC

13.5V

0V

V_CTL

5V

V_thH

V_RO

t_WHt_WL

t_d

≒V_o

V_CT

V_CLK

V_O

V_{CT_H}

V_{CT_L}

0V

5V

V_RHYS

V_RT

Figure 24. Timing Chart 1

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BD4271xxx-C Series

Timing Chart – continued

2. When output control voltage V_CTLis ON ↔ OFF (Not to input CLK voltage V_CLKwhen output voltage V_O= Low)

V_CC

13.5V

V_CTL

5V

V_thH

0V

V_thL

V_RO

t_wHt_wL

t_d

≒V_o

V_CT

V_{CT_H}

V_{CT_L}

V_CLK

0V

5V

V_O

V_RHYS

V_RT

Figure 25. Timing Chart 2

The Delay Time ( t_d) is estimated roughly by following calculation.

V_{CT_H}[V] × ꢀ_CT[F]

[ ]

t_ds ≈

I_{CT_C}[A]

Basically, verify the Delay Time ( t_d) by the ratio of the value at C_CT= 0.1 μF specified in datasheet and the actual C_CT

capacitance used to calculate.

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BD4271xxx-C Series

Timing Chart – continued

3. When WDT threshold Voltage V_CLKis ON ↔ OFF

V_CC

13.5V

V_CTL

5V

V_thH

V_RO

t_dt_wHt_wL

≒V_o

V_CT

V_{CT_H}

V_{CT_L}

V_CLK

t_PCLK

5V

0V

V_O

V_RHYS

5V

V_RT

Figure 26. Timing Chart 3

The WDT Monitor Time ( t_WH) and the WDT Reset Time ( t_WL) is estimated roughly by following calculation.

|V_{CT_H}− V_{CT_L}|[V] × ꢀ_CT[F]

I_{CT_D}[A]

|V_{CT_L}− V_{CT_H}|[V] × ꢀ_CT[F]

[ ]

t_WHs ≈

[ ]

t_WLs ≈

I_{CT_C}[A]

Basically, verify the WDT Monitor Time ( t_WH) and the WDT Reset Time ( t_WL) by the ratio of the value at C_CT= 0.1 μF

specified in datasheet and the actual C_CTcapacitance used to calculate

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Disable WDT behavior

VCC

CTL

CLK

VO

RO

CT

C_IN

C_O

R_CT

CT_SW

GND

C_CT

Figure 27. Application Circuit

V_O

5V

CT_SW

OFF

CT_SW

ON

CT_SW

OFF

V_CT

V_o

V_{CT_H}

V_{CT_L}

V_RO

t_wH

t_wL

Figure 28. Timing Chart 4

By pulling up the CT pin to the VO pin and keeping CT voltage above V_{CT_H}, RO switching and WDT behavior are disabled.

However, if under voltage reset is detected with the CT pin pulled up to the VO pin, the circuit that rapidly discharges the C_CT

electron will operate and current will flow into the CT pin. Therefore, when pulling up the CT pin to the VO pin, the pull up

resister must be required between the VO pin and the CT pin for limiting current.

Recommended pull up resistance: 10 kΩ ~ 200 kΩ

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Selection of Components Externally Connected

・VCC pin capacitor

Insert capacitors with a capacitance of 0.1 μF or higher between the VCC and GND pin. We recommend using ceramic

capacitor generally featuring good high frequency characteristic. When selecting a ceramic capacitor, please be

consider about temperature and DC-biasing characteristics. Place capacitors closest possible to VCC-GND pin. When

input impedance is high, e.g. in case there is distance from battery, line voltage drop needs to be prevented by large

capacitor. Choose the capacitance according to the line impedance between the power smoothing circuit and the VCC

pin. Selection of the capacitance also depends on the applications. Verify the application and allow sufficient margins

in the design. We recommend using a capacitor with excellent voltage and temperature characteristics.

・Output pin capacitor

In order to prevent oscillation, a capacitor needs to be placed between the output pin and GND pin. We recommend

using a ceramic capacitor with a capacitance of 6 μF or higher. In selecting the capacitor, ensure that the capacitance

of 6 μF or higher is maintained at the intended applied voltage and temperature range. Due to changes in temperature

the capacitor's capacitance can fluctuate possibly resulting in oscillation.

In actual applications the stable operating range is influenced by the PCB impedance, input supply impedance and

load impedance. Therefore verification of the final operating environment is needed. When selecting a ceramic

capacitor, we recommend using X7R or better components with excellent temperature and DC-biasing characteristics

and high voltage tolerance.

In case of the transient input voltage and the load current fluctuation, output voltage may fluctuate. In case this

fluctuation can be problematic for the application, connect low ESR capacitor (capacitance > 6 μF, ESR < 1 Ω) in

paralleled to large capacitor with a capacitance of 13 μF or higher and ESR of 5 Ω or lower. Electrolytic and tantalum

capacitors can be used as large capacitor. When selecting an electrolytic capacitor, please consider about increasing

ESR and decreasing capacitance at cold temperature.

Place the capacitor closest possible to output pin.

6

Unstable Available Area

5

4

3

Stable Available Area

2

1

0

1

10

100

1000

Output Capacitance : C_O[μF]

Figure 29. Output Capacitance ESR Available Area

-40 °C ≤ Tj ≤ +150 °C, 6 V ≤ V_CC≤ 45 V, V_CTL= 5 V, I_O= 0 mA to 550 mA

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Power Dissipation

◼

HRP7

IC mounted on ROHM standard board based on JEDEC.

(1) : 1-layer PCB

10

(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)

Board material: FR4

8

Board size: 114.3 mm x 76.2 mm x 1.57 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

(2) : 4-layer PCB

(2) 5.7 W

6

4

2

0

(2 inner layers and Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm)

Board material: FR4

Board size: 114.3 mm x 76.2 mm x 1.60 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

2 inner layers copper foil area of PCB:

74.2 mm x 74.2 mm, 1 oz. copper.

Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm, 2 oz. copper.

Condition (1): θ_JA= 96.0 °C/W, Ψ_JT(top center) = 6 °C/W

Condition (2): θ_JA= 22.0 °C/W, Ψ_JT(top center) = 2 °C/W

(1) 1.3 W

25

0

50

75

100

125

150

Ambient Temperature: Ta [°C]

Figure 30. HRP7 Package Data

◼

TO263-7

IC mounted on ROHM standard board based on JEDEC.

(1) : 1-layer PCB

10

(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)

Board material: FR4

8

Board size: 114.3 mm x 76.2 mm x 1.57 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

(2) : 4-layer PCB

(2) 6.16 W

6

4

2

0

(2 inner layers and Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm)

Board material: FR4

Board size: 114.3 mm x 76.2 mm x 1.60 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

2 inner layers copper foil area of PCB:

74.2 mm x 74.2 mm, 1 oz. copper.

(1) 1.55 W

0

25

50

Ambient Temperature: Ta [°C]

Figure 31. TO263-7 Package Data

75

100

125

150

Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm, 2 oz. copper.

Condition (1): θ_JA= 80.7 °C/W, Ψ_JT(top center) = 8 °C/W

Condition (2): θ_JA= 20.3 °C/W, Ψ_JT(top center) = 2 °C/W

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Power Dissipation – continued

◼

HTSOP-J8

IC mounted on ROHM standard board based on JEDEC.

(1) : 1-layer PCB

5

(Copper foil area on the reverse side of PCB: 0 mm x 0 mm)

Board material: FR4

(2) 3.79 W

Board size: 114.3 mm x 76.2 mm x 1.57 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

(2) : 4-layer PCB

4

3

2

1

0

(2 inner layers and Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm)

Board material: FR4

Board size: 114.3 mm x 76.2 mm x 1.60 mmt

Mount condition: PCB and exposed pad are soldered.

Top copper foil: ROHM recommended

footprint + wiring to measure, 2 oz. copper.

2 inner layers copper foil area of PCB:

74.2 mm x 74.2 mm, 1 oz. copper.

Copper foil area on the reverse side of PCB:

74.2 mm x 74.2 mm, 2 oz. copper.

Condition (1): θ_JA= 131.7 °C/W, Ψ_JT(top center) = 12 °C/W

Condition (2): θ_JA= 33 °C/W, Ψ_JT(top center) = 5 °C/W

(1) 0.95W

0

25

50

Ambient Temperature: Ta [°C]

Figure 32. HTSOP-J8 Package Data

75

100

125

150

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Thermal Design

This product exposes a frame on the back side of the package for thermal efficiency improvement.

Within this IC, the power consumption is decided by the dropout voltage condition, the load current and the circuit current.

Refer to power dissipation curves illustrated in Figure 30, 31 and 32 when using the IC in an environment of Ta ≥ 25 °C. Even

if the ambient temperature Ta is at 25 °C, depending on the input voltage and the load current, chip junction temperature can

be very high. Consider the design to be Tj ≤ Tjmax = 150 °C in all possible operating temperature range.

Should by any condition the maximum junction temperature Tjmax = 150 °C rating be exceeded by the temperature increase

of the chip, it may result in deterioration of the properties of the chip. The thermal impedance in this specification is based on

recommended PCB and measurement condition by JEDEC standard. Verify the application and allow sufficient margins in

the thermal design by the following method is used to calculate the junction temperature Tj.

Tj can be calculated by either of the two following methods.

1. The following method is used to calculate the junction temperature Tj.

Tj = Ta + P_C× θ_JA

Tj

: Junction Temperature

Ta

P_C

θ_JA

: Ambient Temperature

: Power Consumption

: Thermal Impedance (Junction to Ambient)

2. The following method is also used to calculate the junction temperature Tj.

Tj = T_T+ P_C× Ψ_JT

Tj

: Junction Temperature

T_T

P_C

Ψ_JT

: Top Center of Case’s (mold) Temperature

: Power Consumption

: Thermal Impedance (Junction to Top Center of Case)

The following method is used to calculate the power consumption P_C(W).

P_C= (V_CC- V_O) × I_O+ V_CC× I_CC

P_C

V_CC

V_O

I_O

: Power Consumption

: Supply Voltage

: Output Voltage

: Load Current

I_CC

: Circuit Current

・Calculation Example

If V_CC= 13.5 V, V_O= 5.0 V, I_O= 200 mA, I_CC= 85 μA, the power consumption P_Ccan be calculated as follows:

P_C= (V_CC- V_O) × I_O+ V_CC× I_CC

= (13.5 V – 5.0 V) × 200 mA + 13.5 V × 85 μA

= 1.7 W

At the ambient temperature Ta = 85 °C, the thermal impedance (Junction to Ambient) θ_JA= 22.0 °C/W (4-layer PCB),

Tj = Ta + P_C× θ_JA

= 85 °C + 1.7 W × 22.0 °C/W

= 122.4 °C

When operating the IC, the top center of case’s (mold) temperature T_T= 100 °C, Ψ_JT= 6 °C/W (1-layer PCB),

Tj = T_T+ P_C× Ψ_JT

= 100 °C + 1.7 W × 6 °C/W

= 110.2 °C

For optimum thermal performance, it is recommended to expand the copper foil area of the board, increasing the layer and

thermal via between thermal land pad.

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Application Examples

・Applying positive surge to the VCC

If the possibility exists that surges higher than 45 V will be applied to the VCC, a Zener Diode should be placed between

the VCC and GND as shown in the figure below.

VCC

VO

GND

・Applying negative surge to the VCC

If the possibility exists that negative surges lower than the GND are applied to the VCC, a Shottky Diode should be place

between the VCC and GND as shown in the figure below.

VCC

VO

GND

・Implementing a Protection Diode

If the possibility exists that a large inductive load is connected to the output pin resulting in back-EMF at time of startup

and shutdown, a protection diode should be placed as shown in the figure below.

VCC

VO

GND

・Reverse Polarity Diode

In some applications, the VCC and the VO potential might be reversed, possibly resulting in circuit internal damage or

damage to the elements. For example, the accumulated charge in the output pin capacitor flowing backward from the VO

to the VCC when the VCC shorts to the GND. In order to minimize the damage in such case, use a capacitor with a

capacitance less than 1000 μF. Also by inserting a reverse polarity diode in series to the VCC, it can prevent reverse current

from reverse battery connection or the case. When the point A is short-circuited GND, if there may be any possible case

point B is short-circuited to GND, we also recommend using a bypass diode between the VCC and the VO.

Bypass Diode

Reverse Polarity Diode

A

VCC

VO

B

GND

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BD4271xxx-C Series

I/O Equivalence Circuits ^{(Note 1)}

VCC

CTL

VCC

CTL

340 kΩ

370 kΩ

5 kΩ

IC

370 kΩ

140 kΩ

RO

CT

VO

30 kΩ

1 kΩ

0.1 kΩ

RO

CT

50 kΩ

CLK

VO

VCC

VO

50 kΩ

CLK

10 kΩ

1550 kΩ

Reset

Block

IC

1000 kΩ

525 kΩ

(Note 1) Resistance value is Typical.

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

terminals.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Separate the ground and supply lines of the

digital and analog blocks to prevent noise in the ground and supply lines of the digital block from affecting the analog

block. Furthermore, connect a capacitor to ground at all power supply pins. Consider the effect of temperature and

aging on the capacitance value when using electrolytic capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Thermal Consideration

The power dissipation under actual operating conditions should be taken into consideration and a sufficient margin

should be allowed for in the thermal design. On the reverse side of the package this product has an exposed heat pad

for improving the heat dissipation. Use both the front and reverse side of the PCB to increase the heat dissipation

pattern as far as possible. The amount of heat generated depends on the voltage difference across the input and output,

load current, and bias current. Therefore, when actually using the chip, ensure that the generated heat does not exceed

the Pd rating.

Should by any condition the maximum junction temperature Tjmax = 150 °C rating be exceeded by the temperature

increase of the chip, it may result in deterioration of the properties of the chip. The thermal impedance in this

specification is based on recommended PCB and measurement condition by JEDEC standard. Verify the application

and allow sufficient margins in the thermal design.

6. Recommended Operating Conditions

These conditions represent a range within which the expected characteristics of the IC can be approximately obtained.

The electrical characteristics are guaranteed under the conditions of each parameter.

7. Rush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

8. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

9. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

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Operational Notes – continued

10. Unused Input Terminals

Input terminals of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance

and extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input terminals should be connected to

the power supply or ground line.

11. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P/N junctions are formed at the intersection of these P layers with the N layers of other elements to create

a variety of parasitic elements.

For example, in case a resistor and a transistor are connected to the pins as shown in the figure below then:

○ The P/N junction functions as a parasitic diode when the GND > pin A for the resistor, or the GND > pin B for the

transistor.

○ Also, when the GND > pin B for the transistor (NPN), the parasitic diode described above combines with the N layer

of the other adjacent elements to operate as a parasitic NPN transistor.

Parasitic diodes inevitably occur in the structure of the IC. Their operation can result in mutual interference between

circuits and can cause malfunctions and, in turn, physical damage to or destruction of the chip. Therefore do not

employ any method in which parasitic diodes can operate such as applying a voltage to an input pin that is lower than

the (P substrate) GND.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

12. Ceramic Capacitor

When using a ceramic capacitor, determine the dielectric constant considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

13. Thermal Shutdown Circuit (TSD)

This IC incorporates and integrated thermal shutdown circuit to prevent heat damage to the IC. Normal operation

should be within the power dissipation rating, if however the rating is exceeded for a continued period, the junction

temperature (Tj) will rise and the TSD circuit will be activated and turn all output pins OFF. After the Tj falls below the

TSD threshold the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

14. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

15. Functional Safety

“ISO 26262 Process Compliant to Support ASIL-*”

A product that has been developed based on an ISO 26262 design process compliant to the ASIL level described in

the datasheet.

“Safety Mechanism is Implemented to Support Functional Safety (ASIL-*)”

A product that has implemented safety mechanism to meet ASIL level requirements described in the datasheet.

“Functional Safety Supportive Automotive Products”

A product that has been developed for automotive use and is capable of supporting safety analysis with regard to the

functional safety.

Note: “ASIL-*” is stands for the ratings of “ASIL-A”, “-B”, “-C” or “-D” specified by each product's datasheet.

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Ordering Information

B D 4

2

7

1

x

-

C x x

Part Number

Package

Product Rank

HFP: HRP7

FP2: TO263-7

EFJ: HTSOP-J8

C: for Automotive

Packaging and forming specification

TR: Embossed tape and reel

E2: Embossed tape and reel

Marking Diagram

HRP7 (TOP VIEW)

TO263-7 (TOP VIEW)

Part Number Marking

LOT Number

Part Number Marking

LOT Number

Pin 1 Mark

Pin 1

HTSOP-J8 (TOP VIEW)

Part Number Marking

LOT Number

Pin 1 Mark

Part Number Marking

Package

HRP7

Orderable Part Number

BD4271HFP-CTR

BD4271FP2-CE2

BD4271

TO263-7

HTSOP-J8

BD4271EFJ-CE2

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Physical Dimension, Tape and Reel Information

Package Name

HRP7

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BD4271xxx-C Series

Physical Dimension, Tape and Reel Information – continued

Package Name

TO263-7

< Tape and Reel Information >

Tape

Embossed carrier tape

500pcs

Quantity

Direction of feed E2

The direction is the pin 1 of product is at the lower left when you hold

reel on the left hand and you pull out the tape on the right hand

Direction of feed

1Pin

Reel

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Physical Dimension and Packing Information – continued

Package Name

HTSOP-J8

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Revision History

Date

Revision

001

Changes

New Release.

Mar.30.2016

Jun.21.2016

TO263-7 PKG added.

Thermal resistance format updated.

002

Subtitle correction.

Symbol correction “Reset Detection Hysteresis”.

Symbol correction “CT Upper-side Threshold”.

Symbol correction “CT Lower-side Threshold”.

Symbol correction “CT Charge Current”.

Symbol correction “CT Discharge Current”.

Formula correction “WDT Monitor Time”.

Formula correction “WDT Reset Time”.

Graph title correction Figure 13.

003

Mar.25.2021

Vertical axis label and Graph title correction Figure 14.

Legend correction Figure 17.

Legend correction Figure 18.

Vertical axis label and Graph title correction Figure 19.

Vertical axis label and Graph title correction Figure 20.

HTSOP-J8 PKG added.

Add Key Specifications “Functional Safety Supportive Automotive Products”

Electrical Characteristics parameter correction. “CLK Input High Level Voltage”.

Electrical Characteristics parameter correction. “CLK Input Low Level Voltage”.

Data correction Figure 11.

004

Mar.30.2023

Add Operational Notes “15. Functional Safety”.

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Notice

Precaution on using ROHM Products

(Note 1)

1. If you intend to use our Products in devices requiring extremely high reliability (such as medical equipment

,

aircraft/spacecraft, nuclear power controllers, etc.) and whose malfunction or failure may cause loss of human life,

bodily injury or serious damage to property (“Specific Applications”), please consult with the ROHM sales

representative in advance. Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses incurred by you or third parties arising from the use of any

ROHM’s Products for Specific Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are not designed under any special or extraordinary environments or conditions, as exemplified below.

Accordingly, ROHM shall not be in any way responsible or liable for any damages, expenses or losses arising from the

use of any ROHM’s Products under any special or extraordinary environments or conditions. If you intend to use our

Products under any special or extraordinary environments or conditions (as exemplified below), your independent

verification and confirmation of product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.); or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PAA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PAA-E

Rev.004


型号：	BD4271HFP-C
厂家：	ROHM
描述：	BD4271HFP-C是45V高耐压稳压器，内置监视其输出的复位电路(RESET)及看门狗计时器(WDT) 。输出电流能力550mA，但待机电流很低，适合用来降低系统的消耗电流。有对输出进行ON/OFF的CTL引脚，将CTL设为L可关闭输出，且能减少电流消耗。稳压器输出低于4.65V(Typ)时输出复位信号。复位信号的复位延迟时间、看门狗计时器监视时间可通过外接电容器进行调整。复位电路电容器稳压器
文件：	总34页 (文件大小：1950K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

BD4271HFP-C [ROHM]

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