BD5291GWL_技术文档

Datasheet

Operational Amplifiers

Input/Output Rail to Rail

Low Input Offset Voltage

Operational Amplifier

BD5291GWL

Key Specifications

General Description

◼ Operating Supply Voltage Range (Single Supply):

The BD5291GWL is a single operational amplifier with

Input/Output Rail-to-Rail. This features Input/Output

Rail-to-Rail operation with a supply voltage as low as 1.7

V, wide Input/Output range when operated at low voltage.

In addition, ultra low input bias current (1 pA typical) due

to MOSFET input, it is suitable for using sensor

amplifiers.

1.7 V to 5.5 V

2.5 V/µs (Typ)

-40 °C to +85 °C

◼ Slew Rate:

◼ Operating Temperature Range:

◼ Input Common-mode Voltage Range: V_SSto V_DD

◼ Input Offset Voltage:

±2.5 mV (Max)

70 dB (Min)

◼ Common-mode Rejection Ratio:

Package

UCSP50L1 (5Pin)

W (Typ) x D (Typ) x H (Max)

0.84 mm x 1.14 mm x 0.55 mm

Features

◼ Low Operating Supply Voltage

◼ Input/Output Rail-to-Rail

◼ Low Input Offset Voltage

◼ High Common Mode Rejection Ratio

◼ High Slew Rate

◼ Small Package WLCSP

Applications

◼ Buffer

◼ Active Filter

◼ Sensor Amplifier

◼ Battery-powered Equipment

Typical Application Circuit

R_F= 100 kΩ

V_DD= +1.65 V

R_IN= 1 kΩ

푅_퐹

푉_푂푈푇= −

푅_퐼푁

푉

퐼푁

V_IN

V_OUT

V_SS= -1.65 V

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays.

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Pin Configuration

1Pin Mark

Land Number

Pin Name

C

A

-IN

+IN

VDD

OUT

A1

A3

B2

C1

C3

OUT

VDD

VSS

-IN

B

A

B

VSS

C

VDD

3

+IN

3

OUT

1

-IN

1

2

+IN

Bottom View

Top View

(Mark Side)

Figure 1. Pin Configuration

Pin Description

Pin No.

Pin Name

Function

A1

A3

B2

C1

C3

OUT

VDD

VSS

-IN

Output

Positive power supply

Negative power supply / Ground

Inverting input

+IN

Non-inverting input

Block Diagram

C3

B2

C1

A3

A1

VDD

OUT

+IN

VSS

-IN

Iref

+

AMP

-

Description of Blocks

1. AMP:

This block is a full-swing output operational amplifier with class-AB output circuit and Rail-to-Rail differential input stage.

2. Iref:

This block supplies reference current which is needed to operate AMP block.

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Ordering Information

B D 5

2

9

1 G W L

-

E2

Part Number

BD5291GWL

Package

GWL: UCSP50L1

Packaging and forming specification

E2: Embossed tape and reel

(UCSP50L1)

Absolute Maximum Ratings(Ta = 25 °C)

Parameter Symbol

Supply Voltage

Ratings

Unit

V_DD-V_SS

V_ID

7

V

Differential Input Voltage^{(Note 1)}

V_DD- V_SS

Input Common-mode Voltage

Range

V_ICMR

(V_SS– 0.3) to (V_DD+ 0.3 )

V

Input Current^{(Note 2)}

I_I

±10

-55 to +150

150

mA

°C

Storage Temperature Range

Maximum Junction Temperature

Tstg

Tjmax

°C

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing

board size and copper area so as not to exceed the maximum junction temperature rating.

(Note 1) The differential input voltage indicates the voltage difference between inverting input and non-inverting input.

The input pin voltage is set to V_SSor more.

(Note 2) An excessive input current will flow when input voltages of more than V_DD+ 0.6 V or less than V_SS- 0.6 V are applied.

The input current can be set to less than the rated current by adding a limiting resistor.

Thermal Resistance ^{(Note 3)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

2s2p^{(Note 5)}

UCSP50L1

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 4)}

θ_JA

322.5

4.0

°C/W

Ψ_JT

(Note 3) Based on JESD51-2A (Still-Air).

(Note 4) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface

of the component package.

(Note 5) Using a PCB board based on JESD51-9.

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.5 mm x 101.5 mm x 1.6 mmt

2 Internal Layers

4 Layers

Top

Copper Pattern

Bottom

Copper Pattern

99.5 mm x 99.5 mm

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Thickness

70 μm

Footprints and Traces

99.5 mm x 99.5 mm

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

5.5

Unit

Single Supply

Dual Supply

1.7

Operating Supply Voltage

Vopr

Topr

3.3

V

±0.85

-40

±2.75

+85

Operating Temperature

+25

°C

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Electrical Characteristics

(Unless otherwise specified V_DD= 3.3 V, V_SS= 0 V, Ta = 25 °C)

Limits

Temperature

Parameter

Symbol

V_IO

Unit

Condition

Range

Min

-

Typ

0.1

Max

2.5

Input Offset Voltage ^{(Note 1) (Note}

25 °C

mV

V_DD= 1.8 V, 3.3 V

-

2)

Full range

-

3.8

Input Offset Voltage

ΔV_IO/ΔT Full range

-

0.8

-

μV/°C

Temperature Drift ^{(Note 1) (Note 2)}

Input Offset Current ^{(Note 1)}

Input Bias Current ^{(Note 1)}

I_IO

I_B

25 °C

-

1

-

pA

-

25 °C

-

650

-

900

R_L= ∞, Av = 0 dB,

V_+IN= V_DD/2

Supply Current ^{(Note 2)}

I_DD

V_OH

V_OL

μA

V

Full range

25 °C

-

970

V_DD-0.1

-

Maximum Output Voltage

(High) ^{(Note 2)}

R_L= 10 kΩ

V_DD= 1.8 V

V_DD= 3.3 V

Full range V_DD-0.1

-

25 °C

Full range

25 °C

-

V_SS+0.1

Maximum Output Voltage

(Low) ^{(Note 2)}

V

-

V_SS+0.1

80

0

105

-

Full range

25 °C

-

Large Signal Voltage Gain

A_V

dB

(Note 2)

110

-

Full range

-

1.8

V_DD= 1.8 V, V_SSto V_DD

V_DD= 3.3 V, V_SSto V_DD

Input Common-mode Voltage

Range

V_ICMR

CMRR

PSRR

I_SOURCE

25 °C

V

0

-

3.3

25 °C

Full range

25 °C

70

68

70

68

4

90

-

Common-mode Rejection

Ratio ^{(Note 2)}

dB

mA

-

90

-

Power Supply Rejection Ratio

(Note 2)

Full range

6

V_OUT= V_DD- 0.4 V

output short current

V_OUT= V_SS+ 0.4 V

output short current

Output Source Current ^{(Note 3)}

25 °C

-

17

15

35

2.5

9

Output Sink Current ^{(Note 3)}

Slew Rate

I_SINK

SR

25 °C

-

V/μs C_L= 25 pF

V_DD= 1.8 V, f = 100 kHz,

Open loop

-

3.0

3.2

-

MHz

Gain Bandwidth

GBW

25 °C

V_DD= 3.3 V, f = 100 kHz,

Open loop

Phase Margin

θ

25 °C

-

40

18

-

deg Open loop

Av = 40 dB, f = 1 kHz

Input Referred Noise Voltage

Vn

nV/ Hz

Total Harmonics Distortion

THD+N

0.005

%

V_OUT= 0.4 V_P-P, f = 1 kHz

(Note 1) Absolute value

(Note 2) Full range: Ta = -40 °C to +85 °C

(Note 3) Under the high temperature environment, consider the thermal resistance of IC when selecting the output current.

When the pin short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.

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Description of Electrical Characteristics

Described here are the terms of electric characteristics used in this datasheet. Items and symbols used are also shown. Note

that item name and symbol and their meaning may differ from those on another manufacture’s document or general document.

1. Absolute maximum ratings

Absolute maximum rating item indicates the condition which must not be exceeded. Application of voltage in excess of absolute

maximum rating or use out of absolute maximum rated temperature environment may cause deterioration of characteristics.

(1) Power supply voltage (VDD/VSS)

Indicates the maximum voltage that can be applied between the VDD pin and the VSS pin without deterioration or

destruction of characteristics of internal circuit.

(2) Differential input voltage (V_ID)

Indicates the maximum voltage that can be applied between the +IN pin and the -IN pin without deterioration and

destruction of characteristics of IC.

(3) Input common-mode voltage range (V_ICMR

)

Indicates the maximum voltage that can be applied to the +IN pin and the -IN pin without deterioration or destruction

of characteristics of IC. Input common-mode voltage range of the maximum ratings do not assure normal operation of IC.

When normal Operation of IC is desired, the input common-mode voltage range of electrical characteristics item must

be followed.

2.Electrical characteristics item

(1) Input offset voltage (V_IO)

Indicates the voltage difference between the +IN pin and the -IN pin. It can be translated into the input voltage

difference required for setting the output voltage at 0 V.

(2) Input offset voltage drift (ΔV_IO/ΔT)

Denotes the ratio of the input offset voltage fluctuation to the ambient temperature fluctuation.

(3) Input offset current (I_IO)

Indicates the difference of input bias current between the +IN pin and the -IN pin.

(4) Input bias current (I_B)

Indicates the current that flows into or out of the input pin. It is defined by the average of input bias current at the +IN

pin and input bias current at the -IN pin.

(5) Supply current (I_DD

Indicates the IC current that flows under specified conditions and no-load steady status.

(6) Maximum Output Voltage (High) / Maximum Output Voltage (Low) (V_OH/V_OL

)

Indicates the voltage range that can be output by the IC under specified load condition. It is typically divided into

maximum output voltage high and low. Maximum output voltage high indicates the upper limit of output voltage.

Maximum output voltage low indicates the lower limit.

(7) Large signal voltage gain (Av)

Indicates the amplifying rate (gain) of output voltage against the voltage difference between the +IN pin and the -IN

pin. It is normally the amplifying rate (gain) with reference to DC voltage.

Av = (Output voltage)/(Differential Input voltage)

(8) Input common-mode voltage range (V_ICMR

)

Indicates the input voltage range where IC operates normally.

(9) Common-mode rejection ratio (CMRR)

Indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. It is normally the

fluctuation of DC.

CMRR = (Change of Input common-mode voltage)/(Input offset voltage fluctuation)

(10) Power supply rejection ratio (PSRR)

Indicates the ratio of fluctuation of input offset voltage when supply voltage is changed. It is normally the fluctuation of DC.

PSRR = (Change of power supply voltage)/(Input offset voltage fluctuation)

(11) Output source current/ output sink current (I_SOURCE/I_SINK

)

The maximum current that can be output under specific output conditions such as output voltage, load conditions. It is

divided into output source current and output sink current. The output source current indicates the current flowing out

of the IC, and the output sink current the current flowing into the IC.

(12) Slew Rate (SR)

SR is a parameter that shows movement speed of operational amplifier. It indicates rate of variable output voltage

as specified unit time.

(13) Gain Bandwidth (GBW)

Indicates to multiply by the gain and the frequency where the voltage gain decreases 6 dB/octave.

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Description of Electrical Characteristics – continued

(14) Phase Margin (θ)

Indicates the margin of phase from 180 degree phase lag at the frequency at which the gain of operational amplifier

becomes 1.

(15) Input referred noise voltage (Vn)

Indicates a noise voltage generated inside the operational amplifier equivalent by ideal voltage source connected in

series with input pin.

(16) Total harmonic distortion (THD+N)

Indicates the fluctuation of harmonic components and noise components in the output signal.

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Typical Performance Curves

800

750

700

650

600

550

500

450

400

800

750

700

650

600

5.5 V

+85 °C

+25 °C

3.3 V

1.8 V

-40 °C

550

500

450

400

1

2

3

4

5

6

-50

-25

0

25

50

75

100

Ambient Temperature: Ta [°C]

Supply Voltage: V_DD[V]

Figure 3. Supply Current vs Ambient Temperature

Figure 2. Supply Current vs Supply Voltage

6

5

4

3

2

1

0

6

5

4

3

2

1

0

5.5 V

3.3 V

+85 °C

+25 °C

-40 °C

1.8 V

-50

-25

0

25

50

75

100

1

2

3

4

5

6

Supply Voltage:V_DD[V]

Ambient Temperature: Ta [°C]

Figure 4. Maximum Output Voltage (High) vs Supply Voltage

(R_L= 10 kΩ)

Figure 5. Maximum Output Voltage (High)

vs Ambient Temperature

(R_L= 10 kΩ)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

10

8

10

8

+85 °C

1.8 V

6

+25 °C

5.5 V

3.3 V

4

-40 °C

2

0

1

2

3

4

5

6

-50

-25

0

25

50

75

100

Supply Voltage: V_DD[V]

Ambient Temperature: Ta [°C]

Figure 6. Maximum Output Voltage (Low) vs Supply Voltage

(R_L= 10 kΩ)

Figure 7. Maximum Output Voltage (Low)

vs Ambient Temperature

(R_L= 10 kΩ)

40

35

30

80

70

60

50

40

30

20

10

0

+25 °C

-40 °C

25

+25 °C

-40 °C

20

15

+85 °C

10

5

0

1

2

3

4

5

6

0

1

2

3

4

Output Voltage: V_OUT[V]

Figure 9. Output Source Current

vs Output Voltage

Figure 8. Output Source Current vs Output Voltage

(V_DD= 3.3 V)

(V_DD= 5.5 V)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

20

18

16

14

70

60

50

40

30

20

10

0

-40 °C

12

5.5 V

10

3.3 V

8

+85 °C

+25 °C

6

1.8 V

4

2

0

-50

-25

0

25

50

75

100

0

1

2

3

4

Ambient Temperature: Ta [°C]

Output Voltage: V_OUT[V]

Figure 11. Output Sink Current vs Output Voltage

(V_DD= 3.3 V)

Figure 10. Output Source Current vs Ambient Temperature

(V_OUT= V_DD- 0.4 V)

40

140

120

-40 °C

30

20

10

0

100

80

5.5 V

3.3 V

+25 °C

60

+85 °C

40

20

0

1.8 V

-50

-25

0

25

50

75

100

0

1

2

3

4

5

6

Ambient Temperature: Ta[°C]

Output Voltage: V_OUT[V]

Figure 13. Output Sink Current

vs Ambient Temperature

(V_OUT= V_SS+ 0.4 V)

Figure 12. Output Sink Current vs Output Voltage

(V_DD= 5.5 V)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

4

3

4

3

2

3.3 V

5.5 V

+85 °C

+25 °C

1

0

-40 °C

1.8 V

-1

-2

-3

-4

-2

-3

-4

1

2

3

4

5

6

-50

-25

0

25

50

75

100

Supply Voltage: V_DD[V]

Ambient Temperature: Ta [°C]

Figure 14. Input Offset Voltage vs Supply Voltage

Figure 15. Input Offset Voltage

vs Ambient Temperature

4

3

160

140

120

100

80

+85 °C

2

+85 °C

+25 °C

1

-40 °C

+25 °C

0

-40 °C

-1

-2

-3

-4

60

40

20

0

-1

0

1

2

3

4

5

1

2

3

4

5

6

Input Common-mode Voltage: V_ICM[V]

Supply Voltage: V_DD[V]

Figure 17. Large Signal Voltage Gain

vs Supply Voltage

Figure 16. Input Offset Voltage vs Input

Common-mode Voltage

(V_DD= 3.3 V)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

160

140

160

140

120

100

80

5.5 V

3.3 V

120

100

+25 °C

-40 °C

1.8 V

80

+85 °C

60

40

20

0

60

40

20

0

-50

-25

0

25

50

75

100

1

2

3

4

5

6

Supply Voltage: V_DD[V]

Ambient Temperature: Ta [°C]

Figure 18. Large Signal Voltage Gain

vs Ambient Temperature

Figure 19. Common-mode Rejection Ratio

vs Supply Voltage

160

120

100

80

60

40

20

0

5.5 V

140

120

100

80

5.5 V

3.3 V

1.8 V

60

40

20

0

-50

-25

0

25

50

75

100

2

3

4

5

6

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

10 10 10 10 10 10

Ambient Temperature: Ta [°C]

Frequency: f [Hz]

FREQUENCY [Hz]

Figure 21. Common-mode Rejection Ratio

vs Frequency

Figure 20. Common-mode Rejection Ratio

vs Ambient Temperature

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

120

100

80

60

40

20

0

200

180

160

140

120

100

80

5.5 V

3.3 V

1.8 V

60

40

20

0

2

3

4

5

6

1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06

-50

-25

0

25

50

75

100

10

Frequency: f [Hz]

Ambient Temperature: Ta [°C]

AMBIENT TEMPERATURE[℃]

FREQUENCY [Hz]

Figure 22. Power Supply Rejection Ratio

vs Ambient Temperature

Figure 23. Power Supply Rejection Ratio

vs Frequency

(V_DD= 1.7 V to 5.5 V)

140

120

100

80

500

450

400

350

300

250

200

150

100

50

…..

60

40

20

0

1

10

10²

100

10³

1000

10⁴

10000

-50 -25

0

25

50

75

100 125

Frequency: f [Hz]

FREQUENCY [Hz]

Ambient Temperature: Ta [°C]

Figure 25. Input Referred Noise Voltage vs

Frequency

(V_DD= 3.3 V)

Figure 24. Input Bias Current

vs Ambient Temperature

(V_DD= 3.3 V)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves – continued

120

180

135

90

4.5

4

100

Phase

80

60

40

3.5

3

45

5.5 V

0

2.5

2

Gain

20

-45

-90

-135

-180

3.3 V

1.8 V

0

-20

-40

1.5

1

0.5

10²

10³

10⁴

10⁵

10⁶

10⁷

1.E+02 1.E+03 1.E+04 1.E+05 1.E+06 1.E+07

Frequency: f [Hz]

-50

-25

0

25

50

75

100

Ambient Temperature: Ta [°C]

TEMPERATURE [℃]

FREQUENCY [Hz]

Figure 26. Voltage Gain, Phase vs Frequency

(V_DD= 3.3 V, Open loop)

Figure 27. Unity Gain Frequency

vs Ambient Temperature

70

60

50

40

30

20

10

0

5

4.5

5.5 V

3.3 V

4

5.5 V

1.8 V

3.3 V

3.5

3

1.8 V

2.5

2

10

100

1000

-50

-25

0

25

50

75

100

LOAD CAPACITANCE [pF]

Load Capacitance: C_L[pF]

Ambient Temperature: Ta [°C]

TEMPERATURE [℃]

Figure 29. Phase Margin

vs Load Capacitance

Figure 28. Gain Bandwidth

vs Ambient Temperature

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves – continued

4

3

2

1

0

rise

3

2

fall

1

0

-50 -25

0

25

50

75 100 125

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

Supply Voltage: V [V]

Ambient Temperature: Ta [°C]

SUPPLY VOLTEGE [V]

DD

TEMPERATURE [℃]

Figure 30. Slew Rate vs Supply Voltage

Figure 31. Slew Rate

vs Ambient Temperature

(V_DD= 3.3 V)

0.25

0.55

0.50

0.45

0.40

0.35

0.30

0.25

0.20

0.15

0.10

0.05

4

9

8

7

6

5

4

3

2

1

0

-1

4

0.25

V_IN: 0.05 V/Div

V_IN:1.0V/Div

3

0.20

2

0.15

1

0.10

0

0.05

-1

0.00

V_OUT: 1.0V/Div

-2

3

0.25

-0.05

V_OUT: 0.05 V/Div

-3

2

0.20

-0.10

1

-4

0.15

-0.15

0

-5

0.10

-0.20

0.05

-6

-0.25

6

8

10 12 14 16 18 20 22 24 26 28

Ti

IM

6

8

10 12 14 16 18 20 22 24 26 28

Time [μs]

T E[μs]

me [μs]

TIME[μs]

Figure 32. Input and Output Wave Form

(V_DD= 5 V, A_V= 1, R_L= 2 kΩ, C_L= 10 pF

V_IN= 3 V_P-P, Ta = 25 °C)

Figure 33. Input and Output Wave Form

(V_DD= 5 V, A_V= 1, R_L= 2 kΩ, C_L= 10 pF

V_IN= 100 mV_P-P, Ta = 25 °C)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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Typical Performance Curves - continued

4

9

8

7

6

5

4

3

2

1

0

-1

4

0.25

0.45

0.4

V_IN: 1.0 V/Div

V_IN: 0.05 V/Div

3

0.20

2

0.15

0.35

0.3

1

0.10

0

0.05

0.25

0.2

-1

-2

0.00

V_OUT: 1.0 V/Div

V_OUT: 0.05 V/Div

3

-0.05

0.25

0.15

0.1

2

-3

-00..2100

1

-4

0.15

-0.15

0.05

0

0.10

-5

-0.20

0.05

-0.25

-0.05

-6

6

8

10 12 14 16 18 20 22 24 26 28

6

8

10 12 14 16 18 20 22 24 26 28

TIME[μs]

Time [μs]

Figure 35. Input and Output Wave Form

(V_DD= 5 V, A_V= -1, R_L= 2 kΩ, C_L= 10 pF

V_IN= 100 mV_P-P, Ta = 25 °C)

Figure 34. Input and Output Wave Form

(V_DD= 5 V, A_V= -1, R_L= 2 kΩ, C_L= 10 pF

V_IN= 3 V_P-P, Ta = 25 °C)

(*)The above characteristics are measurements of typical sample, they are not guaranteed.

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BD5291GWL

Application Information

NULL method condition for Test Circuit 1

V_DD, V_SS, E_K, V_ICM,V_RLUnit: V

V_RLCalculation

Parameter

V_F

SW1 SW2 SW3

V_DD

3.3

V_SS

0

E_K

V_ICM

Input Offset Voltage

V_F1

V_F2

V_F3

V_F4

V_F5

ON

OFF

-1.65 1.65

-

1.65

-

1

2

-0.5

0.9

-2.5

Large Signal Voltage Gain

ON

3.3

0

-1.5

Common-mode Rejection Ratio

(Input Common-mode Voltage Range)

ON

OFF

0

3

4

3.3

-

V_F6

V_F7

1.7

5.5

-

Power Supply Rejection Ratio

-0.9

0

Calculation

|ꢀ

|

ꢁ1

푉

퐼푂

=

[V]

1. Input Offset Voltage (V_IO)

ꢂ+ꢃ /ꢃ

ꢁ

푆

×(ꢂ+ꢃ /ꢃ )

퐴_ꢀ= 20퐿표푔 ^∆ꢀ

[dB]

퐸퐾

ꢁ

푆

|ꢀ ꢅꢀ

|

2. Large Signal Voltage Gain (Av)

ꢁꢄ

ꢁ3

×(ꢂ+ꢃ /ꢃ )

퐶푀푅푅 = 20퐿표푔 ^∆ꢀ

[dB]

ꢆꢇꢈ

ꢁ

푆

3. Common-mode Rejection Ratio (CMRR)

4. Power Supply Rejection Ratio (PSRR)

|ꢀ ꢅꢀ

|

ꢁ4

ꢁ5

×(ꢂ+ꢃ /ꢃ )

푃ꢉ푅푅 = 20퐿표푔 ^∆ꢀ

[dB]

퐷퐷

ꢁ

푆

|ꢀ ꢅꢀ

|

ꢁ6

ꢁ7

0.1 µF

R_F= 50 kΩ

0.01 µF

500 kΩ

SW1

V_DD

E_K

+15 V

NULL

-15 V

Vo

R_S= 50 Ω R_I= 1 MΩ

500 kΩ

0.015 µF

DUT

0.015 µF

SW3

R_L

R_I= 1 MΩ

1000 pF

R_S= 50 Ω

50 kΩ

VF

V_ICM

SW2

V_RL

V_SS

Figure 36. Test circuit 1

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BD5291GWL

Application Information - continued

Switch Condition for Test Circuit 2

Parameter

SW1 SW2 SW3 SW4 SW5 SW6 SW7 SW8 SW9 SW10 SW11 SW12

Supply Current

OFF OFF ON OFF ON OFF OFF OFF OFF OFF OFF OFF

OFF ON OFF OFF ON OFF OFF ON OFF OFF ON OFF

OFF ON OFF OFF ON OFF OFF OFF OFF ON OFF OFF

OFF OFF ON OFF OFF OFF ON OFF ON OFF OFF ON

ON OFF OFF ON ON OFF OFF OFF ON OFF OFF ON

Maximum Output Voltage R_L= 10 kΩ

Output Current

Slew Rate

Unit gain frequency

SW3

R2 100 kΩ

SW4

●

V_DD

－

＋

SW1 SW2

SW5 SW6 SW7

SW8 SW9 SW10 SW11 SW12

R1

1 kΩ

V_SS

R_LC_L

VIN+

V_OUT

VIN-

Figure 37. Test circuit 2

Input voltage

VH

VL

t

Input wave

Output voltage

90 %

SR = ΔV/Δt

VH

ΔV

10 %

VL

Δt

t

Output wave

Figure 38. Slew rate input output wave

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Application Information - continued

V_DD

1. Unused Circuits

When there are unused circuits, it is recommended that they are connected

as in right figure, and set the non-inverting input pin to electric potential within

the input common-mode voltage range (V_ICMR).

+

-

Connect

to V_ICM

V_ICM

2. Input Voltage

Applying V_DD+ 0.3 V to the input pin is possible without causing deterioration

of the electrical characteristics or destruction, regardless of the supply

voltage. However, this does not ensure circuit operation. Note that the circuit

operates normally only when the input voltage is within the common-mode

input voltage range of the electric characteristics.

V_SS

Figure 39. Example of application

unused circuit processing

3. Power Supply (single/dual)

The Op-Amp operates when the voltage is supplied between the VDD and

VSS pins. Therefore, the single supply Op-Amp can be used as dual supply

Op-Amp as well.

4. Output Capacitor

When the VDD pin is shorted to VSS(GND) electric potential in a state where electric charge is accumulated in the external

capacitor that is connected to the output pin, the accumulated electric charge flow through parasitic elements or pin

protection elements inside the circuit and discharges to the VDD pin. It may cause damage to the elements inside the

circuit (thermal destruction). When using this IC as an application circuit which does not constitute a negative feedback

circuit and does not occur the oscillation by an output capacitive load such as a voltage comparator, connect a capacitor

of 0.1 µF or less to the output pin to prevent IC damage due to accumulated discharge of the capacitor connected to the

output pin as mentioned above.

5. Oscillation by Output Capacitor

Phase margin of this IC is 40°. When using an application circuit that constitutes a feedback circuit, be careful about

oscillation due to a capacitive load. If the circuits has large size capacitor that is connected to output pin, insert of isolation

resistor between output pin and capacitive load.

6. Operation Under Strong Electromagnetic Field

Operating the IC in the presence of a strong electromagnetic field may cause the IC to malfunction.

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BD5291GWL

Application Example

Voltage follower

V_DD

Voltage gain is 0 dB.

Using this circuit, the output voltage (OUT) is configured

to be equal to the input voltage (IN). This circuit also

stabilizes the output voltage (OUT) due to high input

impedance and low output impedance. Expression for

output voltage (OUT) is shown below.

OUT

IN

ꢊꢋꢌ = ꢍꢎ

V_SS

Figure 40. Voltage follower

Inverting amplifier

R2

For inverting amplifier, input voltage (IN) is amplified by

a voltage gain and depends on the ratio of R1 and R2.

The out-of-phase output voltage is shown in the next

expression.

V_DD

R1

ꢊꢋꢌ = −(푅2/푅ꢏ) × ꢍꢎ

IN

OUT

This circuit has input impedance equal to R1.

R1//R2

V_SS

Figure 41. Inverting amplifier circuit

Non-inverting amplifier

For non-inverting amplifier, input voltage (IN) is amplified

by a voltage gain, which depends on the ratio of R1 and

R2. The output voltage (OUT) is in-phase with the input

voltage (IN) and is shown in the next expression.

R1

R2

V_DD

ꢊꢋꢌ = (ꢏ ꢐ 푅2/푅ꢏ) × ꢍꢎ

OUT

R1//R2

IN

Effectively, this circuit has high input impedance since its

input side is the same as that of the operational amplifier.

V_SS

Figure 42. Non-inverting amplifier circuit

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BD5291GWL

I/O Equivalence Circuits

Pin No.

Pin Name

Pin Description

Equivalence Circuit

A3

A1

OUT

Output

A1

B2

A3

C1

C3

-IN

+IN

C1, C3

B2

Input

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BD5291GWL

Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3.

4.

Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

8.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

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BD5291GWL

Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 43. Example of monolithic IC structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Disturbance Light

In a device where a portion of silicon is exposed to light such as in a WL-CSP and chip products, IC characteristics

may be affected due to photoelectric effect. For this reason, it is recommended to come up with countermeasures that

will prevent the chip from being exposed to light.

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BD5291GWL

Marking Diagram

UCSP50L1

Pin 1 Mark

(TOP VIEW)

Part Number Marking

LOT Number

KV

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BD5291GWL

Physical Dimension and Packing Information

Package Name

UCSP50L1 (BD5291GWL)

< Tape and Reel Information >

Tape

Embossed carrier tape

3000pcs

Quantity

Direction of feed E2

The direction is the pin 1 of product is at the upper left when you hold

reel on the left hand and you pull out the tape on the right hand

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BD5291GWL

Revision History

Date

Revision

001

Changes

02.Sep.2022

New Release

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BD5291GWL
厂家：	ROHM
描述：	The BD5291GWL is a single operational amplifier with Input/Output Rail-to-Rail. This features Input/Output Rail-to-Rail operation with a supply voltage as low as 1.7V, wide Input/Output range when operated at low voltage. In addition, ultra low input bias current (1pA typical) due to MOSFET input, it is suitable for using sensor amplifiers.
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BD5291GWL [ROHM]

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