BD60GA3WEFJ [ROHM]
BDxxGA3WEFJ系列是可提供0.3A输出电流的稳压器。输出精度为±1%。有可使用外接电阻在1.5V～13.0V范围内任意设置输出电压的可变型以及1.5V/1.8V/2.5V/3.0V/3.3V/5V/6V/7V/8V/9V/10V/12V固定输出型两种。封装组件采用散热性优良的HTSOP-J8。可用于数字家电等广泛用途。本机型内置用于防止因输出短路等发生IC破坏的过电流保护电路、关断时使电路电流为0µA的ON/OFF开关、以及防止因过负荷状态等使IC发生热破坏的温度保护电路。另外，采用了陶瓷电容器，有助于整机的小型化和长寿化。;
| 型号： | BD60GA3WEFJ |
| 厂家： | 
ROHM |
| 描述： | BDxxGA3WEFJ系列是可提供0.3A输出电流的稳压器。输出精度为±1%。有可使用外接电阻在1.5V～13.0V范围内任意设置输出电压的可变型以及1.5V/1.8V/2.5V/3.0V/3.3V/5V/6V/7V/8V/9V/10V/12V固定输出型两种。封装组件采用散热性优良的HTSOP-J8。可用于数字家电等广泛用途。本机型内置用于防止因输出短路等发生IC破坏的过电流保护电路、关断时使电路电流为0µA的ON/OFF开关、以及防止因过负荷状态等使IC发生热破坏的温度保护电路。另外，采用了陶瓷电容器，有助于整机的小型化和长寿化。 开关 过电流保护 电源电路 电容器 陶瓷电容器 线性稳压器IC |
| 文件： | 总12页 (文件大小：381K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Secondary Variable Output LDO Regulator Series for Local Power Supplies
300mA Secondary Variable Output
LDO Regulators for Local Power Supplies
No.10026EAT05
BD00GA3WEFJ
●Description
BD00GA3WEFJ is a LDO regulator with output current 0.3A. The output accuracy is ±1% of output voltage. With
external resistance, it is available to set the output voltage at random (from 1.5V to 13.0V) and also provides output
voltage fixed type without external resistance. It is used for the wide applications of digital appliances. It has package
type: HTSOP-J8. Over current protection (for protecting the IC destruction by output short circuit), circuit current
ON/OFF switch (for setting the circuit 0μA at shutdown mode), and thermal shutdown circuit (for protecting IC from heat
destruction by over load condition) are all built in. It is usable for ceramic capacitor and enables to improve smaller set
and long-life.
●Features
1) Output current 0.3A
2) High accuracy reference voltage circuit
3) Built-in Over Current Protection circuit (OCP)
4) Built-in Thermal Shut Down circuit (TSD)
5) With shut down switch
6) Output voltage variable type (1.5V to 13.0V)
7) Package: HTSOP-J8
●Output voltage differential Line up
Product name
Variable
Package
BD00GA3WEFJ
○
HTSOP-J8
Product name : BD00GA3WEFJ
a b c d
e
Signal
a
Description
Output voltage (V)
00
Variable
Voltage resistance(V)
E
F
24V
H
I
10V
7V
b
c
20V
15V
G
Output current (A)
A1
A3
A5
0.1A
0.3A
0.5A
C0
C5
D0
1.0A
1.5A
2.0A
Shutdown switch
“W”
Shutdown switch is built in
d
e
“
”
Shutdown switch is not built in
Package
EFJ
HTSOP-J8
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2010.04 - Rev.A
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© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BD00GA3WEFJ
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Vcc
Limits
15.0 *1
15.0
Unit
V
Power supply voltage
EN voltage
VEN
V
Output voltage
VOUT
VFB
15.0
V
Feedback voltage
15.0
V
Power dissipation
HTSOP-J8
Pd*2
2110 *2
-25～+85
-55～+150
+150
mW
℃
℃
℃
Operating Temperature Range
Storage Temperature Range
Topr
Tstg
Junction Temperature
Tjmax
*1 Not to exceed Pd
*2 Reduced by 16.9mW/℃ for each increase in Ta of 1℃ over 25℃. (when mounted on a board 70mm×70mm×1.6mm glass-epoxy board, two layer)
●Operating conditions (Ta=25℃)
Parameter
Input power supply voltage
EN voltage
Symbol
Vcc
VEN
Vo
Min.
4.5
0.0
1.5
0.0
Max.
14.0
14.0
13.0
0.3
Unit
V
V
Output voltage setting range
Output current
V
Io
A
This product should not be used in a radioactive environment.
●Electrical Characteristics
(Unless otherwise noted, Ta=25℃, EN=3V, Vcc=6V, R1=43kΩ, R2=8.2kΩ)
Parameter
Circuit current at shutdown mode
Bias current
Symbol
Isd
Min.
Typ.
0
Max.
5
Unit
μA
μA
mV
mV
V
Conditions
-
EN=0V, OFF mode
Icc
-
600
25
25
0.6
0.800
-
900
50
Line regulation
Reg.I
Reg Io
Vco
-
Vcc=( Vo+0.9V )→14.0V
Io=0→0.3A
Load regulation
-
75
Minimun dropout Voltage
Output reference voltage
EN Low voltage
-
0.792
0
0.9
0.808
0.8
14.0
9
Vcc=5V,Io=0.3A
Io=0mA
VFB
V
VEN (Low)
VEN (High)
IEN
V
EN High voltage
2.4
1
-
V
EN Bias current
3
μA
●I/O Equivalent circuits
8pin(VCC) / 1pin(VO)
2pin(FB)
5pin(EN)
Vcc
2pin(FB)
8pin(Vcc)
5pin(EN)
Vcc
1pin(Vo)
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2010.04 - Rev.A
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© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BD00GA3WEFJ
●Reference Data (Unless otherwise noted, Ta=25℃, EN=3V, Vcc=6V, R1=43kΩ, R2=8.2kΩ)
VEN
Vo
50mV/div
2V/div
Vo
50mV/div
Vcc
5V/div
Io
Io
0.2A/div
0.2A/div
Vo
5V/div
10usec/div
40ｍsec/div
200usec/div
Fig.1 Transient Response
Fig.2 Transient Response
Fig.3 Input sequence 1
(0→0.3A)
Co=1μF
(0.3→0A)
Co=1μF
Co=1μF
VEN
VEN
VEN
2V/div
2V/div
2V/div
Vcc
Vcc
Vcc
5V/div
5V/div
5V/div
Vo
Vo
Vo
5V/div
5V/div
5V/div
40msec/div
40msec/div
1ｍsec/div
Fig.6 OFF sequence 2
Fig.5 Inpurt sequence 2
Fig.4 OFF sequence 1
Co=1μF
Co=1μF
Co=1μF
1.0
800
5.2
0.8
0.6
0.4
0.2
0.0
700
600
500
400
5.1
5.0
4.9
4.8
85
75
-25
0
25
50
85
75
-25
0
25
50
85
75
-25
0
25
50
Ta [
]
℃
Ta [℃]
Ta [℃]
Fig.7 Ta-Vo (Io=0mA)
Fig.8 Ta-Icc
Fig.9 Ta-Isd
(VEN=0V)
5.2
5.0
4.0
3.0
2.0
1.0
0.0
8.0
6.0
4.0
2.0
0.0
5.1
5.0
4.9
4.8
85
-25
0
25
50
75
0
0.1
0.2
0.3
0
2
4
6
8
10
12
14
io [A]
Ta [ ]
℃
Vcc [V]
Fig.10 Ta-IEN
Fig.11 Io-Vo
3/11
Fig.12 Vcc-Isd
(VEN=0V)
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.04 - Rev.A
Technical Note
BD00GA3WEFJ
●Reference Data
6.0
4.0
2.0
0.0
6
6
5
4
3
2
1
0
4
2
0
0
2
4
6
8
10
12
14
100
120
140
Ta [
160
]
180
200
0
0.2
0.4
Io〔A〕
0.6
0.8
Vcc [V]
℃
Fig.13 Vcc-Vo (Io=0mA)
Fig.14 TSD (Io=0mA)
Fig.15 OCP
900
800
700
600
500
400
0.6
0.5
0.4
0.3
0.2
10.00
1.00
0.10
0.01
Safety area
0
0.1
0.2
0.3
85
-25
0
25
50
75
0
0.1
0.2
0.3
Io [A]
Ta [ ]
℃
Io[A]
Fig.18 Io-Icc
Fig.16 Minimum dropout Voltage1
Fig.17 ESR condencer
（Vcc=5V、Io=-0.3A）
0.6
0.5
0.4
0.3
0.2
0.1
0
100
0.6
0.5
0.4
0.3
0.2
0.1
0
80
60
40
20
0
0
0.1
0.2
0.3
0.1
1
10
100
0
0.1
0.2
0.3
Frequency[KHｚ]
Io [A]
Io[A]
Fig.19 PSRR(Io=0mA)
Fig.20 Minimum dropout Voltage 2
Fig.21 Minimum dropout Voltage 3
（Vcc=4.5V、Ta=25℃）
（Vcc=6V、Ta=25℃）
0.6
0.6
0.6
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
0.5
0.4
0.3
0.2
0.1
0
0
0.1
0.2
0.3
0
0.1
0.2
0.3
0
0.1
0.2
0.3
Io[A]
Io[A]
Io [A]
Fig.24 Minimum dropout Voltage 6
Fig.22 Minimum dropout Voltage 4
Fig.23 Minimum dropout Voltage 5
（Vcc=8V、Ta=25℃）
（Vcc=10V、Ta=25℃）
（Vcc=12V、Ta=25℃）
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.04 - Rev.A
4/11
Technical Note
BD00GA3WEFJ
●Heat Dissipation Characteristics
◎HTSOP-J8
Measure condition: mounted on a ROHM board, and IC
4.0
⑤3.76W
Substrate size: 70mm × 70mm × 1.6mm
(Substrate with thermal via)
・Solder the substrate and package reverse exposure heat
radiation part
3.0
④2.11W
① IC only
2.0
θj-a=249.5℃/W
② 1-layer（copper foil are :0mm×0mm）
θj-a=153.2℃/W
③ 2-layer（copper foil are :15mm×15mm）
θj-a=113.6℃/W
④ 2-layer（copper foil are :70mm×70mm）
θj-a=59.2℃/W
③1.10W
②0.82W
①0.50W
1.0
0
0
25
50
75
100
125
150
]
Ambient Temperature :Ta [℃]
⑤ 4-layer（copper foil are :70mm×70mm）
θj-a=33.3℃/W
●About Input-to-output capacitor
It is recommended that a capacitor is placed nearby pin between Input pin and GND, output pin and GND.
A capacitor, between input pin and GND, is valid when the power supply impedance is high or drawing is long. Also as for a
capacitor, between output pin and GND, the greater the capacity, more sustainable the line regulation and it makes improvement
of characteristics by load change. However, please check by mounted on a board for the actual application. Ceramic capacitor
usually has difference, thermal characteristics and series bias characteristics, and moreover capacity decreases gradually by
using conditions.
For more detail, please be sure to inquire the manufacturer, and select the best ceramic capacitor.
Ceramic capacitor capacity- DC bias characteristics
(Characteristics example)
10 Voltage resistance
B1 characteristics
10
GRM188B11A105KA61D
0
10 Voltage resistance
B characteristics
6.3 Voltage resistance
-10
B characteristics
-20
-30
10 Voltage resistance
F characteristics
-40
-50
4 Voltage resistance
-60
X6S characteristics
10 Voltage Resistance
F characteristics
-70
-80
-90
-100
0
1
2
3
4
DC Bias Voltage [V]
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© 2010 ROHM Co., Ltd. All rights reserved.
2010.04 - Rev.A
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Technical Note
BD00GA3WEFJ
●Heat Loss
Thermal design should allow operation within the following conditions. Note that the temperatures listed are the allowed
temperature limits, and thermal design should allow sufficient margin from the limits.
1. Ambient temperature Ta can be no higher than 85℃.
2. Chip junction temperature (Tj) can be no higher than 150℃.
Chip junction temperature can be determined as follows:
① Calculation based on ambient temperature (Ta)
Tj=Ta+θj-a×W
＜Reference values＞
1-layer substrate (copper foil density 0mm×0mm)
2-layer substrate (copper foil density 15mm×15mm)
2-layer substrate (copper foil density 70mm×70mm)
4-layer substrate (copper foil density 70mm×70mm)
θj-a: HTSOP-J8 153.2℃/W
113.6℃/W
59.2℃/W
33.3℃/W
Substrate size: 70×70×1.6mm3 (substrate with thermal via)
Most of the heat loss that occurs in the BD00GA3WEFJ is generated from the output Pch FET. Power loss is determined by
the total Vcc-Vo voltage and output current. Be sure to confirm the system input and output voltage and the output current
conditions in relation to the heat dissipation characteristics of the VIN and Vo in the design. Bearing in mind that heat
dissipation may vary substantially depending on the substrate employed (due to the power package incorporated in the
BD00GA3WEFJ make certain to factor conditions such as substrate size into the thermal design.
Power consumption (W) = Input voltage (VCC)- Output voltage (Vo) ×Io(Ave)
Example) Where VCC=5.0V, VO=3.3V, Io(Ave) = 0.1A,
Power consumption (W)
=
5.0(V)-3.3(V) ×0.1(A)
=0.17(W)
●About equivalent series resistance ESR (ceramic capacitor etc.)
Capacitor usually has ESR（Equivalent Series Resistance）, and
operates stable in ESR-OUT range, showed right. Generally, ESR of
ceramic, tantalum and electronic capacitor etc. is different for each,
so please be sure to check a capacitor which is going to use, and use
it inside the stable range, showed right. Then, please evaluate for the
actual application.
Capacity-Bias characteristics
100
10
1
0.1
0.01
0
50
100
150
200
IOUT [mA]
(Characteristics example)
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2010.04 - Rev.A
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© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BD00GA3WEFJ
●Block Diagram
BD00GA3WEFJ
(VO+0.90) to 14.0V
GND
VCC
≧ 1μF
Ceramic
Capacitor
OCP
SOFT
1.5V to 13.0V
VO
FB
R1
R2
≧ 1μF
Ceramic
Capacitor
EN
TSD
●Pin number ・ Pin name
Pin No.
Pin name
VOUT
FB
Pin Function
1
Output voltage pin
Feedback pin
2
3
GND
N.C.
EN
GND pin
4
Non Connection
Enable pin
5
6
N.C.
N.C.
VCC
FIN
Non Connection
Non Connection
Input voltage pin
Substrate(GND pin)
7
8
Reverse
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2010.04 - Rev.A
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© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BD00GA3WEFJ
●Evaluation Board Circuit
C3
C7
8
1
VOUT
VCC
N.C
C6
C5
R1
R2
C2
C1
C9
2
3
7
FB
C4
C10
R5
6
5
GND
N.C.
N.C
EN
U2
GND
U1
R6
SW1
4
EN
C8
R4
VOUT
R3
Gate
●Evaluation Board Parts List
Designation Value
Part No.
Company Designation Value
Part No.
Company
R1
R2
R3
R4
R5
R6
C1
C2
C3
43kΩ
8.2kΩ
‐
MCR01PZPZF4302
ROHM
C4
C5
C6
C7
C8
C9
C10
U1
U2
‐
‐
‐
MCR01PZPZF8201
‐
ROHM
‐
1uF
CM105B105K16A
KYOCERA
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
‐
1uF
‐
CM105B105K16A
KYOCERA
‐
BD00GA3WEFJ
‐
‐
‐
‐
ROHM
‐
‐
●About Board Layout
EN
GND
Cin
VCC (Vin)
R2
R1
Co
VO
･Input capacitor Cin of VCC (Vin) should be placed very close to VCC(Vin) pin as possible, and used broad wiring pattern.
Output capacitor Co also should be placed close to IC pin as possible. In case connected to inner layer GND plane, please
use several through hole.
・VFB pin has comparatively high impedance, and is apt to be effected by noise, so floating capacity should be minimum as
possible. Please be careful in wiring drawing
・Please take GND pattern space widely, and design layout to be able to increase radiation efficiency.
・For output voltage setting
Output voltage can be set by FB pin voltage（0.800V typ.）and external resistance R1, R2.
R1+R2
VO = VFB×
R2
（The use of resistors with R1+R2=5k to 90k is recommended）
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Technical Note
BD00GA3WEFJ
●Operation Notes
(1). Absolute maximum ratings
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc., can
break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit. If any
over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices, such as
fuses.
(2). Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
(3). Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply line,
separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply terminals to
ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic capacitors in the
circuit, not that capacitance characteristic values are reduced at low temperatures.
(4). GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
(5). Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating conditions.
(6). Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
(7). Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(8). ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
(9). Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is designed
only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation. Do not
continue to use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is
assumed.
TSD ON Temperature[℃] (typ.)
Hysteresis Temperature [℃] (typ.)
BD00GA3WEFJ
175
15
(10). Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to stress.
Always discharge capacitors after each process or step. Always turn the IC’s power supply off before connecting it to or
removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an antistatic
measure. Use similar precaution when transporting or storing the IC.
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2010.04 - Rev.A
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Technical Note
BD00GA3WEFJ
(11). Regarding input pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC.
The operation of parasitic diodes can result in mutual interference among circuits, operational faults, or physical damage.
Accordingly, methods by which parasitic diodes operate, such as applying a voltage that is lower than the GND (P substrate)
voltage to an input pin, should not be used.
Resistor
Transistor (NPN)
B
Pin A
Pin B
Pin B
C
E
Pin A
B
C
E
N
N
N
P+
P+
P+
P+
N
P
P
Parasitic
element
N
N
Parasitic
element
P substrate
P substrate
GND
GND
GND
GND
Parasitic element
Other adjacent elements
(12). Ground Wiring Pattern.
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns, placing a
single ground point at the ground potential of application so that the pattern wiring resistance and voltage variations caused by
large currents do not cause variations in the small signal ground voltage. Be careful not to change the GND wiring pattern of any
external components, either.
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2010.04 - Rev.A
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© 2010 ROHM Co., Ltd. All rights reserved.
Technical Note
BD00GA3WEFJ
●Type Designations (Ordering Information)
B D
0 0
G
A 3
W
E F J - E 2
Voltage
resistance
E:24V
F:20V
Shutdown switch Package
“W”：Built in EFJ ：HTSOP-J8
”：None
ROHM
Part Number
Output voltage
00 : Variable
Output cuurent
A1:0.1A
Packaging
specifications
E2:Emboss tape reel
“
A3:0.3A
A5:0.5A
G:15V
H:10V
I:7V
C0:1.0A
C5:1.5A
D0:2.0A
HTSOP-J8
<Tape and Reel information>
4.9 0.1
(MAX 5.25 include BURR)
Tape
Embossed carrier tape
2500pcs
(3.2)
+
Quantity
6
°
°
4°
−4
8
7
2
6
3
5
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
(
)
1
4
1PIN MARK
+0.05
-0.03
0.545
0.17
S
1.27
+0.05
0.42
0.08
-
0.04
M
0.08
S
Direction of feed
1pin
Reel
(Unit : mm)
Order quantity needs to be multiple of the minimum quantity.
∗
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2010.04 - Rev.A
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Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
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Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
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nication devices, electronic appliances and amusement devices).
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