BD64008MUV [ROHM]
是一款系统电机驱动器，在1枚芯片中集成了双通道H-Bridge驱动器（并联专用）、内置功率MOS的双通道降压开关稳压器（SWREG）以及复位输出功能。;
| 型号： | BD64008MUV |
| 厂家： | 
ROHM |
| 描述： | 是一款系统电机驱动器，在1枚芯片中集成了双通道H-Bridge驱动器（并联专用）、内置功率MOS的双通道降压开关稳压器（SWREG）以及复位输出功能。 开关 电机 驱动 驱动器 稳压器 |
| 文件： | 总39页 (文件大小：1502K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Datasheet
System Motor Driver
BD64008MUV
General Description
Key Specifications
This is a system motor driver with integrated 2ch
H-bridge driver (Parallel is for exclusive use), 2ch buck
switching regulator (SWREG) with built-in Power MOS,
and Reset output.
◼
◼
◼
◼
◼
◼
Input Voltage Range
9.0 V to 45.0 V
2.0 A/Phase
0 A to 2.0 A
0 A to 1.4 A
-25 °C to +85 °C
100 µA (Max)
Motor Rated Output Current
SWREG1 Output Current Range
SWREG2 Output Current Range
Operating Temperature Range
Standby Current
Features
◼
◼
◼
◼
◼
Low ON-resistance Output H-bridge Driver (2ch)
Built-in Regular Current Chopping Function
Over-current Protection in H-bridge Driver
3-line Serial Type Interface
H-bridge Parallel Driver (Large Mode) Single
Purpose
Package
W (Typ) x D (Typ) x H (Max)
7.0 mm x 7.0 mm x 1.0 mm
VQFN048V7070
◼
◼
◼
◼
◼
◼
◼
◼
◼
◼
SWREG (CH1) with Built-in P-ch Power DMOS FET
High Efficiency SWREG Function
Soft Start Function in SWREG
Over-current Protection (OCP) in SWREG
Output Under Voltage Protection (UVLO) in SWREG
SWREG Enable Function
Thermal Shutdown Function (TSD)
Power ON Reset
VBB Drop Detection Function
Micro Type, Ultra-thin Type, High Heat Dissipation
(Back side heat radiation) Package
Applications
◼
◼
Business Inkjet Printers
Large Format Printer, etc.
Typical Application Circuit
VBBA
VREFA
4bit DAC
(1/10)
OUTAP
OUTAM
RNFAS
RNFA
VREFB
RNFAS
PRE
DRIVER
LOGIC
VBBB
SLEEP
ENBA,ENBB
CLK,STB(LD),DAT
ID0,ID1,ID2
OUTBP
OUTBM
internal reg.
RSTIN
RNFB
RNFBS
ENBSW1
ENBSW2
PWM
internal reg.
VBBSW1
SWOUT1
MODE
PRE
DRIVER
R
S
Q
Q
DAC for
soft start
FB1
OSC
FB1
BOOT
R
S
DAC for
soft start
VINSW2
SWOUT2
PGNDSW2
FB2
PRE
DRIVER
COMP
OSC
internal reg.
Regulator
Clock
OCP
FB2
OCPDET
UVDET
RESET
UVDETIN
TSD
UVP
GND
〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays
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© 2017 ROHM Co., Ltd. All rights reserved.
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BD64008MUV
Pin Configuration
Block Diagram
[TOP VIEW]
29
VBBA
VREFA
2
4bit DAC
(1/5or1/10)
30
26
OUTAP
OUTAM
RNFAS
VREFB
3
28
27
RNFA
RNFAS
36 35 34 33
30 29 28 27 26 25
32 31
PRE
DRIVER
LOGIC
SLEEP
ENBA,ENBB
CLK,STB(LD),DAT
ID0,ID1,ID2
4
to 10
12
10
37
38
39
40
VBBSW1
VBBSW1
32
31
VBBB
24 PGNDSW2
RSTIN
46
OUTBP
23
22
SWOUT2
SWOUT2
35 OUTBM
internal reg.
internal reg.
13
33
SWOUT1
SWOUT1
ENBSW1
ENBSW2
PWM
RNFB
3
3
14
34 RNFBS
15
21
20
BOOT
37
GND 41
FB1 42
VINSW2
VBBSW1
38
47
MODE
39
PRE
DRIVER
SWOUT1
40
19
18
17
16
15
14
13
VINSW2
FB2
R
S
Q
Q
DAC for
soft start
FB1
43
44
45
46
47
48
OCPDET
OSC
42
21
FB1
UVDET
RESET
RSTIN
COMP
BOOT
GND
R
S
DAC for
soft start
FB2
PRE
DRIVER
19
20
VINSW2
EXP-PAD
PWM
OSC
22
23
COMP 17
SWOUT2
PGNDSW2
Internal reg.
MODE
24
25
ENBSW2
ENBSW1
UVDETIN
Regulator
Clock
OCP
18
43
44
45
FB2
OCPDET
UVDET
RESET
1
2
3
4
5
6
7
8
9
10 11 12
48
UVDETIN
TSD
UVP
1
16 36 41
GND
Pin Description
No. Pin Name
I/O
Function
No. Pin Name
25 PGNDSW2
I/O
Function
1
2
GND
-
Ground
-
SWREG2 power ground
VREFA
I
H-Bridge A output current setting 26
OUTAM
RNFAS
O
H-Bridge A output (-)
H-Bridge A current detection
3
VREFB
I
Connect to VREFA
27
I
input pin
4
5
6
7
8
9
SLEEP
ENBA
ENBB
CLK
I
I
-
I
I
I
Sleep mode setting
H-Bridge A enable input
No function (OPEN or GND)
Serial CLK input
28
29
30
31
32
33
RNFA
VBBA
O
-
H-Bridge A current detection pin
H-Bridge A power supply (42 V)
H-Bridge A output (+)
OUTAP
OUTBP
VBBB
O
O
-
H-Bridge B output (+)
STB(LD)
DAT
Serial STB(LD) input
Serial DAT input
H-Bridge B power supply (42 V)
H-Bridge B current detection pin
RNFB
O
H-Bridge B current detection
input pin
10
ID0
I
ID 0 setting
34
RNFBS
I
11
12
ID1
ID2
I
I
I
I
I
-
ID 1 setting
35
36
37
38
OUTBM
GND
O
-
H-Bridge B output (-)
Ground
ID 2 setting
13 ENBSW1
14 ENBSW2
SWREG1 enable input
SWREG2 enable input
SWREG2 PWM compulsion
Ground
VBBSW1
VBBSW1
-
SWREG1 power supply (42 V)
SWREG1 power supply (42 V)
SWREG1 output
SWREG1 output
Ground
-
15
16
17
18
19
20
21
PWM
GND
39 SWOUT1
40 SWOUT1
O
O
-
COMP
FB2
I/O SWREG2 phase compensation
41
42
43
44
45
46
47
48
GND
FB1
I
-
SWREG2 feedback
I
SWREG1 feedback
OCP detection
VINSW2
VINSW2
BOOT
SWREG2 power supply (5 V)
SWREG2 power supply (5 V)
SWREG2 H-side Nch booster
SWREG2 output
OCPDET
UVDET
RESET
RSTIN
MODE
UVDETIN
O
O
O
I
-
VBB drop detection
Reset out
I
22 SWOUT2
23 SWOUT2
24 PGNDSW2
O
O
-
Reset input
SWREG2 output
I
Connect to GND
UVDET setting
SWREG2 power ground
I
The EXP-PAD is connected to
GND.
-
EXP-PAD
-
-
-
-
-
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BD64008MUV
Absolute Maximum Ratings (Ta = 25 °C)
Parameter
Symbol
VBB
Limit
-0.4 to +50.0
-0.4 to +50.0
-0.4 to +50.0
-0.4 to +7.0
-0.4 to +7.0
-0.4 to +5.5
5.5
Unit
VBB Applied Voltage(Note 1)(Note 2)
Motor Output Voltage(Note 3)
SWOUT1 Voltage
V
VMOUT
VSWOUT1
VINSW2
VSWOUT2
VLI
V
V
VINSW2 Applied Voltage(Note 1)
V
SWOUT2 Voltage
Logic Input Voltage(Note 4)
Logic Output Voltage(Note 5)
V
V
VLO
V
RNF Voltage (DC)
RNF Voltage (peak)(Note 6)
Power Dissipation(Note 7)
VRNF(DC)
VRNF(peak)
Pd
0.55
V
2.5
V
4.83
W
Motor Output Current (DC)(Note 1)
SWOUT1 Output Current (DC)(Note 1)
SWOUT1 Output Current (peak)(Note 1)(Note 6)
SWOUT2 Output Current (DC)(Note 1)
SWOUT2 Output Current (peak)(Note 1)(Note 6)
Storage Temperature Range
Maximum Junction Temperature
IOMAXMT(DC)
2.0
A/Phase
2.2
A
A
IOMAXSW1(DC)
IOMAXSW1(peak)
IOMAXSW2(DC)
IOMAXSW2(peak)
Tstg
2.4
1.5
A
1.65
A
-55 to +150
°C
Tjmax
150
°C
Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit
between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is
operated over the absolute maximum ratings.
Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the
properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with power dissipation taken into consideration by
increasing board size and copper area so as not to exceed the maximum junction temperature rating.
(Note 1) Must not exceed Pd and Tj = 150 °C
(Note 2) Supply = VBBA, VBBB, VBBSW1
(Note 3) Motor Output = OUTAP, OUTAM, OUTBP, OUTBM
(Note 4) Logic Input = SLEEP, ENBA, ENBB, CLK, STB(LD), DAT, ID0, ID1, ID2, ENBSW1, ENBSW2, PWM, RSTIN, MODE
(Note 5) Logic Output = OCPDET, UVDET, RESET
(Note 6) peak = 1 μs
(Note 7) When mounted on a 4-layer recommended board (74.2 mm x 74.2 mm x 1.6 mm), reduce by 37.3 mW/°C when Ta ≥ 25 °C
Recommended Operating Conditions
Parameter
Symbol
Min
Typ
Max
Unit
Operating Temperature
Topr
VBB
-25
9.0
-
-
-
+85
45.0
-
°C
V
VBB Applied Voltage(Note 8)(Note 9)
CLK Max Operating Frequency
SWREG1 Output Voltage Setting
SWREG2 Output Voltage Setting
SWREG1 Output Current(Note 10)
SWREG2 Output Current(Note 10)
VINSW2 Applied Voltage
fCLOCK
VOUT1
VOUT2
ISW1
40
-
MHz
V
3.0
0.8
0
13.0
3.6
2.0
1.4
5.5
-
V
-
A
ISW2
0
-
A
VINSW2
3.0
-
V
(Note 8) When VBB is under POR, H-Bridge, SWREG and circuit protection are disabled.
(Note 9) Supply = VBBA, VBBB, VBBSW1
(Note 10) Must not exceed Pd and Tj = 150 °C
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© 2017 ROHM Co., Ltd. All rights reserved.
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BD64008MUV
Electrical Characteristics (Unless otherwise specified VBB = 42 V, Ta = 25 °C)
Specification
Parameter
Symbol
Unit
Conditions
Min
Typ
Max
[Overall]
VBB Current (Standby)(Note 1)
VBB Current (Active)(Note 1)
VINSW2 Current
IBBST
IBB
-
-
20
8.5
0
100
13.0
10
µA
SLEEP = L, ENBSW1 = H
mA SLEEP = H, ENBSW1 = L
µA
IINSW2
VPORH
VPORHY
-
POR Threshold Voltage H
POR Hysteresis Voltage
[H-Bridge]
6
7
8
V
V
VBB Input timing
0.5
1.0
1.5
Output ON-Resistance (H-side)
Output ON-Resistance (L-side)
RONH
RONL
-
-
0.75
0.45
1.05
0.75
Ω
Ω
IOUT = 1 A
IOUT = 1 A
Built-in Diode Forward Voltage
(H-side)
Built-in Diode Forward Voltage
(L-side)
VFH
VFL
-
-
1.0
1.0
1.3
1.3
V
V
IOUT = 1 A
IOUT = 1 A
[Current Control]
VREF Voltage Range
VREF Input Current
RNF Input Current
VVREF
IVREF
IRNF
0
-1
5
-
0
3.7
+1
30
+4
V
µA
µA
%
VVREF = 3.3 V
VVREF = 3.3 V
15
0
(Note2)
VREF to RNFS Offset Voltage
VOFST
-4
[Control Logic 1 (DAT, CLK, STB(LD), ENBA, ENBB, SLEEP, RSTIN, ID0, ID1, ID2)]
H Level Input Voltage 1
L Level Input Voltage 1
Input Current 1
VIN1H
VIN1L
IIN1
2.0
-
-
-
-
V
V
0.8
50
15
33
µA
Input voltage = 3.3 V
[Control Logic 2 (ENBSW1, ENBSW2, PWM)]
H Level Input Voltage 2
L Level Input Voltage 2
Input Current 2
VIN2H
VIN2L
IIN2
2.0
-
-
-
-
V
V
0.8
-3
-18
-9
µA
Input voltage = 0 V
Input voltage = 0 V
[Control Logic 3 (MODE)]
Input Current
IIN3
-85
-50
-30
µA
[Switching Regulator 1 Block]
FB1 Threshold Voltage
Output ON-Resistance
FB1 Pin Current
VFBSW1
RONSW1
IFBSW1
0.99
-
1.00
0.65
0
1.01
0.85
+0.1
0.79
V
Ω
ISWOUT1 = 1 A
-0.1
0.71
µA
V
VFB1 = 1 V
FB1 Low Input Voltage
[Switching Regulator 2 Block]
FB2 Threshold Voltage
Output ON-Resistance (H-side)
Output ON-Resistance (L-side)
FB2 Pin Current
VFBUVP1
0.75
Common with RESET detection
VFBSW2
RONHSW2
RONLSW2
IFBSW2
0.792 0.800 0.808
V
Ω
-
0.20
0.20
0
0.26
0.26
+0.1
0.52
ISWOUT2 = 1 A
ISWOUT2 = 1 A
VFB2 = 0.8 V
-
Ω
-0.1
0.28
µA
V
FB2 Low Input Voltage
[RESET, UVDET, OCPDET]
Low Output Voltage
VFBUVP2
0.40
VOD
tRST
-
-
0.2
60
V
IOUT = 1 mA
RESET Output Delay Time
40
50
ms
RSTIN Minimum Input Pulse
Width
tRSTIN
-
-
13
µs
Refer to P.7 1.4
UVDET Base Voltage
VUV
0.552 0.600 0.648
0.05
V
V
UVDET Hysteresis Voltage
VUVHYS
-
-
(Note 1) Total current value of the VBBA, VBBB, VBBSW1 pins.
(Note 2) VOFST = ((VVREF × Current_Ratio / α) – VRNFS) / (VVREF × Current_Ratio / α), α = 10
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BD64008MUV
Recommended Range of External Constants
Characteristics may vary due to factors such as the mounting conditions and the temperature dependence of the external
parts. Be certain to evaluate these values with respect to the actual intended application.
VBBA
VREFA
0.01 µF220 µF
4bit DAC
(1/10)
OUTAP
OUTAM
RNFAS
RNFA
VREFB
RNFAS
PRE
DRIVER
LOGIC
VBBB
SLEEP
ENBA,ENBB
CLK,STB(LD),DAT
ID0,ID1,ID2
OUTBP
OUTBM
C3
internal reg.
C3
RSTIN
RNFB
RNFBS
ENBSW1
ENBSW2
PWM
internal reg.
VBBSW1
SWOUT1
MODE
L1
PRE
C1
DRIVER
R1
C2
R
S
Q
Q
DAC for
soft start
FB1
R2
OSC
FB1
BOOT
0.1 µF
R
S
DAC for
soft start
VINSW2
SWOUT2
PGNDSW2
FB2
PRE
DRIVER
C4
L2
COMP
OSC
R5
R3
R4
Internal reg.
C5 C6
2700 pF
Regulator
Clock
OCP
FB2
OCPDET
UVDET
RESET
UVDETIN
TSD
UVP
GND
Figure 1. BD64008MUV Recommended Range of External Components Circuit Diagram
Recommended Values
Parameter
Symbol
Unit
Min
Typ
330
Max
470
470
22
SWOUT1 (5 V setting)
SWOUT1 (3.3 V setting)
SWOUT1
C1
C1
220
µF
µF
µF
pF
µF
µF
µH
µH
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
kΩ
220
330
-
C2
0
OUTxx(Note 1) (50 V capacity)
VINSW2-PGNDSW2
SWOUT2
C3
-
1000
40
-
C4
10
22
20 / 20
47
C5 / C6
L1
-
33
-
SWOUT1
68
SWOUT2
L2
1.5
1.8
2.2
-
FB1 (5 V setting)
R1 / R2
R1 / R2
R3 / R4
R3 / R4
R3 / R4
R3 / R4
R5
3.3 / 0.82
3.0 / 1.3
-
33 / 8.2
30 / 13
75 / 24
30 / 24
13 / 15
33 / 82
18
-
-
-
-
-
-
-
-
FB1 (3.3 V setting)
FB2 (3.3 V setting)
FB2 (1.8 V setting)
FB2 (1.5 V setting)
FB2 (1.125 V setting)
COMP (3.3 V setting)
COMP (1.5 V to 1.8 V setting)
COMP (1.125 V setting)
-
1.3 / 1.5
3.3 / 8.2
-
-
R5
9.1
-
R5
8.2
(Note 1) xx = AP, AM, BP, BM.
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BD64008MUV
Pin Processing • Condition List
1
Pin Connections when H-Bridge is Not in Use
The pin processing shown in the table below is recommended.
To use H-bridge in parallel, please set Ach and Bch at the same time.
When H-Bridge is in use, refer to 6.
RNFx(Note 1)
OUTxP(Note 1)
ENBx(Note 1)
VREFx(Note 1)
RNFxS(Note 1)
OUTxM(Note 1)
Ach
Bch
OPEN or GND
OPEN or GND
GND
GND
GND
GND
OPEN
OPEN
(Note 1) x = A, B
The overcurrent protection may fail if VREFx and RNFx/RNFxS are left OPEN.
(However, there is no problem even if Voltage is applied to the VREFx pin only when ENBx is Low and output is open
with no serial input.)
2
Pin Connections when SWREG is Not in Use
The pin processing shown in the table below is recommended.
ENBSWx(Note 2)
FBx(Note 2)
SWOUTx(Note 2)
COMP
-
BOOT
-
VINSW2
-
1ch
2ch
OPEN
GND
OPEN
OPEN
GND
OPEN
OPEN
OPEN
OPEN
(Note 2) x = 1, 2
3
4
Condition of the MODE pin
Please connect the MODE pin to GND by all means.
Active Condition of Logic Input Pins
Logic input pins
Non-active condition
Active condition
(OPEN case)
DAT, CLK, STB(LD), ENBA, ENBB,
SLEEP, RSTIN, ID0, ID1, ID2
H (2.0 V or more)
L (0.8 V or less)
L (0.8 V or less)
H (2.0 V or more)
ENBSW1, ENBSW2, PWM
5
6
Condition of the SLEEP pin
Logic input pins
Data accept mode
H (2.0 V or more)
Power save mode
L (0.8 V or less)
SLEEP
When SLEEP = L, ENBSW1 = H and ENBSW2 = H, the condition is stand-by. The IC switches to power save mode.
In this case, RESET output (P.7), Thermal shutdown (P.24), over-current (P.24) and output under voltage protection
turn OFF.
Processing of Bch Pins
To use H-Bridge in parallel, please don’t set Bch independently. Please obey the following instructions.
Pins
Method of processing
OPEN or connect with GND
OPEN or connect with VREFA
Connect with RNFA
ENBB
VREFB
RNFB
RNFBS
OUTBP
OUTBM
Connect with RNFAS
Connect with OUTAP
Connect with OUTAM
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BD64008MUV
Explanation of Block Operation
BD64008MUV is composed of four blocks namely; H-Bridge Driver, SWREG1, SWREG2, and Protection Function block as
shown in Figure 2.
29
VBBA
4bit DAC
(1/5or1/10)
VREFA
2
3
30
26
OUTAP
OUTAM
RNFAS
VREFB
28
27
RNFA
RNFAS
PRE
DRIVER
SLEEP
ENBA,ENBB
CLK,STB(LD),DAT
ID0,ID1,ID2
LOGIC
4
to
12
32
31
VBBB
46
RSTIN
OUTBP
35 OUTBM
13
14
15
33
ENBSW1
ENBSW2
PWM
H-Bridge Driver
RNFB
34 RNFBS
SWREG
37
SWREG1
VBBSW1
38
47
MODE
39
PRE
DRIVER
SWOUT1
40
R
S
Q
Q
DAC for
soft start
FB1
OSC
42
21
FB1
BOOT
R
S
DAC for
soft start
PRE
DRIVER
FB2
19
20
VINSW2
OSC
22
23
COMP 17
SWOUT2
PGNDSW2
SWREG2
24
25
Internal reg.
Regulator
Clock
OCP
18
43
44
45
FB2
OCPDET
UVDET
RESET
TSD
UVP
48
UVDETIN
Protection
Function
1
16 36 41
GND
Figure 2. Explanation of Circuit Operation
1
Overall
1.1 Power supply (VBB) input
Input power supply 300 µs or more at 0 V to VPORH (7 V (Typ))
1.2 Control Logic Input
Control logic input for DAT, CLK, STB(LD), ENBA, ENBB, SLEEP, RSTIN, ID0, ID1, ID2, ENBSW1, ENBSW2,
PWM is implemented with a Schmitt trigger, with hysteresis.
Design values
Min
Typ
Max
200 mV
300 mV
400 mV
1.3 Power-On RESET Function
A Power-On RESET circuit is built-in for VBB
.
When VBB rises to VPORH level (7.0 V (Typ)) or higher at the time of power ON, SWREG1 activates by a soft start.
After soft start, the state of the serial port RESET is cleared. In addition, hysteresis is established at the time of
power-down to turn all outputs OFF with VPORH-VPORHY (1.0 V (Typ)) and reset the serial ports.
1.4 Reset Timing, VBB Drop Detection Function
After detecting Power-On RESET release, FB1 ≥ 0.75 V (Typ) and RSTIN = L, RESET output becomes H level
after 50 ms (Typ). Meanwhile UVDET output only depends on VBB. It becomes L level with any voltage by
external resistance. In addition, inputting H pulse (over 10 µs (Typ), 13 µs (Max)) into the RSTIN pin makes
RESET output L level.
RESET output table is shown below (Values at the table are all typical. VBB has hysteresis).
VBB
FB1
RSTIN
RESET Output
Unstable
(IC internal circuit stops)
Under 7.0 V
Don’t Care
Don’t Care
Under 0.75 V
0.75 V or more
Under 0.75 V
0.75 V or more
H
H
L
L
L
7.0 V or more
L
L
H (50 ms after detection)
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Explanation of Block Operation – continued
2
H-Bridge Driver
2.1 Power Save Mode
When the SLEEP = L, H-Bridge will cause the circuit to enter standby state, with only SWREG1 and SWREG2
active. Serial ports are reset in power save mode.
SLEEP pin
Mode
L
Power Save Mode
Normal (active) Mode
H
Be sure driver outputs are in the OFF state when switching modes with the SLEEP pin.
2.2 ID Setting
Setting the identification code of the device with the ID0, ID1 and ID2 pins.
ID pin is always monitored.
ID2
ID1
ID0
Identification code (D20, D19, D18)
L
L
L
Driven by Serial interface 2
1 (001)
L
L
H
L
H
L
2 (010)
L
H
H
3 (011)
H
L
L
4 (100)
H
L
H
5 (101)
H
H
H
H
L
H
6 (110)
7 (111)
Don’t care
Don’t care
Don’t care
All IC reply (000)
Identification code 1, 3, 5, 7 is triggered in the falling edge of CLK only, identification code 2, 4, 6 and serial
interface 2 is triggered in the rising edge of CLK only.
2.3 MODE Setting
Please connect the MODE pin to GND by all means.
MODE
L
Pin state
GND
H-Bridge-A
H-Bridge-B
DC motor (Large Mode(Note 1)) (VREF voltage splitting ratio α = 10)
(Note 1) Large Mode: Connect the two H-Bridge in parallel and drive one DC motor.
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2
H-Bridge Driver ― continued
2.4 Serial Interface 1
21-bit, 3-linear type serial interface (DAT, CLK, STB(LD)) is provided to set the operation and the value of
current limit. DAT logic for each channel is sent to the internal shift register on the edge of CLK signal according
to the identification code in the L area of STB(LD) signal.
The data of the shift register appoints a device code in D20, D19, and D18.
Identification codes 1, 3, 5, 7 is triggered on the falling edge of CLK, and in the case of (D20, D19, D18) = (000),
identification codes 2, 4, 6 is triggered on the rising edge of CLK. According to address data of D17, D16, D15,
D14, word setting write the data on an appropriate address of the internal memory of 3 x 14 bit at the rising
edge of the STB(LD) signal.
The input order of serial data is from D20 to D0. After SLEEP changes from L to H, serial data inputs are only
valid after 10 µs.
Serial port write timing is described in the figure below, and the respective minimum timing values are
specified as follows:
A
B
C
D
:
:
:
:
DAT Setup Time
DAT Hold Time
CLK High Pulse Width ········ 25 ns
CLK Low Pulse Width ········ 25 ns
········ 7.5 ns
········ 5 ns
STB(LD)
CLK
A
B
A
B
C
D
A
B
A
B
LSB D0
DAT
CLK
MSB D20
LSB D0
PD0
DAT
PD2
ND3
PD1
ND2
PD0
ND1
ND0
PD20
PD1
STB(LD)
Figure 3. Serial Port Write Timing of Serial Interface 1
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2
H-Bridge Driver ― continued
2.5 Serial Data Allotment (Serial Interface 1)
Address Data
Initial
D17
Word
D16
Word
D15
Word
D14
Word
WORD A
DAT
Word Select
Select 3 Select 2 Select 1 Select 0
D0
D1
Watch Dog Timer LSB
0
0
-
1
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
WORD A
WORD B
Watch Dog Timer MSB
D2
-
WORD C
D3
-
-
WORD D
D4
-
-
Rohm Reserved
WORD E
D5
-
-
D6
-
-
WORD F
D7
-
-
WORD G
D8
-
-
WORD H
D9
-
-
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
-
-
Rohm Reserved denotes a special mode-setting port for
inspection at shipment.
-
-
-
-
If the Word Select 3, 2, 1, and 0 are set to “0,0,1,1” by
mistake, it may cause malfunctions. Therefore, be careful
NOT to implement this setting.
-
-
Word Select 0 = 1
1
1
1
1
-
Word Select 1 = 1
Word Select 2 = 1
Word Select 3 = 1
-
-
-
-
-
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2.5 Serial Data Allotment (Serial Interface 1) ― continued
WORD B
(H-Bridge-A Specific)
Initial
DAT
WORD C
(H-Bridge-B Specific)
Initial
DAT
WORD D
H-Bridge-A-B General
Initial
DAT
D0 Blank Time LSB
0
0
0
0
0
0
1
0
0
0
0
0
0
-
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Don’t care
-
-
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
-
-
D1 Blank Time MSB
D2 Off Time LSB
-
-
D3 Off Time Bit1
-
-
D4 Off Time Bit2
-
-
D5 Off Time Bit3
-
-
D6 Off Time MSB
D7 Fast Decay Time LSB
D8 Fast Decay Time Bit1
D9 Fast Decay Time Bit2
D10 Fast Decay Time MSB
D11 Sync. Rect. Control
D12 Sync. Rect. Enable
D13 Don’t care
-
-
Internal PWM Mode
for H-Bridge-A
External PWM Mode
for H-Bridge-A
Phase
for H-Bridge-A
DAC LSB
for H-Bridge-A
DAC Bit1
for H-Bridge-A
-
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
DAC Bit2
for H-Bridge-A
DAC MSB
-
-
for H-Bridge-A
D14 Word Select 0 = 0
D15 Word Select 1 = 0
D16 Word Select 2 = 0
D17 Word Select 3 = 0
D18 ID Bit0
0
0
0
0
-
Word Select 0 = 1
Word Select 1 = 0
Word Select 2 = 0
Word Select 3 = 0
ID Bit0
1
0
0
0
-
Word Select 0 = 0
Word Select 1 = 1
Word Select 2 = 0
Word Select 3 = 0
ID Bit0
D19 ID Bit1
-
ID Bit1
-
ID Bit1
-
D20 ID Bit2
-
ID Bit2
-
ID Bit2
-
Rohm Reserved denotes a special mode-setting port for inspection at shipment.
If you set it by mistake, it may cause malfunctions.
Therefore, be careful NOT to implement this setting.
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2.5 Serial Data Allotment (Serial Interface 1) ― continued
WORD E
(H-Bridge-A Specific)
Initial
DAT
WORD F
(H-Bridge-B Specific)
Initial
DAT
D0 EN A PWM Cycle Time LSB
D1 EN A PWM Cycle Time Bit1
D2 EN A PWM Cycle Time Bit2
D3 EN A PWM Cycle Time Bit3
D4 EN A PWM Cycle Time Bit4
D5 EN A PWM Cycle Time Bit5
D6 EN A PWM Cycle Time Bit6
D7 EN A PWM Cycle Time Bit7
D8 EN A PWM Cycle Time Bit8
D9 EN A PWM Cycle Time Bit9
D10 EN A PWM Cycle Time Bit10
D11 EN A PWM Cycle Time Bit11
D12 EN A PWM Cycle Time MSB
D13 Don’t care
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Don’t care
0
0
0
0
0
0
0
0
0
0
0
0
0
-
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Word Select 0 = 1
Word Select 1 = 0
Word Select 2 = 1
Word Select 3 = 0
ID Bit0
D14 Word Select 0 = 0
0
0
1
0
-
1
0
1
0
-
D15 Word Select 1 = 0
D16 Word Select 2 = 1
D17 Word Select 3 = 0
D18 ID Bit0
D19 ID Bit1
-
ID Bit1
-
D20 ID Bit2
-
ID Bit2
-
WORD G
(H-Bridge-A Specific)
Initial
DAT
WORD H
(H-Bridge-B Specific)
Initial
DAT
D0 EN A PWM On Time LSB
D1 EN A PWM On Time Bit1
D2 EN A PWM On Time Bit2
D3 EN A PWM On Time Bit3
D4 EN A PWM On Time Bit4
D5 EN A PWM On Time Bit5
D6 EN A PWM On Time Bit6
D7 EN A PWM On Time Bit7
D8 EN A PWM On Time Bit8
D9 EN A PWM On Time Bit9
D10 EN A PWM On Time Bit10
D11 EN A PWM On Time Bit11
D12 EN A PWM On Time MSB
D13 Phase for H-Bridge-A
D14 Word Select 0 = 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
-
Don’t care
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
-
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Word Select 0 = 1
Word Select 1 = 1
Word Select 2 = 1
Word Select 3 = 0
ID Bit0
D15 Word Select 1 = 1
D16 Word Select 2 = 1
D17 Word Select 3 = 0
D18 ID Bit0
D19 ID Bit1
-
ID Bit1
-
D20 ID Bit2
-
ID Bit2
-
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H-Bridge Driver ― continued
2.6 Serial Interface 2
16-bit, 3-line type serial interface (CLK, DAT, STB(LD)) sets the operation and the value of current limit. DAT
logic for each channel is sent to the internal shift register on the rising edge of the CLK pin in the L area of the
STB(LD) pin. Shift register data are written in an appropriate address of internal memory of 3 x 14 bit on the
rising edge of the STB(LD) pin corresponding to the address data of D15 and D14.
The input order of serial data is from D15 to D0. After SLEEP changes from L to H, serial data inputs are only
valid after 10 µs.
Serial port write timing is described in the figure below, and the respective minimum timing values are
specified as follows:
Address data
D15 D14
A
B
C
D
E
F
:
:
:
:
:
:
:
DAT Setup Time
DAT Hold Time
Setup STB(LD) to CLK Rising Edge ········ 50 ns
CLK High Pulse Width
CLK Low Pulse Width
Setup CLK Rising Edge to STB(LD) ········ 50 ns
STB(LD) Pulse Width ········ 50 ns
········ 15 ns
········ 10 ns
Word Select
WORD0
0
0
1
1
0
1
0
1
········ 50 ns
········ 50 ns
WORD1
WORD2
Rohm Reserved
G
Rohm Reserved is a special mode setting port for factory inspection, etc.
Please be careful not to set it as it may cause malfunction if it is set incorrectly.
STB(LD)
CLK
G
C
D
E
F
A
B
DAT
MSB D15
LSB D0
Figure 4. Serial Port Write Timing of Serial Interface 2
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2
H-Bridge Driver ― continued
2.7 Serial Data Allotment (Serial Interface 2)
WORD0
(H-Bridge-A Specific)
Initial
DAT
WORD1
(H-Bridge-B Specific)
Initial
DAT
WORD2
H-Bridge-A-B General
Initial
DAT
D0 Blank Time LSB
0
0
0
0
0
0
1
0
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
-
-
-
-
-
-
-
-
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
Don’t care
-
-
D1 Blank Time MSB
D2 Off Time LSB
D3 Off Time Bit1
-
-
D4 Off Time Bit2
-
D5 Off Time Bit3
-
D6 Off Time MSB
D7 Fast Decay Time LSB
-
Internal PWM Mode
for H-Bridge-A
External PWM Mode
for H-Bridge-A
Phase
for H-Bridge-A
DAC LSB
for H-Bridge-A
DAC Bit1
for H-Bridge-A
0
D8 Fast Decay Time Bit1
D9 Fast Decay Time Bit2
D10 Fast Decay Time MSB
D11 Sync. Rect. Control
0
0
0
0
Rohm Reserved
Rohm Reserved
Rohm Reserved
Rohm Reserved
-
-
-
-
0
0
0
0
DAC Bit2
for H-Bridge-A
DAC MSB
D12 Sync. Rect. Enable
D13 Don’t care
0
-
Rohm Reserved
Don’t care
-
-
-
-
0
0
-
for H-Bridge-A
D14 Word Select 0 = 0
D15 Word Select 1 = 0
-
Word Select 0 = 1
Word Select 1 = 0
Word Select 0 = 0
Word Select 1 = 1
-
-
Rohm Reserved denotes a special mode-setting port for inspection at shipment.
If you set it by mistake, it may cause malfunctions.
Therefore, be careful NOT to implement this setting.
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2
H-Bridge Driver ― continued
2.8 Explanation of Serial Port · H-Bridge Operation
H-Bridge is in active mode when the SLEEP pin is H and in decay mode when it is L. All serial input time settings
are determined by the internal clock (40 MHz (Typ) ±15 % (Ta = 25 °C)) and have the same degree of variation
and temperature dependence as the clock.
2.8.1 Blank Time D0 to D1: WORD0 / WORD1
The current-limit comparator monitors the RNFxS(Note 1) pin voltage and sets the current limit. However, the
RNFxS pin voltage is not detected during the switch to BLANK TIME to avoid misdetection due to noise
spikes that occurs at the time of the switching.
(1) PHASE switching time
(2) When ENBA switches ON (L → H)
(3) When output is ON at current chopping drive time, and Off Time has finished
(1) PHASE switching time
D1
0
D0
0
Blank Time [µs]
PHASE signal
1.0
1.5
3.0
6.0
0
1
MOTOR current
1
0
MASK interval
1
1
BLANK TIME
(2) When ENBA switches ON (L→H)
(3) When output is ON at current chopping drive time, and Off Time has finished
ENBA
RNF voltage
MOTOR current
MASK interval
MASK interval
BLANK TIME
Off Time
BLANK TIME
(Note 1) x = A, B
Figure 5. Blank Time
2.8.2 Off Time D2 to D6: WORD0 / WORD1
Off Time is set by the following equation:
(
)
푡푂퐹퐹 = 1 + 푁 × 8 × 0.25 − 0.25 [µs]
:
:
is the Off Time.
tOFF
N
is set by the serial bit: 0 to 31.
For example, if N = 0, the Off Time setting is as follows:
푡푂퐹퐹 = (1 + 0) × 8 × 0.25 − 0.25 = 1.75 [µs]
2.8.3 Fast Decay Time D7 to D10: WORD0 / WORD1
Fast Decay Time is set by the following equation:
푡퐹퐷 = (1 + 푁) × 8 × 0.25 − 0.25 [µs]
:
:
is the Fast Decay Time.
tFD
N
is set by the serial bit: 0 to 15.
For example, if N = 0, the Fast Decay Time setting is as follows:
푡퐹퐷 = (1 + 0) × 8 × 0.25 − 0.25 = 1.75 [µs]
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2.8
Explanation of Serial Port · H-Bridge Operation ― continued
2.8.4 Sync. Rect. Control D11: WORD0 / WORD1
At Fast Decay Mode Synchronous rectification,
make settings related to reverse energization of the motor current.
D11
Sync. Rect. Cont.
Function
Detects motor current at 0 A, switches synchronous rectification
OFF and prevents reverse energization.
0
ACTIVE
Permits reverse energization; switches synchronous rectification
1
PASSIVE
OFF when current reaches the ITRIP
.
⁄
퐼푇푅ꢀ푃 = 푉ꢁ퐸ꢂ × ꢃ퐴퐶푣푎푙푢푒(퐶푢푟푟푒푛푡_ꢁ푎푡푖표) (훼 × ꢁ푠푒푛푠푒) [A]
is the motor current limit, established by the formula above.
Is the output current value setting voltage.
is the VREF voltage division ratio (α = 10).
is the Current detection resistance value.
ITRIP
:
:
:
:
:
VREF
α
Rsense
DACvalue(Current_Ratio)
is refer to table below.
2.8.5 DAC value (Current_Ratio) D3 to D6 / D10 to D13: WORD2
MSB
D6 / D13
Bit2
D5 / D12
Bit1
D4 / D11
LSB
D3 / D10
Current_Ratio [%]
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
100.00
98.08
95.69
92.39
88.19
83.15
77.30
70.71
63.44
55.56
47.14
38.27
29.03
19.51
9.80
Disable
2.8.6 Sync. Rect. Enable D12: WORD0 / WORD1
In current decay mode, D12 value enables or disables synchronous rectification.
D12
Sync. Rect. En.
Function
No synchronous
rectification
0
Disabled
Synchronous
rectification
1
Enabled
implemented
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2.8 Explanation of Serial Port · H-Bridge Operation ― continued
2.8.7 Internal PWM Mode D0 / D7: WORD2
In current decay mode, this data sets the motor current regeneration method.
Mixed Decay setting: During Off Time, the Fast Decay Time is set for Fast regeneration mode.
For the rest of the time, it is set to Slow regeneration. In this scheme, if Fast Decay Time is longer than Off
Time, Fast regeneration becomes the only operative mode.
When Sync. Rect. Control = Active and 0 A is detected in Fast regeneration mode, the regeneration mode
will switch to Slow, once all outputs are OFF and the Fast Decay Time period has finished.
D0 / D7
Mode
Mixed
Slow
0
1
2.8.8 External PWM Mode D1 / D8: WORD2
Sets the motor current regeneration mode when ENBA = L.
Motor current regeneration is triggered by the falling edge of the ENBA pin logic.
Therefore, this mode is not synchronized with the clock.
D1 / D8
Mode
Fast
0
1
Slow
2.8.9 Phase D2 / D9: WORD2
Sets the motor drive rotational direction.
D2 / D9
Direction
Reverse
Forward
OUT(A-B)P
OUT(A-B)M
0
1
L
H
L
H
There is a Phase bit in WORD D, WORD G, WORD H, and last updated WORD is reflected.
For example, when Phase D2: WORD D ”0”, Phase D13: WORD G ”0”, Phase D13: WORD G ”1”,
Phase setting is forward detection. And when Phase D2: WORD D ”0”, Phase D13: WORD H ”0”, Phase
D2: WORD D ”1”, Phase setting is forward detection.
2.8.10 PWM Cycle Time D0 to D12: WORD E / WORD F
PWM Cycle Time setting. PWM Cycle Time is accomplished using the equation:
푡푃푊푀 = 푁 × 25푛 [s]
tPWM
N
:
:
is the PWM Cycle Time.
is set by the serial bit: 0 to 8191.
For example, when N = 4000,
푡푃푊푀 = 4000 × 25푛 = 100 [µs]
When N = 0 is set, external enable becomes active. On the other hand, internal PWM becomes active
when N > 0 is set.
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2.8 Explanation of Serial Port · H-Bridge Operation ― continued
2.8.11 PWM ON Time D0 to D12: WORD G / WORD H
PWM ON Time setting. PWM ON Time is accomplished using the equation:
푡푂ꢄ = 푁 × 25푛 [s]
tON
N
:
:
is the PWM ON Time.
is set by the serial bit: 0 to 8191.
For example, when N = 1000,
푡푂ꢄ = 1000 × 25푛 = 25 [µs]
(The frequency of the internal clock becomes 30 MHz (Min) or more)
A
B
Figure 6. Relationship Diagram of PWM Cycle Time and PWM ON Time
A: PWM Cycle Time
B: PWM ON Time
Section B is ON section. The end of section A is OFF section from the end of section B (Slow Decay or
Fast Decay).
Example)
PWM ON Time: when N = 1000, 1000 x 25 ns = 25 µs
PWM Cycle Time: when N = 4000, 4000 x 25 ns = 100 µs
Therefore, PWM period is 100 µs (section A), ON Time is 25 µs (section B), OFF Time is 75 µs (section B
to section A).
2.8.12 Watch Dog Timer D0 / D1: WORD A
A counter improves when setting value to a start register. When setting the time, this IC turn OFF motor
output. The A side and the B side can be set individually.
(Usage example)
1. Set the A side time at 180 s
2. Initiate the A side start register and start timer count.
3. A side motor drives.
4. When the motor stops, it clears the start register and the timer count is reset.
In case step 4 did not function in the sequence mentioned above and the start register is not cleared (with
a field anomaly relaxation method overrun and a bug) for more than 180 s, turn OFF motor driver output.
In addition, if you set it to 180 s again within 180 s after setting it to 180 s, the count is restarted from there.
Time (s)
D1
D0
Min
Typ
Max
0
0
1
1
0
1
0
1
Infinity (default)
Infinity (default)
Infinity (default)
50
60
70
150
250
180
300
210
350
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H-Bridge Driver ― continued
2.9 Current Decay Mode
For the PWM constant current drive of this series, the current decay modes (FAST DECAY / SLOW DECAY) can
be set. The state of output transistor and the route of motor’s regenerative current during current decay for each
decay mode are as follows.
FAST DECAY
SLOW DECAY
OFF→OFF
ON→OFF
ON→OFF
OFF→ON
OFF→OFF
ON→ON
ON→OFF
OFF→ON
M
M
When output ON
When Current Decay
Figure 7. Route of Regenerated Current during Current Decay
The merits of each decay mode are as follows:
2.9.1 SLOW DECAY
When the current decay, the voltage between motor coils is small and the regenerative current decreases
slowly. Current ripple also decreases, which improves motor torque. At the same time, the output current
increases due to the deterioration of current control characteristic in the small current region; it is also
easily affected by motor's BEMF at the time of high pulse rate drive. Therefore, change of current limit
value cannot be followed, current waveform distorts and motor vibration increases. It is most suitable to
FULL STEP and low pulse rate drive.
2.9.2 FAST DECAY
Because of sudden decrease of regenerative current, distortion of current waveform related to high pulse
rate drive can be reduced. However, because the output current’s ripple gets larger, the average current
decreases, so (1) motor torque decreases (increasing the current limit value can cope with the problem,
but it is necessary to take the rated output current into consideration), (2) motor’s loss gets larger causing
heat radiation to also increase. If there are no problems of (1) and (2), it is most suitable to the modes that
are of high pulse rate drive.
There is the Mixed Decay mode that can improve the problem related to Slow Decay mode and Fast
Decay mode. Due to switching between Fast Decay and Slow Decay, the current control characteristic
can be improved without making the current ripple larger during current decay.
This IC can change the time ratio of Slow Decay and Fast Decay during Mixed Decay, so the optimal
control state for every motor can be achieved. During Mixed Decay, the first half X % (between t1 and t2) of
the discharge interval in the chopping cycle is Fast Decay time, and the remaining interval is Slow Decay
time (between t2 and t3).
t1 t2
t3
1 cycle
Output
current
Current setting value
SLOW DECAY
0 A
ꢀFAST DECAY
Motor output current (DC): to 2.0 A/Phase
Motor output current (peak): to 6.0 A/Phase
Figure 8. Mixed Decay Diagram
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Explanation of Block Operation – continued
3
SWREG
VBBSW1
SWOUT1
Current
Detection
Soft Start DAC
gmAMP
VBIAS
L
Q
Pre Driver
R
S
VOUT
R1
R2
C1
OSC
Figure 9. SWREG1 Block Diagram (SWREG2: Synchronous and VBBSW → VINSW2)
3.1 Basic Operation
This IC incorporates 2ch of switching regulator circuit that repeats ON/OFF, synchronized with an internal clock
(SWCLK), 1ch SWREG operates by 250 kHz (Typ) ±15 % and 2ch SWREG operates by 1 MHz (Typ) ±20 %.
Startup output voltage SWOUT1 begins switching and the VOUT1 slowly ramps up with a soft start at VBB
power-on (VBB > VPORH) and ENBSW1 = L. And startup output voltage SWOUT2 begins switching at the time of a
soft start, while the VOUT2 slowly ramps up at VBB power-on (VBB > VPORH) and ENBSW2 = L. When ENBSW1 = H
and ENBSW2 = H, the IC doesn’t work.
Input power supply 300 µs or more at 0 V to VPORH (7 V (Typ))
Output voltage is determined with external resistance by using the following equation:
{(
)⁄ }
푉푂푈푇 = 푉퐵ꢀꢅ푆 × ꢁꢆ + ꢁꢇ ꢁꢇ [V]
VOUT
is the output voltage.
is the FB1 voltage.
VBIAS
R1, R2
is the external resistance.
Note that the external LC filter constant should be set to optimize output ripple voltage (VRIP). This is
accomplished using the equation below:
{(
)⁄
⁄
}
푉푅ꢀ푃 = 퐼푅ꢀ푃 × 퐸ꢈꢁ + 1 푓
퐶푂푈푇/8 [V]
푆푊
VRIP
IRIP
ESR
fSW
:
:
:
:
:
is the output ripple voltage.
is the output ripple current.
is the equivalent series resistance.
is the switching frequency.
is the output capacitance.
COUT
⁄
⁄
⁄
푆푊
퐼푅ꢀ푃 = 푉푂푈푇 퐿 × 푉퐵퐵푆푊 − 푉푂푈푇 푉퐵퐵푆푊 × 1 푓
[A]
L
:
:
is the inductance.
is the applied voltage.
VBBSW
3.2 Skip Mode Operation
In certain run modes, such as when output load is low, gmAMP output (COMP) voltage exceeds the current
detection level at the SWCLK rising edge. In this case, output will not switch ON.
3.3 MAX DUTY
In certain run modes, such as when output load is high, if the COMP voltage level does not reach the current
detection level, output MAX DUTY (90 %) will force the output OFF.
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3
SWREG ― continued
3.4 Operation Timing
Operation timing under light, normal and heavy loads are respectively described in the charts below.
Normal operation
SWCLK
(MAX DUTY)
Current
detection
COMP
SWOUT
VOUT
Light operation
SWCLK
(MAX DUTY)
COMP
Current
detection
SWOUT
VOUT
Heavy operation
SWCLK
(MAX DUTY)
Current
detection
COMP
SWOUT
VOUT
Figure 10. Operation Timing of Light Loads, Normal Loads and Heavy Loads
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3
SWREG ― continued
3.5 SWREG1 Soft Start (at power-on, with ENBSW1 = L)
At the time of power-on, VOUT1 ramps up slowly with a soft start
The rising edge of SWREG1 is synchronized with the timing when ENBSW1 = L and POR release.
VUVHYS (depends on the
external resistor)
VUV (depends on the
external resistor)
VBB
VPORH (7.0 V Typ)
VPORL (6.0 V Typ)
(VPORH-VPORHY
)
3.9 kHz CLOCK
(Generated by dividing
the internal standard
clock)
Oscillation
POR signal
ENBSW1
0 V
Counter output
SWOUT1
0 1 2
32
63
Duty
Increase
Constant ON Duty
ON Duty = VOUT/VBB
DAC1 output
2.0 V
1.0 V
0 V
VOUT1 x 75 %
VOUT1
0 V
t1 = 8.2 ms (Typ)
t2 = 16.4 ms (Typ)
50 ms (Typ)
RESET output
UVDET output
Figure 11. SWREG1 Soft Start Operation Timing Diagram
This soft start method is realized by linearly changing the negative side voltage of the gmAMP by using DAC.
Soft start time t1 is constant, regardless of VBB
.
Specification
Typ
Parameter
Unit
Min
6.97
Max
9.43
Soft start time (t1)
8.20
ms
ms
Count finish time (t2)
13.94
16.40
18.86
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3
SWREG ― continued
3.6 SWREG2 Operation
SWREG2 is a synchronous rectifying step-down switching regulator that achieves faster transient response by
employing current mode PWM control system. It utilizes switching operation in PWM (Pulse Width Modulation)
mode for heavier load, while it utilizes SLLMTM (Simple Light Load Mode) control for lighter load to improve
efficiency.
(1) SLLMTM Control
(2) PWM Control
Output Current IOUT [A]
Figure 12. Efficiency (SLLMTM Control and PWM Control)
3.6.1 Basic Function
SWREG2 works forcibly with fixed frequency PWM mode when the PWM pin is H. SLLMTM control is
enabled, SLLMTM control and fixed frequency PWM mode becomes active automatically when the PWM
pin is L.
When the logic of the PWM pin is switched during SWREG2 operation, the output voltage may decrease.
Fix the logic of the PWM pin to H (2.0 V or more) or L (0.8 V or less) before the SWREG2 start(Note 1), and
do not change during operation.
(Note 1) Before start means the ENBSW2 = H state or before UVLO release of SWREG2.
3.6.2 Enable Control
The SWREG2 shutdown can be controlled by the voltage applied to the ENBSW2 Pin. When ENBSW2 =
L, the internal circuit is activated and the SWREG2 starts up. To shutdown control with the ENBSW2 Pin,
the shutdown interval (H level interval of ENSW2) must be set to 100 µs or longer.
3.7 Reference efficiency (It does not do the all quantity measurement.)
Efficiency
(Typ)
Channel
Unit
%
Conditions
Notes
VBBSW1 = 12 V, VOUT1 = 5.0 V, IOUT1
50 mA
VBBSW1 = 12 V, VOUT1 = 3.3 V, IOUT1
=
DS126C2 B953AS-680M(TOKO)
RB050L-60TE25(ROHM)
DS126C2 B953AS-680M(TOKO)
RB050L-60TE25(ROHM)
NRS6045T1R8NMGK
(TAIYO YUDEN)
87
SWREG1
=
=
=
85
88
86
%
%
%
50 mA
VINSW2 = 3.3 V, VOUT2 = 1.1 V, IOUT2
50 mA
SWREG2
VINSW2 = 3.3 V, VOUT2 = 1.5 V, IOUT2
50 mA
NRS5040T1R5NMGJ
(TAIYO YUDEN)
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Explanation of Block Operation – continued
4
Protection Functions
4.1 Protection Circuits
Overall
Overheating protection
H-Bridge drive circuit
Over-current protection
Over-current protection,
output low voltage protection
SWREG circuit
4.1.1 Overheating protection
Turns OFF all output functions in response to junction temperature rise.
Output is restored when the system powers on again.
Thermal shutdown
Hysteresis
None
Restart
temperature
175 °C (Typ)
-
4.1.2 Over-current protection (H-Bridge)
Detects current flowing to H-Bridge output, turns OFF all H-Bridge outputs
at the end of Mask time. Output is restored at the SLEEP pin = H→L→H
Set current
3.5 A (Typ)
Mask time
3 µs (Typ)
Restart
SLEEP
4.1.3 Over-current protection (H-Bridge) detect function
The OCPDET output detects that the over-current protection of the H-Bridge has worked and becomes L
level at the timing of turnning OFF all H-Bridge outputs.
4.1.4 Over-current protection (SWREG1)
Detects current flowing to SWREG1 output. After Mask time, SWREG1 is turned OFF between 256 µs to
512 µs (Typ) at the timing of detection.
When protection operation is complete, normal operation resumes.
Channel
Set current
5.0 A (Typ)
Mask time
Restart
SWREG1
0.15 µs (Typ)
-
4.1.5 Over-current protection (SWREG2)
It becomes activated by confining current flowing through the upper part MOSFET of SWREG2 to every 1
cycle of the switching frequency.
Channel
Set current
5.0 A (Typ)
SWREG2
4.1.6 Output low voltage protection (SWREG1)
Monitors the FB1 pin voltage of the SWREG1 circuit.
If the FB1 pin voltage is less than 0.75 V (Typ) only SWREG1 is turned
OFF after mask time. Output is restored at the ENBSW1 pin = L → H → L
Set voltage
Mask time
Restart
< 0.75 V (Typ)
10 µs (Typ)
ENBSW1
Note that output under-voltage protection does not work until the soft start count is complete (16.4 ms
(Typ)).
4.1.7 Output low voltage protection (SWREG2)
Monitors the FB2 pin voltage of the SWREG2 circuit.
It activates when the FB2 pin voltage is less than 0.4 V (Typ).
SWREG2 is turned OFF when the state continues for 1 ms (Typ).
Output under-voltage
Set voltage
Mask time
Restart
protection operation
< 0.4 V (Typ)
1 ms (Typ)
ON
ENBSW2 reboot
> 0.4 V (Typ)
-
OFF
-
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4
Protection Functions ― continued
4.2 Over-current protection circuit operation current
Design value
Typ
Function Block
Min
Max
4.5 A
3.6 µs
6.9 A
Operation
2.5 A
3.5 A
3 µs
current
H-Bridge
Mask time
2.4 µs
2.3 A
Operation
current
SWREG1
SWREG2
5.0 A
Operation
current
2.05 A
5.00 A
6.90 A
The over-current protection circuit’s only aim is to prevent the destruction of the IC from irregular situations such
as motor output shorts, and is not meant to be used as protection or surety for the set. Therefore, sets should not
be designed to take into account this circuit’s functions. After the OCP activates, if the return by power
reactivation or the reset by the SLEEP pin in an abnormal state, the OCP operation may be repeated in the order
of latch → recovery → latch, which may cause heat generation or deterioration of the IC. Please note that. If the L
value of the wiring is large, such as the wiring is long when the motor outputs are shorted VCC or GND or other
outputs, the output pin voltage jumps after an overcurrent flows, and if it exceeds the absolute maximum rating, it
may be destroyed. Also, when current which is over the output current rating and under the OCP detection
current flows, the IC may heat up to over Tjmax = 150 °C and can deteriorate, so current which exceeds the
output rating should not be applied. This value is design level and is not the guaranteed value that is measured
by total inspection.
4.3 Timing of output low voltage protection (SWREG1)
When the switching regulator output current is large enough to reach a detection threshold 5.0 A (Typ), the output
is shut OFF for a period of 256 µs to 512 µs (Typ). Then, output is restored to the normal ON state by the timing
of the next ON switching cycle. Repeated large current outflows will cause this operation to implement
continuously, which in turn will gradually lower the output voltage. Consequently, when it detects that the voltage
at the FB pin (output voltage feedback pin) has fallen below 0.75 V (Typ), it latches the output OFF after a mask
time of 10 µs (Typ). At this time, all outputs except the switching regulator are turned off at the same time.
SWOUT1
Limit value
(5.0 A (Typ))
I_SWOUT1
FB1: 1.0 V (Typ)
±0.5 % (0 °C ≤ Tj ≤ 125 °C)
FB1
FB1 undervoltage
Protection value
(0.75 V (Typ))
OFF period
at over-current limit
(256 µs to 512 µs (Typ))
Mask time
(10 µs (Typ))
Figure 13. Timing of SWREG1 Protection Operation Diagram
FB1 under-voltage protection will not operate during the soft start period (t2), If abnormal FB1 voltage is produced
during a soft start, the IC will not shut OFF until the soft start is complete.
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Protection Functions ― continued
4.4 Soft Start (at power-on, with ENBSW2 = L)
At the time of power-on, VOUT2 ramps up slowly with a soft start.
The rising edge of SWREG2 is synchronized with the timing when ENBSW2 = L and POR release of VBB
.
4.5 Operation Timing of malfunction protection circuit at output low voltage protection (SWREG2)
This IC has a built-in malfunction protection circuit at low voltage (Under Voltage Lock Out: UVLO circuit) to
prevent false operation such as the output during power supply under voltage. When the applied voltage to the
VINSW2 pin goes under 2.45 V (Typ), the output is set to OFF state. This switching voltage has a 0.2 V (Typ)
hysteresis to prevent false operation by noise etc. This value is design level and is not the guaranteed value that
is measured by total inspection.
UVLO OFF
VINSW2
2.65 V
2.45 V
HYS
UVLO ON
0 V
0 V
ENBSW2
Soft Start t3
VOUT2
FB2: 0.8 V (Typ)
±0.5 % (0 °C ≤ Tj ≤ 125 °C)
High-side
MOSFET Gate
Low-side
MOSFET Gate
Normal operation
UVLO
Normal operation
Figure 14. SWREG2 Protection Operate Timing and Soft Start Timing
Specification
Parameter
Unit
Min
0.8
Typ
1.0
Max
1.2
Soft Start Time (t3)
ms
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Precautions of Board Layout
Consider the following key points when designing board layout:
1
Key points and precautions concerning the H-Bridge
1.1 VBBA, VBBB / H-Bridge Power supply Pin
Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance.
VBBx(Note 1) may have big fluctuations due to motor back EMF, PWM switching noise, etc., so you must arrange the
bypass capacitor of about over 220 μF as close to the pin as possible and adjust VBBx is stable. Increase the
capacitance if needed, especially when a large current is used or motors that have great back electromotive
force are used.
In addition, for the purpose of reducing the power supply’s impedance in wide frequency bandwidth, parallel
connection of multi-layered ceramic capacitor of 0.01 µF to 0.1 μF etc. is recommended. Extreme care must be
used to make sure that VBBx does not exceed the rating even for a moment.
VBBA and VBBB are shorted inside IC, so be sure to short externally VBBA and VBBB when using. If used
without shorting, malfunction or destruction may occur because of concentration of current routes etc. Moreover,
in the power supply pin, there is a built-in clamp component for preventing of electrostatic destruction. If steep
pulse or voltage of surge exceeding the maximum absolute rating is applied, this clamp component operates. As
a result, there is danger of destruction, so make sure that the maximum absolute rating is not exceeded. It is
effective to mount a Zener diode about the maximum absolute rating. Also, a diode for preventing electrostatic
destruction is inserted between the VBBx pin and GND pin, as a result there is the danger of IC destruction if
reverse voltage is applied between the VBBx pin and GND pin, so be careful.
(Note 1) x = A, B
1.2 OUTAP, OUTAM, OUTBP, OUTBM / H-Bridge output Pin
Motor’s drive current is flowing in it, so the wire is thick and short and has low impedance. It is also effective to
add a Schottky diode if output has big positive or negative fluctuations when large current is used, etc., for
example, if counter electromotive voltage, etc. is big. Moreover, in the output pin, there is a built-in clamp
component for preventing electrostatic destruction. If a steep pulse or voltage surge exceeding the maximum
absolute rating is applied, this clamp component operates, but there is still the danger of destruction, so make
sure that the maximum absolute rating is not exceeded.
1.3 RNFA, RNFB / H-Bridge Connection Pin of resistor for detecting of output current
Connect the resistor for current detection between this pin and GND. In view of the power consumption of the
2
current-detecting resistor, determine the resistor that W = IOUT x R [W] does not exceed the power dissipation of
the resistor. In addition, wire has low impedance and does not have impedance in common with other GND
patterns because motor’s drive current flows in the pattern through the RNFx(Note 2) pin to current-detecting
resistor to GND. Do not exceed the rating because there is the possibility of circuit malfunction, etc. if the RNFx
voltage has exceeded the maximum rating (0.55 V). Moreover, be careful because if the RNFx pin is shorted to
GND, large current flows without normal PWM constant current control, then there is the danger that OCP or
TSD will operate. If the RNFx pin is open, there is the possibility of such malfunction as output current does not
flow either, so do not leave it open.
(Note 2) x = A, B
2
Key points and precautions concerning the switching regulator
2.1 VBBSW1, SWOUT1 / SWREG1 power supply pins, SWREG1 output
SWOUT1 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest,
lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching
current noise, the following loop should be kept as short as possible: bypass capacitor → VBBSW1 → SWOUT1
→ Schottky diode → GND.
To lessen the impact of coupling capacitance noise, position the FB1 feedback resistor away from the SWOUT1
pattern and components.
2.2 VINSW2, SWOUT2 / SWREG2 power supply pins, SWREG2 output
SWOUT2 is a high-voltage line and a possible source of switching noise. For that reason, the thickest, shortest,
lowest-impedance wire possible should be used in the pattern design. Meanwhile, to reduce the switching
current noise, the following loop should be kept as short as possible: bypass capacitor → VINSW2 → SWOUT2
→ GND.
To lessen the impact of coupling capacitance noise, position the FB2 feedback resistor away from the SWOUT2
pattern and components.
3
Other key points and precautions
3.1 GND, PGNDSW / Ground Pin
In order to reduce noise caused by the switching current and to stabilize the internal reference voltage of the IC,
keep the wiring impedance from this pin as low as possible. The design should enable the lowest electrical
potential in any operating state. In addition, be sure this wiring does not share common impedance with other
GND patterns.
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Reference Data
40.0
30.0
20.0
10.0
0.0
4
3
2
1
0
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
1.0
0.0
VBB (down)
VBB (up)
0
10
20
30
40
50
5
6
7
8
0
10
20
30
40
50
Supplyvoltage :VBB[V]
Supply voltage :VBB[V]
Supply voltage :VBB[V]
Figure 15. VBB Current1 (Ta = 25 °C)
(SLEEP = H: Active Mode)
Figure 16. VBB Current2 (Ta = 25 °C)
(SLEEP = L: Sleep Mode)
Figure 17. POR Threshold
Voltage (Ta = 25 °C)
2.0
1.5
1.0
0.5
0.0
2.0
1.5
1.0
0.5
0.0
1.2
0.8
0.4
0.0
0
500
1000
1500
2000
0
500
1000
1500
2000
0
500
1000
1500
2000
Supply current :Io[mA]
Supply current :Io[mA]
Supply current :Io[mA]
Figure 20. OUTB Output Voltage
H (source side, Ta = 25 °C)
Figure 18. OUTA Output Voltage
H (source side, Ta = 25 °C)
Figure 19. OUTA Output Voltage
L (sink side, Ta = 25 °C)
1.2
0.8
0.4
0.0
0.9
0.6
0.3
0.0
100
90
VBBSW1 = 12 V
VBBSW1 = 44.1 V
80
70
60
50
0
500
1000
1500
2000
0
500
1000
1500
2000
0
500
1000
Supply current :Io[mA]
Output current :Io[mA]
Supply current :Io[mA]
Figure 21. OUTB Output Voltage
L (sink side, Ta = 25 °C)
Figure 22. SWREG1 Output
Voltage H (Ta = 25 °C)
Figure 23. SWREG1 Efficiency-1
(5.0 V setting, Ta = 25 °C)
100
100
100
VBBSW1 = 12 V
VBBSW1 = 12 V
90
80
90
90
80
70
60
50
VBBSW1 = 12 V
80
VBBSW1 = 44.1 V
VBBSW1 = 44.1 V
70
70
VBBSW1 = 44.1 V
60
50
60
50
0
50
100
150
200
0
500
1000
1500
2000
0
50
100
150
200
Output current :Io[mA]
Output current :Io[mA]
Output current :Io[mA]
Figure 24. SWREG1 Efficiency-2
Figure 25. SWREG1 Efficiency-1
Figure 26. SWREG1 Efficiency-2
(5.0 V setting, Ta = 25 °C)
(3.3 V setting, Ta = 25 °C)
(3.3 V setting, Ta = 25 °C)
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Reference Data - continued
100
90
80
70
60
50
100
90
80
70
60
50
100
V=3.0V
IMSW2
VIMSW2 = 3.0 V
VIMSW2 = 3.0 V
90
V=5.5V
IMSW2
V
= 5.5 V
IMSW2
VIMSW2 = 5.5 V
80
70
60
50
0
50
100
150
200
0
250
500
750
1000
0
100
200
300
400
500
Output current :Io[mA]
Output current :Io[mA]
Output current :Io[mA]
Figure 28. SWREG2 Efficiency
SLLM-2 (1.5 V setting, Ta = 25 °C)
Figure 29. SWREG2 Efficiency
PWM-1 (1.5 V setting, Ta = 25°C)
Figure 27. SWREG2 Efficiency
SLLM-1 (1.5 V setting, Ta = 25 °C)
100
100
100
VINSW2 = 3.0 V
VINSW2 = 3.0 V
90
90
90
VINSW2 = 3.0 V
80
80
80
VINSW2 = 5.5 V
VINSW2 = 5.5 V
70
70
60
50
70
60
50
VINSW2 = 5.5 V
60
50
0
50
100
150
200
0
100
200
300
400
500
0
50
100
150
200
Output current :Io[mA]
Output current :Io[mA]
Output current :Io[mA]
Figure 30. SWREG2 Efficiency
Figure 31. SWREG2 Efficiency
Figure 32. SWREG2 Efficiency
PWM-2 (1.5 V setting, Ta = 25 °C)
SLLM-1 (1.125 V setting, Ta = 25 °C)
SLLM-2 (1.125 V setting, Ta = 25 °C)
100
100
VIMSW2 = 3.0 V
VIMSW2 = 3.0 V
90
90
VIMSW2 = 5.5 V
80
80
VIMSW2 = 5.5 V
70
60
50
70
60
50
0
250
500
750
1000
0
50
100
150
200
Output current :Io[mA]
Output current :Io[mA]
Figure 33. SWREG2 Efficiency
Figure 34. SWREG2 Efficiency
PWM1 (1.125 V setting, Ta = 25 °C)
PWM2 (1.125 V setting, Ta = 25 °C)
SWREG1: RCH110BENP-470(SUMIDA), EC30QSA065(Nihon inter)
SWREG2: NRS5024T1R5NMGJ(TAIYO YUDEN)
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Power Dissipation
VQFN048V7070 is designed with a heat sink metal on the backside of IC to perform heat dissipation treatment using
through hole from backside. Before use, be sure to connect to the GND plane on the board with solder and make the GND
pattern as wide as possible to secure a sufficient heat dissipation area. Note that the power dissipation described below
may not be assured when not connecting by solder. The back metal is shorted with the backside of the IC chip that is a GND
potential. There is a possibility for malfunction or destruction if it is shorted with any potential other than GND, which should
be avoided. Please note that it has been assumed that this product will be used in the condition of this back metal
performed heat dissipation treatment for increasing heat dissipation efficiency.
5.0
Package thermal resistor
D 4.83 W
Board
θJA [°C/W]
240.4
107.8
29.1
C 4.29 W
4.0
3.0
2.0
1.0
0.0
Board A
Board B
Board C
Board D
25.9
PCB size: 74.2 mm x 74.2 mm x 1.6 mmt
B 1.16 W
A 0.51 W
(): Copper foil pattern area size
Board A: Package only
Board B: 1 layer PCB (1 layer: 34.09 mm2)
Board C: 4 layer PCB (1, 4 layer: 34.09 mm2. 2, 3 layer: 5505 mm2)
Board D: 4 layer PCB (all layers: 5505 mm2)
Values in derating curve and packaged thermal resistor are tested values
0
25
50
75
100
125
150
AMBIENT TEMPERATURE [°C]
Figure 35. Thermal Derating Curve
(VQFN048V7070)
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BD64008MUV
I/O Equivalent Circuit
No.
Pin Name
Equivalent Circuit
No.
43
Pin Name
OCPDET
Equivalent Circuit
10 kΩ
10 kΩ
FB1
OCPDET
UVDET
RESET
42
FB1
44
45
UVDET
RESET
20 kΩ
20 kΩ
FB2
18
FB2
Internal Power
Supply2
Internal Power
Supply2
Internal Power
Supply1
13
14
15
ENBSW1
ENBSW2
PWM
100 kΩ
10 kΩ
MODE
500 kΩ
47
MODE
Internal Power
Supply2
10 kΩ
9
7
DAT
CLK
VINSW2
Internal Power
Supply2
8
4
5
6
46
10
11
12
STB(LD)
SLEEP
ENBA
ENBB
RSTIN
ID0
40 Ω
17
COMP
10 kΩ
COMP
10 kΩ
100 kΩ
ID1
ID2
BOOT
Internal Power
Supply2
21
BOOT
2
3
VREFA
VREFB
SWOUT2
BOOT
VINSW2
VREFA 30 kΩ
30 kΩ
19
20
VREFB
VINSW2
SWOUT2
VINSW2
10 kΩ
UVDETIN
130 Ω
22
23
SWOUT2
VBBA
48
UVDETIN
29
32
30
26
31
35
28
33
VBBSW1
SWOUT1
37
38
VBBSW1
SWOUT1
RNFAS
VBBB
VBBX
200 kΩ
OUTAP
39
40
Internal Power
Supply2
OUTAM
OUTBP
OUTBM
RNFA
OUTXX
Internal Power
Supply2
27
34
200 kΩ
RNFX
15 kΩ
Internal
Circuit
RNFXS
RNFBS
RNFB
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Operational Notes
1
Reverse Connection of Power Supply
Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when
connecting the power supply, such as mounting an external diode between the power supply and the IC’s power
supply pins.
2
Power Supply Lines
Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at
all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic
capacitors.
3
4
Ground Voltage
Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.
Ground Wiring Pattern
When using both small-signal and large-current ground traces, the two ground traces should be routed separately but
connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal
ground caused by large currents. Also ensure that the ground traces of external components do not cause variations
on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.
5
6
Recommended Operating Conditions
The function and operation of the IC are guaranteed within the range specified by the recommended operating
conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical
characteristics.
Inrush Current
When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow
instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power
supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and
routing of connections.
7
Testing on Application Boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may
subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply
should always be turned off completely before connecting or removing it from the test setup during the inspection
process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during
transport and storage.
8
9
Inter-pin Short and Mounting Errors
Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in
damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.
Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and
unintentional solder bridge deposited in between pins during assembly to name a few.
Unused Input Pins
Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and
extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small
charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and
cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the
power supply or ground line.
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Operational Notes – continued
10 Regarding the Input Pin of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example (refer to figure below):
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
Pin B
B
E
C
Pin A
B
C
E
P
P+
P+
N
P+
P
P+
N
N
N
N
N
N
N
Parasitic
Elements
Parasitic
Elements
P Substrate
GND GND
P Substrate
GND
GND
Parasitic
Elements
Parasitic
Elements
N Region
close-by
Figure 36. Example of Monolithic IC Structure
11 Ceramic Capacitor
When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with
temperature and the decrease in nominal capacitance due to DC bias and others.
12 Thermal Shutdown Circuit (TSD)
This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always
be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the
junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. The IC should
be powered down and turned ON again to resume normal operation because the TSD circuit keeps the outputs at the
OFF state even if the Tj falls below the TSD threshold.
Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no
circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from
heat damage.
13 Over Current Protection Circuit (OCP)
This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This
protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should
not be used in applications characterized by continuous operation or transitioning of the protection circuit.
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BD64008MUV
Technical information (Exempt from guarantee)
1
About logic input pins for control
Response time from rising edge of CLK signal is 20 µs.
2
In case RESET function is used when SWREG is unused
Divide the power supply (VBB) by resistor voltage divider, and input into the FB1 pin.
In doing so, using RESET function becomes possible.
In this case, it is necessary to make ENBSW1 L level.
Because this function is only assumed when designing, evaluate and confirm it.
3
4
5
Internal power supply 1
Internal power supply 1 applies 4.4 V (Typ) ±10 % dispersion.
Internal power supply 2
Internal power supply 2 applies 5 V (Typ) ±10 % dispersion.
VREF to RNFS offset voltage (Refer P.4)
DAC = 3, accuracy ±10 %
DAC = 15, accuracy ±4 %
6
7
ON-Resistance (H-Bridge)
Listed value is only for IOUT = 1 A, but the value is equal about IOUT = 0.5 A.
Thermal Shutdown Circuit (TSD)
The overheat protection works in 175 °C (Typ), but the overheat protection temperature cannot be less than 150 °C
even if it varies with each IC.
8
Adjacent Pins short
When VBBx(Note 1) and RNFx(Note 1) short-circuits, the IC may destroy it.
(Note 1) x = A, B
Ordering Information
M U
V
B D 6
4
0
0
8
-
E 2
Package
MUV: VQFN048V7070
Packaging and forming specification
E2: Embossed tape and reel
Part Number
Marking Diagram
VQFN048V7070 (TOP VIEW)
Part Number Marking
BD64008
LOT Number
Pin 1 Mark
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BD64008MUV
Physical Dimension and Packing Information
Package Name
VQFN048V7070
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BD64008MUV
Revision History
Date
Revision
001
Changes
13.Oct.2017
New Release
P.22 RESET OUT truth table changed.
Update new format
08.Mar.2019
002
P.7 to P.26 Changed index
P.7 (3), (4) Changed place from P.23
P.23 (1) Added explanation
20.Dec.2019
003
15.Jan.2020
16.Nov.2020
004
005
P.31 Changed I/O Equivalence Circuit
Updated according to the latest format.
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Notice
Precaution on using ROHM Products
1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,
OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you
intend to use our Products in devices requiring extremely high reliability (such as medical equipment (Note 1), transport
equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car
accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or
serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.
Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any
damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific
Applications.
(Note1) Medical Equipment Classification of the Specific Applications
JAPAN
USA
EU
CHINA
CLASSⅢ
CLASSⅣ
CLASSⅡb
CLASSⅢ
CLASSⅢ
CLASSⅢ
2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor
products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate
safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which
a failure or malfunction of our Products may cause. The following are examples of safety measures:
[a] Installation of protection circuits or other protective devices to improve system safety
[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure
3. Our Products are designed and manufactured for use under standard conditions and not under any special or
extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way
responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any
special or extraordinary environments or conditions. If you intend to use our Products under any special or
extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of
product performance, reliability, etc, prior to use, must be necessary:
[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents
[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust
[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,
H2S, NH3, SO2, and NO2
[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves
[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items
[f] Sealing or coating our Products with resin or other coating materials
[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.
However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble
cleaning agents for cleaning residue after soldering
[h] Use of the Products in places subject to dew condensation
4. The Products are not subject to radiation-proof design.
5. Please verify and confirm characteristics of the final or mounted products in using the Products.
6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,
confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power
exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect
product performance and reliability.
7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in
the range that does not exceed the maximum junction temperature.
8. Confirm that operation temperature is within the specified range described in the product specification.
9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in
this document.
Precaution for Mounting / Circuit board design
1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product
performance and reliability.
2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must
be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,
please consult with the ROHM representative in advance.
For details, please refer to ROHM Mounting specification
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Precautions Regarding Application Examples and External Circuits
1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the
characteristics of the Products and external components, including transient characteristics, as well as static
characteristics.
2. You agree that application notes, reference designs, and associated data and information contained in this document
are presented only as guidance for Products use. Therefore, in case you use such information, you are solely
responsible for it and you must exercise your own independent verification and judgment in the use of such information
contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses
incurred by you or third parties arising from the use of such information.
Precaution for Electrostatic
This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper
caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be
applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,
isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).
Precaution for Storage / Transportation
1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:
[a] the Products are exposed to sea winds or corrosive gases, including Cl2, H2S, NH3, SO2, and NO2
[b] the temperature or humidity exceeds those recommended by ROHM
[c] the Products are exposed to direct sunshine or condensation
[d] the Products are exposed to high Electrostatic
2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period
may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is
exceeding the recommended storage time period.
3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads
may occur due to excessive stress applied when dropping of a carton.
4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of
which storage time is exceeding the recommended storage time period.
Precaution for Product Label
A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.
Precaution for Disposition
When disposing Products please dispose them properly using an authorized industry waste company.
Precaution for Foreign Exchange and Foreign Trade act
Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign
trade act, please consult with ROHM in case of export.
Precaution Regarding Intellectual Property Rights
1. All information and data including but not limited to application example contained in this document is for reference
only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any
other rights of any third party regarding such information or data.
2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the
Products with other articles such as components, circuits, systems or external equipment (including software).
3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any
third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM
will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to
manufacture or sell products containing the Products, subject to the terms and conditions herein.
Other Precaution
1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.
2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written
consent of ROHM.
3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the
Products or this document for any military purposes, including but not limited to, the development of mass-destruction
weapons.
4. The proper names of companies or products described in this document are trademarks or registered trademarks of
ROHM, its affiliated companies or third parties.
Notice-PGA-E
Rev.004
© 2015 ROHM Co., Ltd. All rights reserved.
Daattaasshheeeett
General Precaution
1. Before you use our Products, you are requested to carefully read this document and fully understand its contents.
ROHM shall not be in any way responsible or liable for failure, malfunction or accident arising from the use of any
ROHM’s Products against warning, caution or note contained in this document.
2. All information contained in this document is current as of the issuing date and subject to change without any prior
notice. Before purchasing or using ROHM’s Products, please confirm the latest information with a ROHM sales
representative.
3. The information contained in this document is provided on an “as is” basis and ROHM does not warrant that all
information contained in this document is accurate and/or error-free. ROHM shall not be in any way responsible or
liable for any damages, expenses or losses incurred by you or third parties resulting from inaccuracy or errors of or
concerning such information.
Notice – WE
Rev.001
© 2015 ROHM Co., Ltd. All rights reserved.
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