BD65520MUV (开发中)

Datasheet

High-efficiency 36 V Withstand Voltage

Stepping Motor Drive

BD65520MUV

General Description

Key Specifications

BD65520MUV is a 36 V power supply rated, 2.0 A output

current rated, low-consumption bipolar PWM constant

current driven High-efficiency Driver. The input interface

adopts the CLK-IN drive system, and the excitation mode

supports FULL STEP to 1/32 STEP mode via a built-in

DAC. FAST / SLOW DECAY of current decay mode ratio

linear variable freely. Pin settings and detailed settings

by SPI are set to make an optimum current control

possible according to the load of every motor for a

High-efficiency Drive. In addition, the power supply may

also be driven by a single system, contributing to a

simple set design.

◼ Power Supply Voltage Range

◼ Rated Output Current (Continuous)

◼ Rated Output Current (Peak value)

◼ Operating Temperature Range

◼ Output ON Resistance

8 V to 28 V

2.0 A/Phase

2.5 A/Phase

-25 °C to +85 °C

0.55 Ω (Typ)

(Total upper and lower)：

Package

VQFN040V6060

W (Typ) x D (Typ) x H (Max)

6.0 mm x 6.0 mm x 1.0 mm

Features

◼ Built-in High-efficiency Drive Mode

(Drive Current Value Output Function, High-efficiency

Drive Setting Function)

◼ Motor Load Status Output Function

◼ Pin Setting Mode / SPI Setting Mode

◼ Detailed Setting Function by SPI Input

◼ Output Current Rating (DC) 2.0 A

◼ Low ON Resistance DMOS Output

◼ CLK-IN Drive System

◼ PWM Constant Current Control (Other Oscillation)

◼ Built-in Spike Noise Blanking Function

(No external Noise Filter required)

◼ FULL STEP to 1/32 STEP Compatible

◼ Excitation Mode Switching Free Timing

◼ Current Decay Mode Switching Function

(FAST DECAY / SLOW DECAY Ratio Linear Variable

(MIX DECAY))

Typical Application Circuit

GND

PS

CWCCW_CSB

TEST1

TEST2

MODE0_SCLK

MODE1_SI

CLK

INVREF

MCU

ENABLE

STOMGN

VCC1

◼ Current Decay Mode Optimization Function (AUTO

DECAY)

SO

◼ Forward / Reverse Switching Function

◼ Power Save Function

◼ Built-in Logic Input Pull-down Resistor

◼ Power ON Reset Function

◼ Temperature Protection Circuit (TSD)

◼ Overcurrent Protection Circuit (OCP)

◼ Low Voltage Malfunction Prevention Function (UVLO)

◼ Overvoltage Output OFF Function (OVLO)

◼ Malfunction Prevention Function if no power applied

(“Ghost Supply Prevention” function)

◼ Protection Status Output Function

◼ Adjacent Pin Short Protection

OUT1A

FO

OUT1B

RNF1

GAMOD1

GAMOD2

RNF1S

VCC2

HIEFEN

HIFESEL

VREFMIN

VREF

OUT2A

OUT2B

RNF2

MTH

CR

◼ Ultra-compact, Ultra-thin, High Heat Dissipation

(Backside Heat Dissipation) Package

RNF2S

GND

VREGD

Application

VREGA

◼ PPC, Multifunction Printer, Laser Beam Printer, Inkjet

Printer, Surveillance Camera, WEB Camera, Sewing

Machine, Photo Printer, Fax, Scanner, Mini Printer, Toy,

Robot

VREGDAC

Figure 1. Application Circuit Diagram (SPI Setting Mode)

〇Product structure : Silicon integrated circuit 〇This product has no designed protection against radioactive rays

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Table of Contents

General Description........................................................................................................................................................................1

Features..........................................................................................................................................................................................1

Application ......................................................................................................................................................................................1

Key Specifications ..........................................................................................................................................................................1

Package..........................................................................................................................................................................................1

Typical Application Circuit ...............................................................................................................................................................1

Table of Contents ...........................................................................................................................................................................2

Pin Configuration ............................................................................................................................................................................5

Pin Description................................................................................................................................................................................5

Block Diagram ................................................................................................................................................................................6

Absolute Maximum Rating..............................................................................................................................................................7

Recommended Operating Condition...............................................................................................................................................7

Thermal Resistance........................................................................................................................................................................7

Electrical Characteristics.................................................................................................................................................................8

Pin Function Description...............................................................................................................................................................11

1 CLK / Phase Advance Clock Input Pin ...................................................................................................................................11

2 ENABLE / Output Enable Pin.................................................................................................................................................11

3 PS / Power Saving Pin ...........................................................................................................................................................11

4 GAMOD1 and GAMOD2 / High-efficiency Drive Setting Select Pin and Interface Mode Setting Pin .....................................11

5 MODE0_SCLK, MODE1_SI Motor Excitation Mode Setting Pin and SPI Setting Mode Input Pin .........................................12

6 CWCCW_CSB / Motor Rotation Direction Setting Pin and SPI Chip Select Input Pin ...........................................................12

7 SO / SPI Setting Mode Output Pin .........................................................................................................................................12

8 FO / Protection Status Output Pin..........................................................................................................................................12

9 HIEFSEL / High-efficiency Drive Setting Pin ..........................................................................................................................12

10 HIEFEN / High-efficiency Drive Enable Pin..........................................................................................................................12

11 VCC1, VCC2 / Power Supply Pin .........................................................................................................................................13

12 GND / Ground Pin................................................................................................................................................................13

13 OUT1A, OUT1B, OUT2A, OUT2B / H Bridge Output Pin.....................................................................................................13

14 RNF1, RNF2 / Output Current Detection Resistance connection pin ...................................................................................13

15 RNF1S, RNF2S / Current Detection Comparator Input Pin..................................................................................................13

16 VREF / Output Current Value Setting Pin.............................................................................................................................13

17 VREFMIN / Output Current Value Lower Limit Setting Pin...................................................................................................14

18 CR / Chopping Frequency Setting Pin..................................................................................................................................14

19 MTH / Current Decay Mode Setting Pin ...............................................................................................................................14

20 INVREF / Internal VREF Output Pin.....................................................................................................................................14

21 STOMGN / Step-out Margin Output Pin ...............................................................................................................................14

22 VREGD / 1.5 V Regulator Output Pin...................................................................................................................................14

23 VREGA / 5 V Regulator Output Pin ......................................................................................................................................14

24 VREGDAC / IC Internal ADC and DAC 5 V Regulator Output Pin .......................................................................................14

25 TEST1 / Test Pin ..................................................................................................................................................................14

26 TEST2 / Test Pin ..................................................................................................................................................................15

27 NC........................................................................................................................................................................................15

28 IC Back Metal.......................................................................................................................................................................15

Various Circuits for Protection.......................................................................................................................................................16

1 Temperature Protection Circuit (TSD) ....................................................................................................................................16

2 Overcurrent Protection Circuit (OCP).....................................................................................................................................16

3 Malfunction Prevention Function When Low Voltage (UVLO) ................................................................................................16

4 Output OFF function When Overvoltage (OVLO)...................................................................................................................16

5 Malfunction Prevention Function When No Power Loading (Ghost Supply Prevention Function)..........................................16

6 Operation in a Strong Magnetic Field.....................................................................................................................................16

PWM Constant Current Control ....................................................................................................................................................17

1 Current Control Operation......................................................................................................................................................17

2 Noise Canceling Function ......................................................................................................................................................17

3 CR Timer................................................................................................................................................................................17

4 Current Decay Mode..............................................................................................................................................................19

4.1 SLOW DECAY.................................................................................................................................................................19

4.2 FAST DECAY...................................................................................................................................................................19

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4.3 MIX DECAY .....................................................................................................................................................................19

4.4 AUTO DECAY..................................................................................................................................................................19

Translator Circuit Operation in CLK-IN Drive System ...................................................................................................................21

1 Reset Operation.....................................................................................................................................................................21

1.1 Initialization Process When Turning the Power ON .........................................................................................................21

1.1.1 When Power ON in PS = L ...........................................................................................................................................21

1.1.2 When Power ON in PS = H...........................................................................................................................................21

1.2 Initialization operation during motor operation.................................................................................................................21

2 Control Input Timing...............................................................................................................................................................21

3 FULL STEP A, CWCCW_CSB = L, ENABLE = H ..................................................................................................................22

4 HALF STEP A, CWCCW_CSB = L, ENABLE = H..................................................................................................................22

5 HALF STEP B, CWCCW_CSB = L, ENABLE = H..................................................................................................................23

6 QUARTER STEP A, CWCCW_CSB = L, ENABLE = H..........................................................................................................23

7 HALF STEP C, CWCCW_CSB = L, ENABLE = H..................................................................................................................24

8 QUARTER STEP B, CWCCW_CSB = L, ENABLE = H .........................................................................................................24

9 Step Sequence Table (FULL STEP B, HALF STEP C, QUARTER STEP B, 1/ 8 STEP, 1/ 16 STEP, 1/ 32 STEP)................25

10 Reset timing chart (QUARTER STEP, CWCCW_CSB = L, ENABLE = H) ...........................................................................28

11 Motor rotation direction switching timing chart (FULL STEP A, ENABLE = H)......................................................................28

12 ENABLE Switching Timing Chart (FULL STEP A)................................................................................................................29

13 Motor Excitation Mode Switching .........................................................................................................................................29

14 Precautions When Doing Both Motor Rotation Direction and Excitation Mode Switching....................................................29

SPI Interface.................................................................................................................................................................................30

1 3 Wires 32 Bit SPI Input Method ............................................................................................................................................30

2 3 Wires 32 Bit SPI Transmission Cancellation .......................................................................................................................31

Command Register.......................................................................................................................................................................32

1 Command Register Description .............................................................................................................................................32

2 Command List........................................................................................................................................................................32

3 Command Register Detailed Description ...............................................................................................................................33

3.1 MODESET.......................................................................................................................................................................33

3.2 READSEL........................................................................................................................................................................34

3.3 READ_READSEL............................................................................................................................................................34

3.4 READ_DIAGNOSTIC ......................................................................................................................................................35

3.5 READ_CURRENT_VREF................................................................................................................................................36

3.6 READ_MARGIN ..............................................................................................................................................................37

3.7 STOMGN_PEAKHOLD_CLEAR......................................................................................................................................38

3.8 VREFSET........................................................................................................................................................................39

3.9 VREFMINSET .................................................................................................................................................................40

3.10 KESET...........................................................................................................................................................................41

3.11 MTHSET........................................................................................................................................................................42

3.12 CRTIMESET..................................................................................................................................................................43

3.13 MIN_FREQ_ON_SET....................................................................................................................................................44

3.14 MIN_FREQ_OFF_SET..................................................................................................................................................45

3.15 HIEF_SET .....................................................................................................................................................................46

3.16 VBEMFAVESET.............................................................................................................................................................47

3.17 GAIN_SET.....................................................................................................................................................................48

3.18 GAIN1_SET...................................................................................................................................................................49

3.19 GAIN2_SET...................................................................................................................................................................49

3.23 VREFOFFSETSET........................................................................................................................................................51

3.24 GAIN4_SET...................................................................................................................................................................52

3.25 GAIN5_SET...................................................................................................................................................................52

3.26 GAIN6_SET...................................................................................................................................................................52

3.27 VBEMFMONSET...........................................................................................................................................................53

3.28 STOMGN_PEAKHOLD_SET.........................................................................................................................................55

3.29 FULLSTEPWINDOWSET..............................................................................................................................................57

3.30 HIEFSELMAX................................................................................................................................................................58

3.31 HIEFSELMIN.................................................................................................................................................................59

3.32 UNLOCK........................................................................................................................................................................60

Induced-voltage Reading Circuit...................................................................................................................................................61

High-efficiency Drive.....................................................................................................................................................................62

Step-out Margin Detection ............................................................................................................................................................63

Power Dissipation.........................................................................................................................................................................64

I/O Equivalent Circuit....................................................................................................................................................................65

Application Example (Pin setting mode) .......................................................................................................................................67

Application Example (SPI setting mode).......................................................................................................................................68

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Operational Notes.........................................................................................................................................................................69

1.

2.

3.

4.

5.

6.

7.

8.

Reverse Connection of Power Supply............................................................................................................................69

Power Supply Lines........................................................................................................................................................69

Ground Voltage...............................................................................................................................................................69

Ground Wiring Pattern....................................................................................................................................................69

Recommended Operating Conditions.............................................................................................................................69

Inrush Current.................................................................................................................................................................69

Testing on Application Boards ........................................................................................................................................69

Inter-pin Short and Mounting Errors ...............................................................................................................................69

Unused Input Pins ..........................................................................................................................................................69

Regarding the Input Pin of the IC ...................................................................................................................................70

Ceramic Capacitor..........................................................................................................................................................70

Thermal Shutdown Circuit (TSD)....................................................................................................................................70

Over Current Protection Circuit (OCP) ...........................................................................................................................70

9.

10.

11.

12.

13.

Ordering Information.....................................................................................................................................................................71

Marking Diagram ..........................................................................................................................................................................71

Physical Dimension and Packing Information...............................................................................................................................72

Revision History............................................................................................................................................................................73

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Pin Configuration

(TOP VIEW)

30

29

28

27

26

25

24

23

22

21

31

32

33

34

35

36

37

38

39

40

20

19

18

17

16

15

14

13

12

11

OUT1A

VCC1

NC

OUT2A

VCC2

NC

GAMOD1

MTH

GAMOD2

TEST2

TEST1

GND

VREF

VREFMIN

HIEFSEL

CLK

EXP-PAD

HIEFEN

CR

ENABLE

VREGDAC

1

2

3

4

5

6

7

8

9

10

Figure 2. Pin Layout Diagram

Pin Description

Pin Name

No.

Function

Pin No. Pin Name

Function

1

2

PS

Power save pin

21

22

NC

No connection

CWCCW_ Motor rotation direction setting pin ^{(Note 1)}

OUT2B

H bridge output pin

CSB

Chip select input pin ^{(Note 2)}

MODE0_ Motor excitation mode setting pin ^{(Note 1)}

SCLK

3

4

23

24

NC

No connection

Serial clock input pin ^{(Note 2)}

Motor excitation mode setting pin ^{(Note 1)}

Serial data input pin ^{(Note 2)}

MODE1_SI

RNF2

Output current detection resistor connection pin

5

SO

FO

Serial data output pin

Protect status output pin

Internal VREF output pin

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

RNF2S

GND

Current detection comparator input pin

Ground pin

6

7

INVREF

RNF1S

RNF1

OUT1B

NC

Current detection comparator input pin

Output current detection resistor connection pin

H bridge output pin

8

STOMGN Step-out margin output pin

9

VREGD

VREGA

1.5 V Regulator output pin

5 V Regulator output pin

10

11

12

13

14

15

16

17

18

19

20

-

No connection

VREGDAC DAC 5 V Regulator output pin

OUT1A

VCC1

NC

H bridge output pin

CR

Chopping frequency setting pin ^{(Note 3)}

Ground pin

Power pin

GND

No connection

TEST1

TEST2

Test pin (Set OPEN)

MTH

Current decay mode setting pin ^{(Note 3)}

Output current value setting pin ^{(Note 3)}

Test pin (Use while connected with GND)

VREF

GAMOD2 High-efficiency Drive gain setting pin

GAMOD1 High-efficiency Drive gain setting pin

VREFMIN Output current value lower limit setting pin ^{Note 3)}

HIEFSEL High-efficiency Drive setting pin ^{(Note 3)}

NC

No connection

CLK

Phase-advancing clock input pin

High-efficiency Drive enable pin ^{(Note 4)}

Output enable pin

VCC2

OUT2A

Power supply pin

H bridge output pin

HIEFEN

ENABLE

EXP-PAD Connect the EXP-PAD to GND

(Note 1) Function in pin setting mode.

(Note 2) Function in SPI setting mode.

(Note 3) Not used in SPI setting mode. Connect with GND.

(Note 4) Not used in SPI setting mode. Open or connect to GND.

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Block Diagram

GND

SO

CWCCW_CSB

MODE0_SCLK

MODE1_SI

SPI

TSD

OCP

TEST1

TEST2

OVLO

UVLO

RESET

PS

FO

Translator

CLK

ENABLE

HIEFEN

GAMOD2

GAMOD1

HIEFSEL

INVREF

DAC

STOMGN

VREFMIN

VREF

ADC

VCC1

OUT1A

OUT1B

CR

OSC

RNF1

RNF1S

Mix decay

control

MTH

VCC2

OUT2A

OUT2B

VREGD

VREGA

VREGD

VREGA

RNF2

VREGDAC

RNF2S

GND

OUT1A

OUT1B

VREF

CALC

RNF1S DAC

RNF2S

ADC

OUT2A

OUT2B

Figure 3. BD65520MUV Block Diagram

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Absolute Maximum Rating (Ta = 25 °C)

Parameters

Supply Voltage

Symbol

V_CC1,V_CC2

V_IN

Rating

Unit

-0.2 to +36.0

-0.2 to +5.5

0.7

V

Input Voltage for Control Pin

RNF Maximum Voltage

V

V_RNF

Output Current (Continuous)

Output Current (Peak) ^{(Note 2)}

Storage Temperature Range

Maximum Junction Temperature

I_OUT

2.0^{(Note 1)}

2.5^{(Note 1)}

-55 to +150

+150

A/Phase

°C

I_OUTPEAK

Tstg

Tjmax

°C

(Note 1) Do not exceed Tjmax = 150 °C.

(Note 2) Pulse width tw ≤ 2 ms, duty 20 %.

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is operated

over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded, the rise in temperature of chip may result in deterioration of the properties

of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing board size

and copper area so as not to exceed the maximum junction temperature rating.

Recommended Operating Condition

Parameters

Operating Temperature

Supply Voltage

Symbol

Topr

Min

-25

Typ

+25

Max

+85

Unit

°C

V_CC1,V_CC2

I_OUT

8

24

28

V

Maximum Output Current

(Continuous)

0^{(Note 3)}

1.0^{(Note 3)}

2.0^(Note3)

A/Phase

(Note 3) Must not exceed Tjmax = 150 °C.

Thermal Resistance ^{(Note 4)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 6)}

2s2p^{(Note 7)}

VQFN040V6060

Junction to Ambient

Junction to Top Characterization Parameter^{(Note 5)}

θ_JA

85.2

8

30.5

5

°C/W

Ψ_JT

(Note 4) Based on JESD51-2A (Still-Air), using a BD65520MUV Chip.

(Note 5) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside

surface of the component package.

(Note 6) Using a PCB board based on JESD51-3.

(Note 7) Using a PCB board based on JESD51-5, 7.

Layer Number of

Measurement Board

Material

Board Size

Single

FR-4

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Thermal Via^{(Note 8)}

Material

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

Pitch

Diameter

4 Layers

FR-4

1.20 mm

Φ0.30 mm

Top

Copper Pattern

Bottom

Thickness

70 μm

Copper Pattern

Thickness

Copper Pattern

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

35 μm

74.2 mm x 74.2 mm

(Note 8) This thermal via connect with the copper pattern of layers 1,2, and 4. The placement and dimensions obey a land pattern.

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Electrical Characteristics (Unless otherwise specified, Ta = 25 °C, V_CC1,V_CC2= 24 V)

Limits

Parameter

Symbol

Unit

Condition

Min

Typ

Max

[General]

Circuit Current at Standby

Circuit Current

I_CCST

I_CC

-

10

25

µA

PS = L

PS = H, VREF = 2.5 V

10

mA

[Control Input] (PS, ENABLE, CLK, CWCCW_CSB, MODE0_SCLK, MODE1_SI, GAMOD1, GAMOD2, HIEFEN)

H Level Input Voltage

L Level Input Voltage

H Level Input Current

L Level Input Current

V_INH

V_INL

I_INH

I_INL

2.0

-

V

0.8

100

-

35

-10

50

0

µA

V_{IN =}5 V

V_{IN =}0 V

[Output] (OUT1A, OUT1B, OUT2A, OUT2B)

Output ON Resistor

R_ON

I_LEAK

I_OUTR

-

0.55

-

0.85

10

Ω

I_OUT= ±1.0 A (Top/Bottom Total)

V_OUT= 24 V

Output MOS Leak

μA

Output Inflow Current

[Current Control Unit]

RNF_XS Inflow Current^(Note1)

RNF_XInflow Current^(Note1)

VREF Inflow Current

VREF Input Voltage Range

MTH Inflow Current

120

200

V_OUT= 24 V

I_RNFS

I_RNF

-2.0

-80

-2.0

0

-0.1

-40

-0.1

-

µA

V

RNF_XS = 0 V

RNF_X= 0 V

VREF = 0 V

I_VREF

V_VREF

I_MTH

-

3.0

-

-2.0

0

-0.1

-

µA

V

MTH = 0 V

MTH Input Voltage Range

V_MTH

t_ONMIN

V_CTH

3.5

1.7

0.627

Minimum ON Time

(Blank Time)

0.5

0.573

1.2

0.600

µs

V

C = 1000 pF, R = 39 kΩ

VREF = 3.0 V

Comparator Threshold

VREF = 3.0 V,

OUT1 comparator Threshold

- OUT2 comparator Threshold

Comparator Threshold

1phase/2phase difference

V_dcTH

-0.27

0

+0.27

V

[Regulator Output]

VREGA Output Voltage

VREGD Output Voltage

V_A

V_D

-

5.0

1.5

5.0

-

V

VREGDAC Output Voltage

V_DAC

(Note 1) x = 1, 2

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Electrical Characteristics – Continued

(Unless otherwise specified, Ta = 25 °C, V_CC1,V_CC2= 24 V)

Limits

Parameter

Symbol

Unit

Condition

Min

Typ

Max

[High-efficiency Drive Setting]

VREFMIN Inflow Current

I_VREFMIN

V_VREFMIN

I_HIEFSEL

-2.0

0

-0.1

-

3.0

-

µA

V

VREFMIN = 0 V

VREFMIN Input Voltage

Range

-

-0.1

-

HIEFSEL Inflow Current

-2.0

0

µA

V

HIEFSEL = 0 V

HIEFSEL Input Voltage Range V_HIEFSEL

[Analog Output]

3.99

I_LOAD= 0 mA, VREGDAC = 5 V,

GAMOD1 = 5 V, GAMOD2 = 5 V

VREFSET = 1.00

I_LOAD= 0 mA, VREGDAC = 5 V,

OUT1A = 4 V, OUT1B = 0 V,

(When OUT1-side is OPEN)

INVREF Output Voltage

STOMGN Output Voltage

V_INVREF

0.95

3.90

1.00

4.00

1.05

4.10

V

V_STOMGN

[FO Output]

Output L Voltage

Output Leak Current

[SO Output]

V_OLF

-

0.05

0.10

10

V

I_LOAD= -1 mA

I_{FO_LEAK}

-

µA

Output H Voltage

Output L Voltage

Output Leak Current

V_OHS

V_OLS

I_OS

V_A-0.2

V_A-0.1

-

V

I_LOAD= +1 mA

-

0.1

0.2

10

I_LOAD= -1 mA

-

µA

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Electrical Characteristics - Continued

(Unless otherwise specified, Ta = 25 °C, V_CC1,V_{CC2 =}24 V)

Signal

Symbol

Parameter

CSX “H” Pulse

Width

Min

Typ

Max

Unit

Comment

t_CHW

400

-

ns

t_CSSW

t_CSHW

t_CSSR

t_CSHR

CSX-SCL Time

(Write)

CSX-SCL Time

(Read)

200

600

-

ns

CWCCW_CSB

Serial Clock

Cycle

SCL “H” Pulse

Width

SCL “L” Pulse

Width

Serial Clock

Cycle

SCL “H” Pulse

Width

SCL “L” Pulse

Width

Data Setup

Time

t_SCYCW

t_SHW

t_SLW

1000

500

-

ns

MODE0_SCLK

(Write)

500

t_SCYCR

t_SHR

2000

1000

200

MODE0_SCLK

(Read)

t_SLR

t_SDS

MODE1_SI

SO

Data Hold

Time

Access Time

Output Disable

Time

t_SDH

t_ACC

t_OH

200

-

1000

-

ns

Max Condition: CL = 30 pF

Min Condition: CL = 8 pF

100

Caution 1: t_rand t_f(signal rise/fall) should be at 15 ns or less.

t_CHW

t_CSSW

t_CSSR

t_CSHW

t_CSHR

CWCCW_CSB

t_SCYCW

t_SCYCR

t_SLW

t_SLR

MODE0_SCLK

MODE1_SI

SO

t_SHW

t_SHR

t_f

t_r

t_SDS

t_SDH

t_OH

t_ACC

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Pin Function Description

1 CLK / Phase Advance Clock Input Pin

This pin operates at rising edge. The Electrical angle advances by one for each CLK input. Motor misstep will occur if noise

mixed in the CLK pin so, design the pattern in such a way that there is no noise mixing in.

2 ENABLE / Output Enable Pin

This pin forcibly turns off all output transistors (motor output OPEN). During ENABLE = L, CLK input is cut off so the phase

advance operation of the internal translator circuit will stop. However, if the excitation mode (MODE0, MODE1) is switched in

the ENABLE = L interval, the excitation mode when ENABLE pin returns from Low to High becomes enabled in the switched

mode. Also, in the SPI setting mode, if the register setting is MODESET D5 = 1 even if at ENABLE = L, the phase advance

operation will operate.

ENABLE

Motor Output

OPEN (electrical angle maintained)

ACTIVE

L

H

3 PS / Power Saving Pin

Standby mode can be set and motor output can be OPEN. When entering a standby state, the translator circuit will RESET

(initialized) and the electrical angle will be initialized. Notice that after returning from standby state to normal state when PS =

L becomes H, there will a delay of 1 ms (Max) until the motor output returns to the ACTIVE state.

PS

Status

Standby State (RESET)

ACTIVE

L

H

The electrical angle (initial electrical angle) for each excitation mode right after RESET shall be as follows.

Excitation Mode

FULL STEP A

HALF STEP A

HALF STEP B

QUARTER STEP A

FULL STEP B

HALF STEP C

QUARTER STEP B

1/8 STEP

Initial Electrical Angle

45°

1/16 STEP

1/32 STEP

4 GAMOD1 and GAMOD2 / High-efficiency Drive Setting Select Pin and Interface Mode Setting Pin

This pin performs settings for pin setting mode and SPI setting mode.

This pin performs a High-efficiency Drive setting when in pin setting mode.

GAMOD1 GAMOD2

Interface

High-efficiency Drive Setting

Preset 1 (GAIN1_SET, GAIN4_SET)

Preset 2 (GAIN2_SET, GAIN5_SET)

Preset 3 (GAIN3_SET, GAIN6_SET)

GAIN1_SET, GAIN4_SET

L

H

L

Pin Setting Mode

SPI Setting Mode

H

This pin selects preset when in pin setting mode by GAMOD1 and GAMOD2 pin logic, and the circuit initial values of the

corresponding register settings are used. Select the optimum High-efficiency Drive setting depending on the motor and load

conditions.

This pin performs High-efficiency Drive setting in SPI setting mode by register setting of GAIN1_SET and GAIN4_SET.

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Pin Function Description - Continued

5 MODE0_SCLK, MODE1_SI Motor Excitation Mode Setting Pin and SPI Setting Mode Input Pin

This pin sets the motor excitation mode when at pin setting mode.

MODE0_SCLK MODE1_SI

Excitation Mode

L

H

L

FULL STEP

HALF STEP A

HALF SETP B

QUARTER STEP A

H

MODE0_SCLK pin becomes SPI clock input pin and MODE1_SI pin becomes SPI data input pin when in SPI setting mode.

For each excitation mode, refer to the timing chart and motor torque vector diagram.

This pin forcibly reflects the setting change regardless of CLK.

This pin carries out the motor excitation mode setting in the register setting when in the SPI setting mode.

6 CWCCW_CSB / Motor Rotation Direction Setting Pin and SPI Chip Select Input Pin

This pin sets the motor rotation direction when pin setting mode, and reflects the rising edge of CLK immediately after setting

change.

CWCCW_CSB

Rotating Direction

L

Clockwise (CH2 current output is delay by 90° phase with respect to CH1 current)

Counter Clockwise (CH2 current output is advance by 90° phase with respect to CH1 current)

H

CWCCW_CSB is the SPI chip select input pin when in the SPI setting mode.

This pin carries out the motor rotating direction setting in the register setting when in SPI setting mode.

7 SO / SPI Setting Mode Output Pin

This is the serial data output pin when in the SPI setting mode. H Level is VA level(5 V Typ).

Open is recommended when you don’t use SPI read.

SO pin is Hi-z without Read condition. So, it is recommended to attach 5 kΩ or more Pulldown resistance or Pullup

resistance.

8 FO / Protection Status Output Pin

This pin outputs the status of protection with TSD, OCP, and OVLO.

The FO pin outputs L level when detects each protection function.

It is recommended to attach 5 kΩ or more Pullup resistance.

When SPI setting mode

FO pin is L level output after IC power on until READ_DIAGNOSTIC command sent.

When IC is receipt READ_DIAGNOSTIC command and TSD, OCP or OVLO are not detected, FO output is H level.

9 HIEFSEL / High-efficiency Drive Setting Pin

This pin sets the current decay ratio during High-efficiency driving in the pin setting mode.

This pin divides the values of the preset registers HIEFSELMAX (Page 58) and HIEFSELMIN (Page 59) into 16 as shown in

the

following formula and the values are determined by the voltage setting of HIEFSEL.

Current Decay Ratio = HIEFSELMIN + (HIEFSELMAX – HIEFSELMIN) / 16 * n

[Relationship between n and HIEFSEL voltage setting]

n = 0: HIEFSEL = 4/16/2

= 0.125 V

n = 1: HIEFSEL = 4/16/2 + 4/16 = 0.375 V

n = 2: HIEFSEL = 4/16/2 + 4/16*2 = 0.625 V

n = 15: HIEFSEL = 4/16/2 + 4/16*15 = 3.875 V

Not used in SPI setting mode.

10 HIEFEN / High-efficiency Drive Enable Pin

This pin enables the High-efficiency Drive operation in pin setting mode.

This pin performs a High-efficiency Drive enable setting in SPI setting mode by register setting.

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Pin Function Description - Continued

11 VCC1, VCC2 / Power Supply Pin

Motor drive current is flowing in this pin so wire in such a way that the wire is thick, short and has low impedance. Voltage

VCC may have great fluctuation, so place a bypass capacitor (100 μF to 470 µF) as close to the pin as possible and adjust in

such a way that the voltage VCC is stable. Increase the capacity if needed especially when a large current is used or those

motors that have great back electromotive force are used. In addition, to lower the impedance of the power supply in a wide

band, it is recommended that a multilayer ceramic capacitor of about 0.01 µF to 0.1 µF to be placed in parallel. Be careful not

to exceed the rating even if the VCC voltage is instantaneous. Although VCC1 and VCC2 are shorted inside the IC, be sure

to short externally VCC1 and VCC2 before using. If not shorted, the current path may be concentrated resulting in

malfunction or destruction. The power supply pin has a built-in clamp element to prevent electrostatic damage. If a steep

pulse signal or voltage such as a surge that exceeds the absolute maximum rating is applied, this clamp element may

operate and cause damage. Therefore, never exceed the absolute maximum rating. It is also effective to attach a zener

diode with an absolute maximum rating. Also, note that a diode for preventing static electricity destruction is inserted

between the VCC pin and the GND pin, and if a reverse voltage is applied to the VCC pin and the GND pin, the IC may be

destroyed.

12 GND / Ground Pin

In order to reduce noise due to switching current and stabilize the reference voltage inside the IC, make the impedance of

the wiring from this pin as low as possible so that it has the lowest potential under any operating conditions. Also, design the

pattern so that it does not have a common impedance with other GND patterns.

13 OUT1A, OUT1B, OUT2A, OUT2B / H Bridge Output Pin

Motor drive current is flowing in this pin so wire in such a way that the wire is thick, short and has low impedance. It is also

effective to add a schottky diode when the output fluctuates greatly positively or negatively when using a large current such

as a back electromotive force. The output pin has a built-in clamp element to prevent electrostatic breakdown. If a steep

pulse signal or voltage such as a surge that exceeds the absolute maximum rating is applied, this clamp element may

operate and cause damage, so never exceed the absolute maximum rating.

14 RNF1, RNF2 / Output Current Detection Resistance connection pin

Connect the resistor of 0.1 Ω to 0.3 Ω for current detection between this pin and GND. In view of the power consumption of

the current-detecting resistor, determine the resistor in such a way that W = I_OUT²･R [W] does not exceed the power

dissipation of the resistor. In addition, Wire in such a way that it has a low impedance and does not have impedance in

common with other GND patterns because motor’s drive current flows in the pattern through RNF pin to current-detecting

resistor to GND. Do not exceed the rating because there is the possibility of circuit malfunction etc. if RNF voltage exceeds

the maximum rating (0.7 V). Moreover, be careful because if RNF pin is shorted to GND, a large current will flow without

normal PWM constant current control, then there is the danger that OCP or TSD will operate. Even if RNF pin is open, there

is the possibility of malfunction such as no output current flowing, so do not put it in such as state.

15 RNF1S, RNF2S / Current Detection Comparator Input Pin

The RNFS pin, which is the input pin of the current detection comparator, is provided independently to reduce the decrease

in current detection accuracy due to the wire impedance inside the IC of the RNF pin. Therefore, when controlling PWM

constant current, be sure to connect the RNF pin and RNFS pin. Furthermore, when connecting, the decrease in current

detection accuracy due to impedance in board pattern between the RNF pin and the current detection resistor can be

reduced by connecting the wiring from the RNFS pin to the immediate vicinity of the current detection resistor. Also, design

the pattern in consideration of wiring with less noise. Take note that if the RNF1S and RNF2S pins are short-circuited to GND,

a large current may flow without normal PWM constant current control, and OCP or TSD may operate.

16 VREF / Output Current Value Setting Pin

This is the pin for setting the output current value to pin setting mode. Output current value can be set base on VREF voltage

and current detection resistor (RNF resistor).

퐼_푂푈푇

=

^푉푅퐸퐹/ ꢀ푁ꢁ

[A]

5

Where:

I_OUTis the Output Current

VREF is the Output Current Value Set Voltage

RNF is the Resistor for Current Detection

If the VREF pin is open, the input becomes indefinite, the VREF voltage rises, the set current increases, and a large current

may flow. Therefore, avoid using the VREF pin when it is open. If a voltage is applied to the VREF pin so that the calculated

value of I_OUTexceeds 2 A, a current exceeding the rating will flow to the output, and OCP or TSD may operate or may even

be destroyed.

Also, when inputting by divided resistance, select the resistance value in consideration of the outflow current (Max 2 µA).

The minimum current that may be controlled from VREF voltage has a minimum ON time for PWM drive therefore, it is

decided based on inductance and resistance values of motor coil and minimum ON time.

In SPI setting mode, the register set value is reflected, so the pin input is invalid. It is recommended that VREF connects

GND in SPI setting mode.

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Pin Function Description - Continued

17 VREFMIN / Output Current Value Lower Limit Setting Pin

This pin is for setting the lower limit of the output current during High-efficiency driving in pin setting mode. The lower limit of

output current can be set base on VREF voltage and current detection resistor (RNF resistor).

퐼_{푂푈푇푀ꢂꢃ}

=

^{푉푅퐸퐹푀ꢂꢃ}/ ꢀ푁ꢁ

[A]

5

Where:

I_OUTMINis the Output Lower Limit Current

VREFMIN is the Output Current Value Lower Limit Set Voltage

RNF is the Resistor for Current Detection

If VREFMIN voltage greater or equal VREF voltage, VREFMIN equals zero in IC internal.

In SPI setting mode, the register set value is reflected so the pin input is disabled. It is recommended that VREFMIN

connects GND in SPI setting mode.

18 CR / Chopping Frequency Setting Pin

This is the pin for setting the chopping frequency of output using pin setting mode.

Connect external capacitor (470 pF to 1500 pF) and Resistance (10 kΩ to 200 kΩ) to GND.

Make sure that the wiring from the external to GND does not have a common impedance with other GND patterns. Also,

keep away from the wiring of steep pulses such as square waves, and design the pattern so that the wiring is less likely to

cause noise. If the CR pin is open or biased from the outside, normal PWM constant current control will not be possible.

Therefore, be sure to attach both capacitor and resistance parts when using with PWM constant current control.

In SPI setting mode, register setting is used. so the pin input is invalid. It is recommended that CR connects GND in SPI

setting mode.

19 MTH / Current Decay Mode Setting Pin

This is the pin for setting the current decay mode using pin setting mode. Current decay mode can be optionally set

according to input voltage.

MTH Pin Input Voltage [V]

Current Decay Mode

SLOW DECAY

MIX DECAY

0 to 0.3

0.4 to 1.0

1.5 to 3.5

FAST DECAY

Connect to GND when using at SLOW DECAY mode. Don’t use missing setting in above table.

If the MTH pin is open, the input will be unsettled and the PWM operation may become unstable. Therefore, avoid using the

MTH pin when it is open. Also, when divided resistance is input, select the resistance value in consideration of the outflow

current (Max 2 µA).

In SPI setting mode, register setting is used. so the pin input is invalid. It is recommended that MTH connects GND in SPI

setting mode.

20 INVREF / Internal VREF Output Pin

This is the pin for the output of internal VREF voltage.

21 STOMGN / Step-out Margin Output Pin

This pin is for output a voltage corresponding to the back electromotive voltage of the connected motor.

This pin acquires counter electromotive voltage during the motor output OPEN period.

Therefore, using it in FULL STEP mode without an OPEN period is not possible. STOMGN voltage hold previous voltage in

FULL STEP mode without an OPEN period. And, STOMGN voltage is 0 V when ENABLE = L.

22 VREGD / 1.5 V Regulator Output Pin

This is the regulator output pin for logic power supply. Place a multilayer ceramic capacitor of about 0.01 µF to 0.1 µF to

stabilize the operation of the IC internal circuit.

23 VREGA / 5 V Regulator Output Pin

Regulator output pin for analog power supply. Place a multilayer ceramic capacitor of about 0.01 µF to 0.1 µF to stabilize the

operation of the IC internal circuit.

24 VREGDAC / IC Internal ADC and DAC 5 V Regulator Output Pin

Regulator output pin for ADC and DAC inside the IC. Place a multilayer ceramic capacitor of about 0.01 µF to 0.1 µF to

stabilize the operation of the IC internal circuit.

25 TEST1 / Test Pin

This pin is used during IC shipping test. When PS = L -> H, 2.8 V is output for about 1 ms, so use to it at OPEN. Take note

that there is a possibility of malfunction if used without OPEN processing.

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Pin Function Description - Continued

26 TEST2 / Test Pin

This pin is for the delivery inspection of IC, and grounded before use.

In addition, using application without grounding may result to a malfunction.

27 NC

This pin is unconnected electrically with IC internal circuit.

28 IC Back Metal

The VQFN040V6060 package has a heat dissipation metal at the back of IC, and it is assumed that this metal will be

heat-treated before use so be sure to connect it to the GND plane on the board with solder and use taking as wide a GND

pattern as possible to secure a sufficient heat dissipation area.

In addition, the back metal is shorted to the back of IC chip, and since it is a GND potential, if it is shorted with a potential

other than GND, it may malfunction or break. Never pass any wiring pattern other than GND at the back of IC.

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Various Circuits for Protection

1 Temperature Protection Circuit (TSD)

This IC has a built-in thermal shutdown circuit as a measure to protect the IC from overheating. If the chip temperature of the

IC exceeds 175 °C (Typ), the motor output will open and L level is output from the FO pin. In addition, it automatically returns

to normal operation when the temperature drops below 150 °C (Typ). However, if, continuously, heat is applied further from

the outside even if the TSD is operating, thermal runaway will occur and result in destruction.

2 Overcurrent Protection Circuit (OCP)

This IC has a built-in overcurrent protection circuit as a countermeasure against damage in the event of a short circuit

between motor outputs, a ceiling fault, or a ground fault. This circuit latches the motor output to the OPEN state when the

specified current flows for 4 µs (Typ), and outputs the L level from the FO pin. It will be restored by turning the power on

again or resetting with the PS pin. The overcurrent protection circuit is a circuit that aims to prevent the IC from being

destroyed by overcurrent in an abnormal state such as a motor output short circuit, and does not aim to protect or guarantee

the set. Therefore, do not design the protection of the set using the function of this circuit. If the power is turned on again or

restored by resetting in an abnormal state after overcurrent protection operation, take note that the overcurrent protection

operation may be repeated in the order of latch -> return -> latch, which may cause heat generation or deterioration of the IC.

If the Inductance value of wiring is large such as when the wiring is long at the time of ceiling fault, ground fault or short

circuit, an overcurrent will flow and the output pin voltage will jump. If it exceeds the absolute maximum rating, it may result in

destruction of the IC. Also, if a current that is greater than or equal to the output current rating and less than or equal to the

OCP detection current flows, the IC may generate heat and the IC may deteriorate beyond Tjmax = 150 °C. Therefore, do

not allow current exceeding the output rating to flow.

3 Malfunction Prevention Function When Low Voltage (UVLO)

This IC has a built-in under voltage lock out function to prevent false operation such as IC output during power supply

under voltage. When the applied voltage to the VCC pin goes under 6 V (Typ), the motor output is set to OPEN.

This switching voltage has a 1 V (Typ) hysteresis to prevent false operation by noise etc. Be aware that this

circuit does not operate during power save mode. Also, the electrical angle is reset when the UVLO circuit operates.

4 Output OFF function When Overvoltage (OVLO)

This IC has a built-in over voltage lock OFF circuit to protect the IC output and the motor during power supply over voltage.

When the applied voltage to the VCC pin goes over 32 V (Typ), the motor output is set to OPEN. This switching voltage has

a 1 V (Typ) hysteresis and a 4 µs (Typ) mask time to prevent false operation by noise etc. Although this over voltage locked

out circuit is built-in, there is a possibility of destruction if the absolute maximum value for power supply voltage is exceeded,

therefore the absolute maximum value should not be exceeded. Be aware that this circuit does not operate during power

save mode.

5 Malfunction Prevention Function When No Power Loading (Ghost Supply Prevention Function)

If a signal (logic input, MTH, VREF) is input when there is no power supplied to this IC, there is a function which

prevents the false operation by voltage supplied via the electrostatic destruction prevention diode from these input

pins to the VCC to this IC or to another IC’s power supply. Therefore, there is no malfunction of the circuit even

when voltage is supplied to these input pins while there is no power supply.

6 Operation in a Strong Magnetic Field

This IC is not intended to operate in a strong electric field. Therefore, when using it in a strong electric field, make sure that

there are no malfunctions.

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PWM Constant Current Control

1 Current Control Operation

When the output transistor is turned on, the output current increases, RNF voltage(voltage that external resistance

attached the RNF pin and output current determined) reaches its voltage to be determined by the VREF pin and IC internal

proper voltage, current detection comparator toggles and it becomes decay mode.

The output transistor turned on again after CR timer reaches decay count time.

This sequence occurs repeatedly that VREF voltage is determined by the VREF pin at pin setting mode.

VREF voltage and decay count time is determined by each registers setting at SPI setting mode.

2 Noise Canceling Function

To avoid false detection of the current detection comparator due to RNF spike noise that occurs when the output is turned

on, minimum ON time t_ONMIN(blank time) is provided to disable current detection from turning ON of output transistor to

minimum ON time. This allows constant current drive without an external filter.

3 CR Timer

In pin setting mode, the CR pin repeats charging and discharging between the V_CRHvoltage and V_CRLvoltage due to the

external capacitor and resistance.

The current detection comparator detection is disabled in a section from the start of charging in V_CRLto V_CRH. This

charging section is the minimum ON time t_ONMIN. Discharge starts after reaching V_CRHand when the output current

reaches the set current value in this discharge section, the current decay mode is entered.

After that, when it is discharged and reaches V_CRL, it returns from current decay mode to output ON mode, and at the

same time it starts charging.

The CR charge time t_ONMINand discharge time t_DISCHARGEare determined using the following equations (Typ) based on

external components capacitor and resistance, and the sum of these two is the chopping cycle t_CHOP

.

′

−푉

푡_{푂ꢃ푀ꢂꢃ}≈ 퐶 × ^{푅 ×푅}

_{푅 +푅}× 푙푛 (_푉^푉

^ꢄꢅ퐿) [s]

ꢄꢅ

′

−푉

ꢄꢅ

ꢄꢅ퐻

Where:

t_ONMINis the Minimum ON Time

C is the External Capacitor

R is the External Resistor

R’ is the CR Pin Internal Impedance 5 kΩ (Typ)

V_CRis the CR Pin internal charge Voltage

V_CRHis the Pin maximum Voltage

V_CRLis the CR Pin minimum Voltage

푅

ꢆ_ꢇ푅= ꢆ × _{푅 +푅}[V]

′

Where:

V is the Internal Regulator Voltage 5 V (Typ)

′

ꢆ_ꢇ푅ꢈ= ꢆ_ꢇ푅ꢉ ꢊꢆ ꢉ 1ꢋ × 푒푥푝ꢊꢉ푡푢/ꢊ퐶 × ^{푅 ×푅}

_{푅 +푅}ꢋ) [V]

ꢇ푅

′

Where:

tu is the Internal proper time 3.32x10-7 s (Typ)

ꢆ_ꢇ푅ꢌ= 0.4 × 푒푥푝 (ꢉ ^{ꢍ푑+ꢇ×푅×훼}) [V]

ꢇ×R

Where:

td is the Internal proper time 1.25x10^-6s (Typ)

α is the Internal proper value 0.0656 (Typ)

푡_{퐷ꢂ푆ꢇꢈ퐴푅퐺퐸}≈ 퐶 × ꢀ × 푙푛 (^푉_푉^ꢄꢅ퐻) [s]

ꢄꢅ퐿

Where:

t_DISCHARGEis the CR Discharge Time

푡_ꢇꢈ푂푃= 푡_{푂ꢃ푀ꢂꢃ}ꢎ 푡_{퐷ꢂ푆ꢇꢈ퐴푅퐺퐸}[s]

Where:

t_CHOPis the Chopping Cycle

In SPI setting mode, it is determined by register setting.

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3 CR Timer - Continued

Spike Noise

Current Set Value

0 mA

Output Current

Current Set Value

RNF Voltage

GND

V_CRH

CR Voltage

V_CRL

Discharge Time

t_DISCHARGE

GND

Chopping Cycle

t_CHOP

Minimum ON Time

t_ONMIN

Figure 4. CR Voltage, RNF Voltage and Output Current Timing Chart

The resistance of the CR pin does not reach the V_CRHvoltage when the resistance value is low so use 10 kΩ or more (10

kΩ to 200 kΩ is recommended). Regarding capacity, if a capacitor of several thousand pF or more is used, the minimum

ON time t_ONMINbecomes longer, and depending on the inductance and resistance values of the motor coil, output current

may flow more than the current set value (470 pF to 1500 pF is recommended).

Furthermore, if the chopping cycle t_CHOPis set too long, the ripple of output current becomes large which may reduce the

average current and reduce the rotation efficiency so be careful. Select the optimal value to minimize motor drive noise,

output current waveform distortion, etc. The CR pin is not used in SPI setting mode. Both t_ONMINand t_DISCHARGEcan be

decided in the register setting.

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PWM Constant Current Control - Continued

4 Current Decay Mode

In PWM constant current drive, the current decay mode (FAST DECAY / SLOW DECAY) can be optionally set. The following

diagrams show the route of state of output transistor and the motor regenerative current path during current decay for each

decay mode.

FAST DECAY

SLOW DECAY

OFF→OFF

ON→ON

OFF→ON

ON→OFF

OFF→ON

ON→OFF

OFF→ON

M

Output ON

Current Decay

Figure 5. Regenerative Current Path During Current Decay

When in pin setting mode, set by the MTH pin voltage, and when in SPI setting mode, set by register setting.

MTH Pin Input Voltage [V]

0 to 0.3

Current Decay Mode

SLOW DECAY

MIX DECAY

0.4 to 1.0

1.5 to 3.5

FAST DECAY

The current decay setting in SPI setting mode is set in the register setting. Don’t use missing setting in above table.

The features of each decay mode are as follows.

4.1 SLOW DECAY

The voltage applied between the motor coils during current decay is small, and the regenerative current gradually

decreases so the current ripple is small, which is advantageous for motor torque. However, the output current increases.

due to fall-off of current control characteristics in the low-current region, or due to reverse EMF of the output motors

exhibited in half-step, quarter step, 1/8 step, 1/16 step and 1/32 step modes when driving at high pulse rate. The current

waveform is distorted because it cannot follow the change in current limit value, and motor vibration increases. Thus,

this decay mode is most suited to full step modes or low pulse rate drive half step, quarter step, 1/8 step, 1/16 step and

1/32 step modes.

4.2 FAST DECAY

The regenerative current decreases sharply so the distortion in current waveform in high pulse rate drive can be

reduced. However, since the ripple in output current increases, the average current decreases;

(1) decrease in motor torque(it can be dealt with by increasing the current limit value, but it is necessary to consider the

output rated current) and (2) dissipation in motor becomes large and heat generation increases. If there is no problem

particularly with (1) and (2), this mode is most suited for half step, quarter step, 1/8 step, 1/16 step, and 1/32 step modes

in high pulse rate drive.

MIX DECAY method / AUTO DECAY method are available as a way to improve the problems that occur in SLOW

DECAY and FAST DECAY.

4.3 MIX DECAY

Switching between SLOW DECAY and FAST DECAY during current decay can improve the current controllability

without increasing the current ripple. Also, depending on the voltage input to the MTH pin, time ratio can be changed for

SLOW DECAY and FAST DECAY and can achieve the optimal control conditions for all motors. During MIX DECAY, the

first half, x % (t₁to t₂), of discharge section in the chopping cycle t_CHOPis SLOW DECAY, and the remaining section (t₂to

t₃) is FAST DECAY. However, if the current set value is not reached during the first half, x % (t₁to t₂), of this discharge

section, SLOW DECAY is not performed and only FAST DECAY is performed. The SPI setting mode is set by register

setting.

4.4 AUTO DECAY

Normally, the SLOW DECAY mode is applied in decay, only when rapid decay requires switching to the FAST

DECAY mode so that current controllability can be improved without increasing the current ripple. FAST DECAY is set

only when the output current reaches the current set value during the minimum ON time. However, the AUTO DECAY

mode can only be used in the SPI setting mode.

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4 Current Decay Mode - Continued

t₁

t₂

t₃

1.0 V

CR Voltage

MTH Voltage

0.4 V

GND

Chopping Cycle

t_CHOP

Current Set Value

Output Current

FAST DECAY

SLOW

DECAY

0 A

Figure 6. CR Voltage and Output Current During MIX DECAY

Current Set Value

Output Current

SLOWꢀ

ꢀFASTꢀ

DECAY

0 A

Minimum ON Time

t_ONMIN

Chopping Cycle

t_CHOP

Figure 7. Output current during AUTO DECAY

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Translator Circuit Operation in CLK-IN Drive System

This IC has a built-in translator circuit that may drive the stepping motor in the CLK-IN drive system. The translator circuit in the

CLK-IN drive system is described as follows.

1 Reset Operation

The translator circuit goes through an initialization process in power ON reset function and the PS pin.

1.1 Initialization Process When Turning the Power ON

1.1.1 When Power ON in PS = L (This is the normal sequence so recommended to use this.)

When power is turned on, the power ON reset function will work inside the IC to initialize it. However, the motor output

will remain in OPEN state as long as PS = L whether ENABLE = H or not. After turning on the power, by setting to PS = L

-> H, the motor output will be in the ACTIVE state, and excitation will be applied at the initial electric angle.

However, take note that when in PS = L -> H, there is a delay of 1 ms (Max) until the motor output returns

to the ACTIVE state from standby state to the normal state.

Reset Cancel

ACTIVE

Delay

PS

CLK

OUT1A

OUT1B

Motor Output OPEN

Motor Output ON

1.1.2 When Power ON in PS = H

After the power ON reset function works inside the IC, the power turns on and the circuit is initialized. If the motor output

is ENABLE = H, it becomes active, and excitation is applied at the initial electric angle.

1.2 Initialization operation during motor operation

When initializing the translator circuit while the motor is operating, input a reset signal to the PS pin.

However, when PS = L -> H, there is a delay of 1 ms (Max) until the motor output returns to the ACTIVE state from the

standby state to the normal state.

2 Control Input Timing

The translator circuit basically operates at the rising edge of CLK signal so observe the input timing as shown below. Take

note that the translator circuit may behave unexpectedly if the input is set in violation of this timing. Also, take note that when

in PS = L -> H, there will be a delay of 1 ms (Max) until the motor output returns to the ACTIVE state from the standby state to

the normal state, and even with the CLK input in the delay section, the phase advance operation is not performed.

Similar sections are disabled for SPI transfer as well.

A: PS Minimum Input L Pulse Width 20µs

A: PS Minimum L Pulse width 20 µs

B: PS Rising Edge to CLK Rising Edge Input Maximum Delay Time 1 ms

C: CLK Minimum Cycle 4 µs

D: CLK Minimum Input H Pulse Width 2 µs

E: CLK Minimum Input L Pulse Width 2 µs

F: MODE0_SCLK, MODE1_SI, CWCCW_CSB and ENABLE Setup Time 1 µs

G: MODE0_SCLK, MODE1_SI, CWCCW_CSB and ENABLE Hold Time 1 µs

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Translator Circuit Operation in CLK-IN Drive System - Continued

3 FULL STEP A, CWCCW_CSB = L, ENABLE = H

①

②

③

④

①

OUT1A

PS

100 %

CLK

67 %

33 %

1

2

4

3

OUT1A

OUT1B

OUT2A

OUT2B

OUT2A

OUT2B

OUT1B

100 %

67 %

33 %

4CLK = Electrical Angle 360°

I_OUT(CH1)

-33 %

-67 %

-100 %

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

4 HALF STEP A, CWCCW_CSB = L, ENABLE = H

①

②

③

④

⑤

⑥

⑦

⑧

①

②

OUT1A

8

100 %

PS

67 %

33 %

CLK

1

3

7

5

OUT1A

OUT1B

OUT2A

OUT2B

OUT2A

6

2

4

100 %

67 %

33 %

-33 %

-67 %

-100 %

OUT1B

I_OUT(CH1)

8CLK = Electrical Angle 360°

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

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Translator Circuit Operation in CLK-IN Drive System - Continued

5 HALF STEP B, CWCCW_CSB = L, ENABLE = H

①

②

③

④

⑤

⑥

⑦

⑧

①

②

OUT1A

8

PS

100 %

67 %

CLK

OUT1A

OUT1B

OUT2A

OUT2B

33 %

1

3

7

5

OUT2B

OUT2A

2

6

4

100 %

67 %

33 %

OUT1B

I_OUT(CH1)

8CLK = Electrical Angle 360°

-33 %

-67 %

-100 %

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

6 QUARTER STEP A, CWCCW_CSB = L, ENABLE = H

OUT1A

CLK

100 %

OUT1A

67 %

33 %

15

14

16

13

1

5

OUT1B

OUT2A

OUT2B

12

11

10

2

3

4

OUT2A

OUT2B

9

8

6

7

100 %

67 %

33 %

OUT1B

I_OUT(CH1)

-33 %

-67 %

-100 %

16CLK = Electrical Angle 360°

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

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Translator Circuit Operation in CLK-IN Drive System - Continued

7 HALF STEP C, CWCCW_CSB = L, ENABLE = H

①

②

③

④

⑤

⑥

⑦

⑧

①

②

OUT1A

8

PS

100 %

67 %

CLK

OUT1A

OUT1B

OUT2A

OUT2B

33 %

1

3

7

5

OUT2B

OUT2A

2

6

4

100 %

67 %

33 %

OUT1B

I_OUT(CH1)

-33 %

-67 %

-100 %

8CLK = Electrical Angle

360°

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

8 QUARTER STEP B, CWCCW_CSB = L, ENABLE = H

① ② ③ ④ ⑤ ⑥ ⑦ ⑧ ⑨ ⑩ ⑪ ⑫ ⑬ ⑭ ⑮ ⑯ ① ② ③ ④

OUT1A

100 %

67 %

33 %

PS

15

14

16

CLK

13

1

5

12

11

2

3

OUT1A

OUT1B

OUT2A

OUT2B

OUT2A

OUT2B

4

10

9

6

8

7

OUT1B

100 %

67 %

33 %

16CLK = Electrical

Angle 360°

I_OUT(CH1)

-33 %

-67 %

-100 %

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

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Translator Circuit Operation in CLK-IN Drive System – Continued

9 Step Sequence Table (FULL STEP B, HALF STEP C, QUARTER STEP B, 1/ 8 STEP, 1/ 16 STEP, 1/ 32 STEP)

Initial Excitation Position = Step Angle 45°

FULL

HALF

QUARTE

RSTEP B

1/8

1/16

1/32

CH1

CH2

STEP

STEP B

STEP C

STEP

Current [%]

Angle [°]

1

2

3

1

2

1

2

1

2

100.00

99.88

99.52

98.92

98.08

97.00

95.69

94.15

92.39

90.40

88.19

85.77

83.15

80.32

77.30

74.10

70.71

67.16

63.44

59.57

55.56

51.41

47.14

42.76

38.27

33.69

29.03

24.30

19.51

14.67

9.80

0.00

4.91

0.00

2.81

5.63

3

9.80

4

14.67

19.51

24.30

29.03

33.69

38.27

42.76

47.14

51.41

55.56

59.57

63.44

67.16

70.71

74.10

77.30

80.32

83.15

85.77

88.19

90.40

92.39

94.15

95.69

97.00

98.08

98.92

99.52

99.88

100.00

99.88

99.52

98.92

98.08

97.00

95.69

94.15

92.39

90.40

88.19

85.77

83.15

80.32

77.30

74.10

8.44

3

5

11.25

14.06

16.88

19.69

22.50

25.31

28.13

30.94

33.75

36.56

39.38

42.19

45.00

47.81

50.63

53.44

56.25

59.06

61.88

64.69

67.50

70.31

73.13

75.94

78.75

81.56

84.38

87.19

90.00

92.81

95.63

98.44

101.25

104.06

106.88

109.69

112.50

115.31

118.13

120.94

123.75

126.56

129.38

132.19

6

4

7

8

2

3

4

5

6

3

5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

6

4

7

8

1

5

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

6

7

8

4.91

9

0.00

-4.91

-9.80

-14.67

-19.51

-24.30

-29.03

-33.69

-38.27

-42.76

-47.14

-51.41

-55.56

-59.57

-63.44

-67.16

10

11

12

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9 Step Sequence Table - Continued

FULL

HALF

QUARTE

RSTEP B

EIGHTH

STEP

1/16

1/32

CH1

CH2

STEP

STEP B

STEP C

STEP

Current [%]

Angle [°]

2

4

5

6

7

13

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

68

69

70

71

72

73

74

75

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

-70.71

-74.10

-77.30

-80.32

-83.15

-85.77

-88.19

-90.40

-92.39

-94.15

-95.69

-97.00

-98.08

-98.92

-99.52

-99.88

-100.00

-99.88

-99.52

-98.92

-98.08

-97.00

-95.69

-94.15

-92.39

-90.40

-88.19

-85.77

-83.15

-80.32

-77.30

-74.10

-70.71

-67.16

-63.44

-59.57

-55.56

-51.41

-47.14

-42.76

-38.27

-33.69

-29.03

-24.30

-19.51

-14.67

-9.80

70.71

67.16

63.44

59.57

55.56

51.41

47.14

42.76

38.27

33.69

29.03

24.30

19.51

14.67

9.80

135.00

137.81

140.63

143.44

146.25

149.06

151.88

154.69

157.50

160.31

163.13

165.94

168.75

171.56

174.38

177.19

180.00

182.81

185.63

188.44

191.25

194.06

196.88

199.69

202.50

205.31

208.13

210.94

213.75

216.56

219.38

222.19

225.00

227.81

230.63

233.44

236.25

239.06

241.88

244.69

247.50

250.31

253.13

255.94

258.75

261.56

264.38

267.19

14

15

16

17

18

19

20

21

22

23

24

8

4.91

9

0.00

-4.91

-9.80

-14.67

-19.51

-24.30

-29.03

-33.69

-38.27

-42.76

-47.14

-51.41

-55.56

-59.57

-63.44

-67.16

-70.71

-74.10

-77.30

-80.32

-83.15

-85.77

-88.19

-90.40

-92.39

-94.15

-95.69

-97.00

-98.08

-98.92

-99.52

-99.88

10

11

12

3

-4.91

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9 Step Sequence Table - Continued

FULL

HALF

QUARTE

RSTEP B

EIGHTH

STEP

1/16

1/32

CH1

CH2

STEP

STEP B

STEP C

STEP

Current [%]

Angle [°]

7

13

25

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

97

98

99

0.00

-100.00

-99.88

-99.52

-98.92

-98.08

-97.00

-95.69

-94.15

-92.39

-90.40

-88.19

-85.77

-83.15

-80.32

-77.30

-74.10

-70.71

-67.16

-63.44

-59.57

-55.56

-51.41

-47.14

-42.76

-38.27

-33.69

-29.03

-24.30

-19.51

-14.67

-9.80

270.00

4.91

9.80

272.81

275.63

278.44

281.25

284.06

286.88

289.69

292.50

295.31

298.13

300.94

303.75

306.56

309.38

312.19

315.00

317.81

320.63

323.44

326.25

329.06

331.88

334.69

337.50

340.31

343.13

345.94

348.75

351.56

354.38

357.19

100

101

102

103

104

105

106

107

108

109

110

111

112

113

114

115

116

117

118

119

120

121

122

123

124

125

126

127

128

14.67

19.51

24.30

29.03

33.69

38.27

42.76

47.14

51.41

55.56

59.57

63.44

67.16

70.71

74.10

77.30

80.32

83.15

85.77

88.19

90.40

92.39

94.15

95.69

97.00

98.08

98.92

99.52

99.88

26

27

28

29

30

31

32

14

15

16

4

8

-4.91

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Translator Circuit Operation in CLK-IN Drive System – continued

10 Reset timing chart (QUARTER STEP, CWCCW_CSB = L, ENABLE = H)

Input the PS pin to L to reset the translator circuit while the motor operates. Reset operation will run regardless of other input

signals. At this point, the IC internal circuit will come to a standby mode, and the motor output will be set OPEN.

RESET

①

②

③

④

⑤

⑥

⑦

⑧

⑨

⑩

①

②

③

④

⑤

⑥

⑦

⑧

PS

CLK

OUT1A

OUT1B

OUT2A

OUT2B

100 %

67 %

33 %

I_OUT(CH1)

-33 %

-67 %

-100 %

100 %

67 %

33 %

I_OUT(CH2)

-33 %

-67 %

-100 %

11 Motor rotation direction switching timing chart (FULL STEP A, ENABLE = H)

The switching of the motor rotation direction is reflected at the rising edge of CLK immediately after the CWCCW_CSB signal

changes. However, even if the control on the driver IC side is supported, depending on the operating state of the motor at the

time of switching, the motor may not be able to follow. Motor step-out and missteps may occur, so evaluate the switching

sequence thoroughly.

CW

CCW

①

②

③

②

①

PS

CWCCW_CSB

CLK

OUT1A

OUT1B

OUT2A

OUT2B

100 %

-100 %

100 %

-100 %

I_OUT(CH1)

I_OUT(CH2)

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Translator Circuit Operation in CLK-IN Drive System - Continued

12 ENABLE Switching Timing Chart (FULL STEP A)

ENABLE signal switching is reflected by changes in the ENABLE signal regardless of other input signals. In the ENABLE = L

section, the phase advance operation of the internal translator circuit is stopped because the CLK input is cut off as the

motor output becomes OPEN. Therefore, when returning from ENABLE = L to H, it returns to the state immediately before

entering ENABLE = L. Since the excitation mode is switched even in the ENABLE = L section, when the excitation mode is

switched in the ENABLE = L section, it will return by excitation mode after switching to return from ENABLE = L to H.

Output off & Translator stop

①

②

③

PS

ENABLE

CLK

OUT1A

OUT1B

OUT2A

OUT2B

100 %

I_OUT(CH1)

I_OUT(CH2)

-100 %

100 %

-100 %

Returns to the state before entering ENABLE = L.

13 Motor Excitation Mode Switching

Switching the excitation mode is performed at the same time as the excitation mode setting signal changes regardless of

CLK signal. This product has a built-in function to prevent motor step-out due to torque vector mismatch between transition

excitations when switching the excitation mode. However, even if the control on the driver IC side is supported, the motor

cannot follow depending on the operating state of the motor at the time of switching. Since motor step-out or mis-stepping

may occur, carefully evaluate the excitation mode switching sequence before deciding or setting.

14 Precautions When Doing Both Motor Rotation Direction and Excitation Mode Switching

As shown in the figure below, after reset release (PS = L -> H), section A is defined as the period before the first CLK signal is

input while section B is defined as the period after the first CLK signal is input.

Section A

-> There are no restrictions on switching the motor rotation direction and excitation mode.

Section B

-> While in one CLK cycle or while in the ENABLE = L section, perform one from either motor rotation direction or

excitation mode.

If this constraint is violated, a misstep (one more phase advance) may occur and the motor may step out. Therefore, when

switching both motor rotation direction and excitation mode, be sure to input the reset signal to the PS pin and set it to

the state of section A.

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SPI Interface

This IC is equipped with SPI and can read various settings and IC status.

1 3 Wires 32 Bit SPI Input Method

Setting GAMOD1 = H and GAMOD2 = H will enable the 3 wires 32 bit SPI mode and will make the following pins useable as

SPI input / output.

Pin Name

I/O

I

Description

CWCCW_CSB

Chip select signal

L active

MODE0_SCLK

I

Serial clock

Write: Captures data at the rising edge

Read: Outputs data at falling edge

Serial data entry

Input data is invalid when CWCCW_CSB is H

Serial data output

MODE1_SI

SO

I

O

The upper 8 bits are the register address and the lower 24 bits are the register data.

The register data is read/write in ‘MSB first’ every 8 bits.

When writing

CWCCW_CSB

Address Section

Data Section

D0 D15 D14 D13 D12 D11 D10

A7

A6

A5

A4

A3

A2

A1

A0

D7

D6

D5

D4

D3

D2

D1

D9

D8 D23 D22 D21 D20 D19 D18 D17 D16

MODE1_SI

MODE0_SCLK

Hi-z

SO

When reading

CWCCW_CSB

Address Section

Data Section

XX(Invalid DATA)

A7

A6

A5

A4

A3

A2

A1

A0

MODE1_SI

MODE0_SCLK

Output Data Section

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8 DO23 DO22 DO21 DO20 DO19 DO18 DO17 DO16

Hi-z

SO

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SPI Interface - Continued

2 3 Wires 32 Bit SPI Transmission Cancellation

Hold the CWCCW_CSB pin at L while transmitting 32-bit data. If the CWCCW_CSB pin is set to H during transmission, the

transmission will be cancelled.

When the number of transmission register data bits is 8 bits or more, the data cancellation range differs depending on the

register type (Type1, Type2).

Transmission cancellation (register address)

CWCCW_CSB

Address Section(Invalid)

Data Section(Invalid)

xx

MODE1_SI

MODE0_SCLK

Hi-z

SO

Transmission Register Data Cancellation (less than 8 bits)

CWCCW_CSB

Address Section(Invalid)

Data Section(Invalid)

xx

MODE1_SI

MODE0_SCLK

Hi-z

SO

Transmission Register Data Cancellation (8 Bit or more, Type1)

CWCCW_CSB

Address Section

Data Section(Valid)

Data Section(Invalid)

A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx xx

MODE1_SI

MODE0_SCLK

Hi-z

SO

Transmission Register Data Cancellation (8 Bit or more, Type2)

CWCCW_CSB

Address Section

Data Section(Invalid)

A7

A6

A5

A4

A3

A2

A1

A0

xx

MODE1_SI

MODE0_SCLK

Hi-z

SO

Read Cancellation

CWCCW_CSB

Address Section

Data Section

XX(Invalid DATA)

A7

A6

A5

A4

A3

A2

A1

A0

MODE1_SI

MODE0_SCLK

Output Data Section(Valid)

DO7 DO6 DO5 DO4 DO3 DO2 DO1 DO0 DO15 DO14 DO13

Invalid

Hi-z

SO

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Command Register

1 Command Register Description

This IC has a command register consisting of 8-bit address + 24-bit data.

The write command register is roughly divided into Type 1 and Type 2, and Type1 and Type2 write reflect timings are different.

Write command register

Description

type

Type1

Data is reflected every 8 bits of transmission

Reflected when all 24 bits of transmission are received

Enabled after sending UNLOCK command ^{(Note 9)}

Type2

2 Command List

No.

Command

Hex

Function

Type

R/W

MODE setting, rotation direction,

High-efficiency Drive setting

1

MODESET

01

Type1

R/W

2

3

READSEL

02

03

Read command settings

Read READSEL settings

Type1

W

R

READ_READSEL

-

Read TSD, OCP, OVLO protection

status

4

READ_DIAGNOSTIC

04

-

R

5

6

READ_CURRENT_VREF

READ_MARGIN

STOMGN_PEAKHOLD_CLEAR ^{(Note 9)}

05

06

07

10

Read drive VREF set value

Load state read

-

R

-

7

8

STOMGN peak hold state OFF

Drive VREF setting

Type2

W

VREFSET

R/W

VREF setting for minimum drive

during High-efficiency Drive

9

VREFMINSET

11

Type2

R/W

10

11

12

KESET

MTHSET

12

13

14

Motor constant setting

Current decay mode setting

Chopping time setting

Type2

R/W

CRTIMESET

High-efficiency Drive OFF -> ON

frequency setting

13

MIN_FREQ_ON_SET

15

Type2

R/W

High-efficiency Drive ON -> OFF

frequency setting

14

15

16

MIN_FREQ_OFF_SET

HIEF_SET

16

17

18

Type2

R/W

High-efficiency Drive setting

Internal induced-voltage reading

setting

VBEMFAVESET

High-efficiency Drive gain setting 1

17

18

19

20

21

22

GAIN_SET

GAIN1_SET

GAIN2_SET

RESERVE

19

1A

1B

1C

1D

1E

Type2

R/W

High-efficiency Drive gain setting 2

High-efficiency Drive gain setting 3

Type2

R/W

Type2

R/W

RESERVE

-

OUT2A / OUT2B output current

setting Offset setting

23

VREFOFFSETSET

1F

Type2

R/W

High-efficiency Drive gain setting 5

24

25

26

27

28

GAIN4_SET

GAIN5_SET

20

21

22

23

24

Type2

R/W

High-efficiency Drive gain setting 6

High-efficiency Drive gain setting 7

GAIN6_SET

VBEMFMONSET

STOMGN_PEAKHOLD_SET

Step-out margin read setting

STOMGN peak hold setting

Current reading period setting during

FULL STEP

29

FULLSTEPWINDOWSET

25

Type2

R/W

Current decay ratio upper limit setting

30

31

32

HIEFSELMAX

HIEFSELMIN

UNLOCK

26

27

A0

Type2

Type1

R/W

W

Current decay ratio lower limit setting

Type2 command enabled

(Note 9) STOMGN_PEAKHOLD_CLEAR is a Type2 register, but it is enabled regardless of the UNLOCK command.

Do not use command addresses other than those in this table.

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Command register-continued

3 Command Register Detailed Description

3.1 MODESET

MODESET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

01

-

0

D6

0

D5

0

D3

0

D2

0

D1

0

1

D0

0

D4

0

00

D15-D8

-

00

D23-D16

-

0

00

Motor excitation mode setting

Description

FULL STEP A

HALF STEP A

HALF STEP B

D3

0

1

D2

0

1

0

1

D1

0

1

0

1

0

1

0

1

D0

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

QUARTER STEP A

FULL STEP B

HALF STEP C

QUARTER STEP B

1/8 STEP

1/16 STEP

1/32 STEP

Inhibit

Motor rotation direction setting

D4

Description

Clockwise (CH2 current outputs with a phase delay of 90° with respect to CH1 current.)

0

Counter Clockwise (CH2 current outputs with a phase advancement by 90° with respect to

CH1 current.)

1

Output enable setting

D5

Description

Output enable OFF

0

1

Output enable ON

The output enable setting is valid only in SPI setting mode.

The relationship between the OUT1A/OUT1B/OUT2A/OUT2B pin outputs, the D5 output enable setting, and the

ENABLE pin is as follows.

OUT1A/OUT1B/OUT2A/OUT2B pin output

ENABLE pin logic

D5

0

OPEN (electrical angle retention)

L

H

L

ACTIVE

0

1

H

High-efficiency Drive setting

D6

Description

0

1

High-efficiency Drive OFF

High-efficiency Drive ON

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3 Command Register Detailed Description - Continued

3.2 READSEL

READSEL

Command

D7-D0

Hex

DATA

Initial

-

Remarks

02

-

0

1

D1

D9

0

D0

D8

0

00

D15-D8

-

00

D23-D16

-

00

MODESET Read Setting

D0

Description

0

1

MODESET command operates as a write command

MODESET command operates as a read command

Type 2 Command Read Settings

D1

Description

0

1

Type 2 command (command address 10h to 27h) operates as a write command

Type 2 command (command address 10h to 27h) operates as a read command

READ_MARGIN Read value setting

Description

12bit load state is read

D9

0

D8

0

1

STOMGN output voltage set value is read

Internally induced voltage value is read

Inhibit

1

0

1

3.3 READ_READSEL

READ_READSEL

Command

Hex

DATA

Initial

-

Remarks

03

-

0

1

D7-D0

0

DO1 DO0

DO9 DO8

00

D15-D8

-

00

D23-D16

-

0

00

READSEL D0 Reading

DO0

Description

0

1

READSEL command D0 setting reading. D0 = 0

READSEL command D0 setting reading. D0 = 1

READSEL D1 Reading

DO1

Description

0

1

READSEL command D1 setting reading. D1 = 0

READSEL command D1 setting reading. D1 = 1

READSEL D8 Reading

DO8

Description

0

1

READSEL command D8 setting reading. D8 = 0

READSEL command D8 setting reading. D8 = 1

READSEL D9 Reading

DO9

Description

0

1

READSEL command D9 setting reading. D9 = 0

READSEL command D9 setting reading. D9 = 1

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3 Command Register Detailed Description - Continued

3.4 READ_DIAGNOSTIC

READ_DIAGNOSTIC

Command

D7-D0

Hex

DATA

Initial

-

Remarks

04

-

0

1

0

1

0

DO3 DO2 DO1 DO0

88

D15-D8

-

0

00

D23-D16

-

00

TSD Status Reading

DO0

Description

0

TSD undetected

TSD detected

1

TSD stated is detected, DO0 is 1.

When the TSD state is released after TSD state is detected, the read value holds DO0 = 1 until this command

used.

Notice that SPI read sequence does not complete when read sequence does not exceed D23.

So the read value continue to hold DO0 = 1, TSD state is released also.

OVLO Status Reading

DO1

Description

0

OVLO undetected

OVLO detected

1

When VCC voltage exceeded the detection voltage during OVLO mask time, it will not be detected.

OVLO stated is detected, DO1 is 1.

When the OVLO state is released after OVLO state is detected, the read value holds DO1 = 1 until this command

used.

Notice that SPI read sequence does not complete when read sequence does not exceed D23.

So the read value continue to hold DO1 = 1, OVLO state is released also.

OCP Status Reading

DO2

Description

0

OCP undetected

OCP detected

1

When detection current is exceeded during the OCP mask time, it will not be detected.

OCP stated is detected, DO2 is 1.

Even when the OCP state is released, the state of the IC is output OFF and the read value is detected.

DO2 clear PS = L or power supply OFF.

Initial Status Reading

DO3

Description

0

Second or more Reading

1

Initial read value after Power On

When this Command is used first time after IC power on, DO3 read value is 1.

Second time or more, DO3 read value is 0.

Notice that SPI read sequence does not complete when read sequence does not exceed D23.

So the read value continue to hold DO3 = 1, second or more Reading also.

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3 Command Register Detailed Description - Continued

3.5 READ_CURRENT_VREF

READ_CURRENT_VREF Hex

DATA

Initial

-

Remarks

Command

D7-D0

05

-

0

1

0

1

0

DO1 DO0

00

D15-D8

D23-D16

-

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

DO16

00

-

0

00

Drive VREF Setting Integer-side Reading

Description

DO1

DO0

0

1

0

1

0

1

0

1

2

3

Drive VREF Setting Decimal-side Reading

DO15 DO14 DO13 DO12 DO11 DO10 DO9

Description

0

DO8

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0.00390625

0.0078125

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

1

0

1

0

1

0.98828125

0.9921875

0.99609375

Drive VREF = VREF setting integer-side + VREF setting decimal-side

The decimal-side are values added to each bit as DO15 = 0.5, DO14 = 0.25, DO8 = 0.00390625 and so on.

Example: Read value DO7-DO0 = 01, DO15-DO8 = 5A

VREF setting integer-side = 01 = 1

VREF setting decimal-side = 5A = 0.25 + 0.0625 + 0.03125 + 0.0078125 = 0.3515625

Drive VREF = 1 + 0.3515625= 1.3515625

High-efficiency Drive Status Reading

DO16

Description

0

Normal operating condition

1

High-efficiency Drive state

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3 Command Register Detailed Description - Continued

3.6 READ_MARGIN

READ_MARGIN

Command

D7-D0

Hex

DATA

Initial

-

Remarks

06

-

0

1

0

DO4 DO3 DO2 DO1 DO0

00

D15-D8

-

DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

00

D23-D16

-

0

00

In READ_MARGIN, read value contents changes by READSEL D8 and D9.

3.6.1 D9 = 0 and D8 = 0: 12 Bit Load Status Reading

Description

DO3 DO2 DO1 DO0 DO15 DO14 DO13 DO12 DO11 DO10 DO9 DO8

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

Load Status Heavy

1

0

1

0

1

Load Status Small

DO3-DO0, DO15-DO8 is 12bit of load read value. If the value is large, the load is applied.

DO4 is inhibit.

3.6.2 READSEL D9 = 0 and D8 = 1: STOMGN Output Voltage Set Value Reading

STOMGN Output Voltage Set Value Integer Side

Description

DO2

0

DO1

0

DO0

0

1

0

1

0

2

0

1

3

4

1

0

1

0

1

5

1

0

Inhibit

1

STOMGN output voltage set decimal-side

Description

0

DO15 DO14 DO13 DO12 DO11 DO10 DO9

DO8

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0.00390625

0.0078125

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

1

0

1

0

1

0.98828125

0.9921875

0.99609375

Reading of the STOMGN output voltage set value.

STOMGN output voltage set value = STOMGN output voltage set value integer-side + STOMGN output

voltage set value decimal-side.

The decimal-side are values added to each bit as DO15 = 0.5, DO14 = 0.25, DO8 = 0.00390625 and so on.

DO4 and DO3 are inhibit.

Decimal-side is 8bit. However, circuit accuracy is around 4bit.

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3 Command Register Detailed Description – Continued

3.6.2 READSEL D9 = 1 and D8 = 0: Internal Induced-voltage Value Reading

Internal Induced-voltage Value Integer-side

Description

DO4

DO3

DO2

DO1

DO0

0

:

0

:

0

:

0

1

:

0

1

0

:

0

1

2

:

1

:

0

:

0

:

0

:

0

:

16

1

0

1

30

31

Internal induced-voltage Value decimal-side

DO15 DO14 DO13 DO12 DO11 DO10 DO9

Description

0

DO8

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0.00390625

0.0078125

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

1

0

1

0

1

0.98828125

0.9921875

0.99609375

Reading of the internal induced-voltage value.

Internal induced-voltage value = internal induced-voltage value integer-side + internal induced-voltage value

decimal-side.

The decimal-side are values added to each bit as DO15 = 0.5, DO14 = 0.25, DO8 = 0.00390625 and so on.

Decimal-side is 8bit. However, circuit accuracy is around 4bit.

For the internal induced-voltage, refer to Induced-voltage Reading Circuit (Page 61).

3.7 STOMGN_PEAKHOLD_CLEAR

READ_CURRENT_VREF Hex

DATA

Initial

-

Remarks

Command

D7-D0

07

-

0

1

0

1

0

1

0

00

D15-D8

D23-D16

-

00

-

00

If this command is used when the STOMGN pin is in peak hold status, it will disappear in the peak hold status.

This command does not depend on the value of D23-D0, but the peak hold status is released when a 24-bit data is

transmitted.

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3 Command Register Detailed Description – Continued

3.8 VREFSET

VREFSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

10

-

0

1

0

D1

D9

0

D0

D8

0

01

D15-D8

-

D15 D14 D13 D12 D11 D10

00

D23-D16

-

0

00

Drive VREF Setting Integer-side

Description

D1

0

D0

0

1

2

3

0

1

0

1

0

Drive VREF Setting Decimal-side

Description

0

D15

D14

D13

D12

D11

0

D10

D9

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

0.00390625

0.0078125

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

Drive VREF = VREF setting integer-side + VREF setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

Example: When setting to Drive VREF setting = 1.4

VREF setting integer-side = 1: D7-D0 = 01

VREF setting decimal-side = 0.4^(Note1)≈ 0.3984375 = 0.25 + 0.125 + 0.015625 + 0.0078125: D15-D8 = 66

(Note1) means setting the decimal-side to exactly 0.4 is not possible.

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3 Command Register Detailed Description - Continued

3.9 VREFMINSET

VREFMINSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

11

-

0

1

0

D1

D9

0

1

D0

D8

0

00

D15-D8

-

D15 D14 D13 D12 D11 D10

80

D23-D16

-

0

00

High-efficiency Drive VREF Minimum Value Setting Integer-side

Description

D1

0

D0

0

1

2

3

0

1

0

1

High-efficiency Drive VREF Minimum Value Setting Decimal-side

Description

0

D15

D14

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

0.00390625

0.0078125

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

High-efficiency Drive VREF minimum value = VREF minimum value setting integer-side + VREF minimum value

setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

This register is not used in normal operations. If VREFSET setting is less than the VREFMINSET set value,

the minimum setting for High-efficiency Drive will be 0 regardless of the set value.

Example: When setting to High-efficiency Drive VREF minimum value = 0.2

High-efficiency Drive VREF minimum value setting integer-side = 0: D7-D0 = 00

High-efficiency Drive VREF minimum value setting Integer-side = 0.2^(Note1)≈ 0.19921875

= 0.125 + 0.0625 + 0.0078125 + 0.00390625: D15-D8 = 33

(Note1) means setting the decimal-side to exactly 0.2 is not possible.

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3 Command Register Detailed Description – Continued

3.10 KESET

KESET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

12

-

0

1

0

1

D1

D9

0

D0

D8

0

D7

D6

D5

D4

D3

D2

01

D15-D8

D23-D16

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

40

-

0

00

Motor Integer Setting

Description

D7

0

:

D6

0

:

D5

0

:

D4

0

:

D3

0

:

D2

0

:

D1

0

:

D0

0

:

D23 D22 D21 D20

0

:

0

:

0

1

:

0

1

0

:

0

0.00000095367431640625

0.0000019073486328125

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.99999713897705078125

0.9999980926513671875

0.99999904632568359375

The motor constant is set to 20 bits. There is no integer-side. Use the 20 bits as decimal numbers.

Motor constants are D7 = 0.5, D6 = 0.25 D0 = 0.00390625, D23 = 0.00000762939453125 and

D20 = 0.00000095367431640625 and so on which are values added to each bit.

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3 Command Register Detailed Description - Continued

3.11 MTHSET

MTHSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

13

-

0

1

0

1

D1

D9

0

1

0

D0

D8

D16

00

D15-D8

-

D15 D14 D13 D12 D11 D10

00

D23-D16

-

0

00

MTH Setting Integer-side

Description

D1

0

D0

0

1

2

3

0

1

0

1

MTH Setting Decimal-side

Description

0

D15

D14

D13

D12

D11

0

D10

D9

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

0.00390625

0.0078125

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

MTH setting = MTH setting integer-side + MTH setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

AUTO DECAY mode setting

D16

0

Description

AUTO DECAY OFF

AUTO DECAY ON

1

D0-D15 bit setting are invalid and operate AUTO DECAY during current decay when AUTO DECAY is ON.

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3 Command Register Detailed Description – Continued

3.12 CRTIMESET

CRTIMSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

14

-

0

1

0

1

0

D1

D9

0

D0

D8

0

D5

D4

D3

D2

05

D15-D8

-

D13 D12 D11 D10

20

D23-D16

-

0

00

PWM Constant Current Control Minimum ON Time Setting

Description

inhibit

D5

0

:

D4

0

:

D3

0

:

D2

0

:

D1

0

1

:

D0

0

1

0

:

0.083 μs

0.166 μs

:

0

:

0

:

0

:

1

:

0

:

1

:

0.4166 μs

:

1

0

1

5.166 μs

5.25 μs

PWM Constant Current Control Current Decay Time Setting

Description

inhibit

2 μs

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

4 μs

:

1

:

0

:

0

:

0

:

0

:

64 μs

:

1

0

1

0

1

122 μs

124 μs

126 μs

1

PWM constant current control chopping cycle is determined by minimum ON time + current decay time setting.

When using the SPI mode setting, setting of chopping cycle by the CR pin becomes disabled.

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3 Command Register Detailed Description - Continued

3.13 MIN_FREQ_ON_SET

MIN_FREQ_ON_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

15

-

0

1

0

1

0

D1

D9

0

1

D0

D8

0

D4

D3

D2

00

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22

20

D23-D16

-

0

00

High-efficiency Drive Enabled Frequency Setting (OFF -> ON) Integer-side

Description

inhibit

1 Hz

D4

0

:

D3

0

:

D2

0

:

D1

0

:

D0

0

:

D15 D14 D13 D12 D11 D10

D9

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

2 Hz

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

1

:

0

:

0

:

0

:

0

:

0

:

32 Hz

:

1

0

1

8190 Hz

8191 Hz

High-efficiency Drive Enabled Frequency Setting (OFF -> ON) Decimal-side

D23 D22

Description

0 Hz

0

1

0

1

0

1

0.25 Hz

0.5 Hz

0.75 Hz

High-efficiency Drive enabled frequency setting (OFF -> ON) enables High-efficiency Drive valid (HIEFEN = H for

pin setting mode or MODESET D5 = 1 when using SPI setting), and if input CLK satisfies the following condition

expressions, a High-efficiency Drive is performed.

Input CLK frequency > High-efficiency Drive enabled frequency setting (OFF -> ON) x ratio

Ratio: The magnification rate determined by excitation mode

Ratio

4

Excitation Mode

FULL STEP A

FULL STEP B

HALF STEP A

HALF STEP B

HALF STEP C

QUARTER STEP A

QUARTER STEP B

EIGHTH STEP

1/16 STEP

4

8

16

32

64

128

1/32 STEP

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3 Command Register Detailed Description – Continued

3.14 MIN_FREQ_OFF_SET

MIN_FREQ_OFF_SET Hex

DATA

Initial

-

Remarks

Command

D7-D0

16

-

0

1

0

1

D1

D9

0

D0

D8

0

D4

D3

D2

00

D15-D8

D23-D16

-

D15 D14 D13 D12 D11 D10

D23 D22

10

-

0

00

High-efficiency Drive Disabled Frequency Setting (ON -> OFF) Integer-side

Description

inhibit

1 Hz

D4

0

:

D3

0

:

D2

0

:

D1

0

:

D0

0

:

D15 D14 D13 D12 D11 D10

D9

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

2 Hz

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

1

:

0

:

0

:

0

:

0

:

16 Hz

:

1

0

1

8190 Hz

8191 Hz

High-efficiency Drive Enabled Frequency Setting (ON -> OFF) Decimal Setting

D23 D22

Description

0 Hz

0

1

0

1

0

1

0.25 Hz

0.5 Hz

0.75 Hz

High-efficiency Drive disabled frequency setting (ON -> OFF) enables High-efficiency Drive valid (HIEFEN = H for

pin setting mode or MODESET D5 = 1 when using SPI setting), and if input CLK satisfies the following condition

expressions, the operation will switch from High-efficiency Drive to normal operation.

In addition, this setting must be set a value smaller than MIN_FREQ_ON_SET set value.

Input CLK frequency < High-efficiency Drive disabled frequency setting (ON -> OFF) x ratio

Ratio: The magnification rate determined from excitation mode

Ratio

4

Excitation Mode

FULL STEP A

FULL STEP B

HALF STEP A

HALF STEP B

HALF STEP C

QUARTER STEP A

QUARTER STEP B

EIGHTH STEP

1/16 STEP

4

8

16

32

64

128

1/32 STEP

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3 Command Register Detailed Description - Continued

3.15 HIEF_SET

HIEF_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

17

-

0

1

0

1

D1

D9

0

1

D0

D8

0

D4

D3

D2

05

D15-D8

-

D15 D14 D13 D12 D11 D10

C0

00

D23-D16

-

0

High-efficiency Drive High-efficiency Rate Setting Integer-side

Description

D4

0

D3

0

D2

0

D1

0

D0

0

1

0

1

0

1

0

2

:

1

0

30

31

1

High-efficiency Drive High-efficiency Rate Setting Decimal-side

Description

D15 D14 D13 D12 D11 D10

D9

0

D8

0

:

0

1

:

0

:

0

:

0

:

0

:

0

0.00390625

0.0078125

:

0

1

0

:

1

0.75

1

0.857

High-efficiency rate setting = High-efficiency rate setting integer-side + High-efficiency rate setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

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3 Command Register Detailed Description – Continued

3.16 VBEMFAVESET

VBEMFAVESET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

18

-

0

1

0

D1

D9

0

D0

D8

0

00

D15-D8

-

00

D23-D16

-

00

Measurement Internal Induced-voltage Averaging Setting

Description

D1

0

D0

0

No average

0

1

Twice average

1

0

Four times average

Eight times average

1

Performs the process of averaging on the internal induced-voltage to measure within one OPEN cycle.

For the averaged value, use the value measured just before the output goes from OPEN to ACTIVE.

If the averaging process is enabled and if two times measurements/ four times measurement/ eight times

measurement cannot be made while OPEN process, no average / two times / four times measurements will be used

instead.

No Average: The values measured immediately before the change from OPEN to ACTIVE

Two Times Average: The average of the values measured immediately before the change from OPEN to ACTIVE

and of the one measurement before that.

Four Times Average: The average of the values measured immediately before the change from OPEN to ACTIVE

and of the three measurements before that.

Eight Times Average: The average of the values measured immediately before the change from OPEN to ACTIVE

and of the seven measurements before that.

Measurement Internal Induced-voltage Acquisition Setting

Description

1 phase/2 phase alternately

Only 1 phase

D9

0

D8

0

1

0

Only 2 phases

1

Inhibit

Set the internal induced-voltage to be measured.

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3 Command Register Detailed Description – Continued

3.17 GAIN_SET

GAIN_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

19

-

0

1

0

D1

D9

0

1

0

D3

D2

D0

D8

D16

01

D15-D8

-

D15 D14 D13 D12 D11 D10

F0

00

D23-D16

-

0

High-efficiency Drive, Drive Gain Setting Integer-side

Description

D3

0

D2

0

D1

0

D0

0

1

2

0

1

0

1

0

:

1

0

14

15

1

High-efficiency Drive, Drive Gain Setting Decimal-side

Description

D15

D14

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

0.00390625

0.0078125

:

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

High-efficiency Drive, drive gain setting = High-efficiency Drive, drive gain setting integer-side + High-efficiency

Drive drive gain setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

The drive gain setting during High-efficiency driving is enabled when GAMOD1, GAMOD2 = L, L or GAMOD1,

GAMOD2 = H, H.

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3 Command Register Detailed Description – Continued

3.18 GAIN1_SET

GAIN1_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

1A

0

1

0

1

D1

D9

0

D0

D8

0

-

0

D3

D2

02

D15-D8

D15 D14 D13 D12 D11 D10

F0

00

D23-D16

0

High-efficiency Drive, Drive Gain Setting Integer-side

Description

D3

0

:

D2

0

:

D1

0

1

:

D0

0

1

0

:

0

1

2

:

1

0

1

0

1

0

1

12

13

14

15

High-efficiency Drive, Drive Gain Setting Decimal-side

Description

D15

D14

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

0.00390625

0.0078125

:

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

High-efficiency Drive, drive gain setting = High-efficiency Drive, drive gain setting integer-side + High-efficiency Drive,

drive gain setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

The drive gain setting during High-efficiency driving is enabled when GAMOD1, GAMOD2 = H, L.

3.19 GAIN2_SET

GAIN2_SET

Hex

DATA

Initial

-

Remarks

Command

D7-D0

1B

0

1

0

1

D1

D9

0

1

D0

D8

0

-

0

D3

D2

04

D15-D8

D23-D16

D15 D14 D13 D12 D11 D10

F0

00

0

High-efficiency Drive, Drive Gain Setting Integer-side

Description

D3

0

D2

0

D1

0

D0

0

1

2

0

1

0

1

0

:

1

0

14

15

1

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3 Command Register Detailed Description - Continued

High-efficiency Drive, Drive Gain Setting Decimal-side

Description

D15

D14

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

:

0

:

0

0.00390625

0.0078125

:

0

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

1

High-efficiency Drive, drive gain setting = High-efficiency Drive, drive gain setting integer-side + High-efficiency Drive,

drive gain setting decimal-side.

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D8 = 0.00390625 and so on.

The drive gain setting during High-efficiency driving is enabled when GAMOD1, GAMOD2 = L, H.

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3 Command Register Detailed Description – Continued

3.23 VREFOFFSETSET

VREFOFFSETSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

1F

0

1

0

1

0

1

0

1

-

0

D0

D8

00

D15-D8

D15

D9

00

D23-D16

D23 D22 D21 D20 D19 D18 D17 D16

00

OUT2A / OUT2B Output Current Setting Offset Setting

D0

0

Description

Offset Setting OFF

Offset Setting ON

1

OUT2A / OUT2B Output Current Setting Offset Set Value Integer-side

Description

D9

0

D8

0

1

2

3

0

1

0

1

OUT2A / OUT2B Output Current Setting Offset Set Value Symbol-side

Description

D15

0

1 (offset positive number)

-1 (offset negative number)

1

OUT2A / OUT2B Output Current Setting Offset Set Value Decimal-side

Description

0

D23

D22

D21

D20

D19

D18

D17

D16

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0.00390625

0.0078125

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

1

0

1

0

1

0.98828125

0.9921875

0.99609375

OUT2A / OUT2B output current setting offset setting value

= OUT2A / OUT2B output current setting offset set value symbol-side * (offset integer-side + offset decimal-side)

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D16 = 0.00390625 and so on.

The symbol-side is determined by D15, and is treated as a positive offset when D15 = 0 and a negative offset when

D15 = -1.

Therefore, when OUT2A / OUT2B output current setting is D0 = 1,

it becomes the VREFSET command set value+ OUT2A / OUT2B output current setting offset set value.

In addition, if OUT2A / OUT2B output current setting is less than 0 or if OUT2A / OUT2B output current setting is

greater than 4, it will be clipped to 0 and 4, respectively.

If VREFOFFSETSET was set in pin setting mode, since the set value is added to the voltage value set from the

VREF pin, do not use the offset setting with D0 = 0 (circuit initial value).

If High-efficiency Drive is enabled, set to D0 = 0 and do not use the offset setting.

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3 Command Register Detailed Description - Continued

3.24 GAIN4_SET

GAIN4_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

20

-

0

1

0

D1

D9

0

D0

D8

0

D7

D6

D5

D4

D3

D2

00

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

FF

00

D23-D16

-

0

High-efficiency Drive, Drive Gain Setting Integer-side

D7 D6 D5 D4 D3 D2 D1 D0 D15 D14 D13 D12 D11 D10 D9 D8

Description

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0

1

2

:

1

0

1

65534

65535

High-efficiency Drive, Drive Gain Setting Decimal-side

Description

0

D23

D22

D21

D20

0

:

0

:

0

1

:

0

1

0

:

0.0625

0.125

:

1

0

1

0.875

0.9375

High-efficiency Drive, drive gain setting

= High-efficiency Drive, drive gain setting integer-side + High-efficiency Drive, drive gain setting decimal-side.

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D20 = 0.0625 and so on.

The drive gain setting during High-efficiency Drive for GAIN4_SET is enabled when GAMOD1, GAMOD2 = L, L or

GAMOD1, GAMOD2 = H, H.

3.25 GAIN5_SET

GAIN5_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

21

-

0

1

0

D1

D9

0

1

D0

D8

0

D7

D6

D5

D4

D3

D2

01

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

FF

00

D23-D16

-

0

High-efficiency Drive, drive gain setting = High-efficiency Drive, drive gain setting integer-side + High-efficiency

Drive

drive gain setting decimal-side.

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D20 = 0.0625 and so on.

The drive gain setting during High-efficiency Drive for GAIN5_SET is enabled when GAMOD1, GAMOD2 = H, L.

3.26 GAIN6_SET

GAIN6_SET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

22

-

0

1

0

1

D1

D9

0

D0

D8

0

D7

D6

D5

D4

D3

D2

02

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

FF

00

D23-D16

-

0

High-efficiency Drive, drive gain setting

= High-efficiency Drive, drive gain setting integer-side + High-efficiency Drive drive gain setting decimal-side.

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D20 = 0.0625 and so on.

The drive gain setting during High-efficiency Drive for GAIN6_SET is enabled when GAMOD1, GAMOD2 = L, H.

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3 Command Register Detailed Description – Continued

3.27 VBEMFMONSET

VBEMFMONSET

Command

D7-D0

Hex

DATA

Initial

-

Remarks

23

-

0

D6

0

1

0

1

D5

D4

D3

D2

D1

D9

D0

D8

00

D15-D8

-

D15

D13 D12 D11 D10

00

D23-D16

-

D23 D22 D21 D20 D19 D18 D17 D16

00

STOMGN Output Pin Constant Factor

Description

x1

D3

0

D2

0

D1

0

D0

0

1

x2

0

1

0

x4

0

1

x8

0

1

0

x16

0

1

0

1

x32

0

1

0

x1/2

x1/4

x1/8

x1/16

x1/32

Inhibit

0

1

0

1

0

1

0

1

0

others

The above constant factor is applied to the internal induced-voltage.

If adding a moving average or offset, multiply the values by a constant after each process.

STOMGN Output Pin Moving Average

Description

No moving average

D6

0

D5

0

D4

0

1

(a_n+ a_n-1)/2

0

1

0

(a_n+ a_n-1+ a_n-2+ a_n-3)/4

(2*a_n+ a_n-1+ a_n-2)/4

0

1

0

(a_n+ a_n-1+ a_n-2+ a_n-3+ a_n-4+ a_n-5+ a_n-6+ a_n-7)/8

(a_n+ a_n-1+ a_n-2+ … + a_n-14+ a_n-15)/16

inhibit

1

0

1

0

1

inhibit

a_n= the last measured internal induced-voltage. a_n-1= the previous internal induced-voltage.

a_n-15= the 15th previous internal induced-voltage.

Follow the settings in D6 to D4 to obtain a moving average using a_nto a_n-15

.

The initial values of a_nto a_n-15are 0, respectively.

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3 Command Register Detailed Description – Continued

STOMGN Output Pin Offset Integer-side

Description

D13

D12

D11

0

D10

D9

0

1

:

D8

0

1

0

:

0

:

0

:

0

:

0

1

0

2

:

1

0

1

0

1

61

62

63

1

STOMGN Output Pin Offset Symbol-side

Description

D15

0

1(Offset positive number)

-1(Offset negative number)

1

STOMGN Output Pin Offset decimal-side

Description

D23

D22

D21

D20

D19

D18

D17

D16

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0

0.00390625

0.0078125

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

STOMGN output pin offset = STOMGN output pin offset symbol-side * (offset integer-side + offset decimal-side)

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D16 = 0.00390625 and so on.

The symbol-side is determined by D15, and is treated as a positive offset when D15 = 0 and a negative offset when

D15 = -1.

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3 Command Register Detailed Description - Continued

3.28 STOMGN_PEAKHOLD_SET

STOMGN_PEAKHOLD

Hex

DATA

Initial

Remarks

_SET

Command

D7-D0

24

-

0

D7

0

D6

0

1

D5

0

D3

0

1

0

-

D4

D2

D1

D9

D0

D8

00

D15-D8

D23-D16

-

D12

D10

-

D23 D22 D21 D20 D19 D18 D17 D16

STOMGN PEAKHOLD Setting Constant

Description

D7

0

D6

0

D5

0

D4

0

D3

0

D2

0

D1

0

D0

0

PEAKHOLD Unnecessary

0

1

1 time

2 times

:

0

1

0

:

1

0

254 times

255 times

1

If D23-D8 (STOMGN PEAKHOLD threshold) is smaller continuously in the frequency set for D7-D0, with respect to

internal STOMGN calculated value, the STOMGN output is not the internal STOMGN calculated value but instead, the

minimum value of internal STOMGN calculated value detected during continuous PEAKHOLD OFF is output.

If D7-D0 = 00 is set, PEAKHOLD will not be used.

STOMGN PEAKHOLD Threshold Integer-side

Description

D10

0

D9

0

D8

0

1

2

0

1

0

1

3

1

0

4

1

0

1

inhibit

1

0

1

STOMGN PEAKHOLD Threshold Decimal-side

Description

D23

D22

D21

D20

D19

D18

D17

D16

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0

0.00390625

0.0078125

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0.5

:

1

0

1

0

1

0.98828125

0.9921875

0.99609375

STOMGN PEAKHOLD Threshold = (Integer-side + Decimal-side)

The decimal-side are values added to each bit as D23 = 0.5, D22 = 0.25, D16 = 0.00390625 and so on.

If set to STOMGN PEAKHOLD threshold >= 5, PEAKHOLD will not be used.

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3 Command Register Detailed Description – Continued

PEAKHOLD Application Timing Mask When STOMGN PEAKHOLD ENABLE = L -> H

Description

Timing Mask OFF

Timing Mask ON

D12

0

1

Notice When ENABLE = L -> H.

If the STOMGN_PEAKHOLD_SET command was set and using the PEAKHOLD function, under the condition that the

STOMGN output pin moving average setting of the VBEMFMONSET command is also used, it is recommended that the

STOMGN_PEAKHOLD_SET command is set to either [1] or [2] below to prevent PEAKHOLD ON immediately after

ENABLE L -> H.

[1] Turn on the PEAKHOLD timing mask (D12 = 1)

[2] STOMGN PEAKHOLD setting constant greater than STOMGN output pin moving average setting moving

average number (VBEMFMONSET D6 to D4)

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3 Command Register Detailed Description – Continued

3.29 FULLSTEPWINDOWSET

FULLSTEPWINDOWSET Hex

DATA

Initial

-

Remarks

Command

D7-D0

25

-

0

1

0

1

D2

0

D1

D9

0

1

D0

D8

0

D4

0

02

D15-D8

D23-D16

-

00

-

0

00

FULLSTEPWINDOWSET Setting Cycle

Description

D2

0

:

D1

0

1

:

D0

0

1

0

:

Input CLK cycle x 4 x 1/2

Input CLK cycle x 4 x 1/4

Input CLK cycle x 4 x 1/8

:

1

0

1

0

1

Input CLK cycle x 4 x 1/64

Input CLK cycle x 1/128

Input CLK cycle x 1/256

Set the time to OPEN the motor drive when the excitation mode is FULL STEP during High-efficiency Drive.

Measure the input CLK cycle inside the IC and base on that cycle, decide the period to OPEN.

Non-High-efficiency Drive FULL STEP OPEN Setting

Description

‘Without’ OPEN

‘With’ OPEN

D4

0

1

Setting the motor drive to 'with' OPEN when the excitation mode is FULL STEP during non-High-efficiency Drive.

Set when using the STOMGN pin in FULL STEP.

High-efficiency Output OFF Period Setting

Description

1 CLK range

2 CLK range

3 CLK range

5 CLK range

D9

0

D8

0

1

0

1

Set the period to open the output during micro steps of 1/8 STEP or above during High-efficiency driving.

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3 Command Register Detailed Description – Continued

3.30 HIEFSELMAX

HIEFSELMAX

Command

D7-D0

Hex

DATA

Initial

-

Remarks

26

-

0

1

0

1

D1

D9

0

D0

D8

0

D2

00

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

CC

00

D23-D16

-

0

Pin Setting Mode High-efficiency Drive Current Decay Ratio Upper Limit Integer-side

Description

D2

0

D1

0

D0

0

1

2

0

1

0

1

0

:

1

0

6

7

1

Pin Setting Mode High-efficiency Drive Current Decay Ratio Upper Limit Decimal-side

Description

D15

D14

D13

D12

D11

0

D10

D9

0

:

D8

0

:

D23

D22

D21

D20

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0

0.0078125

:

0.5

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

1

0

1

0

1

Pin setting mode High-efficiency Drive current decay ratio upper limit

= pin setting mode High-efficiency Drive current decay ratio upper limit integer-side

+ pin setting mode High-efficiency Drive current decay ratio upper limit decimal-side

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D20 = 0.000244141 and so on.

Pin setting mode High-efficiency Drive current decay ratio upper limit is valid only in pin setting mode. Decide the

current decay ratio during High-efficiency driving in pin setting mode in conjunction with the set value of

HIEFSELMIN command.

On how to decide, refer to HIEFSEL / High-efficiency Drive Setting Pin (Page 12).

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3 Command Register Detailed Description – Continued

3.31 HIEFSELMIN

HIEFSELMIN

Command

D7-D0

Hex

DATA

Initial

-

Remarks

27

-

0

1

0

1

D1

D9

0

1

D0

D8

0

D2

00

D15-D8

-

D15 D14 D13 D12 D11 D10

D23 D22 D21 D20

01

D23-D16

-

0

40

Pin Setting Mode High-efficiency Drive Current Decay Ratio Lower Limit Integer-side

Description

D2

0

D1

0

D0

0

1

2

:

0

1

0

1

0

:

1

0

6

7

1

Pin Setting Mode High-efficiency Drive Current Decay Ratio Lower Limit Decimal-side

Description

D15

D14

D13

D12

D11

0

D10

D9

0

:

D8

0

:

D23

D22

D21

D20

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

1

:

0

1

0

:

0

0.0078125

:

0.5

:

1

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

0

:

1

0

1

0

1

Pin setting mode High-efficiency Drive current decay ratio lower limit

= pin setting mode High-efficiency Drive current decay ratio lower limit integer-side

+ pin setting mode High-efficiency Drive current decay ratio lower limit decimal-side

The decimal-side are values added to each bit as D15 = 0.5, D14 = 0.25, D20 = 0.000244141 and so on.

Pin setting mode High-efficiency Drive current decay ratio lower limit is valid only in pin setting mode.

Decide the current decay ratio during High-efficiency driving in pin setting mode in conjunction with the set value of

HIEFSELMAX command.

On how to decide, refer to HIEFSEL / High-efficiency Drive Setting Pin (Page 12).

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3 Command Register Detailed Description – Continued

3.32 UNLOCK

UNLOCK

Command

D7-D0

Hex

DATA

Initial

-

Remarks

-

A0

0

1

-

D7

D6

D5

D4

D3

D2

D1

D9

D0

D8

55

Password1

Password2

Password3

D15-D8

D15 D14 D13 D12 D11 D10

AA

D23-D16

D23 D22 D21 D20 D19 D18 D17 D16

Setting Password1 = AA, Password2 = 55, Password3 = 55 will enable the Type2 commands (command addresses

10 to 27).

The initial values are Password1 = 55, Password2 = AA and Password3 = AA, and since Type2 command will be

disabled after PS is released, always set the Password1 = AA, Password2 = 55 and Password3 = 55 when using the

Type2 command.

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Induced-voltage Reading Circuit

BD65520MUV measures the voltage of each pin during the period when the output pins OUT1A/OUT1B/OUT2A/OUT2B are

OPEN, and calculate the voltage difference between OUT1A, OUT1B / OUT2A and OUT2B.

The measured value immediately before the change from OPEN to ACTIVE is the internally induced voltage value, and

based on that value, High-efficiency Drive and step-out margin detection circuit operates.

Induced-voltage Measurement Period

(OUT1A,OUT1B OPEN Period)

(OUT2A,OUT2B OPEN Period)

ACTIVE

OUT1A Pin Voltage

OUT1B Pin Voltage

ACTIVE

OUT2A Pin Voltage

OUT2B Pin Voltage

CLK

OUT1A,OUT1B OPEN Control Signal

(Internal Signal)

OUT1A,OUT1B Voltage Mearsument

Control Signal(Internal Signal)

OUT2A,OUT2B OPEN Control Signal

(Internal Signal)

OUT2A,OUT2B Voltage Mearsument

Control Signal(Internal Signal)

1

1.2

1.5

2

2.3

0.1

…

2

0

2

0

OUA1A Voltage Measurement Value

OUA1B Voltage Measurement Value

OUA2A Voltage Measurement Value

OUA2B Voltage Measurement Value

Internal Induced-voltage Value

0.2

0.1

0

1

1.3

1.6

2.2

2.1

0

2.1

0

…

2.2

0.1

0.2

0.1

2.2

2

2.1

It is possible to change the averaging and the measurement pin (OUT1A, OUT1B / OUT2A, OUT2B) to measure by register

setting (VBEMFAVESET).

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High-efficiency Drive

Adjust the internal VREF with the PI controller from the internal induced-voltage value of the induced-voltage reading circuit,

the input cycle of the CLK pin and the excitation mode.

In SPI setting mode, High-efficiency Drive current value can be controlled by KESET register set value and HIEF_SET

register set value. In the pin setting mode, the current value of High-efficiency Drive can be controlled by the HIEFSEL input

voltage.

The P gain constant and I gain constant settings of the PI controller are decided as follows.

P Gain Constant Enabled Register

GAMOD2

GAMOD1

0

GAIN_SET

GAIN1_SET

GAIN2_SET

0

1

0

1

GAIN_SET

I Gain Constant Enabled Register

GAMOD2

GAMOD1

0

1

0

1

0

1

GAIN4_SET

GAIN5_SET

GAIN6_SET

GAIN4_SET

Reference: High-efficiency Drive-side Control Block Diagram

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Step-out Margin Detection

Performs the operation below for the internal induced-voltage value of induced-voltage reading circuit, and outputs from the

STOMGN pin as analog voltage output.

MovingAverage

Processing

Offset

(-64 V to +64 V)

ConstantFactor

(x1/32 to x32)

Internal induced-voltage value

STOMGN Output

PEAKHOLDCircuit

Figure 8. Step-out Margin Detection Block Diagram

Moving average processing, offset and constant factor can be changed by register setting (VBEMFMONSET).

However, adjust the offset and constant factor so that the STOMGN pin output is 0 V < STOMGN < 5 V.

If it is outside the range of 0 V < STOMGN < 5 V, it will be clipped to 0 V and 5 V, respectively.

PEAKHOLD Circuit

If STOMGN_PEAKHOLD_SET is set and the PEAKHOLD function is used, the pre-set threshold voltage below will continue

and the STOMGN pin output the constant voltage regardless of internal induced-voltage.

[Waveform Example: PEAKHOLD Count Setting 3 and Threshold 2.75]

ACTIVE

OPEN

ACTIVE

OPEN

ACTIVE

OUT1APIN

OUT2APIN

ACTIVE

OPEN

ACTIVE

Internal Induced-Voltage Value

3.0

3.1

3.2

2.8

3.5

[1]

2.4

2.3

[2]

1.8

2.8

2

2.4

3

2

STOMGN

Internal PEAKHOLD Count Value

PEAKHOLD Status

3

0

1

2

OFF

ON

PEAKHOLD Set Frequency

PEAKHOLD Set Value

3

2.75

When the motor output pin is open, the induced-voltage is read and that value is used as internal induced voltage to

calculate the STOMGN pin voltage value. Since the internal induced-voltage is less than or equal to the PEAKHOLD set

value in [1], and because it fell below the PEAKHOLD set value three times in a row in [2], the STOMGN pin output will

output a constant voltage regardless of the internal induced-voltage.

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Power Dissipation

Confirm that the IC’s chip temperature Tj is not over 150 °C, while considering the IC’s power consumption (W),

Thermal Resistance (°C/W) and ambient temperature (Ta). When Tj = 150 °C is exceeded the functions as a semiconductor

do not

operate and problems such as parasitism and leaks occur. Constant use under these circumstances leads to deterioration

and eventually destruction of the IC. Tjmax = 150 °C must be strictly obeyed under all circumstances.

1 Heat Calculation

The approximate power consumption of the IC can be calculated from the power supply voltage (VCC), circuit current (I_CC),

output ON resistance (R_ONH, R_ONL) and motor output current value (I_OUT).

Here, the calculation method in FULL STEP drive and SLOW DECAY mode is shown.

푊_푉ꢇꢇ= ꢆ_ꢇꢇ× 퐼_ꢇꢇ

[W]

W_V

V_CC

I_CC

V_CCPower Consumption

Supply Voltage

Circuit Current

：

CC

푊_퐷푀푂푆= 푊_푂ꢃꢎ 푊_{퐷퐸ꢇ퐴푌}[W]

푊_푂ꢃ= ꢀ_푂ꢃꢈꢎ ꢀ_푂ꢃꢌ× 퐼_푂푈푇²× ꢏ × 표푛_ꢐ푢푡푦 [W]

ꢊ

ꢋ

2

ꢊ

ꢋ

ꢊ

ꢋ

푊_{퐷퐸ꢇ퐴푌}= ꢏ × ꢀ_푂ꢃꢌ× 퐼_푂푈푇× ꢏ × 1 ꢉ 표푛_ꢐ푢푡푦

[W]

Where:

W_DMOSis the Output DMOS Power Consumption

W_ONis the Output ON Power Consumption

W_DECAYis the Power consumption during current regeneration

R_ONHis the Top-side Pch DMOS ON Resistance

R_ONLis the Bottom-side Nch DMOS ON Resistance

I_OUTis the Motor Output Current

푡_푂ꢃ

on_duty is the PWM on duty=

“ 2 ” is the H-bridge for 2ch

⁄

푡_ꢇꢈ푂푃

t_ON(Output ON time) differs depending on the inductance and resistance values of the motor coil and the current set value.

Check by actual measurement or calculate by estimation.

t_CHOPis a chopping cycle determined by the constant current control.

Product No.

Top Pch DMOS ON Resistance R_ONH[Ω] (Typ)

0.35

Bottom Nch DMOS ON Resistance R_ONL[Ω] (Typ)

0.20

BD65520MUV

푊_푡표푡푎푙 = 푊_푉ꢇꢇꢎ 푊_퐷푀푂푆[W]

ꢑ푗 = ꢑ푎 ꢎ 휃푗푎 × 푊_푡표푡푎푙 [°C]

Where:

W_total is the IC Entirety Power Consumption

Tj is the Temperature Junction

Ta is the Temperature Ambient

θja is the Thermal Resistance

However, the thermal resistance value θja [°C/W] varies greatly depending on the board conditions. The above are only

theoretically calculated values. In the actual thermal design, not only the theory but also the thermal evaluation of the

application board to be used should be sufficiently performed, and the thermal design should have a sufficient margin so

as not to exceed Tjmax = 150 °C. In addition, although it is basically unnecessary in normal usage, when it is used under

particularly severe thermal conditions, take into account the heat generation of the IC is reduced by connecting a schottky

diode to GND at the motor output pin.

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I/O Equivalent Circuit

PS

CWCCW_CSB

MODE0_SCLK

MODE1_SI

GAMOD2

GAMOD1

HIEFEN

Internal

Circuit

内部回路

ENABLE

CLK

5 kΩ

100 kΩ

VREGA(内部電源)

VREGA (Internal Power Supply)

FO

SO

VREGA (Internal Power Supply)

VREGA(内部電源)

INVREF

STOMGN

Internal

内部回路

Circuit

2.5 kΩ

VREF

VREFMIN

HIEFSEL

MTH

5 kΩ

Internal

内部回路

Circuit

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I/O Equivalent Circuit - Continued

Internal

内部回路

Circuit

VREGA

VREGD

VREGDAC

150 kΩ

45 kΩ

368 kΩ

109 kΩ

155 kΩ

VREGA(内部電源)

VREGA (Internal Power Supply)

5 kΩ

CR

5 kΩ

VCC1,VCC2

OUT1A

OUT2A

OUT1B

OUT2B

RNF1S

RNE2S

5 kΩ

210 kΩ

30 kΩ

210 kΩ

30 kΩ

RNF1

RNF2

Internal

内部回路

Circuit

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Application Example (Pin setting mode)

SPI output pin.

Not use for Pin setting mode.

Recommended Open setting

Refer to Page 12 for detail.

SO

2

3

4

CWCCW_CSB

MODE0_SCLK

MODE1_SI

5

SPI

10 kΩ

Logic input pin

Refer to Page 11 and

Page 12 for detail.

Test Pin

TEST1 : OPEN

TEST2 : GND

GND

13

TEST1

14

Refer to Page 14 and

Page 15 for detail.

Translator

38

40

CLK

15 TEST2

TSD

OCP

ENABLE

OVLO UVLO

Power save pin.

Refer to Page 11 for detail.

39

16

17

HIEFEN

GAMOD2

GAMOD1

PS

1

RESET

3.3 V or 5.0 V

10 kΩ

FO

6

37

Set the High-efficiency drive

setting.

HIEFSEL

Input by resistor division.

Set to GND when not to use High

efficiency Drive.

Protect status output pin.

Pull up 3.3 V or 5 V more

than 5 kΩ.

Refer to Page 12 for detail.

7

8

INVREF

36

35

VREFMIN

VREF

ADC

Set the minimum output current

during High-efficiency drive.

Input by resistor division.

Set to GND when not to use

High efficiency Drive.

Internal VREF output pin.

Refer to Page 14 for detail.

DAC

STOMGN

Refer to Page 14 for detail.

Step out margin output pin.

Refer to Page 14 for detail.

Set the output current.

Input by resistor division.

Refer to Page 13 for detail.

VCC1

32

CR

12

OSC

OUT1A

31

29

M

1000 pF

39 kΩ

0.1 µF

100 µF

OUT1B

RNF1

28

27

RNF1S

0.2 Ω

Set the chopping frequency.

Setting range is

C: 470 pF to 1500 pF

R: 10 kΩ to 200 kΩ

Bypass capacitor.

Setting range is

100 μF to 470 μF

(electrolytic)

0.01 μF to 0.1 μF (multilayer

ceramic etc.)

Refer to Page 14,Page 17 for detail.

Mix decay

control

34

MTH

VCC2

19

Refer to Page 13 for detail.

Be sure to short VCC1 and

VCC2.

OUT2A

M

20

22

Set the current decay mode.

1) SLOW DECAY

=> Connect to GND.

2) MIX DECAY / AUTO DECAY

=> Input by resistor division.

Refer to Page 14, Page 19 for detail.

OUT2B

RNF2

24

25

RNF2S

0.2 Ω

VREGD

GND

VREGD

VREGA

9

26

0.1 µF

VREGA

OUT1A

Resistor for current detection.

Setting range is

0.1 Ω to 0.2 Ω.

10

11

VREGDAC

VREF

CALC

OUT1B

ADC

0.1 µF

VREGDAC

RNF1S

RNF2S

Refer to Page 13 for detail.

0.1 µF

OUT2A

OUT2B

Internal regulator attach capacitor.

C : 0.01 μF to 0.1μF

Refer to Page 14 for detail.

Figure 8. BD65520MUV Application Example (Pin setting mode)

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Application Example (SPI setting mode)

SPI output pin.

Pull-down more than 5 kΩ when this

pin used.

Logic input pin

Refer to Page 11 and

Page 12 for detail.

Refer to Page 12 for detail.

Test Pin

TEST1 : OPEN

TEST2 : GND

SO

2

3

4

CWCCW_CSB

MODE0_SCLK

MODE1_SI

5

SPI

10 kΩ

GND

13

Refer to Page 14 and

Page 15 for detail.

TEST1

14

Translator

38

40

CLK

15 TEST2

TSD

OCP

ENABLE

3.3 V or 5.0 V

OVLO UVLO

HIEFEN

GAMOD2

GAMOD1

Power save pin.

Refer to Page 11 for detail.

39

16

17

PS

1

3.3 V or 5.0 V

RESET

3.3 V or 5.0 V

10 kΩ

FO

6

HIEFSEL

37

Protect status output pin.

Pull up 3.3 V or 5 V more

than 5 kΩ.

Refer to Page 12 for detail.

VREFMIN

VREF

7

8

INVREF

36

35

Internal VREF output pin.

Refer to Page 14 for detail.

ADC

DAC

STOMGN

Step out margin output pin.

Refer to Page 14 for detail.

Not use for SPI setting mode

each pins.

Recommendation for GND.

VCC1

32

CR

0.1 µF

100 µF

12

OSC

OUT1A

31

29

M

OUT1B

RNF1

28

27

RNF1S

0.2 Ω

Bypass capacitor.

Setting range is

100 μF to 470 μF

(electrolytic)

0.01 μF to 0.1 μF (multilayer

ceramic etc.)

Refer to Page 13 for detail.

Be sure to short VCC1 and

VCC2.

Mix decay

control

MTH

34

VCC2

19

OUT2A

M

20

22

OUT2B

RNF2

24

25

RNF2S

0.2 Ω

VREGD

VREGA

GND

VREGD

VREGA

9

26

0.1 µF

OUT1A

10

11

Resistor for current detection.

Setting range is

0.1 Ω to 0.2 Ω.

VREGDAC

VREF

CALC

OUT1B

ADC

0.1 µF

VREGDAC

RNF1S

RNF2S

0.1 µF

OUT2A

OUT2B

Refer to Page 13 for detail.

Internal regulator attach capacitor.

C : 0.01 μF to 0.1 μF

Refer to Page 14 for detail.

Figure 9. BD65520MUV Application Example (SPI setting mode)

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Operational Notes

1. Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power

supply pins.

2. Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3. Ground Voltage

Ensure that no pins are at a voltage below that of the ground pin at any time, even during transient condition.

4. Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5. Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

6. Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power

supply. Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and

routing of connections.

7. Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may

subject the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply

should always be turned off completely before connecting or removing it from the test setup during the inspection

process. To prevent damage from static discharge, ground the IC during assembly and use similar precautions during

transport and storage.

8. Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

9. Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small

charge acquired in this way is enough to produce a significant effect on the conduction through the transistor and

cause unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the

power supply or ground line.

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Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 10. Example of Monolithic IC Structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others.

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from

heat damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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BD65520MUV

Ordering Information

B D 6

5

2

0 M U V

-

E 2

Package

Packing and forming specification

MUV: VQFN040V6060

E2: Reel-type embossed taping

Marking Diagram

VQFN040V6060 (TOP VIEW)

Part Number Marking

BD65520

LOT Number

Pin 1 Mark

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BD65520MUV

Physical Dimension and Packing Information

Package Name

VQFN040V6060

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BD65520MUV

Revision History

Date

Revision

001

Contents of Revision

New Release

14.Oct.2021

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BD65520MUV (开发中)
厂家：	ROHM
描述：	BD65520MUV is a 36V power supply rated, 2.0A output current rated, low-consumption bipolar PWM constant current driven High-efficiency Driver. The input interface adopts the CLK-IN drive system, and the excitation mode supports FULL STEP to 1/32 STEP mode via a built-in DAC. FAST / SLOW DECAY of current decay mode ratio linear variable freely. Pin settings and detailed settings by SPI are set to make an optimum current control possible according to the load of every motor for a High-efficiency Drive. In addition, the power supply may also be driven by a single system, contributing to a simple set design.
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中文：	中文翻译
下载：	下载PDF数据表文档文件

BD65520MUV (开发中) [ROHM]

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