BD8355MWV [ROHM]
Regulators ICs for Digital Cameras and Camcorders System Switching Regulator IC with Built-in FET (10V); 稳压器IC，用于数码相机和摄像机系统开关稳压器IC具有内置FET （ 10V ）
| 型号： | BD8355MWV |
| 厂家： | 
ROHM |
| 描述： | Regulators ICs for Digital Cameras and Camcorders System Switching Regulator IC with Built-in FET (10V) |
| 文件： | 总21页 (文件大小：1174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Regulators ICs for Digital Cameras and Camcorders
System Switching Regulator IC
with Built-in FET (10V)
BD8355MWV
No.11036EAT20
●Description
BD8355MWV is a system switching regulator for Li 2 cell composed of 6 step-down synchronous rectification channels and
1 step-up Di rectification channel for LED application. Using a charge-pump system for high side FET driver and including
power MOSFET reduce the number of peripheral devices and realize high efficiency.
●Functions
1) Includes step-down 6 CH (CH1~6), step-up for LED 1CH (7CH) total 7CH included.
2) Includes Power MOSFET for all channels.
3) Includes Charge-pump circuit for high side driver.
4) Operating frequency of 750 kHz.
5) CH1 and 4 are common, 3 and 5 are also common, and others are possible to turn ON/OFF independently.
6) Includes Short Circuit Protection (SCP), Under Voltage Lock Out (UVLO) and Thermal Shut Down (TSD).
7) Includes Short Circuit Protection for CH6 (SCP6).
8) Includes Over Voltage Protection for CH7.
9) Thermally enhanced UQFN056V7070 package (7mm×7mm, 0.4mm pitch)
●Applications
For digital single-lens reflex camera, digital video camera
●Absolute maximum ratings（Ta＝25℃）
Parameter
Symbol
Ratings
Unit
VCC, VBAT, VHx1~6
VLx1~6
-0.3~11.0
-0.3~VHx
-0.3~28.0
-0.3~15.0
V
V
V
V
VLx7
Power Supply Voltage
HVREG
CTL14, CTL2,
CTL35, CTL6
-0.3~11.0
V
CTL7
IomaxLx1, Lx4, Lx5
IomaxLx2, Lx3
IomaxLx6
-0.3~7.0
±1.5
V
A
±0.8
A
Maximum Current
Power Dissipation
±2.0
A
IomaxLx7
+1.0
A
420 (*1)
930 (*2)
-25~+85
-55~+125
125
mW
mW
℃
℃
℃
Pd
Operating Temperature
Storage Temperature
Junction Temperature
Topr
Tstg
Tjmax
*1 Without external heat sink, power dissipation degrades by 4.2mW/℃ above 25℃.
*2 Power dissipation degrades by 9.3mW/℃ above 25℃, when mounted on a 74.2mm×74.2mm×1.6mmt grass epoxy PCB.
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2011.12 - Rev.A
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Technical Note
BD8355MWV
●Recommended Operating Conditions(Ta=-25~+85℃)
Ratings
Typ.
7.2
Parameter
Symbol
Unit
Min.
4.0
Max.
10.0
2.2
VCC, VBAT, VHx1~6
CVREGA
CVREGD
CHVREG
CFLY
V
μF
μF
μF
μF
kHz
kΩ
Power Supply Voltage
0.47
0.47
0.47
0.047
500
1.0
VREGA Output Capacitor
VREGD Output Capacitor
HVREG Output Capacitor
Flying Capacitor
1.0
2.2
1.0
2.2
0.1
0.22
1800
82
Fosc
750
47
Oscillator Frequency
Timing Resistor
RRT
15
●Electrical Characteristics(Ta=25℃,Vcc=VBAT=7.2V, fosc=750kHz with no designation)
Limits
Parameter
Symbol
Unit
Conditions
Min.
Typ.
Max.
【Reference Voltage】
VREGA Output Voltage
Line Regulation
VREGA
DVli
3.54
3.60
3.66
10
V
VREGA=-1mA
-
-
-
-
mV
mV
VCC=4V~10V, VREGA=-1mA
VREGA=-1mA~-5mA
Load Regulation
DVlo
10
【Bias Voltage】
VREGD Output Voltage
【Charge Pump】
VREGD
3.50
3.60
3.70
V
VREGD=-10mA
VBAT VBAT
+3.50 +3.60
HVREG Output Voltage
HVREG
-
V
Iout=0mA, FB=2.5V
Output Impedance
【Oscillator】
RHVREG
-
24
40
ꢀ
Iout=-30mA, CFLY=0.1µF
Oscillator Frequency
Oscillator Frequency cofficient
【PWM Comparator】
CH7 0% Duty Threshold Voltage
CH7 Max Duty
fosc
Df
650
-
750
0
850
2
kHz
%
RT=47kꢀ
VCC=4V~10V
Vth0
0.2
86
0.3
92
-
V
Dmax
96
%
【Error Amplifier 1】(CH1)
Threshold Voltage
Veth1
VFBL1
VFBH1
Isink1
0.790
-
0.800
0.03
3.5
0.810
0.2
-
V
V
Output Voltage L
INV1=0.9V
Output Voltage H
3.3
4.0
-
V
INV1=0.7V
Output Sink Current
Output Source Current
Input Bias Current
17.0
-140
0
-
mA
µA
nA
INV1=0.9V, FB1=1.75V
INV1=0.7V, FB1=1.75V
INV1=0V
Isource1
Ibias1
-70
100
-100
【Error Amplifier 2】(CH2~6)
Threshold Voltage
Veth
VFBL
VFBH
Isink
0.990
-
1.000
0.03
3.5
1.010
0.2
-
V
V
Output Voltage L
INV=1.1V
Output Voltage H
3.3
4.0
-
V
INV=0.9V
Output Sink Current
Output Source Current
Input Bias Current
17.0
-140
0
-
mA
µA
nA
INV=1.1V, FB=1.75V
INV=0.9V, FB=1.75V
INV=0V
Isource
Ibias
-70
100
-100
【Error Amplifier 3】(CH7)
Threshold Voltage
Veth7
VFBL7
VFBH7
Isink7
0.285
-
0.300
0.03
3.5
0.315
0.2
-
V
V
Output Voltage L
INV=0.4V
Output Voltage H
3.3
4.0
-
V
INV=0.2V
Output Sink Current
Output Source Current
Input Bias Current
17.0
-140
0
-
mA
µA
nA
INV=0.4V, FB=1.75V
INV=0.2V, FB=1.75V
INV7=0V
Isource7
Ibias7
-70
50
-50
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
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Technical Note
BD8355MWV
Limits
Typ.
Parameter
Symbol
Unit
Conditions
Min.
Max.
【Soft Start】
CH1 Soft Start Time
Tss1
1.3
1.5
2.5
3.1
3.7
4.6
msec CH1
msec CH2~6
msec CH7
CH2-6 Soft Start Time
Tss2-6
TDTC7
CH7 Duty Restriction Time
【 Driver】
12.0
15.0
18.0
RLx
300
500
0.27
0.15
0.42
0.30
0.52
0.20
0.20
0.30
0.23
0.22
0.22
0.30
0.50
700
0.44
0.24
0.68
0.48
0.84
0.32
0.32
0.48
0.37
0.36
0.36
0.48
0.80
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
ꢀ
CTL=0V
CH1~6 Lx Pull-down Resistor
CH1 High Side Nch FET On Resistor
CH1 Low Side Nch FET On Resistor
CH2 High Side Nch FET On Resistor
CH2 Low Side Nch FET On Resistor
CH3 High Side Nch FET On Resistor
CH3 Low Side Nch FET On Resistor
CH4 High Side Nch FET On Resistor
CH4 Low Side Nch FET On Resistor
CH5 High Side Nch FET On Resistor
CH5 Low Side Nch FET On Resistor
CH6 High Side Nch FET On Resistor
CH6 Low Side Nch FET On Resistor
CH7 Nch FET On Resistor
【Under Voltage Lock Out(UVLO)】
Threshold Voltage1
RonH1
RonL1
RonH2
RonL2
RonH3
RonL3
RonH4
RonL4
RonH5
RonL5
RonH6
RonL6
Ron7
-
-
-
-
-
-
-
-
-
-
-
-
-
Lx1=-50mA
Lx1=50mA
Lx2=-50mA
Lx2=50mA
Lx3=-50mA
Lx3=50mA
Lx4=-50mA
Lx4=50mA
Lx5=-50mA
Lx5=50mA
Lx6=-50mA
Lx6=50mA
Lx7=50mA
Vthuvlo1
DVuv
3.3
25
-
3.4
100
2.5
3.5
200
2.7
V
mV
V
VCC pin voltage
VCC pin voltage
VREGA pin voltage
VREGD pin voltage
Hysteresis Voltage
Vthuvlo2
Vthuvlo3
Threshold Voltage2
-
3.15
3.35
V
Threshold Voltage3
【Short Circuit Protection(SCP)】
Timer Start Voltage
Vstart
Vstart6
Vscpth
Vscp6th
Iscp
2.65
0.45
0.9
0.9
-1.4
-1.4
-
2.8
0.50
1.0
1.0
-1.0
-1.0
10
2.95
0.55
V
V
FB1~5, 7 pin v oltage
INV6 pin voltage
CH6 Timer Start Voltage
1.1
V
SCP pin Threshold Voltage
SCP6 pin Threshold Voltage
SCP pin Source Current
1.1
V
-0.6
-0.6
100
100
µA
µA
mV
mV
SCP=0.1V
Iscp6
SCP6=0.1V
SCP6 pin Source Current
Vstscp
Vstscp6
CTL=3V, FB=0V
CTL6=3V, INV6=1.0V
SCP pin Stand-by Voltage
-
10
SCP6 pin Stand-by Voltage
【Over Voltage Protection(OVP)】
CH7 OVP Threshold Voltage
【Control】
VOVP7
26.5
28.0
29.5
V
Vo7 pin voltage
VCTLH
VCTLL
VCTLH
VCTLL
RCTL
2
-
-
VCC
0.4
V
V
Active
CTL1-6
Control Voltage
-0.3
2
Non-Active
Active
-
5.5
V
CTL7
Control Voltage
-0.3
0.6
-
0.4
V
Non-Active
1.0
1.4
Mꢀ
CTL pin Pull-Down Resistor
【Whole device】
Istb1
Istb2
Istb3
Icc
-
-
-
-
0
0
5
5
µA
µA
µA
mA
CTL=0V
VCC pin
Hx1~6=10V, sum of Hx1~6
Lx7=28V
Stand-by Current
Circuit Current
Hx pin
0
5
Lx7 pin
6.0
9.0
CTL=3V, FB=2.5V
◎This product is not designed for normal operation within a radioactive environment.
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2011.12 - Rev.A
3/20
Technical Note
BD8355MWV
●Package dimensions
Fig. 1 Package dimension
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2011.12 - Rev.A
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Technical Note
BD8355MWV
●PIN Assignments
Pin No. Pin Name
Pin Descriptions
CH7 Error Amplifier Negative Input Pin
CH6 Error Amplifier Output Pin
CH6 Error Amplifier Negative Input Pin
CH5 Error Amplifier Output Pin
CH5 Error Amplifier Negative Input Pin
Ground Pin
Pin No. Pin Name
Pin Descriptions
CTL35 CH3, 5 ON/OFF Control Pin
CTL14 CH1, 4 ON/OFF Control Pin
1
2
INV7
FB6
29
30
31
32
33
34
35
36
37
38
39
40
3
INV6
FB5
PGND12 Ground Pin for CH1, 2 Output
PGND12 Ground Pin for CH1, 2 Output
4
5
INV5
GND
FB4
Lx2
Hx2
Hx3
Lx3
Pin for Connecting to Inductor of CH2
6
CH2 Highside Transistor and Driver Supply Voltage
CH3 Highside Transistor and Driver Supply Voltage
Pin for Connecting to Inductor of CH3
7
CH4 Error Amplifier Output Pin
CH4 Error Amplifier Negative Input Pin
CH3 Error Amplifier Negative Input Pin
CH3 Error Amplifier Output Pin
CH2 Error Amplifier Negative Input Pin
CH2 Error Amplifier Output Pin
8
INV4
INV3
FB3
9
PGND34 Ground Pin for CH3, 4 Output
PGND34 Ground Pin for CH3, 4 Output
10
11
12
INV2
FB2
Lx4
Lx4
Pin for Connecting to Inductor of CH4
Pin for Connecting to Inductor of CH4
CH6 Short Circuit Protection Delay Time Setting Pin
with External Capacitor
13
SCP6
41
CTL6
CH6 ON/OFF Control Pin
14
15
16
CTL7
INV1
FB1
CH7 ON/OFF Control Pin
42
43
44
CTL2
Hx4
CH2 ON/OFF Control Pin
CH1 Error Amplifier Negative Input Pin
CH1 Error Amplifier Output Pin
CH4 Highside Transistor and Driver Supply Voltage
CH4 Highside Transistor and Driver Supply Voltage
Hx4
CH1-5 and CH7 Short Circuit Protection Delay Time
Setting
17
SCP
45
Hx5
CH5 Highside Transistor and Driver Supply Voltage Pin
18
19
20
21
22
23
24
25
26
27
28
RT
Oscillator Frequency Adjustment Pin with External
46
47
48
49
50
51
52
53
54
55
56
Lx5
Pin for Connecting to Inductor of CH5
VREGA 3.6V Reference Output Voltage Pin
VCC Input Supply Voltage Pin
PGND56 Ground Pin for CH5, 6 Output
PGND56 Ground Pin for CH5, 6 Output
VREGD 3.6V Lowside Transistor Bias Voltage Output Pin
CMINUS Pin for Connecting Chargepump Flying Capacitor
HVREG Chargepump Voltage Output Pin
Lx6
Lx6
Hx6
Hx6
Lx7
Pin for Connecting to Inductor of CH6
Pin for Connecting to Inductor of CH6
CH6 Highside Transistor and Driver Supply Voltage
CH6 Highside Transistor and Driver Supply Voltage
Pin for Connecting to Inductor of CH7
CPLUS Pin for Connecting Chargepump Flying Capacitor
VBAT Chargepump Input Supply Voltage Pin
Hx1
Lx1
Lx1
CH1 Highside Transistor and Driver Supply Voltage
Pin for Connecting to Inductor of CH1
PGND7 Ground Pin for CH7 Output
Vo7
FB7
Voltage Monitor Pin for CH7 Over Voltage Protection
CH7 Error Amplifier Output Pin
Pin for Connecting to Inductor of CH1
●PIN Assignments
Fig. 2 Pin Assignments
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
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Technical Note
BD8355MWV
●Block diagram and application circuit
UNREG
A
FB1
HX1
Lx1
3.3kΩ
16kΩ
33kΩ
HVREG
DRIVER
ERRORAMP1
220pF
4.7uF
4.7uH
330pF
A
－
＋
＋
Vo1=1.15V
CH1
Step Down DC/DC
(Current mode)
INV1
75kΩ
VREGD
DRIVER
Iomax=1.2A
10uF
0.8V
PGND12
HX2
FB2
B
47kΩ
HVREG
DRIVER
56kΩ
20kΩ
ERRORAMP2
4.7uF
1000pF
INV2
B
Vo2=3.8V
－
＋
＋
CH2
Lx2
Iomax=0.6A
VREGD
DRIVER
Step Down DC/DC
(Current mode)
10uH
10uF
1.0V
C
FB3
HX3
Lx3
6.8kΩ
330pF
12kΩ
330pF
43kΩ
HVREG
DRIVER
ERRORAMP3
4.7uF
C
Vo3=1.8V
－
＋
＋
CH3
INV3
FB4
Iomax=0.6A
91kΩ//130kΩ
VREGD
DRIVER
Step Down DC/DC
(Current mode)
10uH
10uF
1.0V
1.0V
1.0V
D
HX4
Lx4
39kΩ
HVREG
DRIVER
36kΩ+36kΩ
20kΩ
ERRORAMP4
4.7uF
D
1000pF
－
＋
＋
Vo4=4.6V
CH4
Step Down DC/DC
(Current mode)
INV4
FB5
Iomax=1.2A
VREGD
DRIVER
10uH
10uF
PGND34
E
HX5
20kΩ
HVREG
DRIVER
33kΩ
15kΩ
ERRORAMP5
4.7uF
1000pF
E
Vo5=3.2V
－
＋
＋
CH5
Step Down DC/DC
(Current mode)
Lx5
10uH
INV5
FB6
Iomax=1.2A
VREGD
DRIVER
10uF
F
HX6
39kΩ
HVREG
DRIVER
4.7uF
F
ERRORAMP6
51kΩ
16kΩ
1000pF
Vo6=4.2V
－
＋
CH6
Step Down DC/DC
(Current mode)
Lx6
10uH
Iomax=1.8A
INV6
FB7
VREGD
DRIVER
10uF
1.0V
PGND56
2.7kΩ
30kΩ
560pF
ERRORAMP7
－
OCP
6800pF
1.0uF
Vo7=WLED
33uH
G
Iomax=50mA
1uF
INV7
＋
VREGD
DRIVER
LX7
CH7
Step Up DC/DC
(Voltage mode)
0.3V
PGND7
Vo7
SS TIMER
PROTECTION
Latch
G
CTL7
＋
－
SCP6
SCP
10Ω
SCP6
TIMER
UVLO
0.047uF
0.047uF
0.5V
HVREG
OVPCOMP
CP_SW
C+
1.0uF
－
－
－
－
－
－
SCP
TIMER
VBAT
CP
DRIVER
＋
VREGD
CP_SW
0.1uF
0.1uF
2.8V
C-
VREGD=3.6V
1.0uF
VREGD
SHUT DOWN
OSC
VREGA=3.6V
1.0uF
VREGA
47kΩ
10uF
Fig. 3 Application circuit
* We are confident that the above applied circuit diagram should be recommended, but please thoroughly confirm its cha-
racteristics when using it. In addition, when using it with the external circuit’s constant changed, please make a decision
that allows a sufficient margin in light of the fluctuations of external components and ROHM’s IC in terms of not only static
characteristic but also transient characteristic.
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Technical Note
BD8355MWV
●Timing chart
Fig. 4 CH1-6 startup sequence
Fig. 5 CH7 startup sequence
Fig. 6 stop sequence
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2011.12 - Rev.A
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Technical Note
BD8355MWV
●Functional Description / peripheral devices setting
1. Internal Regulator (VREGA, VREGD)
Both VREGA and VREGD are internal regulator of 3.6 V output. Bypass VREGA/VREGD to GND with a capacitor be-
tween 0.47 µF and 2.2 µF. In addition, it needs care for the voltage between VREGA and VREGD not to excess 0.3 V
to avoid IC malfunctions.
2. Control block (SHUT DOWN)
Inputting voltages to CTL14, 2, 35, 6, and 7 control ON/OFF of respective channels. Note that it is impossible to inde-
pendently control CH1 and 4, and to independently control CH3 and 5. In addition, turn on any CTL1-6 and wait 500
usec before turning on CTL7. Input higher voltage than 2 V to CTL14, 2, 35, or 6 to turn on each channel. Open or in-
put voltage -0.3 ~ 0.4 V to those to turn off. Input 2 ~ 5.5 V to CTL7 to turn on CH7. Open or input voltage -0.3 ~ 0.4 V
to CTL7 to turn off. The states of output terminals (Lx1-7), FB terminals, SCP/SCP6 terminals, and internal regulator
(VREGA and VREGD) are written below.
Each CTL terminal contains pull down resistor of 1Mꢀ (typ.)
CTL
35
L
L
L
Lx
4
L
A
L
L
FB
4
L
A
L
L
VREGA VREGD
SCP6
SCP
14
L
H
L
L
L
2
L
L
H
L
L
6
L
L
L
L
H
7
L
L
L
L
L
H
H
1
L
A
L
L
L
2
L
L
A
L
L
3
L
L
L
A
L
5
L
L
L
A
L
6
L
L
L
L
A
7
1
L
A
L
L
L
2
L
L
A
L
L
3
L
L
L
A
L
5
L
L
L
A
L
6
L
L
L
L
A
7
L
L
L
L
L
A
A
H-Z
H-Z
H-Z
H-Z
H-Z
A
L
A
A
A
A
A
A
L
A
A
A
A
A
A
L
A
A
A
L
L
L
L
H
L
L
L
L
A
L*
A
L* L* L* L*
L* L* L* L* L* L*
L* L* L* L* L* L*
A
A
H
H
H
H
A
A
A
A
A
A
A
A
A
A
A
A
A
* Turn on any CTL1-6 before turn on CTL7. Conditions of Lx1 ～ 6, FB1 ～ 6, SCP6 are
A: active
changed with active channel.
3. Output voltage/current setting
Fig. 7 Setting of feedback resistance
(a) Setting output voltage of CH1-6
The reference voltages of ERROR AMP. are 0.8 V (CH1) and 1 V (CH2-6). The output voltages are determined as
equation (1) and (2). Set the value of feedback resistance R1 and R2 which are connected to INV1-6 pin.
(b) Setting output current of CH7
The reference voltage of CH7 ERROR AMP. is 0.3 V. The current flowing LED is determined as equation (3). Set
the value of feedback resistance R3, considering the tolerance current of LED.
4. Startup/Stop sequence
To avoid rush current on startup, each channel has soft start function. The output voltage of CH1 reaches to the target
in Tss1=2.5msec (typ.) and the output voltage of CH2 ~ 6 reaches to the target in Tss2-6=3.1msec (typ.). In case of
CH7, the output of error amplifier is restricted in TDTC7=15msec (typ.).
Note that Tss1-6, TDTC7 vary from typical value Ttyp as following with setting of switching frequency.
5. Protection matrix
The following table displays state of outputs when protection is operating.
VREGA VREGD HVREG
FB1-6
A
A
NA
NA
NA
NA
NA
Lx1-5 Lx6 Lx7
FB7
A
A
NA
NA
NA
A
SCP SCP6
Short Circuit Protection (CH1-5,7) H-Z
A
H-Z
H-Z
A
A
A
A
A
A
A
-
A
Short Circuit Protection (CH6)
Under Voltage Lockout (VCC)
A
A
-
H-Z H-Z H-Z
A
-
A
A
A
A
-
A
NA
NA
NA
-
NA
NA
NA
NA
NA
NA
NA
NA
NA
NA
Under Voltage Lockout (VREGA) H-Z H-Z H-Z
Under Voltage Lockout (VREGD) H-Z H-Z H-Z
Under Voltage Lockout (HVREG) H-Z H-Z
A
H-Z H-Z H-Z
NA
NA
NA
NA
Thermal Shutdown （TSD）
A: active
NA: non-active
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
8/20
Technical Note
BD8355MWV
6. Short circuit protection (SCP, SCP6)
For CH1 ~ 5 and 7, monitoring the output voltages of error am-
plifier (FB voltage), if the voltages become more than 2.8 V, the
output of SCPCOMP will become “L” level, and transistor “M1”
will turn off. Thus the current “1µA” be supplied to CSCP the
capacitor connected to SCP terminal. The outputs stop when
SCP terminal voltage reaches 1 V. The time from short circuit
detect to outputs stop (tscp) is set as shown below.
Vo1
FB1
INV1
－
＋
FB1
Vo2
Vo3
Vo4
Vo5
FB2
INV2
－
＋
FB2
FB3
FB4
FB5
FB7
tSCP[s] = 1.0 × CSCP[µF]
On the other hand, short circuit of CH6 is detected when the
error amplifier input of CH6 (INV6) becomes less than 0.5 V.
The time from short circuit detect to output stop (tscp6) is set
with CSCP6 as tscp.
To release from short circuit protection latch state, turn CTL
terminal to “L” level. Connect SCP/SCP6 terminal to GND
when the function of short circuit protection is not used.
FB3
INV3
－
＋
1μA
SCP
－
－
－
－
SCP
C
M1
－
－
＋
FB4
2.8V
INV4
－
＋
7. Over voltage protection(OVP)
In CH7, when LED is open, INV7 become L and output voltage
increase suddenly. If that condition continues Lx7 voltage in-
crease and exceed break down voltage.CH7 has over voltage
protection circuit (OVP) not to exceed break down voltage.
When the voltage of VO7 terminal becomes more than 28V
(typ.), OVP function works and CH7 stops operating. Once
OVP is detected, CH7 becomes latch state. To release from
latch state, turn off CTL7.
FB5
INV5
－
＋
Vo7
FB7
INV7
－
＋
8. Thermal shutdown circuit (TSD)
The TSD circuit protects the IC against thermal runaway and
heat damage. The TSD thermal sensor detects junction tem-
perature. When the temperature reaches the TSD threshold
(typ: 175 ), the circuit switches the outputs of all channels,
VREGA, and VREGD OFF. At the same time, it sets the FB1-7
terminals “L” level. The hysteresis width (typ: 15 ) provided
between the TSD function start temperature (threshold) and
the stop temperature serves to prevent malfunctions from tem-
perature fluctuations.
Fig. 8 Block diagram of short circuit protection circuit.
Vo6
1μA
SCP6
INV6
SCP6
C
＋
ー
－
＋
FB6
M2
SS TIMER
0.5V
9. Under Voltage Lockout (UVLO)
Under voltage lockout prevents IC malfunctions that could oth-
erwise occur due to power supply fluctuation at power ON or
abrupt power OFF. This system turns OFF each channel out-
put when the VCC voltage becomes lower than 3.4 V. The
UVLO detect voltage has 0.1 V hysteresis to prevent malfunc-
tions from power supply fluctuation.
Fig. 9 Block diagram of short circuit protection6 circuit.
In addition, UVLO works when an internal regulator voltage
drops down. The outputs of all channels are turned OFF
when VREGD becomes lower than 3.15 V or VREGA becomes
lower than 2.4 V. Moreover, the outputs of CH1-6 are turned
OFF when HVREG becomes lower than VCC+2.5 V.
The switching frequency
The switching frequency is set by the resistor connected to the
RT terminal. Set the frequency with referring fig. 19.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
9/20
Technical Note
BD8355MWV
10. Selection of output inductor
A combination of the output inductor and the output capacitor form a second-order smoothing filter for switch waveform
and provide DC output voltage. If the inductance is low, its package size is minimized, but the penalty is higher ripple
current, with lower efficiency and an increase of output noise. Conversely, higher inductance increases the package
size, but lowers ripple current, consequently, and suppress the output ripple voltage. Generally, set inductance as that
the ripple current is about 20-50 % of their output current. Below equations are the relations of between inductance
and ripple current.
(VIN[V]‐VOUT[V])
V
OUT[V]
1
(step down)
L[H]ꢀ
L[H]ꢀ
ꢂ
ꢂ
ꢁI
L[A]
V
IN[V]
f
osc [Hz]
(VOUT[V]‐VIN[V])
ꢁI [A]
V
IN[V]
1
(step up)
ꢂ
ꢂ
L
V
OUT[V]
f
osc [Hz]
L: inductance
VOUT: output voltage
fosc: switching frequency
VIN: input voltage
⊿IL: ripple current
IOUT: output load current
In addition, set larger values than Ipeak that is calculated from below equation.
⁄
Ipeak=IOUT ꢃ ꢁIL 2
(step down)
(step up)
⁄
V
ꢅ
INꢆ⁄ꢅ ⁄
⁄
η 100 +ꢁIL 2
ꢆꢇ
ꢄ OUT
I
peak= I
× VOUT
（η: efficiency[%]）
11. Phase Compensation
The components shown will add poles and zeros to the loop gain as given by the following expression:
・CFB adds a pole whose frequency is given by:
Application
(A: error amplifier open loop gain)
VOUT
・RFB adds a zero whose frequency is given by:
COUT
RL
・The output capacitor adds both a pole and a zero to the loop:
VOUT
RFB CFB
R1
ERRORAMP
－
＋
(INV)
(FB)
R2
Fig. 10 Phase compensation setting
Where, RL is output load resistance, and ESR is the equivalent series resistance of the output capacitor. CFB forms a
pole and a zero. Changing the value of CFB moves the frequency of both the pole and the zero. The CFB pole is
typically referred to as the dominant pole, and its primary function is to roll off loop gain and reduce the bandwidth.
The RFB zero is required to add some positive phase shift to offset some of the negative phase shift from the two low-
frequency poles. Without this zero, these two poles would cause -180° of phase shift at the unity-gain crossover,
which is clearly unstable.
12. Precaution in the layout of Printed Circuit Board
When switching regulator is operating, large current flow through the path of Power Supply – Inductor – Output
Capacitor. In laying a pattern of the board, make this line as short and wide as possible to decrease impedance.
The switching noise on INV1-7 terminals may cause the output oscillation. To avoid interference of the noise, make
the line between voltage divider resistor and INV terminals as shortened as possible and not crossed at switching
line.
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
10/20
Technical Note
BD8355MWV
●Reference data
10.00
5.00
4.00
3.00
2.00
1.00
0.00
8.00
6.00
4.00
2.00
0.00
0
2
4
6
8
10
12
0
2
4
6
8
10
12
VCC [V]
VCC [V]
Fig. 11 Circuit current vs supply voltage (all cannels ON)
Fig. 12 VREGA vs supply voltage
3.64
0.84
0.82
0.80
0.78
0.76
3.62
3.60
3.58
3.56
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Ambient Temperature [℃]
Ambient Temperature [℃]
Fig. 13 VREGA vs ambient temperature
Fig. 14 CH1 ErrorAmp. INV threshold vs ambient temperature
1.04
1.02
1.00
0.98
0.96
1.04
1.02
1.00
0.98
0.96
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Ambient Temperature [℃]
Ambient Temperature [℃]
Fig. 15 CH2 ErrorAmp. INV threshold vs ambient temperature
Fig. 16 CH6 ErrorAmp. INV threshold vs ambient temperature
0.34
900
850
800
750
0.32
0.30
0.28
0.26
700
650
600
‐conditions‐
・RT=47kΩ
-40
-20
0
20
40
60
80
100
-40
-20
0
20
40
60
80
100
Ambient Temperature [℃]
Ambient Temperature [℃]
Fig. 18 Frequency vs ambient temperature
Fig. 17 CH7 ErrorAmp. INV threshold vs ambient temperature
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
11/20
Technical Note
BD8355MWV
10000
5.0
4.0
3.0
2.0
1.0
0.0
1000
100
0
1
2
3
4
10
100
CTL [V]
RT [kꢀ]
Fig. 20 CTL terminal characteristic
Fig. 19 Switching frequency vs timing resistance
CTL14
CTL14
Vo1
(0.5V/div)
Vo1
(0.5V/div)
1msec
1msec
Lx1
(5V/div)
Lx1 (5V/div)
Iin (50mA)
Iin
(50mA)
Fig. 21 CH1 startup waveform
Fig. 22 CH1 stop waveform
CTL2
CTL2
Vo2
(2V/div)
Vo2
(2V/div)
1msec
1msec
Lx2
(5V/div)
Lx2 (5V/div)
Iin (50mA)
Iin
(50mA)
Fig. 23 CH2 startup waveform
Fig. 24 CH2 stop waveform
CTL35
CTL35
Vo3
(1V/div)
1msec
Vo3
(1V/div)
1msec
Lx3
(5V/div)
Lx3 (5V/div)
Iin (50mA)
Iin
(50mA)
Fig. 25 CH3 startup waveform
Fig. 26 CH3 stop waveform
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
12/20
Technical Note
BD8355MWV
CTL14
CTL4
Vo4
(2V/div)
Vo4
(2V/div)
1msec
1msec
Lx4
(5V/div)
Lx4(5V/div)
Iin (50mA)
Iin
(50mA)
Fig. 27 CH4 startup waveform
Fig. 28 CH4 stop waveform
CTL35
CTL35
Vo5
(2V/div)
1msec
Vo5
(2V/div)
1msec
Lx5
(5V/div)
Lx5 (5V/div)
Iin (50mA)
Iin
(50mA)
Fig. 29 CH5 startup waveform
Fig. 30 CH5 stop waveform
CTL6
CTL6
Vo6
(2V/div)
Vo6
(2V/div)
1msec
1msec
Lx6
(5V/div)
Lx6 (5V/div)
Iin (100mA)
Iin
(100mA)
Fig. 31 CH6 startup waveform
Fig. 32 CH6 stop waveform
CTL7
CTL7
Vo7 (3V/div)
Offset: 7.2V
2msec
Vo7 (3V/div)
Offset: 7.2V
2msec
Lx7 (8V/div)
Lx7 (8V/div)
Iin (300mA)
Iin (300mA)
Fig. 33 CH7 startup waveform
Fig. 34 CH7 stop waveform
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
13/20
Technical Note
BD8355MWV
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VBAT=4.2V
VBAT=5.0V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
VBAT=4.2V
VBAT=5.0V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
L2: DEM3518C 10uH
(TOKO)
Vo2=3.8V
L1: DEM3518C 4.7uH
(TOKO)
Vo1=1.15V
fosc=750kHz
fosc=750kHz
0
100
200
300
400
500
600
700
800
0
200
400
600
800
1000
1200
1400
Iout [mA]
Iout [mA]
Fig. 36 Efficiency vs load current (CH2)
Fig. 35 Efficiency vs load current (CH1)
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VBAT=4.2V
VBAT=5.5V
L4: DEM3518C 10uH
(TOKO)
Vo4=4.6V
VBAT=5.0V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
L3: DEM3518C 10uH
(TOKO)
Vo3=1.8V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
fosc=750kHz
fosc=750kHz
0
0
0
100
200
300
400
500
600
700
800
1400
70
0
200
400
600
800
1000
1200
1400
Iout [mA]
Iout [mA]
Fig. 37 Efficiency vs load current (CH3)
Fig. 38 Efficiency vs load current (CH4)
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
VBAT=4.2V
VBAT=5.5V
L6: DEM4518C 10uH
(TOKO)
Vo6=4.2V
VBAT=5.0V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
L5: DEM3518C 10uH
(TOKO)
Vo5=3.2V
VBAT=7.2V
VBAT=8.4V
VBAT=10V
fosc=750kHz
fosc=750kHzv
200
400
600
800
1000
1200
0
200
400
600
800 1000 1200 1400 1600 1800 2000
Iout [mA]
Iout [mA]
Fig. 39 Efficiency vs load current (CH5)
Fig. 40 Efficiency vs load current (CH6)
100
95
90
85
80
75
70
65
60
55
50
VBAT=10V
VBAT=8.4V
VBAT=7.2V
VBAT=5.0V
VBAT=4.2V
L7: NR3015T330M 33uH
(TAIYO YUDEN)
LED x 4
fosc=750kHzv
10
20
30
40
50
60
Iout [mA]
Fig. 41 Efficiency vs load current (CH7)
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© 2011 ROHM Co., Ltd. All rights reserved.
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14/20
Technical Note
BD8355MWV
●Power Dissipation Reduction
Fig. 42 Power dissipation vs ambient temperature
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
15/20
Technical Note
BD8355MWV
●PIN equivalent circuit
Pin name
Equivalent circuit
Pin name
Equivalent circuit
VREGA
INV1
INV2
INV3
INV4
INV5
INV6
INV7
FB1
FB2
FB3
FB4
FB5
FB6
INV
GND
CTL14
CTL2
CTL35
CTL6
CTL7
FB7
SCP
SCP6
VCC
VREGA
GND
RT
VREGD
CMINUS
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© 2011 ROHM Co., Ltd. All rights reserved.
2011.12 - Rev.A
16/20
Technical Note
BD8355MWV
Pin name
Equivalent circuit
Pin name
Equivalent circuit
HX1
LX1
HX2
Hx
HVREG
VCC
HVREG
VREGD
LX2
PGND12
HX3
CPLUS
Lx
HVREG
CPLUS
VBAT
LX3
HX4
LX4
PGND34
HX5
LX5
HX6
VBAT
GND
PGND
GND
LX6
PGND56
Lx7
PGND7
Vo7
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2011.12 - Rev.A
17/20
Technical Note
BD8355MWV
●Notes for use
1.) Absolute maximum ratings
This product is produced with strict quality control. However, the IC may be destroyed if operated beyond its absolute
maximum ratings. If the device is destroyed by exceeding the recommended maximum ratings, the failure mode will be
difficult to determine (e.g. short mode, open mode). Therefore, physical protection counter-measures (like fuse) should
be implemented when operating conditions beyond the absolute maximum ratings anticipated.
2.) GND potential
Ensure a minimum GND pin potential in all operating conditions. In addition, ensure that no pins other than the GND
pin carry a voltage lower than or equal to the GND pin, including during actual transient phenomena.
3.) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating condi-
tions.
4.) Inter-pin shorts and mounting errors
Use caution direction and position the IC for mounting on printed circuit boards. Improper mounting may result in dam-
age the IC. In addition, Output-output short and output-power supply/ground short condition may destroy the IC
5.) Operation in a strong electromagnetic field
Exposing the IC within a strong electric/magnetic field may cause malfunction.
6.) Common impedance
Power supply and ground wiring should reflect consideration of the need to lower common impedance and minimize
ripple as much as possible (by making wiring as short and thick as possible or rejecting ripple by incorporating induc-
tance and capacitance).
7.) Voltage of CTL pins
The threshold voltage of CTL pins are 0.4 V and 2.0 V. Standby state is set below 0.4 V while running state is set
beyond 2.0 V. The region between 0.4 V and 2.0 V is not recommended and may cause improper operation.
The rise and fall time must be under 10 msec. In case to put capacitors to CTL pins, it is recommended using under
0.01µF.
The maximum permissible voltage of CTL7 is 5.5 V. CTL7 pin should not be connected to VCC voltage.
Turn on any CTL1-6 and wait more than 500 usec before turn on CTL7.
8.) Thermal shutdown circuit (TSD circuit)
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The TSD circuit is designed only to shut the IC off
to prevent runaway thermal operation. It is not designed to protect the IC or guarantee its operation. Do not continue to
use the IC after operating this circuit or use the IC in an environment where the operation of this circuit is assumed.
9.) Applications with modes that VCC/GND and other pins except Lx and HVREG potential are reversed may cause dam-
age internal IC circuits. In addition, modes that each pins sink current may also cause damage the circuits. Therefore,
It is recommended to insert a diode to prevent back current flow or bypass diodes.
Bypass Di
Counterdurrent
prevention Di
VCC
Output pin
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2011.12 - Rev.A
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Technical Note
BD8355MWV
10.) Rush current at the time of power supply injection.
An IC which has plural power supplies could have momentary rush current at the time of power supply injection. Please
take care about power supply coupling capacity and width of power Supply and GND pattern wiring
11.) Please use it so that VCC and PVCC terminal should not exceed the absolute maximum ratings. Ringing might be
caused by L element of the pattern according to the position of the input capacitor, and ratings be exceeded. Please
will assume the example of the reference ,the distance of IC and capacitor, use it by 5.0mm or less when thickness of
print pattern are 35um, pattern width are 1.0mm.
12.) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to
stress. Always discharge capacitors after each process or step. Ground the IC during assembly steps as an antistatic
measure, and use similar caution when transporting or storing the IC. Always turn the IC’s power supply off before
connecting it to or removing it from a jig or fixture during the inspection process.
13.) Thermal fin.
There is no problem in the operating of IC even if the thermal fin on the back of package doesn’t connect anywhere.
But it is recommended to connect GND on the PCB board for radiation.
14.) IC Terminal Input
This IC is a monolithic IC that has a P- board and P+ isolation for the purpose of keeping distance between elements.
A P-N junction is formed between the P-layer and the N-layer of each element, and various types of parasitic elements
are then formed. For example, an application where a resistor and transistor are connected to a terminal (shown in
Fig.43)
○When GND > (terminal A) at the resistor and GND > (terminal B) at the transistor (NPN), the P-N junction oper-
ates as a parasitic diode
○When GND > (terminal B) at the transistor (NPN), a parasitic NPN transistor operates as a result of the N layers
of other elements in the proximity of the aforementioned parasitic diode.
Parasitic elements are structurally inevitable in the IC due to electric potential relationships. The operation of parasitic
elements induces the interference of circuit operations, causing malfunctions and possibly the destruction of the IC.
Please be careful not to use the IC in a way that would cause parasitic elements to operate. For example, by applying
a voltage that is lower than the GND (P-board) to the input terminal.
(Terminal A)
Resistor
Transistor (NPN)
Ｂ
(Terminal A)
(Terminal A)
Ｅ
Parasitic element
Ｃ
GND
GND
(Terminal B)
Ｎ
＋
Ｐ
＋
Ｐ
＋
P
＋
Ｐ
Ｐ
P
N
Ｎ
Ｎ
Ｎ
Ｎ
Ｎ
P-board
P-board
C
B
E
GND
Parasitic element
GND
Parasitic element
GND
Neighboring element
Parasitic element
Fig. 43 Simple Structure of Bipolar IC (Sample)
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2011.12 - Rev.A
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Technical Note
BD8355MWV
●Ordering part number
B
D
8
3
5
5
M W V
-
E
2
Part No.
Part No.
Package
Packaging and forming specification
E2: Embossed tape and reel
MWV: UQFN056V7070
UQFN056V7070
7.0 0.1
<Tape and Reel information>
Tape
Embossed carrier tape
1500pcs
Quantity
E2
Direction
of feed
The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand
1PIN MARK
4.7 0.1
S
(
)
0.08
C0.2
S
1
14
56
15
28
43
Direction of feed
1pin
42
0.9
29 +0.05
-0.04
0.4
0.2
Reel
Order quantity needs to be multiple of the minimum quantity.
(Unit : mm)
∗
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2011.12 - Rev.A
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Notice
N o t e s
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, commu-
nication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel-
controller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
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R1120
A
相关型号：
BD8372UEFJ-M (新产品)
BD8372HFP-M, BD8372EFJ-M and BD8372UEFJ-M are LED source drivers capable of with standing high input voltage (50V MAX). The constant current output is set by either of two external resistors. It has built-in LED open/short protection, external resistance open/short protection and overvoltage protection that can achieve high reliability. It is possible to control all LEDs together and turn OFF even if LED causes short/open in a certain row when driving two or more LEDs by using multiple ICs.
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