BD85506F_技术文档

Datasheet

Internal FET Abnormality Detection Function

High Efficiency / Low Standby Power

2-Channel Secondary Side Synchronous

Rectification Control IC

BD85506F

General Description

Key Specifications

BD85506F is a 2-channel secondary side Synchronous

Rectification (SR) controller for LLC with enhanced

abnormality detection function on the secondary side.

This IC has a function to detect FET abnormalities such

as body diode rectification operation.

◼ Input Voltage Range:

5.0 V to 32 V

◼ Operating Circuit Current

(SW Stopped Mode):

◼ Standby Circuit Current:

◼ Drain Monitor Pin Absolute Voltage:

800 µA(Typ)

300 µA(Typ)

120 V(Max)

In addition, it incorporates a high-accuracy overvoltage

detection circuit, contributing to improved safety and

reduction of external components.

For efficiency, the OFF threshold voltage of the

synchronous rectifier FET can be adjusted with a resistor.

Moreover, by providing the Source monitor pin of each

FET, it is possible to monitor the voltage between Drain

and Source, and further improvement in efficiency is

possible.

◼ Operating Temperature Range: -40 °C to +105 °C

Package

W(Typ) x D(Typ) x H(Max)

8.70 mm x 6.20 mm x 1.71 mm

SOP14

In the burst operation at light load of the primary side

controller, the synchronous rectification operation is

automatically placed in the standby state, suppressing the

switching power and the circuit current of the IC itself and

reducing standby power consumption.

The built-in multipurpose comparator can also be used as

a low consumption shunt regulator in addition to the

abnormality detection comparator.

The operating power supply voltage ranges from 5.0 V to

32 V, covering various output voltage lineups.

Additionally, by adopting a process with a high withstand

voltage of 120 V(Max), it is possible to directly monitor the

Drain voltage.

Applications

Isolated LLC Type AC/DC Power Supply.

Adapter, TV, Printer, Office Equipment, etc.

Typical Application Circuits

Features

◼ Internal FET Abnormality Detection Function for

Secondary Side Synchronous Rectification.

◼ Internal Overvoltage Detection Circuit (OVP).

(Externally adjustable, high accuracy: 2 %)

◼ Efficiency Improvement by FET OFF Threshold

Voltage is Adjustable.

OUT

◼ Source of each FET can be individually monitored.

◼ Internal Standby Mode Automatic Determination

Function.

GND

◼ Internal Multipurpose Comparator. (It can also be

used as a shunt regulator)

◼ With the Slow Start Function, it is possible to set the

FET Abnormality Detection Function at startup and

the during the start of Switching Operation

◼ Wide Input Voltage Range 5.0 V to 32 V

◼ D1, D2 Pin 120 V (Max) Breakdown Voltage

◼ Flow Compatible SOP14 Package

(Remark) The values in the datasheet are typical unless otherwise specified.

FAIL

〇Product structure : Silicon monolithic integrated circuit 〇This product has no designed protection against radioactive rays.

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BD85506F

Pin Configuration

(TOP VIEW)

14

13

12

11

10

9

1

2

3

4

5

6

7

VCC

REG

D1

S1

SH_IN

SH_OUT

AGND

TH

G1

OVP

G2

S2

8

SS

D2

Pin Configuration

Pin Descriptions

Pin No. Pin Name

Function

1

2

VCC

REG

Power supply input pin

Regulator output pin for driver

Multi-purpose comparator input pin/ENABLE input pin

3

SH_IN

4

SH_OUT Multi-purpose comparator output pin/FAIL output pin when abnormality is detected

5

AGND

TH

Analog GND

6

FET OFF Threshold setting pin

7

SS

Mask time setting pin of drive and FET abnormality detection function at start up.

Channel 2 Drain signal input pin

8

D2

9

S2

Channel 2 Source signal input pin

Channel 2 Gate drive signal output pin

Overvoltage detection setting pin

10

11

12

13

14

G2

OVP

G1

Channel 1 Gate drive signal output pin

Channel 1 Source signal input pin

Channel 1 Drain signal input pin

S1

D1

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BD85506F

Block Diagram

OUT

PC1

GND

PC1:

PC2:

FeedBack Latch Protection

C_SS

PC2

50µA

VCC_UVLO

Block

LDO

Block

SYSTEM ON/OFF

120V

Clamper

120V

Clamper

COMP

ENABLE COMP

-

SS COMP

+

0.4V

0.8V

2ch

Synchronous Rectification

Controller Block

FET

OPEN

COUNTER

FET Abnormal

-

Protection

0.5V

+

Block

D

S

Q

Auto

Standby

Block

OVP COMP

TSD

20k

OFF

Threshold

Block

300k

R_TH

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BD85506F

Description of Blocks

1. SET COMP Block

Monitors D1 and D2 pin voltages and outputs a signal to turn ON the FET by detecting -120 mV or less.

2. RESET COMP Block

Monitors D1 and D2 pin voltages and outputs a signal to turn OFF the FET by detecting a voltage greater than the set

voltage at the TH pin.

3. OFF Threshold Block

Sets the D1 and D2 voltages to turn OFF the FET by setting the TH pin resistance. (D1 and D2 become the same setting)

The ON/OFF sequence of secondary side synchronous rectification is shown below. (Shown in the example below is for

setting the TH pin to 200 kΩ, -6 mV setting)

I_FET1

0A

D1

VOUT

0V

-6mV

-120mV

G1

ON

0V

SET COMP

0V

ON

RESET COMP

0V

ON

G2

ON

0V

D2

VOUT

0V

-6mV

-120mV

-6mV

-120mV

I_FET2

0A

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BD85506F

Description of Blocks – continued

4. Auto Standby Block

By detecting the presence or absence of the D1 and D2 pin pulses, the synchronous rectification operation is automatically

operated or stopped, respectively. If a pulse is not detected on the D1 and D2 pins within 200 µs, the chip enters its standby

state and the synchronous rectification operation is stopped. After a total of 4096 pulses is detected on the D1 and D2 pins,

the chip becomes active and resumes the synchronous rectification action.

D1

D2

200µs

ACTIVE

STATE

STANDBY

4096pulse

G1

G2

5.COMP Block

This is a multipurpose comparator. It can be used as a comparator in various voltage detection applications such as set

temperature monitoring and voltage monitoring. It can also be used as a low-consumption shunt regulator via feedback

operation.

6. ENABLE COMP Block

This comparator is for turning ON or OFF the synchronous rectification. When the SH_IN pin goes below or equal to 0.4 V,

the SS pin capacitor is discharged and the synchronous rectification operation, G pin OPEN detection, and D pin OPEN

detection functions are also stopped.

7. OVP Block

This is the overvoltage detection block for the output voltage. Since the lower 20 kΩ resistor is built-in, the detection voltage

can be adjusted by connecting a resistor between the detection node and the OVP pin. After OVP is detected, a FAIL signal

(constant current sink of 2.5 mA) is output from the SH_OUT pin. When the OVP release voltage is reached or when

VCC_UVLO is detected, the constant current sink from SH_OUT is stopped.

8. LDO Block

This is the IC internal power supply generation block. The driver power supply is output at the REG pin, and stable operation

is obtained by connecting a ceramic capacitor on its output.

9. SS COMP Block

Slow start block that sets the operation start time for startup, synchronous rectification, G pin OPEN detection, and D pin

OPEN detection functions. When VCC UVLO has been cancelled, a constant current of 50µA is output from the SS pin

and its capacitor is charged. When the SS pin voltage reaches at least 0.5V, the following operation takes place:

(a) If the SH_IN pin voltage≥0.4 V then the SS pin capacitor continues charging. Synchronous rectification and G, D pin

OPEN detection functions start operating.

(b) If the SH_IN pin voltage < 0.4 V then the SS pin capacitor discharges. Charging of the SS pin capacitor starts again

after the SH_IN pin voltage≥0.4 V. If the SS pin reaches SS≥0.5V, synchronous rectification and G and D pin OPEN

detection functions start operating.

For more details, refer to "The SS pin discharge function by SH_IN voltage" in "Application Part Selection Method".

10. FET Abnormal Protection Block

This block is for the detection of any of the abnormal FET conditions listed below.

(a) One of the G1 and G2 pins is OPEN and the FET is Body Diode rectified;

(b) One of the D1 and D2 pins is OPEN and the FET is Body Diode rectified;

(c) One of the S1 and S2 pins is set to OPEN, and the OFF timing of the FET is abnormal.

When detecting these conditions, the FAIL signal (constant current sink of 2.5 mA) is output from the SH_OUT pin.

For details of each abnormality detection operation, refer to "Abnormality detection function" of "Application circuit".

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BD85506F

Absolute Maximum Ratings (Ta=25 °C)

Parameter

Symbol

Rating

Unit

V_{MAX_VCC}

V_{MAX_OVP}

V_{MAX_SH_IN}

V_{MAX_SH_OUT}

VCC Pin

-0.3 to +40

-0.3 to +VCC

-0.3 to +15

V

OVP Pin

SH_IN Pin

SH_OUT Pin

V_{MAX_G1}, V_{MAX_G2}

V_{MAX_D1}, V_{MAX_D2}

V_{MAX_REG}

V_SS

G1, G2 Pin

D1, D2 Pin

REG Pin

SS Pin

+120^{(Note 1)}

-0.3 to +15

V

-0.3 to +5.5

+150

V_{MAX_TH}

TH Pin

°C

Tjmax

Maximum Junction Temperature

Storage Temperature Range

-55 to +150

Tstg

Caution 1: Operating the IC over the absolute maximum ratings may damage the IC. The damage can either be a short circuit between pins or an open circuit

between pins and the internal circuitry. Therefore, it is important to consider circuit protection measures, such as adding a fuse, in case the IC is

operated over the absolute maximum ratings.

Caution 2: Should by any chance the maximum junction temperature rating be exceeded the rise in temperature of the chip may result in deterioration of the

properties of the chip. In case of exceeding this absolute maximum rating, design a PCB with thermal resistance taken into consideration by increasing

board size and copper area so as not to exceed the maximum junction temperature rating.

(Note 1) When negative voltage is applied, current flows through the ESD protection element. A current limiting resistor is required for D1 and D2 pins so that the

current through these pins is 6 mA or less.

Thermal Resistance ^{(Note 2)}

Thermal Resistance (Typ)

Parameter

Symbol

Unit

1s^{(Note 4)}

2s2p^{(Note 5)}

SOP14

Junction-to-Ambient

Junction-to-Top Characterization Parameter^{(Note 3)}

θ_JA

166.5

26

108.1

22

°C/W

Ψ_JT

(Note 2) Based on JESD51-2A (still air).

(Note 3) The thermal characterization parameter to report the difference between junction temperature and the temperature at the top center of the outside surface

of the component package.

(Note 4) Using a PCB board based on JESD51-3.

(Note 5) Using a PCB board based on JESD51-7.

Layer Number of

Measurement Board

Material

FR-4

Board Size

Single

114.3 mm x 76.2 mm x 1.57 mmt

Top

Copper Pattern

Thickness

70 μm

Footprints and Traces

Layer Number of

Measurement Board

Material

FR-4

Board Size

114.3 mm x 76.2 mm x 1.6 mmt

2 Internal Layers

4 Layers

Top

Copper Pattern

Bottom

Copper Pattern

74.2 mm x 74.2 mm

Thickness

70 μm

Copper Pattern

Thickness

35 μm

Thickness

70 μm

Footprints and Traces

74.2 mm x 74.2 mm

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BD85506F

Recommended Operating Conditions

Parameter

Symbol

Min

Typ

Max

Unit

Power Supply Voltage Range

Operating Temperature

VCC Capacitor Range^{(Note 6)}

VCC Resistor Range

V_CC

Topr

C_VCC

R_VCC

R_TH

5.0

-40

2.2

20

+25

4.7

32

+105

-

V

°C

µF

Ω

100

12

200

1.0

-

TH Resistor Range

REG Capacitor Range^{(Note 6)}

330

2.2

kΩ

µF

C_REG

0.47

(Note 6) Determine a capacitance value considering the change of capacitance with temperature and the decrease in nominal capacitance due to DC bias and

others

Electrical Characteristics

(Unless otherwise specified V_CC=20 V, V_{SH_IN}=0.6 V, Ta=25 °C)

Parameter

Circuit Current Item

Symbol

Min

Typ

1

Max

2

Unit

mA

Conditions

fsw=50 kHz Switching State

Gx=OPEN

Switching Operation Circuit Current

I_ON

0.5

Standby Circuit Current

I_STB

I_ACT

I_OFF

180

450

120

300

800

180

480

1400

300

μA

Standby State

Switching Stop State

V_CC=3.5 V

Switching Stopped Circuit Current

Circuit Current at VCC UVLO Detection

VCC UVLO BLOCK

VCC UVLO Threshold Voltage 1

VCC UVLO Threshold Voltage 2

Slow Start BLOCK

V_UVLO1

V_UVLO2

4.1

3.9

4.5

4.3

4.9

4.7

V

VCC Sweep Up

VCC Sweep Down

Slow Start Completion Voltage

Slow Start Charge Current

ENABLE Voltage

V_SS

I_SS

0.4

-60

0.5

-50

0.6

-40

V

µA

V

V_SS=0 V→1 V, V_{SH_IN}=0.6 V

V_SS=0.3 V, V_{SH_IN}=0.6 V

V_{SH_IN}=0.3 V→0.5 V

V_EN

0.32

0.40

0.48

Synchronous Rectifier Controller BLOCK

GATE ON Threshold Voltage

V_GON

-180

-10

-120

-6

-60

-1

mV

V_Dx=+300 mV→-600 mV

V_Dx=-600 mV→+300 mV

R_TH=200 kΩ

GATE OFF Threshold Voltage

V_GOFF

Standby State Automatic Detection BLOCK

Standby State Detection Time

t_STB

100

-

200

300

-

µs

D1, D2 Stop Pulse

Number of Waiting State Release

Pulses

P_ACT

4096

Pulse D1, D2 total Pulse Number

DRAIN Monitor BLOCK

D1, D2 Pin Sink Current

I_{D_SINK}

I_{D_SO}

120

-8

270

-5

450

-1

μA

V_Dx=120 V

D1, D2 Pin Source Current

Driver BLOCK

V_Dx=-0.6 V→-0.05 V

REG Pin Output Voltage

REG Pin Maximum Output Current

High Side FET ON Resistance

Low Side FET ON Resistance

G1, G2 Pin Turn On Delay Time

V_REG

I_{MAX_REG}

R_HONR

11

20

0.7

0.5

-

12

-

13

-

V

mA

Ω

Switching Stop State

V_CC=20 V, V_REG=0 V

I_OUT= -10 mA

1.5

0.9

90

100

3.0

1.6

-

R_LONR

Ω

I_OUT= +10 mA

t_{DELAY_ON}

ns

V_Dx=5 V→-0.3 V

V_Dx=-0.3 V→5 V

G1, G2 Pin Turn Off Delay Time

t_{DELAY_OFF}

-

(Gx, Dx, Sx means x = 1 or 2)

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BD85506F

Electrical Characteristics – continued

(Unless otherwise specified V_CC=20 V, V_{SH_IN}=0.6 V, Ta=25 °C)

Parameter

COMP BLOCK

Symbol

Min

Typ

Max

Unit

Conditions

Reference Voltage

V_{SH_REF}

V_SHTEMP

0.792

-

0.8

-8

0.808

-

V

Reference Voltage Temperature

Change

mV

Ta=25 °C→105 °C

Reference Input Current

I_{SH_IN}

I_{SH_OUT}

I_{SH_SINK}

-0.2

5

0

10

-

+0.2

20

-

μA

V_{SH_IN}=2 V

SH_OUT Pin Current at SH_IN=L

SH_OUT Sink Current

V_{SH_OUT}=20 V, V_{SH_IN}=0 V

V_{SH_IN}=0.85 V, V_{SH_OUT}=5.0 V

10

mA

Abnormality Detection BLOCK

R_OVP=820 kΩ

V_CCSweep Up

R_OVP=820 kΩ

V_CCSweep Down

Overvoltage Detection Voltage

Overvoltage Release Voltage

V_{OVP_TH1}

20.58

9

21.0

10

21.42

11

V

V_{OVP_TH2}

V_{GOP_TH}

t_GOP

G Pin OPEN Detection Voltage

G Pin OPEN Detection Timing

-405

2

-325

2.5

-245

3.5

mV

µs

V_Dx=0 mV→-500 mV

G Pin OPEN Count Complete Pulse

Number

D1 and D2 Pin

Number of Pulses

P_GOP

V_{DOP_TH}

P_DOP

-

2048

2.0

-

Pulse

V

D Pin OPEN Detection Voltage

1.7

-

2.3

-

V_Dx=3 V→1 V

D Pin OPEN Count Complete Pulse

Number

Dx Pin Connected

Number of Pulses.

128

300

2.5

Pulse

mV

S Pin OPEN Detection Voltage

V_{SOP_TH}

I_{SH_OUT_PRO}

R_{REG_DIS}

200

1.2

400

4.2

3.2

V_Sx=0 mV→500 mV

V_{SH_OUT}=5 V, V_{SH_IN}=0.6 V

V_REG=1 mA

SH_OUT Sink Current at Abnormality

Mode

mA

REG Pin Discharge Resistance

2.2

kΩ

(Gx, Dx, Sx means x = 1 or 2)

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BD85506F

Typical Performance Curves

(Reference Data)

1.0

500

400

300

200

100

0

150 °C

-25 °C

0.8

0.6

25 °C

-25 °C

25 °C

0.4

0.2

0.0

0

5

10

15

20

25

30

0

5

10

15

20

25

30

Power Supply Voltage V_CC[V]

Figure 1. Switching Stopped Circuit Current vs Power Supply

Voltage

Figure 2. Standby Circuit Current vs Power Supply Voltage

16

14

16

150 °C

14

12

150 °C

-25 °C

10

25 °C

8

-25 °C

25 °C

6

4

2

0

4

2

0

5

10

15

20

25

30

0

5

10

15

20

25

30

SH_OUT Voltage V_{SH_OUT}[V]

Power Supply Voltage V_CC[V]

Figure 3. SH_OUT Pin Current at SH_IN=L vs SH_OUT

Voltage (VCC=SHOUT, V_{SH_IN}=0 V)

Figure 4. REG Pin Output Voltage vs Power Supply Voltage

(V_{SH_IN}=0 V)

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BD85506F

Typical Performance Curves – continued

(Reference Data)

4

2

-40

-42

-44

-46

-48

-50

-52

-54

-56

-58

-60

0

-2

-4

-6

-8

-10

-40 -20

0

20

40

60

80 100

-40 -20

0

20

40

60

80 100

Temperature Ta [°C]

Figure 5. GATE OFF Threshold Voltage vs Temperature

(V_CC=20 V, DRAIN Sweep Up)

Figure 6. Slow Start Charge Current vs Temperature

(V_CC=20 V, V_SS=0.3 V)

0.860

0.850

0.840

0.830

0.820

0.810

0.800

0.790

0.780

0.770

0.760

0.750

0.740

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

1.0

0.5

0.0

-40 -20

0

20 40 60 80 100

-40 -20

0

20

40

60

80 100

Temperature Ta [°C]

Figure 7. Reference Voltage vs Temperature

(V_CC=20 V)

Figure 8. G Pin OPEN Detection Timing vs Temperature

(V_CC=20 V)

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BD85506F

Timing Chart

The startup sequence is shown below.

OUT

PC1

GND

PC1:

FeedBack

BD85506F

Startup Sequence SH_IN<0.4 V at SS≥0.5 V

Startup Sequence SH_IN≥0.4 V at SS≥0.5 V

(3)

(2)

VCC

4.5 V

(6)

(5)

0

(5)

SH_IN≥0.4 V

0.4 V

SH_IN

(7)

SH_IN<0.4 V

0

0.5 V

SS

3

1

3

1

D1

D2

D1

D2

2

4

2

4

12 V

(1)

REG

0

(4)

G1

G2

G1

G2

Gate Open Detection

Drain Open Detection

Gate Open Detection

Drain Open Detection

STOP

ACT

STOP

ACT

(1) Primary side controller starts, pulses input to pins D1,

D2 secondary side.

(1) Primary side controller starts, pulses input to pins D1,

D2 secondary side.

(2) VCC(=VOUT)Voltage is boosted.

(2) VCC(=VOUT)Voltage is boosted

(3) When VCC reaches 4.5 V, VCC_UVLO is released

and SS pin capacitor starts charging.

(3) When VCC reaches 4.5 V, VCC_UVLO is released

and SS pin capacitor starts charging.

(4) After VCC_UVLO is released, Startup REG outputs by

inputting four pulses to D1 and D2.

(4) After VCC_UVLO is released, Startup REG outputs by

inputting four pulses to D1 and D2.

(5) When SS reaches 0.5 V, if SH_IN≥0.4 V, SR control,

Gate Open detection and Drain Open detection

functions start.

(5) When SS reaches 0.5 V, if SH_IN<0.4 V, SS pin

capacitor discharges.

(6) When SH_IN reaches 0.4 V, SS pin capacitor starts

charging again.

(7) After reaching SS≥0.5 V, SR control, Gate Open

detection and Drain Open detection functions start.

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BD85506F

Application Examples

1. Abnormality Detection Function

In secondary side synchronous rectification, if the connection between the IC and the FET becomes OPEN due to mounting

failure or similar conditions wherein the FET cannot be driven, and even if the FET cannot be operated through switching,

the FET can still be rectified by its body diode and output. However, when a heavy load is applied, the power loss increases

in the body diode, causing abnormal heat generation. In order to prevent this abnormal heat generation, the safety of the

circuit can be secured by the FET abnormality detection function built-in this IC.

(Body diode rectification operation is a failure mode which is difficult to detect because both voltage and current are output

normally)

In addition, OVP comparators and multipurpose comparators are also built-in, so it is possible to detect abnormality on the

secondary side.

List of Abnormality Detection Function and Purpose

Abnormality Detection

No.

Detection State

Abnormal Operation

Detection Purpose

Function Name

Prevent abnormal heat

generation of rectifier

FET

G Pin OPEN

Detection

Either G1 or G2 in is disconnected FET body diode rectification

1

from secondary side SR FET

due to stoppage of FET drive

Either of D1 or D2 pin is

disconnected from secondary

side SR FET

Either S1 or S2 pin is

disconnected from secondary

side SR FET

Prevent abnormal heat

generation of rectifier

FET

D Pin OPEN

Detection

FET body diode rectification

due to stoppage of FET drive

2

3

S Pin OPEN

Detection

Reverse FET current due to

off threshold fluctuation

FET destruction

protection

Breakdown voltage

failure protection

-

4

5

OVP Detection

Overvoltage

Abnormal boost up

COMP Detection

multi-purpose

-

Detection method and return method of each abnormality detection function

Abnormality

Mask Condition of

No

.

Detection

Function

Name

Action of after Confirming

Abnormality Detection

Detection Condition

Abnormality

Detection

Reset Condition

*2.5 µs after Gx=ON *SS<0.5 V

G Pin OPEN

Detection

1

2

*Dx voltage

<-0.325 V

*Total D1+D2 =2048

pulse continuously

*SS<0.5 V

*2.5 mA sink from SH_OUT VCC_UVLO detection

*2.5 mA sink from SH_OUT

D Pin OPEN

Detection

*Continuous

detection while

Dx=128 pulse

*Driver stop

Dx<2.0 V

Sx>0.3 V

VCC_UVLO detection

*SS discharge

*REG discharge

*2.5 mA sink from SH_OUT

S Pin OPEN

Detection

*Driver stop

*SS discharge

3

Continuous for 9 µs

VCC_UVLO detection

*REG discharge

*2.5 mA sink from SH_OUT Reach OVP cancel

OVP

Detection

Over OVP detection

setting voltage

4

5

Continuous for 25 µs

*SS, REG discharge and

SR stop

voltage or VCC UVLO

detection

COMP

Detection

SH_IN>0.8 V

-

*Sink current from SH_OUT Restore

(Gx, Dx, Sx means x = 1 or 2)

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BD85506F

Abnormality Detection Function – continued

(1) Detection method of G1, G2 OPEN

When one of the G1 and G2 pins of the IC becomes OPEN or when the parts connected to the FET are disconnected, and

even if the FET cannot be operated through switching, the FET will still be able to output normally through Body diode

rectification operation. However, when heavy load is applied, the power loss at body diode increases and may cause

abnormal heat generation. This condition can be detected through the G pin OPEN detection function.

Below is a block diagram with an example for G pin OPEN detection operation.

I_FET2

OUT

(B)

PC1

I_FET1

BODY

DIODE

GND

PC1:

PC2:

FeedBack Latch Protection

PC2

(A)

120V

Clamper

(E)

UVLO

2.5µs

ONE SHOT PULSE

SELECTOR SELECTOR

(C)

IN

2.5µs

(D)

OUT

GATE

OPEN_DETECT

GATE

OPEN

COMP

-

COUNTER

-0.325V

D

S

Q

+

SR CONTROLLER

UVLO

Example of abnormality detection operation

Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality.

Abnormal condition: G1 is OPEN.

A: G1=OPEN

B: The FET is always turned OFF and its body diode performs

rectification. When I_FET1 flows, the voltage between the Drain

and Source of the FET becomes Vf.

C: D1 voltage is monitored after 2.5 µs from the time G1 turns ON.

Detected G1 OPEN state at less than -0.325 V.

D: G1 OPEN detection confirmed when 2048 pulses are

continuously detected.

(Count resets when D1 voltage becomes -0.325 V or more even

at 1 pulse)

E: Sinks the current from SH_OUT and stops the primary side via

the photo coupler (PC2).

(In case of G pin OPEN detection, synchronous rectification

operation is not stopped)

(C)

2.5µs

-0.325V

2.5µs

(B)

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BD85506F

Abnormality Detection Function – continued

(2) Detection method of D1, D2 OPEN

Likewise, if one of the D1 and D2 pins of the IC becomes OPEN or when the parts connected to the FET are

disconnected, the FET cannot be operated through switching, causing abnormal heat generation. But this IC is able to

detect such abnormalities through its D pin OPEN detection function.

Below is a block diagram with an example for D pin OPEN detection operation.

I_FET2

OUT

PC1

I_FET1

BODY

DIODE

GND

PC1:

PC2:

FeedBack Latch Protection

PC2

(A)

120V

Clamper

UVLO

SELECTOR

(D)

(C)

D

S

Q

DRAIN

OPEN

COUNTER

R

-

CH1

+

(B)

2.0V

-

CH2

+

SELECTOR

DRAIN

OPEN_DETECT

COMP

SR CONTROLLER

Example of abnormality detection operation

Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality.

Abnormal condition: D1 is OPEN.

(A)

A: No signal input when D1 = OPEN.

B: D1<2.0 V, chip detects D1 OPEN and starts counting.

C: D1 OPEN detection is confirmed when D1<2.0 V

continuously when the input pulse count at D2 reaches 128.

(Count resets when D1 becomes 2.0 V or more even at 1

pulse)

2.0V

(B)

(C)

128pulse

D: Sinks the current from SH_OUT and stops the primary side

via the photo coupler (PC2).

Synchronous rectification drive is stopped, discharging the

REG and SS pin capacitor.

(D)

REG

SS

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BD85506F

Regarding Abnormality Detection Function – continued

(3) Detection method of S1, S2 OPEN

When either S1 or S2 pin becomes OPEN, the S pin voltage rises by +Vf due to the circuit current. Therefore, since the

reference voltage of RESET COMP is also +Vf, it is not able to turn OFF the FET, which may lead to breakdown due to

FET reverse current. With this IC, S pin OPEN detection function prevents this FET from being destroyed, ensuring

safety of the circuit.

Below is a block diagram with an example for S pin OPEN detection operation.

I_FET2

OUT

PC1

Circuit Current

I_FET1

GND

PC1:

PC2:

FeedBack Latch Protection

PC2

(A)

120V

Clamper

UVLO

Vf

SELECTOR

(D)

SELECTOR

SOURCE COMP

D

S

Q

0.3V

-

9µs

DELAY

+

R

SELECTOR

UVLO

(C)

(B)

-0.12V

-6 mV→+Vf

Example of abnormality detection operation

Circuit configuration: A circuit that causes the PC2 to latch and stop on

the primary side after detection of abnormality.

Abnormal state: When S1 is set to OPEN.

A: When S1=OPEN, S1 voltage increases for +Vf when G1=H.

The voltage becomes S1≥0.3 V. (OFF threshold= - 6 mV should also

add +Vf. G1 cannot be turned off)

B: S1 OPEN is detected and counting starts.

C: After 9 µs of continuous detection, the S1 open state is confirmed.

D: Sinks the current from SH_OUT and stops the primary side via the

photo coupler (PC 2). Synchronous rectification drive is stopped,

discharging the REG and SS pin capacitors.

(C)

T>9µs

(B)

S1

In the S1, S2 OPEN state, FET may be destroyed by current backflow.

This is the system to stop the switching operation quickly. Therefore,

there is no pulse count, and the protection function is independent of the

slow start function.

S1=0.3V

0V

(A)

(D)

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BD85506F

Regarding Abnormality Detection Function – continued

(4) Detection method of overvoltage (OVP)

It is possible to detect when overvoltage has occurred due to abnormal feedback operation. The accuracy is within 2 %,

with high precision, and the mask period is set to 25 µs. Overvoltage detection can be set only by adjusting the upper

resistance since the lower resistor is built-in.

Below is a block diagram with an example of OVP detection operation.

I_FET2

(A)

OUT

PC1

I_FET1

GND

PC1:

PC2:

FeedBack Latch Protection

PC2

120V

Clamper

UVLO

-

SR CONTROLLER

+

OVP COMP

-

(E)

0.5V/0.45V

25µs

Delay

+

(F)

(C)

2.5mA

0.5V/0.25V

20k

(D)

Example of abnormality detection operation

Circuit configuration: A circuit that causes the PC2 to latch and stop on the primary side after detection of abnormality.

Abnormal state: When abnormally boosted.

A: The lower resistor of the shunt regulator shorts to GND.

B: The output voltage abnormally boosts.

(A)

C: The OVP detection voltage is reached.

D: OVP state is confirmed if abnormality persists for 25 µs.

E: Stops the primary side by current sink from SH_OUT, and discharges

REG and SS pin capacitors.

(C)

F: SR Driver is stopped when SS voltage reach SS≤0.45 V.

OVP detection has hysteresis, and it is canceled with 1/2 of the OVP detection

voltage. However, if VCC_UVLO is detected first, VCC_UVLO takes

precedence and OVP detection is canceled. OVP detection is controlled

independently of the slow start function.

(B)

(E)

(D)

0.45V

(F)

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BD85506F

Regarding Abnormality Detection Function – continued

(5) Multipurpose COMP detection method

The multipurpose comparator can use the SH_IN pin as an input pin. In the example below, it forms a circuit that detects

temperature abnormality of a set using a positive characteristic thermistor.

Below is a block diagram with an example of detection operation by COMP.

I_FET2

OUT

PC1

I_FET1

GND

PC1:

PC2:

FeedBack Latch Protection

PC2

(C)

120V

Clamper

(A)

COMP

-

SR CONTROLLER

+

(B)

0.8V

SS

ENABLE COMP

-

+

0.4V

Example of abnormality detection operation

Circuit configuration: A positive characteristic thermistor is used as a heat detecting element. An example of a circuit is

also shown for latching stop on the primary side by PC2 after detection of abnormality.

Abnormal condition: Abnormal heat generation.

A: The temperature rises and the positive characteristic thermistor resistance value rises. The SH_IN voltage rises.

B: The SH_IN pin voltage reaches 0.8 V or more.

C: Comparator output drives the photo coupler (PC2) and stops the primary side.

The detection precision of COMP is as high as 1 %, there is no mask period and no hysteresis. Since the SH_IN pin is

also used as ENABLE, input setting should be made so that SH_IN≥0.48 V during normal operation.

And COMP is controlled independently of the slow start function.

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BD85506F

2.Setting After Abnormality Detection

Depending on the application, operation after abnormality detection can be in any of the following: latch protection, auto

restart protection, judgment only signal output, or unused.

These application circuits and operation methods will be explained in the following sections.

(1) Example of latch protection application

If there is a latch stop protection function on the primary side, the circuit sends a signal to the primary side via the photo

coupler and stops the primary side.

Below is a latch protection application circuit and a sequence example.

OUT

PC1

GND

PC1:

PC2:

FeedBackLatch Protection

PC2

BD85506F

Primary side latched due to drive

PC2 after detection

GATE1

G2 Example of OPEN protection operation sequence

A: G2 is OPEN.

DRAIN1

GATE2

B: Count for G2 OPEN detection state.

C: Count of 2048 pulses completes.

D: Constant current sink from SH_OUT.

E: VOUT drops with primary side latch stop by PC2.

F: SH_IN≤0.35 V, discharge SS and REG.

G: VCC_UVLO is detected at VCC ≤ 4.3 V and

secondary side stops.

(A)

DRAIN2

(C)

(B)

0.6V

0.35V

SH_IN

(F)

VOUT

4.3V

(E)

(G)

SS

(D)

I_SH_OUT

Sink Current

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Setting After Abnormality Detection – continued

(2) Auto restart application example

In this method, function does not stop completely after abnormality detection. In the detection period, the output toggles

between ON and OFF, and if the state returns to normal, the circuit resumes normal operation after detection of UVLO.

Below are examples of application circuits and sequence examples for auto restart protection. (Below is an example of

use of the primary side control IC which completely stops when current is forcibly passed to the feedback photo coupler

PC1)

For this application, COMP cannot be used as protection

OUT

PC1

GND

SHUNT

REGULATOR

PC1:

FeedBack

BD85506F

Example of auto restart application circuit when using an external shunt regulator.

OUT

PC1

GND

PC1:

FeedBack

BD85506F

Example of auto restart application circuit when COMP is used as shunt regulator.

Example for G2 OPEN protection

operation sequence

A: G2 is OPEN.

GATE1

B: Count for G2 OPEN detection state starts.

C: Count of 2048 pulses completes.

D: Constant current sink from SH_OUT.

DRAIN1

E: PC1 stops primary side and VOUT drops.

(C)

F: VCC holds voltage by Diode and capacitor

and secures stop time (heat dissipation

time).

(B)

(A)

GATE2

G: SH_IN≤0.35 V, discharge SS and REG.

H: VCC≤VCC_UVLO is detected at 4.3 V.

SH_OUT Sink current stops, primary side

restarts.

I: VCC≥4.5 V, Releases VCC_UVLO and

starts SS charging.

DRAIN2

0.6V

0.35V

SH_IN

J: SS reaches 0.5 V, synchronous

rectification, G, D pin open detection

function, operation starts.

(F)

VOUT

VCC

(E)

Return to B.

VCC=4.5V

VCC=4.3V

(I)

(H)

(G)

(D)

SS

0.5V

(J)

2.5mA

I_SH_OUT

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BD85506F

Setting After Abnormality Detection – continued

(3) Application example using only judgment signal

Shown below is an example of application to output a FAIL signal to be used in making a High or Low judgment for

shipment inspection, etc.

OUT

PC1

GND

SHUNT

REGULATOR

PC1:

FeedBack

FAIL

BD85506F

(4) Example of application not using the abnormality detection signal

OUT

PC1

GND

SHUNT

REGULATOR

PC1:

FeedBack

BD85506F

When the abnormality detection signal is not used:

* OPEN the SH_OUT pin

* Open the OVP pin

* For the SH_IN pin, input a voltage between 0.48 V (Max) and 0.792 V (Min) by a resistor divider on the VOUT or REG

pin.

By doing this, FAIL output of G pin OPEN detection, OVP detection, COMP detection is disabled.

However, when the D pin OPEN and the S pin OPEN are detected, the secondary side synchronous rectification

operation is stopped.

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Selection of External Components

1. SS Pin Setting

Set the operation start time of the G pin OPEN detection, D pin OPEN detection, and secondary side synchronous

rectification at the startup time by the capacitance value connected to the SS pin. When the SH_IN pin voltage reaches

VCC≥4.5 V, charging starts with a constant current of 50 µA to the SS pin capacitor. When the SS pin voltage V_SS≥0.5 V is

reached, secondary side synchronous rectification operation and G, D pin OPEN detection function start operating.

4.5V

VOUT

0.4V

SH_IN

0.5V

SS

D1,2

G1,2

The formula for setting SS time t_SSand capacitance C_SSis

Pull Down Resistor

푡

(푠)

ꢀꢀ

4V

SS_COMP

⁻⁶( )

퐶_푆푆= 50 × 10 퐴 × _ꢁ.ꢂ(푉)[F]

SS

+

SR

Controller

As an example, the capacitance value for canceling slow start after 5 ms:

-

0.5V

ꢄ3

ꢂ×ꢃꢁ (푠)

⁻⁶( )

퐶_푆푆= 50 × 10 퐴 ×

= 0.5 [µF]

ꢁ.ꢂ(푉)

In addition, it is also effective to connect a pull-down resistor to make the slow start time longer. The slow start time for this

is expressed by the following formula.

( )

푠

푡

ꢀꢀ

퐶_푠푠= ꢅ

[F]

(

)

ꢇ

ꢀꢀ

)

( )

훺 ×푙푛ꢆꢃ−

푅

ꢋ

ꢀꢀ

(

( )

ꢊ

ꢈ

ꢉ ×퐼

ꢀꢀ

Calculation example

The C_SScapacitance for t_SS=140 ms, R_SS=20 kΩ, V_SS=0.5 V, I_SS=50 µA is:

( )

ꢁ.ꢃ4 푠

퐶_푠푠= ꢅ

≅ 10 [µF]

(

)

ꢍ.ꢎ ꢇ

3

( )

2ꢁ×ꢃꢁ 훺 ×푙푛ꢌꢃ−

ꢒ

)

3

ꢄꢑ

(

ꢊ

(

)

ꢏꢍ×ꢐꢍ ꢉ ×ꢎꢍ×ꢐꢍ

However, please set the resistance value of R_SSso as to exceed the slow start completion voltage V_SStaking to account

tolerances of values.

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BD85506F

Application Part Selection Method – continued

2. OVP Pin Setting

Since the lower resistor (20 kΩ) is built-in the OVP pin, it is possible to set the detection voltage by adjusting the resistance

between the detection node and OVP pin. After OVP detection, current sinks from SH_OUT.

OUT

R_OVP

GND

OVP BLOCK

-

+

0.5V

20k

OVP detection theoretical voltage formula

^{( )}× ꢖ0(푘ꢗ) ꢅ ꢖ0(푘ꢗ) [kΩ]

ꢁ.ꢂ(푉)

푉

ꢔꢇꢕ_푇퐻ꢐ

ꢓ_푂푉푃

=

Calculation example

The set resistance value R_OVPwhen V_{OVP_TH1}= 20 V is

2ꢁ(푉)

ꢓ_푂푉푃

= _ꢁ.ꢂ(푉)× ꢖ0(푘ꢗ) ꢅ ꢖ0(푘ꢗ) = 780 [kΩ]

3. TH Pin Setting

By adjusting the resistance at the TH pin, the OFF threshold voltage of secondary side synchronous rectification can be

changed.

15.0

10.0

I_FET1

5.0

0A

0.0

D1

VOUT

0V

-5.0

-120mV

-10.0

-15.0

G1

ON

0V

OFF Threshold

0

50

100

150

200

250

300

350

TH Pin Resistor R_TH[kΩ]

Be careful that OFF threshold accuracy changes depending on the resistor value

The relationship between the GATE OFF threshold voltage V_GOFFand the adjustment resistor R_THis as follows.

(

)

4ꢂ×푅

ꢙ훺

푇퐻

(

)

ꢘ_퐺푂퐹퐹= 1ꢖ 푚ꢘ ꢅ _{ꢚꢛꢁꢁ ꢙ훺 +푅}

[mV]

(

)

(

)

ꢙ훺 ꢜ

푇퐻

Calculation example

The set GATE OFF Threshold value V_GOFFwhen R_TH= 200 kΩ is

4ꢂ×2ꢁꢁꢙ훺

(

)

ꢘ_퐺푂퐹퐹= 1ꢖ 푚ꢘ ꢅ _{ꢚꢛꢁꢁ ꢙ훺 +2ꢁꢁ ꢙ훺 ꢜ}= ꢅꢝ [mV]

(

)

(

)

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BD85506F

Application Part Selection Method – continued

4. SH_IN Pin Setting

The SH_IN pin is the input pin of the multipurpose comparator with 0.8 V reference and SH_OUT as the output. Typical

uses are:

A. Overvoltage detection (double detection together with the OVP pin);

B. Circuit overheat detection; and

C. Shunt Regulator

However, since the SH_IN pin is also used as the ENABLE function, it is necessary to input a voltage to the SH_IN pin

greater than or equal to 0.48 V (Max) during normal operation.

(1) For overvoltage detection

Normally, the OVP pin is used for overvoltage detection, but double detection can be made by using multipurpose COMP

for additional safety improvement.

V_OUT

OUT

R_UP

R_OVP

R_DOWN

GND

COMP

-

+

OVP

0.8V

+

20k

-

4V

0.5V

SS COMP

+

SR

ENABLE COMP

Controller

-

0.5V

+

0.4V

The method on how to set values is shown below. The setting of the resistance dividers R_UPand R_DOWNwhen the output

voltage is V_OUTand the overvoltage output to be detected is V_{SH_OVP}are as follows.

( )

푉 −푉

( )

푉 ꢒ

ꢀ퐻_ꢈ퐸ꢞ

ꢌ푉

ꢀ퐻_ꢔꢇꢕ

(

)

ꢓ_푈푃= ꢓ_퐷푂푊푁푘ꢗ ×

[kΩ]

( )

푉

ꢀ퐻_ꢈ퐸ꢞ

However, during normal operation, the SH_IN pin voltage V_{SH_IN}must satisfy the following conditions.

(

)

ꢙ훺

푅

ꢣꢔꢤꢥ

( )

= 0.ꢡ8ꢘ ≤ ꢘ_푂푈ꢢꢘ × _ꢚ푅

ꢘ

푆ꢟ_ꢠ푁

[V]

)

(

)

(

ꢙ훺 ꢜ

ꢣꢔꢤꢥ

ꢙ훺 +푅

ꢦꢕ

Calculation example

When setting V_OUT=24 V for normal operation and V_{SH_OVP}=28.8 V for OVP detection voltage, the R_UPresistance value

when R_DOWN=12 kΩ is:

( )

ꢚ2ꢧ.ꢧ 푉 −ꢁ.ꢧ 푉 ꢜ

(

)

ꢓ_푈푃= 1ꢖ 푘ꢗ ×

= ꢡꢖ0 [kΩ]

( )

ꢁ.ꢧ 푉

Also, the SH_IN pin voltage during stable operation is

(

)

ꢃ2 ꢙ훺

( )

= ꢖꢡ ꢘ ×

ꢘ

푆ꢟ_ꢠ푁

= 0.ꢝꢝ7ꢘ ≥ 0.ꢡ8 [V]

)

(

)

(

ꢚ42ꢁ ꢙ훺 +ꢃ2 ꢙ훺 ꢜ

The above values meet the condition for operation.

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BD85506F

SH_IN Pin Setting – continued

(2) For overheating detection

By using a positive characteristic thermistor for resistance division at the SH_IN pin, circuit overheat detection is possible.

The characteristics of the positive temperature coefficient thermistor are almost constant resistance value at around room

temperature. But when a certain temperature (Curie point) is exceeded, the resistance value increases sharply. It is

possible to detect the temperature by using this characteristic.

V_OUT

OUT

R_UP

R_POS

R_OVP

R_DOWN

GND

COMP

-

+

OVP

0.8V

+

-

20k

4V

0.5V

SS COMP

+

SR

ENABLE COMP

Controller

-

0.5V

+

0.4V

If the output voltage during normal operation is V_OUT, the positive characteristic thermistor resistance value of the

temperature to be detected is R_POS1, and the lower resistance value of the resistor divider is R_DOWN, the upper resistance

value R_UPis set as shown below.

(

)

ꢙ훺 +푅

ꢕꢔꢀꢐ

(

)

ꢚ푅

^{ꢙ훺 ꢜ}ꢅ ꢚꢓ_퐷푂푊푁푘ꢗ ꢨ ꢓ_푃푂푆ꢃ푘ꢗ ꢜ [kΩ]

ꢣꢔꢤꢥ

( )

ꢓ_푈푃= ꢘ_푂푈ꢢꢘ ×

(

)

(

)

( )

푉

ꢀ퐻_ꢈ퐸ꢞ

However, the following condition must be satisfied for the positive characteristic thermistor resistance value R_POS2at the

normal temperature and the SH_IN pin voltage V_{SH_IN}

.

(

)

(

ꢕꢔꢀꢏ

)

ꢙ훺

푅

ꢙ훺 +푅

ꢣꢔꢤꢥ

( )

ꢘ

푆ꢟ_ꢠ푁

= 0.ꢡ8 ꢘ ≤ ꢘ_푂푈ꢢꢘ × _ꢚ푅

[V]

(

)

(

)

( )

ꢙ훺 ꢜ

ꢕꢔꢀꢏ

ꢙ훺 +푅

ꢦꢕ

ꢣꢔꢤꢥ

Calculation example

For example, using Murata PRF15BB102RB6RC ^{(Note 7)}as a positive characteristic thermistor:

(Note 7) Please refer to the data sheet published by Murata Co. for product information.

When setting the positive characteristic thermistor temperature to detect at 115 °C,

During normal operation V_OUT=24 V,

The positive characteristic thermistor resistance value at the detection temperature of 115 °C is R_POS1=10 kΩ

The R_UPresistance value when R_DOWN=22 kΩ is

(

)

(

)

ꢚ22 ꢙ훺 +ꢃꢁ ꢙ훺 ꢜ

( )

ꢓ_푈푃= ꢖꢡ ꢘ ×

(

)

(

)

ꢅ ꢚꢖꢖ 푘ꢗ ꢨ 10 푘ꢗ ꢜ = 9ꢖ8 [kΩ]

( )

ꢁ.ꢧ 푉

Also, the positive characteristic thermistor resistance value at 25 °C is R_POS2=0.5 kΩ (Min) in consideration of tolerances,

(

)

(

)

22 ꢙ훺 +ꢁ.ꢂ ꢙ훺

( )

ꢘ

푆ꢟ_ꢠ푁

= 0.ꢡ8 ꢘ ≤ ꢖꢡ ꢘ × _{ꢚꢩ2ꢧ ꢙ훺 +22 ꢙ훺 +ꢁ.ꢂ ꢙ훺 ꢜ}= 0.5ꢝ8 [V]

(

)

(

)

(

)

This meets the condition.

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BD85506F

SH_IN Pin Setting – continued

(3) As a shunt regulator

Connecting a feedback resistor to the SH_IN pin makes it usable as a shunt regulator. Since the current consumption

from SH_OUT is as small as 10 µA, it is possible to reduce standby power consumption at no load.

V_OUT

OUT

R_FB1

C_FB1

R_UP

C_FB2

R_FB2

R_DOWN

R_OVP

GND

COMP

-

+

OVP

0.8V

4V

+

-

20k

0.5V

SS COMP

+

-

SR

Controller

ENABLE COMP

-

0.5V

+

0.4V

In normal operation, the output voltage is V_OUT, the feedback resistance divides R_UP, R_DOWNvalues are as follows.

( )

푉 −푉

( )

푉 ꢒ

ꢀ퐻_ꢈ퐸ꢞ

ꢌ푉

ꢔꢦ푇

(

)

ꢓ_푈푃= ꢓ_퐷푂푊푁푘ꢗ ×

[kΩ]

( )

푉

ꢀ퐻_ꢈ퐸ꢞ

Calculation example

The R_UPresistance value when V_OUT=24 V in normal operation and the lower side resistance R_DOWNis 80 kΩ,

( ) ( )

ꢓ_푈푃= 80 푘ꢗ × ^{ꢚ24 푉 −ꢁ.ꢧ 푉 ꢜ}= ꢖꢪꢖ0 [kΩ]

(

)

( )

ꢁ.ꢧ 푉

However, it is necessary to reset the phase compensation of R_FB1, R_FB2, C_FB1, and C_FB2. Therefore, it is recommended to

check with FRA or other instruments, to ensure that the oscillation margin is enough after setting.

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BD85506F

Application Part Selection Method – continued

5.The SS pin discharge function by SH_IN voltage

When the SH_IN pin is set to 0.4 V or less, the SS pin capacitor is discharged. With this function, synchronous

rectification and G, D pin OPEN protection can be stopped arbitrarily by an external signal.

However, this function cannot be used as a reset after error detection.

V_OUT

OUT

ENABLE

GND

COMP

-

+

OVP

0.8V

+

20k

-

0.5V

D

S

Q

G OPEN

Protection Counter

D OPEN

D

S

Q

Protection Counter

4V

SR_ON/OFF

4V

SS COMP

D

S

Q

SS

+

-

ENABLE COMP

-

0.5V

+

VCC_UVLO

0.4V

Also, at startup, a large amount of rush current flows and operation may become unstable. Therefore, after set voltage

had been reached (SH_IN voltage≥0.4 V), SR control and G, D pin OPEN detection starts operation.

In the case of SH_IN<0.4 V at SS≥0.5 V,

In the case of SH_IN≥0.4 V at SS≥0.5 V,

Startup sequence

VCC

4.5V

0

SH_IN≥0.4V

0.4V

SH_IN

SH_IN<0.4V

0

ENABLE COMP

OUTPUT

ENABLE COMP

OUTPUT

0.5V

SS

STATE

ACT

STOP

STATE

STOP

If SS≥0.5 V, when SH_IN≥0.4 V, it is judged that the set output has been reached and the SS pin capacitor continues

charging.

But if SS≥0.5 V, when SH_IN<0.4 V, it is judged that the set voltage has not been reached and the SS pin capacitor is

discharged. And when the voltage reaches SH_IN≥0.4 V, charging of the SS pin capacitor restarts.

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BD85506F

I/O Equivalence Circuits

1pin VCC / 2pin REG / 9pin S2 / 10pin G2

12pin G1 / 13pin S1

3pin SH_IN / 4pin SH_OUT

1.VCC

2.REG

SR

block

12.G1

10.G2

4.SH_OUT

3.SH_IN

5.AGND

13.S1

9.S2

5.AGND

6pin TH

7pin SS

Internal

REG

Internal

REF

6.TH

7.SS

5.AGND

11pin OVP

8pin D2 / 14pin D1

8.D2

14.D1

SR

block

11.OVP

5.AGND

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BD85506F

Layout Notes

(5)

(8)

D₁

R_DRAIN1

R_DRAIN3

OUT

(5)

(8)

GND

6

(7)

R_DRAIN2

R_DRAIN4

D₂

(3)

(4)

(2)

(1)

(6)

R_VCC

C_REG

C_VCC

R_TH

C_SS

FAIL

LLC Application Circuit

(1) The VCC line may malfunction under the influence of switching noise.

Therefore, it is recommended to connect the noise suppression capacitor C_VCC(2.2 µF or more including temperature

characteristics, DC bias characteristics, and tolerances) and resistor R_VCC(100 Ω or more) between near by the VCC pin

and the AGND pin. At this time, the supply voltage drops due to the R_VCCresistance, but please set the resistance value

so that the FET Driver voltage can be sufficiently secured.

(2) The SH_IN pin is a high-impedance line. Layout its wiring as short as possible and make sure it does not run parallel to a

switching line.

(3) The TH pin is OFF threshold setting pin. When the OFF timing is affected by switching, it is recommended to connect

resistor R_THto the TH Pin and AGND as near to the TH pin as possible.

(4) The SS pin is the slow start time setting pin. It is recommended that the capacitor C_SSis connected as closest to the

AGND line as possible.

(5) Since the synchronous rectification controller IC needs to accurately monitor the V_DSgenerated in the FET, ensure to

connect the D1 and D2 pins of the IC to the Drain of the FET and the S1 and S2 pins to the Source of the FET

independently.

It is recommended to set the DRAIN monitoring point of the FET considering the influence of the parasitic inductor due to

the substrate wiring of the current path.

(6) It is recommended that the GND of the different parts connected to the IC is connected to the output GND through

independent wiring.

(7) Because the Drain wiring is a switching line, it should be wired as short as possible and be wire thinly.

(8) Since the D1 and D2 pins detect a very small voltage, it may toggle between ON and OFF depending on the surge

voltage.

Therefore, it is recommended to connect a filter circuit as a measure to absorb surge.

Value setting reference example^{(Note 8)}

:

Schottky barrier diode D₁D₂: RB751G-40 (ROHM)

FET turn off filter resistance R_DRAIN1R_DRAIN2: 0.3 k to 2 kΩ

Drain pin current limit resistor R_DRAIN3R_DRAIN4: 150 Ω

(Note 8) Constants are reference values and not guaranteed values. Please verify on the actual application and set optimum values for the constants.

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BD85506F

Operational Notes

1.

2.

Reverse Connection of Power Supply

Connecting the power supply in reverse polarity can damage the IC. Take precautions against reverse polarity when

connecting the power supply, such as mounting an external diode between the power supply and the IC’s power supply

pins.

Power Supply Lines

Design the PCB layout pattern to provide low impedance supply lines. Furthermore, connect a capacitor to ground at

all power supply pins. Consider the effect of temperature and aging on the capacitance value when using electrolytic

capacitors.

3.

4.

Ground Voltage

Except for pins the output and the input of which were designed to go below ground, ensure that no pins are at a

voltage below that of the ground pin at any time, even during transient condition.

Ground Wiring Pattern

When using both small-signal and large-current ground traces, the two ground traces should be routed separately but

connected to a single ground at the reference point of the application board to avoid fluctuations in the small-signal

ground caused by large currents. Also ensure that the ground traces of external components do not cause variations

on the ground voltage. The ground lines must be as short and thick as possible to reduce line impedance.

5.

6.

Recommended Operating Conditions

The function and operation of the IC are guaranteed within the range specified by the recommended operating

conditions. The characteristic values are guaranteed only under the conditions of each item specified by the electrical

characteristics.

Inrush Current

When power is first supplied to the IC, it is possible that the internal logic may be unstable and inrush current may flow

instantaneously due to the internal powering sequence and delays, especially if the IC has more than one power supply.

Therefore, give special consideration to power coupling capacitance, power wiring, width of ground wiring, and routing

of connections.

7.

Testing on Application Boards

When testing the IC on an application board, connecting a capacitor directly to a low-impedance output pin may subject

the IC to stress. Always discharge capacitors completely after each process or step. The IC’s power supply should

always be turned off completely before connecting or removing it from the test setup during the inspection process. To

prevent damage from static discharge, ground the IC during assembly and use similar precautions during transport and

storage.

8.

9.

Inter-pin Short and Mounting Errors

Ensure that the direction and position are correct when mounting the IC on the PCB. Incorrect mounting may result in

damaging the IC. Avoid nearby pins being shorted to each other especially to ground, power supply and output pin.

Inter-pin shorts could be due to many reasons such as metal particles, water droplets (in very humid environment) and

unintentional solder bridge deposited in between pins during assembly to name a few.

Unused Input Pins

Input pins of an IC are often connected to the gate of a MOS transistor. The gate has extremely high impedance and

extremely low capacitance. If left unconnected, the electric field from the outside can easily charge it. The small charge

acquired in this way is enough to produce a significant effect on the conduction through the transistor and cause

unexpected operation of the IC. So unless otherwise specified, unused input pins should be connected to the power

supply or ground line.

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BD85506F

Operational Notes – continued

10. Regarding the Input Pin of the IC

This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them

isolated. P-N junctions are formed at the intersection of the P layers with the N layers of other elements, creating a

parasitic diode or transistor. For example (refer to figure below):

When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.

When GND > Pin B, the P-N junction operates as a parasitic transistor.

Parasitic diodes inevitably occur in the structure of the IC. The operation of parasitic diodes can result in mutual

interference among circuits, operational faults, or physical damage. Therefore, conditions that cause these diodes to

operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be

avoided.

Resistor

Transistor (NPN)

Pin A

Pin B

B

E

C

Pin A

B

C

E

P

P⁺

N

P⁺

P

P⁺

N

Parasitic

Elements

Parasitic

Elements

P Substrate

GND GND

P Substrate

GND

Parasitic

Elements

Parasitic

Elements

N Region

close-by

Figure 9. Example of monolithic IC structure

11. Ceramic Capacitor

When using a ceramic capacitor, determine a capacitance value considering the change of capacitance with

temperature and the decrease in nominal capacitance due to DC bias and others .

12. Thermal Shutdown Circuit (TSD)

This IC has a built-in thermal shutdown circuit that prevents heat damage to the IC. Normal operation should always

be within the IC’s maximum junction temperature rating. If however the rating is exceeded for a continued period, the

junction temperature (Tj) will rise which will activate the TSD circuit that will turn OFF power output pins. When the Tj

falls below the TSD threshold, the circuits are automatically restored to normal operation.

Note that the TSD circuit operates in a situation that exceeds the absolute maximum ratings and therefore, under no

circumstances, should the TSD circuit be used in a set design or for any purpose other than protecting the IC from heat

damage.

13. Over Current Protection Circuit (OCP)

This IC incorporates an integrated overcurrent protection circuit that is activated when the load is shorted. This

protection circuit is effective in preventing damage due to sudden and unexpected incidents. However, the IC should

not be used in applications characterized by continuous operation or transitioning of the protection circuit.

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BD85506F

Ordering Information

B D 8

5

0

6

F

-

E 2

Part Number

Package

F:SOP14

Packaging and forming specification

E2: Embossed tape and reel

Marking Diagram

SOP14(TOP VIEW)

Part Number Marking

LOT Number

BD 8 5 5 0 6 F

Pin 1 Mark

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BD85506F

Physical Dimension and Packing Information

Package Name

SOP14

(Max 9.05 (include.BURR))

(UNIT: mm)

PKG: SOP14

Drawing No.: EX113-5001

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BD85506F

Revision History

Date

Rev.

Changes

22.Aug.2018

28.Dec.2020

001

002

New Release

Updated packages and part numbers. P33-2,P33-3

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BD85506F

Ordering Information

B D 8

5

0

6

F

-

Z E 2

Part Number

Package

F:SOP14K

Packaging and forming specification

Production site Z: Added

E2: Embossed tape and reel

Marking Diagram

SOP14K(TOP VIEW)

Part Number Marking

LOT Number

B D 8 5 5 0 6 F

Pin 1 Mark

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BD85506F

Physical Dimension and Packing Information

Package Name

SOP14K

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Notice

Precaution on using ROHM Products

1. Our Products are designed and manufactured for application in ordinary electronic equipment (such as AV equipment,

OA equipment, telecommunication equipment, home electronic appliances, amusement equipment, etc.). If you

intend to use our Products in devices requiring extremely high reliability (such as medical equipment ^{(Note 1)}, transport

equipment, traffic equipment, aircraft/spacecraft, nuclear power controllers, fuel controllers, car equipment including car

accessories, safety devices, etc.) and whose malfunction or failure may cause loss of human life, bodily injury or

serious damage to property (“Specific Applications”), please consult with the ROHM sales representative in advance.

Unless otherwise agreed in writing by ROHM in advance, ROHM shall not be in any way responsible or liable for any

damages, expenses or losses incurred by you or third parties arising from the use of any ROHM’s Products for Specific

Applications.

(Note1) Medical Equipment Classification of the Specific Applications

JAPAN

USA

EU

CHINA

CLASSⅢ

CLASSⅣ

CLASSⅡb

CLASSⅢ

2. ROHM designs and manufactures its Products subject to strict quality control system. However, semiconductor

products can fail or malfunction at a certain rate. Please be sure to implement, at your own responsibilities, adequate

safety measures including but not limited to fail-safe design against the physical injury, damage to any property, which

a failure or malfunction of our Products may cause. The following are examples of safety measures:

[a] Installation of protection circuits or other protective devices to improve system safety

[b] Installation of redundant circuits to reduce the impact of single or multiple circuit failure

3. Our Products are designed and manufactured for use under standard conditions and not under any special or

extraordinary environments or conditions, as exemplified below. Accordingly, ROHM shall not be in any way

responsible or liable for any damages, expenses or losses arising from the use of any ROHM’s Products under any

special or extraordinary environments or conditions. If you intend to use our Products under any special or

extraordinary environments or conditions (as exemplified below), your independent verification and confirmation of

product performance, reliability, etc, prior to use, must be necessary:

[a] Use of our Products in any types of liquid, including water, oils, chemicals, and organic solvents

[b] Use of our Products outdoors or in places where the Products are exposed to direct sunlight or dust

[c] Use of our Products in places where the Products are exposed to sea wind or corrosive gases, including Cl2,

H2S, NH3, SO2, and NO2

[d] Use of our Products in places where the Products are exposed to static electricity or electromagnetic waves

[e] Use of our Products in proximity to heat-producing components, plastic cords, or other flammable items

[f] Sealing or coating our Products with resin or other coating materials

[g] Use of our Products without cleaning residue of flux (Exclude cases where no-clean type fluxes is used.

However, recommend sufficiently about the residue.) ; or Washing our Products by using water or water-soluble

cleaning agents for cleaning residue after soldering

[h] Use of the Products in places subject to dew condensation

4. The Products are not subject to radiation-proof design.

5. Please verify and confirm characteristics of the final or mounted products in using the Products.

6. In particular, if a transient load (a large amount of load applied in a short period of time, such as pulse, is applied,

confirmation of performance characteristics after on-board mounting is strongly recommended. Avoid applying power

exceeding normal rated power; exceeding the power rating under steady-state loading condition may negatively affect

product performance and reliability.

7. De-rate Power Dissipation depending on ambient temperature. When used in sealed area, confirm that it is the use in

the range that does not exceed the maximum junction temperature.

8. Confirm that operation temperature is within the specified range described in the product specification.

9. ROHM shall not be in any way responsible or liable for failure induced under deviant condition from what is defined in

this document.

Precaution for Mounting / Circuit board design

1. When a highly active halogenous (chlorine, bromine, etc.) flux is used, the residue of flux may negatively affect product

performance and reliability.

2. In principle, the reflow soldering method must be used on a surface-mount products, the flow soldering method must

be used on a through hole mount products. If the flow soldering method is preferred on a surface-mount products,

please consult with the ROHM representative in advance.

For details, please refer to ROHM Mounting specification

Notice-PGA-E

Rev.004

Precautions Regarding Application Examples and External Circuits

1. If change is made to the constant of an external circuit, please allow a sufficient margin considering variations of the

characteristics of the Products and external components, including transient characteristics, as well as static

characteristics.

2. You agree that application notes, reference designs, and associated data and information contained in this document

are presented only as guidance for Products use. Therefore, in case you use such information, you are solely

responsible for it and you must exercise your own independent verification and judgment in the use of such information

contained in this document. ROHM shall not be in any way responsible or liable for any damages, expenses or losses

incurred by you or third parties arising from the use of such information.

Precaution for Electrostatic

This Product is electrostatic sensitive product, which may be damaged due to electrostatic discharge. Please take proper

caution in your manufacturing process and storage so that voltage exceeding the Products maximum rating will not be

applied to Products. Please take special care under dry condition (e.g. Grounding of human body / equipment / solder iron,

isolation from charged objects, setting of Ionizer, friction prevention and temperature / humidity control).

Precaution for Storage / Transportation

1. Product performance and soldered connections may deteriorate if the Products are stored in the places where:

[a] the Products are exposed to sea winds or corrosive gases, including Cl₂, H₂S, NH₃, SO₂, and NO₂

[b] the temperature or humidity exceeds those recommended by ROHM

[c] the Products are exposed to direct sunshine or condensation

[d] the Products are exposed to high Electrostatic

2. Even under ROHM recommended storage condition, solderability of products out of recommended storage time period

may be degraded. It is strongly recommended to confirm solderability before using Products of which storage time is

exceeding the recommended storage time period.

3. Store / transport cartons in the correct direction, which is indicated on a carton with a symbol. Otherwise bent leads

may occur due to excessive stress applied when dropping of a carton.

4. Use Products within the specified time after opening a humidity barrier bag. Baking is required before using Products of

which storage time is exceeding the recommended storage time period.

Precaution for Product Label

A two-dimensional barcode printed on ROHM Products label is for ROHM’s internal use only.

Precaution for Disposition

When disposing Products please dispose them properly using an authorized industry waste company.

Precaution for Foreign Exchange and Foreign Trade act

Since concerned goods might be fallen under listed items of export control prescribed by Foreign exchange and Foreign

trade act, please consult with ROHM in case of export.

Precaution Regarding Intellectual Property Rights

1. All information and data including but not limited to application example contained in this document is for reference

only. ROHM does not warrant that foregoing information or data will not infringe any intellectual property rights or any

other rights of any third party regarding such information or data.

2. ROHM shall not have any obligations where the claims, actions or demands arising from the combination of the

Products with other articles such as components, circuits, systems or external equipment (including software).

3. No license, expressly or implied, is granted hereby under any intellectual property rights or other rights of ROHM or any

third parties with respect to the Products or the information contained in this document. Provided, however, that ROHM

will not assert its intellectual property rights or other rights against you or your customers to the extent necessary to

manufacture or sell products containing the Products, subject to the terms and conditions herein.

Other Precaution

1. This document may not be reprinted or reproduced, in whole or in part, without prior written consent of ROHM.

2. The Products may not be disassembled, converted, modified, reproduced or otherwise changed without prior written

consent of ROHM.

3. In no event shall you use in any way whatsoever the Products and the related technical information contained in the

Products or this document for any military purposes, including but not limited to, the development of mass-destruction

weapons.

4. The proper names of companies or products described in this document are trademarks or registered trademarks of

ROHM, its affiliated companies or third parties.

Notice-PGA-E

Rev.004


型号：	BD85506F
厂家：	ROHM
描述：	BD85506F是具备各种二次侧异常检测功能的LLC用2ch二次侧同步整流控制器。本IC内置检测BODYDIODE整流动作等FET异常的功能。还内置高精度过电压检测电路，有助于提高安全性并减少外接零部件。在效率方面，可通过电阻调整同步整流FET的OFF阈值电压。而且，通过设置各FET的SOURCE监视端子，可监视各DRAIN-SOURCE间电压，能进一步改善效率。一次侧控制器在轻负载时的启动脉冲串会使同步整流动作自动处于待机状态，抑制开关功率及IC自身的电路电流，减少待机功耗。而且，内置的多功能比较器除用作异常检测比较器外，还可用作低功耗分流稳压器。工作电源电压范围广，为5.0V~32V，适用于各种输出电压产品阵容。采用高耐压120V(Max)处理器，可直接监视漏极电压。开关控制器脉冲比较器稳压器
文件：	总38页 (文件大小：1468K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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